JP4770388B2 - Color image forming apparatus and control method thereof - Google Patents

Description

  The present invention relates to a color image forming apparatus suitable for being applied to a color printer, the same facsimile machine, the same digital copying machine, a complex machine thereof, and the like, and a control method therefor.

  In recent years, tandem type color printers, color copiers, and multi-function machines of these are often used. These color image forming apparatuses include an image writing unit for each of yellow (Y), magenta (M), cyan (C), and black (BK), a developing unit, a photosensitive drum, an intermediate transfer belt, and a fixing unit. And a device.

  For example, an image writing unit for Y color draws an electrostatic latent image on the photosensitive drum based on the image data for Y color. The developing means forms a color toner image by attaching Y color toner to the electrostatic latent image drawn on the photosensitive drum. The photosensitive drum transfers the toner image to the intermediate transfer belt. Similar processing is performed for the other M, C, and BK colors. The color toner image transferred to the intermediate transfer belt is transferred to a sheet and then fixed by a fixing device.

  In this type of color image forming apparatus, an apparatus capable of forming a color image on both sides of a sheet has been developed and manufactured. The double-sided image forming function is used, for example, when creating a booklet and forming images for a front cover and a back cover on a sheet. In many cases, the cover and back cover sheets are thicker than the body sheets. The front and back cover sheets after double-sided image formation are post-processed such as half-folding or stapling. In such double-sided image forming processing, it is known that the paper contracts after an image is formed on one side of the paper. This is because the sheet on which the color toner image has been transferred is thermally contracted by the fixing process, and the contraction is more significant as the sheet is thicker. Therefore, it is necessary to change the image forming conditions in order to match the image positions of the front surface and the back surface of the paper.

  FIGS. 13A and 13B are diagrams for explaining an example of contraction of the paper size during double-sided image formation.

  A sheet P shown in FIG. 13A is in a state before fixing after a color toner image is secondarily transferred. As for the paper size of the paper P, the vertical length is Lmm and the horizontal width is Wmm. The sheet P ′ shown in FIG. 13B is in a state after the sheet P is fixed. Regarding the paper size of the paper P ′, the vertical length is shrunk to L ′ mm, and the horizontal width is shrunk to W ′ mm. The cause of paper size shrinkage is thought to be water divergence during fixing. In response to the shrinkage of the paper size of the paper P, an image must be formed on the back surface of the paper. Incidentally, the image forming positions (sizes) on the front and back sides are shifted unless the image forming conditions are adjusted to the paper size L′ mm × W′mm after shrinkage.

  In response to the shrinkage of the paper size of the paper P, the driving frequency (hereinafter referred to as CLK) of the polygon motor is changed. If the polygon drive CLK frequency before shrinkage, that is, the front side image formation is F0, and the polygon drive CLK frequency after shrinkage, that is, the back side image formation, is F, F = F0 × L / L ′ is set. Made.

  In addition, the pixel CLK frequency for controlling the laser beam is changed. When the pixel CLK frequency before contraction is f0 and the pixel CLK frequency after contraction is f, f = (L / L ′) × (W / W ′) × f0 is set. In this way, by changing the polygon drive CLK frequency and the pixel CLK frequency in response to the shrinkage of the paper size of the paper P, an image with the front and back resists matched can be obtained.

When the process linear velocity before contraction is V0, the interprocess gap before contraction is G0, the distance between units is the process gap G, and the process linear velocity is V, the polygon drive CLK frequency is changed from F0 to F. If you change it,
1. Apparent process linear velocity is V = V0 × F0 / F = V0 × L ′ / L
2. Interprocess gap G (pixel) = G0 × V0 / V = G0 × L / L ′
As shown, the apparent process linear velocity V changes. For this reason, the correction for the front / back variable speed is also required for the color misregistration correction amount corresponding to the inter-process gap G. Accordingly, the polygon mirror having surface phase adjustment performs surface phase control at the time of front / back switching. Here, the process linear velocity corresponds to the rotational speed of a photoconductor as an image forming body to be imaged.

  In relation to this type of image writing unit, Patent Document 1 discloses a laser beam scanning device. According to the laser beam scanning apparatus, the rotation phase control means is provided, and the rotation phase control means is configured to determine the position of the laser beam deflected by the reference polygon mirror and the position of the laser beam deflected by another polygon mirror. A control device that controls the rotation of other polygon mirrors by calculating a time difference and using a frequency that is out of phase by the calculated time difference with respect to the input frequency to the control device that controls the rotation of the reference polygon mirror. Each is input and the rotational phase between a plurality of polygon mirrors is controlled. By providing such a rotational phase control means, a laser beam scanning device that easily controls the direction of the mirror surface of a polygon mirror by using a motor rotation control circuit and a motor driver circuit that have been used conventionally is provided. It can be done.

JP 09-230273 A (page 4, FIG. 2)

  Incidentally, the color image forming apparatus according to the conventional example has the following problems. When a color image forming apparatus is configured by applying a laser beam scanning apparatus as disclosed in Patent Document 1, the magnification of the front and back is adjusted by changing the rotation speed and phase of a polygon motor. Since the phase of each color of the motor is shifted, it is necessary to control the phase of each color. However, the conventional phase control controls the phase by operating the polygon motor at a constant speed in one direction of acceleration or deceleration, so the time required for the polygon motor to rotate stably becomes longer, and the color image is faster. Could not be formed.

  Accordingly, the present invention solves the above-described problems, and when a color image is formed by adjusting the magnification of the image, the phase control time in the drive clock signal is reduced and the polygon motor rotates stably. An object of the present invention is to provide a color image forming apparatus capable of forming a color image at high speed and a control method thereof.

In order to solve the above-described problem, the color image forming apparatus according to claim 1 is configured to control the rotation speed of the polygon motor and the phase of the driving clock signal to adjust the magnification of the image to form a color image. Means for detecting a phase difference between a predetermined pseudo main scanning reference signal having a fixed period and a main scanning reference signal whose period varies by controlling the rotational speed and phase of the polygon motor; and the polygon based on the phase difference. In a color image forming apparatus having means for accelerating and decelerating the polygon motor by controlling the phase of the driving clock signal of the motor, a stable time in the acceleration and deceleration directions of the polygon motor with respect to a predetermined phase shift amount A determination method by comparing the phase difference reference value of equality with the phase difference between the pseudo main scanning reference signal and the main scanning reference signal. When the I by the determining means, when the phase difference is determined to the be more retardation reference value, reducing the division value of the reference clock signal that generates a drive clock signal of the polygon motor The rotational speed of the polygon motor is accelerated, the phase is shifted by a value obtained by subtracting the phase difference from a predetermined period in the pseudo main scanning reference signal, and the phase difference is smaller than the phase difference reference value. If it is determined, the frequency division value of the reference clock signal that generates the driving clock signal of the polygon motor is increased, the rotational speed of the polygon motor is reduced, and the phase is moved. And a phase control means.

According to the color image forming apparatus of the present invention, in the case of forming a color image by controlling the rotation speed of the polygon motor and the phase of the driving clock signal to adjust the magnification of the image, the determination means has a predetermined phase shift. Determination is made by comparing the phase difference reference value at which the stabilization time in the acceleration and deceleration directions of the polygon motor is equal to the amount and the phase difference between the pseudo main scanning reference signal and the main scanning reference signal. If it is determined that the phase difference is greater than or equal to the phase difference reference value , the phase control means decreases the frequency division value of the reference clock signal that generates the polygon motor drive clock signal, and reduces the rotation speed of the polygon motor. If it is determined that the phase is shifted by a value obtained by subtracting the phase difference from the predetermined period in the pseudo main scanning reference signal and the phase difference is determined to be smaller than the phase difference reference value, the polygon motor drive clock signal Is controlled so as to shift the phase by increasing the frequency division value of the reference clock signal that generates the signal, decelerating the rotation speed of the polygon motor . Therefore, the phase control time in the drive clock signal can be reduced.

In order to solve the above-mentioned problem, the color image forming apparatus control method according to claim 3 forms a color image by adjusting the magnification of the image by controlling the rotation speed of the polygon motor and the phase of the drive clock signal. In this case, a phase difference between a predetermined pseudo main scanning reference signal having a fixed period and a main scanning reference signal whose period varies by controlling the rotation speed and phase of the polygon motor is detected, and the phase difference is determined based on the phase difference. In a color image forming apparatus control method for accelerating and decelerating the polygon motor by controlling the phase of the driving clock signal of the polygon motor, the color image forming apparatus includes a determination unit and a phase control unit, and the determination unit includes: Phase difference reference value that makes the stabilization time in the acceleration and deceleration directions of the polygon motor equal for a predetermined amount of phase movement, pseudo main scanning reference signal, and main running Determined by comparing the magnitude of the phase difference between the reference signal, the phase control means if the determined phase difference is equal to or greater than the phase difference reference value, the reference clock signal that generates a drive clock signal of the polygon motor Decrease the frequency division value, accelerate the rotation speed of the polygon motor, calculate the phase shift by subtracting the phase difference from the predetermined period in the pseudo main scanning reference signal, and the determined phase difference is the phase difference reference If the value is smaller than the value, the frequency division value of the reference clock signal that generates the driving clock signal of the polygon motor is increased, the rotation speed of the polygon motor is reduced, and the phase is controlled to move. To do.

  According to the control method of the color image forming apparatus of the present invention, the phase in the drive clock signal is adjusted when forming the color image by controlling the rotation speed of the polygon motor and the phase of the drive clock signal to adjust the magnification of the image. The control time can be reduced. Therefore, the time until the polygon motor rotates stably is shortened, and a color image can be formed at high speed.

To solve the problems described above, the color image forming apparatus according to claim 5 resides in that in Claim 1, the drive clock signal in the deceleration than the phase control width of the drive clock signal definitive to accelerate the polygon motor phase Phase control width setting means for setting the control width to a large value is provided.

  According to the color image forming apparatus of the present invention, when forming a color image by controlling the rotation speed of the polygon motor and the phase of the drive clock signal to adjust the magnification of the image, the phase control width setting means The phase control width of the drive clock signal during motor acceleration and deceleration is set to a different value. For example, the phase control width is set to be larger when decelerating than when the polygon motor is accelerated. Accordingly, the difference in the phase control time in the drive clock signal during acceleration and deceleration can be reduced, so that the phase control time can be reduced.

In order to solve the above-described problem, a control method for a color image forming apparatus according to claim 6 is the method according to claim 3, wherein the color image forming apparatus includes a phase control width setting unit, and the phase control width setting unit includes: and is characterized in that setting the phase control width of the drive clock signal in the deceleration than the phase control width of the drive clock signal definitive to accelerate the polygon motor to a larger value.

  According to the color image forming apparatus control method of the present invention, when a color image is formed by controlling the rotation speed of the polygon motor and the phase of the driving clock signal to adjust the magnification of the image, Since the difference in the phase control time in the drive clock signal can be reduced, the phase control time can be reduced. Therefore, the time until the polygon motor rotates stably is shortened, and a color image can be formed at high speed.

According to the first color image forming apparatus and its control method according to the present invention, when forming a color image by adjusting the magnification of the control and picture images the phases of the rotational speed and the driving clock signal of the polygon motor, the polygon Phase control means for controlling the rotational speed and phase of the motor, the phase control means comprising a phase difference reference value for equalizing the stabilization time in the acceleration and deceleration directions of the polygon motor at a predetermined phase shift amount, and a pseudo main scanning reference If the phase difference determined by comparing the phase difference between the signal and the main scanning reference signal is equal to or greater than the phase difference reference value, the division value of the reference clock signal that generates the driving clock signal for the polygon motor , The rotational speed of the polygon motor is accelerated, the phase difference is calculated by subtracting the phase difference from the predetermined period in the pseudo main scanning reference signal, and the determined phase difference is If less than the retardation reference value, it increases the division value of the reference clock signal that generates a drive clock signal of the polygon motor, and reduces the rotation speed of the polygon motor, and controls to move the phase is there.

  With this configuration, the phase control time in the drive clock signal can be reduced. Therefore, the time until the polygon motor rotates stably is shortened, and a color image can be formed at high speed. As a result, the number of color image formations per unit time is increased and the productivity is improved.

According to the second color image forming apparatus and the control method thereof according to the present invention, when forming a color image by controlling the rotation speed of the polygon motor and the phase of the drive clock signal to adjust the magnification of the image, a control width setting means is for setting the phase control width of the drive clock signal in the deceleration than the phase control width of the drive clock signal definitive to accelerate the polygon motor to a larger value.

  With this configuration, the difference in phase control time in the drive clock signal during acceleration and deceleration can be reduced, so that the phase control time can be reduced. Therefore, the time until the polygon motor rotates stably is shortened, and a color image can be formed at high speed. As a result, the number of color image formations per unit time is increased and the productivity is improved.

  Hereinafter, a color image forming apparatus and a control method thereof according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual diagram showing a configuration example of a color copying machine 100 as an embodiment of the present invention.
A color copying machine 100 shown in FIG. 1 is an example of a color image forming apparatus. When a color image is formed by adjusting the magnification of an image by controlling the rotation speed of a polygon motor and the phase of a driving clock signal, a fixed period is used. Means for detecting a phase difference between a predetermined pseudo main scanning reference signal having a main scanning reference signal whose period varies by controlling the rotational speed and phase of the polygon motor, and a driving clock signal of the polygon motor based on the phase difference. And means for controlling the phase to accelerate and decelerate the polygon motor.

  In addition to the color copying machine 100, the color image forming apparatus according to the present invention may be applied to a color printer, a facsimile machine, a complex machine of these, and the like.

  The color copying machine 100 includes a copying machine main body 101 and an image reading device 102. An image reading device 102 including an automatic document feeder 201 and a document image scanning exposure device 202 is installed on the upper part of the copying machine main body 101. The document 30 placed on the document table of the automatic document feeder 201 is conveyed by a conveying means, and one or both sides of the document are scanned and exposed by the optical system of the document image scanning exposure device 202 to reflect the document image. Incident light is read by the line image sensor CCD.

  The analog image signal photoelectrically converted by the line image sensor CCD is subjected to analog processing, A / D conversion, shading correction, image compression processing, and the like in image processing means (not shown), and becomes digital image data Din. The image data Din is converted into image data Dy, Dm, Dc, Dk for Y, M, C, BK colors, and then image writing units (image writing units) 3Y, 3M, 3C constituting the image forming means 60. , 3K.

  The automatic document feeder 201 described above reads the contents of a large number of documents 30 fed from the document placement table all at once, and stores the document contents in a storage means (electronic RDH function). ). This electronic RDH function is conveniently used when copying the contents of a large number of originals by the copying function or when transmitting a large number of originals 30 by the facsimile function.

  The copying machine main body 101 constitutes a tandem type color image forming apparatus, and includes four image forming units (image forming systems) 10Y, 10M, 10C, and 10K, an endless intermediate transfer belt 6, and a refeed mechanism. A sheet feeding / conveying unit including (ADU mechanism), a fixing device 17 for fixing a toner image, and a sheet feeding unit 20 for feeding a transfer material (hereinafter referred to as a sheet) P to an image forming system are provided. The paper feeding unit 20 is provided below the image forming system. The sheet feeding means 20 is composed of, for example, three sheet feeding trays 20A, 20B, and 20C. The paper P fed out from the paper supply unit 20 is conveyed under the image forming unit 10K.

  The image forming units 10Y, 10M, 10C, and 10K constitute an image forming means 60. Each of the image forming units 10Y, 10M, 10C, and 10K includes a polygon mirror and a photosensitive drum for each color, and includes a main scanning reference signal (hereinafter referred to as an index signal) and a pseudo main scanning reference signal (hereinafter referred to as an indexing main scanning reference signal) A color image is formed on a predetermined sheet P based on a pseudo index signal). For example, the image forming unit 10Y includes a polygon mirror 42Y and a photosensitive drum (image forming body) 1Y, the image forming unit 10M includes a polygon mirror 42M and a photosensitive drum 1M, and the image forming unit 10C includes a polygon. The image forming unit 10K includes a mirror 42C and a photosensitive drum 1K.

  In this example, an image forming unit 10Y that forms a yellow (Y) image includes a photosensitive drum 1Y that forms a Y-color toner image, and a Y-color charging unit disposed around the photosensitive drum 1Y. 2Y, image writing unit 3Y, developing means 4Y, and image forming body cleaning means 8Y.

  An image forming unit 10M that forms a magenta (M) color image includes a photosensitive drum 1M that forms an M color toner image, an M color charging unit 2M, an image writing unit 3M, a developing unit 4M, and an image forming unit. Cleaning means 8M. An image forming unit 10C for forming a cyan (C) color image includes a photosensitive drum 1C for forming a C color toner image, a charging unit 2C for C color, an image writing unit 3C, a developing unit 4C, and an image forming body. Cleaning means 8C. The image forming unit 10K that forms a black (BK) color image includes a photosensitive drum 1K that forms a BK color toner image, a charging unit 2K for BK color, an image writing unit 3K, a developing unit 4K, and an image forming unit. Cleaning means 8K.

  The charging unit 2Y and the image writing unit 3Y, the charging unit 2M and the image writing unit 3M, the charging unit 2C and the image writing unit 3C, and the charging unit 2K and the image writing unit 3K constitute a latent image forming unit. Development by the developing means 4Y, 4M, 4C, and 4K is performed by reversal development in which a developing bias in which an AC voltage is superimposed on a DC voltage having the same polarity (negative polarity in this embodiment) as the polarity of the toner to be used is applied. . The intermediate transfer belt 6 is wound around a plurality of rollers, and is rotatably supported. Each of the Y, M, C, and BK colors formed on the respective photosensitive drums 1Y, 1M, 1C, and 1K. A toner image is transferred.

  Here, an outline of the image forming process will be described below. Each color image formed by the image forming units 10Y, 10M, 10C and 10K has a primary transfer roller 7Y to which a primary transfer bias (not shown) having a polarity opposite to that of the toner to be used (positive polarity in this embodiment) is applied. , 7M, 7C and 7K are sequentially transferred onto the rotating intermediate transfer belt 6 (primary transfer), and the color toner images are superposed (synthesized) to form a color image (color image). The color image is transferred from the intermediate transfer belt 6 to the paper P.

  The paper P stored in the paper feed trays 20A, 20B, and 20C is fed by the feed roller 21 and the paper feed roller 22A provided in the paper feed trays 20A, 20B, and 20C, respectively, and the transport rollers 22B, 22C, and 22D, After passing through the registration rollers 23 and 28 and the like, the sheet is conveyed to the secondary transfer roller 7A, and the color image is collectively transferred to one surface (front surface) on the paper P (secondary transfer).

  The paper P on which the color image has been transferred is fixed by the fixing device 17, is sandwiched between the paper discharge rollers 24, and is placed on a paper discharge tray 25 outside the apparatus. The transfer residual toner remaining on the peripheral surfaces of the photosensitive drums 1Y, 1M, 1C, and 1K after the transfer is cleaned by the image forming body cleaning means 8Y, 8M, 8C, and 8K and enters the next image forming cycle.

  At the time of double-sided image formation, the paper P formed on one side (front surface) and discharged from the fixing device 17 is branched off from the sheet discharge path by the branching unit 26, and constitutes a sheet feeding and conveying unit. After passing through the circulation sheet passing path 27A, the front and back are reversed by a reversing conveyance path 27B which is a refeed mechanism (ADU mechanism), passes through the refeed conveyance section 27C, and merges at the sheet feeding roller 22D. The reversely conveyed paper P is conveyed again to the secondary transfer roller 7A through the registration rollers 23 and 28, and a color image (color toner image) is collectively transferred onto the other surface (back surface) of the paper P.

  The paper P on which the color image has been transferred is fixed by the fixing device 17, is sandwiched between the paper discharge rollers 24, and is placed on a paper discharge tray 25 outside the apparatus. On the other hand, after the color image is transferred onto the paper P by the secondary transfer roller 7A, the residual toner is removed by the intermediate transfer belt cleaning means 8A from the intermediate transfer belt 6 that has separated the curvature of the paper P.

  In forming these images, the paper P is a thin paper of about 52.3 to 63.9 kg / m 2 (1000 sheets), a plain paper of about 64.0 to 81.4 kg / m 2 (1000 sheets), 83.0 A thick paper of about ˜130.0 kg / m 2 (1000 sheets) or a super thick paper of about 150.0 kg / m 2 (1000 sheets) is used. The thickness of the paper P (paper thickness) is about 0.05 to 0.15 mm.

  The copying machine main body 101 is provided with a control means 15, and when an image is formed on both sides of a predetermined sheet P, an index signal whose cycle is changed when the rotational speed of the polygon mirror 42Y or the like is changed and when the phase is controlled, Image formation control on a predetermined surface of the paper P is executed based on a plurality of pseudo index signals having a fixed period with respect to the index signal.

  FIG. 2 is a block diagram illustrating a configuration example of a control system of the color copying machine 100. The color copying machine 100 shown in FIG. 2 has a control unit 15 that determines an image forming start timing on a predetermined surface of the paper P based on two or more pseudo index signals. The control unit 15 is connected to the pseudo index creation circuit 12, the image memory 13, the image processing unit 16, the communication unit 19, the paper feeding unit 20, the operation panel 48, the image forming unit 60, and the image reading device 102.

  The control unit 15 includes a ROM (Read Only Memory) 53, a work RAM (Random Access Memory) 54, and a CPU (Central Processing Unit) 55. The ROM 53 stores system program data for controlling the entire copying machine, data for controlling the rotation speed of the polygon mirror 42Y, and a threshold value Dw as an example of a phase difference reference value for shifting the phase of the polygon mirror 42Y. Is done. The RAM 54 temporarily stores control commands when various modes are executed.

  When the power is turned on, the CPU 55 reads the system program data from the ROM 53, starts the system, and controls the entire copying machine. When forming a color image on the predetermined paper P, the CPU 55 determines the paper P based on an index signal whose period varies due to rotation speed control and phase control of the polygon mirror 42Y and the like and a pseudo index signal having a fixed period. Color image formation control on a predetermined surface is executed. For example, the CPU 55 determines an image forming start trigger (VTOP) signal in the color image forming process from the front surface to the back surface of the paper P based on a single pseudo index signal.

  Although not shown, the operation panel 48 is connected to the control means 15 and includes an operation means 14 configured from a touch panel and a display means 18 configured from a liquid crystal display panel. The operation panel 48 uses GUI (Graphic User Interface) type input means. A power switch and the like are provided on the operation panel 48. For example, the display unit 18 performs a display operation in conjunction with the operation unit 14.

  The operation panel 48 is operated when selecting image forming conditions and the paper feed trays 20A to 20C. For example, when selecting the type (paper type) of paper P such as plain paper, recycled paper, coated paper, or OHT paper, or when selecting the paper feed trays 20A to 20C in which the paper P is stored, the operation means 14 Is operated to set image forming conditions. Note that image forming conditions, paper feed tray selection information, and the like set on the operation panel 48 are output to the CPU 55 as operation data D3.

  The above-described control unit 15 executes color image formation control on a predetermined surface of the paper P based on the operation data D3 output from the operation unit 14 or information received via the communication unit 19. For example, the control unit 15 executes the image size of the front and back of the paper P and the front and back alignment processing of the paper P corresponding to the set type of the paper P or the set paper feed trays 20A to 20C.

  The image reading means 102 is connected to the control means 15 and outputs to the control means 15 digital color image data Din (R, G, and B color component data) obtained by reading an image from the original 30 shown in FIG. To be made. The control means 15 stores the image data Din in the image memory 13. The image processing means 16 reads the image data Din from the image memory 13, and converts the R, G, B color component data into Y color image data Dy, M color image data Dm, C color image data Dc, BK. Color conversion processing is performed on the color image data Dk. The Y, M, C, and K color image data Dy, Dm, Dc, and Dk after the color conversion process are stored in the image memory 13 or an image memory for Y, M, C, and K colors (not shown). The

  The communication means 19 is connected to a communication line such as a LAN, and is used when performing communication processing with an external computer or the like. When the color copying machine 100 is used as a printer, the communication means 19 is used to receive print data Din 'from an external computer in the print operation mode. The print data Din ′ includes image forming conditions, paper feed tray selection information, and the like. The paper feed means 20 is connected to a motor (not shown) for driving the paper feed trays 20A to 20C, controls the rotation of the motor based on the paper feed control signal Sf, and from the paper feed trays 20A, 20B or 20C. It operates so as to convey the fed paper P to the image forming system. The paper feed control signal Sf is supplied from the control means 15 to the paper feed means 20.

  The image forming unit 60 includes Y, M, C, and K color image writing units 3Y, 3M, 3C, and 3K, and Y, M, C, and K color image memories are used. , K color image data Dy, Dm, Dc, and Dk are input, and an image is formed on a predetermined surface of the paper P based on Y, M, C, and K color index signals and pseudo index signals. Operate. The image data Dy, Dm, Dc, and Dk for Y, M, C, and K colors may be received from an external computer or the like via the communication unit 19.

  The pseudo index creating circuit 12 is connected to the control means 15. The pseudo index creating circuit 12 is a reference signal for forming a color image, and an index signal (slave index signal; hereinafter referred to as an IDX signal) whose cycle varies when the rotational speed of the polygon mirror 42Y or the like is changed and when the phase is controlled. The first and second pseudo index signals whose predetermined period can be arbitrarily set are generated. Hereinafter, the first pseudo index signal (first master index signal) is referred to as an MST-IDX1 signal, and the second pseudo index signal (second master index signal) is referred to as an MST-IDX2 signal.

  In this example, the pseudo index creation circuit 12 includes, for example, a first MST-IDX1 signal having a first period and a second MST-IDX2 signal having a second period shorter than the first period. And create. If the MST-IDX2 signal is used to form an image on the back side of the paper P, the image size can be matched between the front and back sides of the paper P even if the paper P shrinks after the front surface image is formed.

  An IDX signal exists for each color. The YIDX signal is a reference signal for controlling the rotational speed and phase of the polygon mirror 42Y for Y color to scan the laser beam on the photosensitive drum 1Y. By detecting the laser beam reflected by the polygon mirror 42Y, the YIDX signal is detected. This is the signal obtained. The MIDX signal is a reference signal for scanning the photosensitive drum 1M with a laser beam by controlling the rotational speed and phase of the polygon mirror 42M for M color, and by detecting the laser beam reflected from the polygon mirror 42M. This is the signal obtained. The CIDX signal is a reference signal for controlling the rotational speed and phase of the C-color polygon mirror 42C to scan the photosensitive drum 1C with the laser beam. By detecting the laser beam reflected by the polygon mirror 42C, the CIDX signal is detected. This is the signal obtained. The KIDX signal is a reference signal for scanning the photosensitive drum 1M with a laser beam by controlling the rotational speed and phase of the polygon mirror 42K for K color, and by detecting the laser beam reflected by the polygon mirror 42K. This is the signal obtained.

  The control unit 15 includes a ROM 53, a RAM 54, and a CPU 55. In this example, the pseudo index creation circuit 12 creates MST-IDX1 and MST-IDX2 signals, and the CPU 55 determines the other side of the sheet P1 based on the MST-IDX1 signal and the MST-IDX2 signal, or Then, the image forming start timing on one side of the next sheet P2 is determined. For example, based on the MST-IDX1 and MST-IDX2 signals and the detection of the leading edge of the paper P, the CPU 55 starts an image formation start trigger (VTOP) signal on the back surface of the paper P1, and starts image formation on the front surface of the paper P2 of the next page. A trigger (VTOP) signal is raised.

  When the CPU 55 forms an image on both sides of a predetermined paper P, the CPU 55 alternately selects the MST-IDX1 signal and the MST-IDX2 signal and based on the MST-IDX1 signal or the MST-IDX2 signal and the IDX signal. Color image formation control on a predetermined surface of P is executed. For example, when performing image forming processing in the image writing units 3Y, 3M, 3C, and 3K, the CPU 55 alternately selects the MST-IDX1 signal and the MST-IDX2 signal, and then sets the leading edge of the paper P to the MST-IDX1. By detecting based on the signal or the MST-IDX2 signal, a VTOP (imaging start trigger) signal is generated. Thereby, for example, when forming color images on the front and back surfaces of the paper, even if the paper P shrinks after the front surface image is formed, the image size can be matched between the front surface and the back surface of the paper P.

  In this example, the pseudo index creating circuit 12 is connected to a crystal oscillator 11 as an example of a signal source, and the crystal oscillator 11 generates a reference clock signal (hereinafter referred to as a CLK1 signal). The CLK1 signal is output to each of the pseudo index creation circuit 12 and the image writing units 3Y, 3M, 3C, and 3K for Y, M, C, and K colors.

  FIG. 3 is a block diagram showing a configuration example of the Y color image writing unit 3Y extracted from FIG. 2 and its peripheral circuits. The image writing unit 3Y for Y color shown in FIG. 3 is connected to the crystal oscillator 11, the pseudo index creation circuit 12, and the CPU 55.

  The pseudo index creation circuit 12 operates to create an MST-IDX1 signal and an MST-IDX2 signal based on a CLK1 signal for creating a polygon drive clock signal for Y color (hereinafter referred to as a YP-CLK signal). The CLK1 signal is output from the crystal oscillator 11 to the pseudo index creation circuit 12 and the polygon drive CLK generation circuit 39Y.

  Here, when the cycle of the YP-CLK (polygon drive clock) signal is Tp, the cycle of the MST-IDX1 signal and the MST-IDX2 signal is Ti, and the natural numbers are n and m, one cycle of the polygon drive clock signal and MST -The relationship between one cycle of the IDX1 signal and the MST-IDX2 signal is set to Tp × n = Ti × m (where n ≦ m). In this example, the pseudo index creation circuit 12 creates an MST-IDX1 signal and an MST-IDX2 signal by performing signal processing on the CLK1 signal obtained from the crystal oscillator 11 so as to satisfy the above-described setting conditions.

  The polygon drive CLK generation circuit 39Y constitutes an example of a determination unit, a phase control unit, and a phase control width setting unit, compares the threshold value Dw provided by the CPU 55 with the detected phase difference, and determines the phase of the polygon motor 36. To control. Further, the phase control width in the YP-CLK signal of the polygon motor 36 is set to a different value for acceleration and deceleration.

  Further, the polygon drive CLK generation circuit 39Y generates a YP-CLK signal by performing signal processing on the CLK1 signal so as to satisfy the above-described setting condition. In this way, the crystal oscillator 11 can be used in common, and the MST-IDX1 signal and the MST-IDX2 signal having the same period as that of the YIDX signal actually created can be created.

  The pseudo index creating circuit 12 is connected to the CPU 55 and outputs a selection control signal SS1 to the polygon drive CLK generation circuit 39Y based on the sequence program. The selection control signal SS1 is set before the start of phase control of the polygon mirror 42Y and the like. Similarly, the CPU 55 outputs the selection control signal SS2 to the Y-VV creation circuit 41Y based on the sequence program. The selection control signal SS2 is set before an image leading edge signal (hereinafter referred to as a VTOP signal) for instructing the back side image formation. The VTOP signal is a signal for adjusting the conveyance timing of the paper P and the image formation timing.

  The selection control signals SS1 and SS2 described above indicate the first selection at a low level (hereinafter referred to as “L” level), and indicate the selection for the back surface at a high level (hereinafter referred to as “H” level). In this way, the CPU 55 can control the frequency of the YP-CLK signal supplied to the polygon motor 36 for Y color independently for each of the other M, C, and BK color image forming units 10M, 10C, and 10K. become.

  The image writing unit 3Y includes, for example, a crystal oscillator 31, an image CLK generation circuit 32, a horizontal synchronization circuit 33, a PWM signal generation circuit 34, a laser (LD) drive circuit 35, a polygon motor 36, a motor drive circuit 37, an index sensor 38, A polygon drive CLK generation circuit 39Y, a timing generator 40, and a Y-VV (Valid) generation circuit 41Y are included.

  An image CLK generation circuit 32 is connected to the crystal oscillator 31, and a reference clock signal (hereinafter referred to as a CLK 2 signal) is oscillated and output to the image CLK generation circuit 32. The image CLK generation circuit 32 operates to generate a Y-color pixel clock signal (hereinafter referred to as a G-CLK signal) based on the frequency control signal Sg output from the CPU and output it to the horizontal synchronization circuit 33. For example, a value obtained by multiplying the frequency f0 of the G-CLK signal at the time of front surface image formation by (L / L ′) · (W / W ′) is set as the Y-color pixel CLK frequency f at the time of back surface image formation.

  The horizontal synchronization circuit 33 is connected to the image CLK generation circuit 32 and the PWM signal generation circuit 34, detects the horizontal synchronization signal Sh based on the YIDX signal, and outputs it to the PWM signal generation circuit 34. The Y-color index sensor 38 detects the laser beam from the polygon mirror 42Y, outputs the detected laser beam as a YIDX signal to the horizontal synchronization circuit 33, and outputs it to the polygon drive CLK generation circuit 39Y.

  Further, the PWM signal generation circuit 34 inputs Y-color image data Dy from the Y-color image memory 83, performs pulse width modulation on the image data Dy, and supplies the Y-color laser drive signal Sy to the LD drive circuit 35. Output to. An LD drive circuit 35 is connected to the PWM signal generation circuit 34 described above. A laser diode (not shown) is connected to the LD drive circuit 35. The LD drive circuit 35 drives the laser diode based on the laser drive signal Sy, generates a Y-color laser beam LY having a predetermined intensity, and radiates it toward the polygon mirror 42Y.

  A timing signal generator 40 for determining the image forming start timing for Y color is connected to the pseudo index creating circuit 12. The timing signal generator 40 is further connected to the CPU 55. For example, the MST-IDX1 signal output from the pseudo index creating circuit 12 based on the VTOP signal and selection control signal SS2 output from the CPU 55 at the time of surface imaging. Is selected, and the number of pulses of the MST-IDX1 signal is counted, and the image forming start timing for the Y color on the paper surface is determined based on the number of pulse counts. With the determination of the Y color image formation start timing, an image formation start signal (hereinafter referred to as an STT signal) is output to the Y-VV creation circuit 41Y.

  The Y-VV creation circuit 41Y counts the number of pulses of the YIDX signal based on the STT signal output from the timing signal generator 40, and based on the pulse count number, Y-color sub-scanning on the front side or the back side of the paper An effective area signal (hereinafter referred to as YVV signal) is created. The YVV signal is output to the image memory 83 for Y color.

  The above-described PWM signal generation circuit 34 is connected to a Y-color image memory 83, and reads Y-color image data Dy based on the YVV signal when forming images on the front and back sides of the paper. As the image data Dy, R, G, B color image data is read from the image memory 13 shown in FIG. 2 by the image processing means 16, and the R, G, B color image data is subjected to color conversion processing. This is one of the Y, M, C, and BK color image data.

  Further, a polygon drive CLK generation circuit 39Y is connected to the crystal oscillator 11, the pseudo index generation circuit 12, and the CPU 55, and a YIDX signal, a CLK1 signal, an MST-IDX1 signal, an MST-IDX2 signal, a speed setting signal Sv, and a selection control signal. Based on SS1, it operates to generate a polygon drive clock signal (YP-CLK signal) for Y color.

  The speed setting signal Sv and the selection control signal SS1 are output from the CPU 55 to the polygon drive CLK generation circuit 39Y when the front and back surfaces are switched. Further, when switching between the front and back surfaces, the CPU 55 acquires the threshold value Dw from the ROM 53, for example, and outputs it to the polygon drive CLK generation circuit 39Y. The YIDX signal is output from the index sensor 38 to the polygon drive CLK generation circuit 39Y. The CLK1 signal is output from the crystal oscillator 11 to the polygon drive CLK generation circuit 39Y. The MST-IDX1 signal and the MST-IDX2 signal are output from the pseudo index generation circuit 12 to the polygon drive CLK generation circuit 39Y. An example of the internal configuration of the polygon drive CLK generation circuit 39Y will be described with reference to FIG.

  A motor drive circuit 37 is connected to the polygon drive CLK generation circuit 39Y. The motor drive circuit 37 is connected to the polygon motor 36 and drives the polygon motor 36 based on the YP-CLK signal. A polygon mirror 42Y is attached to the polygon motor 36, and operates to rotate in the main scanning direction by the driving force of the polygon motor 36.

  The laser beam LY radiated from a diode (not shown) by the LD driving circuit 35 is main-scanned by rotating the polygon mirror 42Y with respect to the photosensitive drum 1Y shown in FIG. 1 rotating in the sub-scanning direction. The electrostatic latent image is written on the photosensitive drum 1Y. The electrostatic latent image written on the photosensitive drum 1Y is developed by a Y-color toner member. The Y color toner image on the photosensitive drum 1Y is transferred to the intermediate transfer belt 6 that rotates in the sub-scanning direction (primary transfer).

  The image writing units 3M, 3C, and 3K for other colors have the same configuration and functions, and thus description thereof is omitted. In this example, the crystal oscillator 31, the image CLK generation circuit 32, the horizontal synchronization circuit 33, the PWM signal generation circuit 34, the polygon drive CLK generation circuit 39Y, the timing generator 40, and the Y-VV generation circuit 41Y are included in the image writing unit 3Y. However, the present invention is not limited to this, and these circuit elements may be included in the image processing means 16 or the control means 15.

  In that case, the CPU 55 is provided with the function of the timing generator 40, and at the time of image formation on the paper, the image leading edge signal VTOP is raised based on the MST-IDX1 signal, and the number of pulses of the MST-IDX1 signal is calculated based on this VTOP signal. Counting may be performed to determine the first Y-color image formation start timing on the paper surface based on the pulse count. Based on the STT signal (image formation start signal) determined here, the number of pulses of the Y color YIDX signal is counted, and based on the number of pulse counts, the Y color YVV signal on the paper surface is created. The image writing unit 3Y and the like are controlled.

  At the time of image formation on the back side of the paper, the CPU 55 raises the image leading edge signal VTOP based on the MST-IDX2 signal, counts the number of pulses of the MST-IDX2 signal based on the VTOP signal, and based on the pulse count number The first Y image forming start timing on the back side of the sheet is determined.

  The CPU 55 counts the number of pulses of the YIDX signal for each color based on the determined image formation start timing, and generates a YVV signal for Y color on the back side of the paper based on the number of pulse counts. 12. The input / output of the image writing unit 3Y and the like may be controlled.

  In this example, the CPU 55 selects one of the MST-IDX1 signal and the MST-IDX2 signal for each color when performing phase control on the polygon mirror 42Y and the like separately from the YVV signal creation control. Thereafter, phase control of the polygon mirror 42Y and the like may be executed based on the MST-IDX1 signal or the MST-IDX2 signal.

  FIG. 4 is a block diagram showing a configuration example in which the polygon driving CLK generation circuit 39Y for Y color and its peripheral circuits are extracted.

  The pseudo index creation circuit 12 and the polygon drive CLK generation circuit 39Y shown in FIG. 4 are connected to the CPU 55 and to the crystal oscillator 11. The CPU 55 is connected to the Y-VV generation circuit via the timing signal generator 40. 41Y etc. are connected.

  The pseudo index creating circuit 12 includes, for example, a PLL & frequency dividing circuit 71 and a first pseudo index generating circuit 72, a PLL & frequency dividing circuit 73, and a second pseudo index generating circuit 74.

  The PLL & frequency dividing circuit 71 is connected to the crystal oscillator 11, divides the CLK1 signal output from the oscillator 11 based on the speed setting signal Sv1, and simulates a master frequency-divided clock signal (hereinafter referred to as MST-CK1 signal). It operates to output to the index generation circuit 72. The pseudo index generation circuit 72 is connected to the PLL & frequency dividing circuit 71 and the CPU 55, and outputs a speed setting signal Sv 1 for generating an MST-CK1 signal to the PLL & frequency dividing circuit 71 based on the speed setting signal Sv output from the CPU 55. Control the oscillation. By this oscillation control, the pseudo index generation circuit 72 operates to generate the MST-IDX1 signal of the first period based on the MST-CK1 signal.

  The PLL & frequency dividing circuit 73 is also connected to the crystal oscillator 11, divides the CLK1 signal output from the oscillator 11 based on the speed setting signal Sv2, and simulates a master frequency-divided clock signal (hereinafter referred to as MST-CK2 signal). It operates to output to the index generation circuit 74. The pseudo index generation circuit 74 is connected to the PLL & frequency dividing circuit 73 and the CPU 55, and outputs a speed setting signal Sv2 for generating an MST-CK2 signal based on the speed setting signal Sv output from the CPU 55 to the PLL & frequency dividing circuit 73. The oscillation is controlled. By this oscillation control, the pseudo index generation circuit 74 operates to generate the MST-IDX2 signal of the second period based on the MST-CK2 signal.

  The polygon drive CLK generation circuit 39Y includes a Y-PLL & frequency dividing circuit 61 and a Y-polygon phase control circuit 62. The Y-PLL & frequency dividing circuit 61 divides the CLK1 signal output from the crystal oscillator 11 based on the speed setting signal Svy output from the Y-polygon phase control circuit 62, and divides the frequency-divided clock signal (hereinafter referred to as Y-). CK signal) is output to the Y-polygon phase control circuit 62.

  The Y-polygon phase control circuit 62 is connected to the CPU 55 and the Y-PLL & frequency dividing circuit 61 and outputs a speed setting signal Sv for generating a Y-CK signal based on the speed setting signal Sv and the selection control signal SS1 output from the CPU 55. Output to the Y-PLL & frequency dividing circuit 61 to control its oscillation. For example, when the CPU 55 shifts from the front surface image formation to the back surface image formation, the speed setting signal Sv is referred to the Y-polygon phase control circuit 62 by referring to the data for speed transfer from the N frequency division data tables in the ROM 53. Operates to supply.

The Y-polygon phase control circuit 62 has a determination means, and a threshold value Dw at which the stabilization time in the acceleration and deceleration directions of the polygon motor 36 is equal to the phase movement amount of one surface of the polygon mirror 42Y, for example, The magnitude difference is determined by comparing the phase difference between the MST-IDX2 signal and the YIDX signal. The Y-polygon phase control circuit 62 has phase control means, and controls the phase by accelerating and decelerating the rotational speed of the polygon motor 36 based on the determination result.

  Here, the threshold value Dw is set as follows. First, the time required for accelerating the polygon motor 36 to move the phase movement amount for one surface of the polygon mirror 42Y and the time required for decelerating the polygon motor 36 and moving the phase movement amount for one surface of the polygon mirror 42Y are required. Time is measured. Next, the stabilization time in the acceleration and deceleration directions is set to be equal from each measured time.

  In the Y-polygon phase control circuit 62 in which the threshold value Dw is set, when the phase difference is equal to or larger than the threshold value Dw, the frequency division value of the CLK1 signal that generates the YP-CLK signal of the polygon motor 36 is decreased. When the rotational speed of the polygon motor 36 is accelerated to shift the phase by a value obtained by subtracting the phase difference from a predetermined period in the MST-IDX2, and the phase difference is smaller than the threshold value Dw, the YP-CLK of the polygon motor 36 Control is performed to increase the frequency division value of the CLK1 signal generating the signal, decelerate the rotational speed of the polygon motor 36, and move the phase. Thereby, the phase control time in the YP-CLK signal can be reduced.

  The Y-polygon phase control circuit 62 has phase control width setting means, and sets the phase control width Dx of the YP-CLK signal for acceleration and deceleration of the polygon motor 36 to different values. For example, the phase control width Dx is set so that it is greater during deceleration than when the polygon motor 36 is accelerated. As a result, the phase control time difference in the YP-CLK signal during acceleration and deceleration can be reduced, so that the phase control time can be reduced.

  Further, when the CPU 55 determines that the front surface image formation by the image writing unit 3Y has been completed, the value obtained by multiplying the polygon drive CLK frequency of the YP-CLK signal at the time of front surface image formation by L / L ′ is the value at the time of back surface image formation. The polygon drive CLK frequency of the YP-CLK signal is set, and a speed setting signal (frequency control signal) Sv is output to the polygon drive CLK generation circuit 39Y.

  The Y-polygon phase control circuit 62 is based on the rising edge of the YIDX signal detected by the index sensor 38 and the rising edge of either MST-IDX1 or MST-IDX2 selected by the selection control signal SS1. A phase difference is detected, and phase control of the YP-CLK signal is performed based on this phase difference.

  Thereby, in the polygon drive CLK generation circuit 39Y, for example, a YP-CLK signal for backside image formation is generated according to the speed setting signal Sv output from the CPU 55, and the YP-CLK signal whose frequency and phase are adjusted is illustrated. It operates to output to the polygon motor 36 in the image writing unit 3Y.

  Although not shown, processing is similarly performed for the M-image writing unit 3M, the C-image writing unit 3C, and the K-image writing unit 3K.

  FIGS. 5A to 5H are time charts showing an operation example when adjusting the Y-color front / back magnification.

  In FIG. 5F, the MST-IDX1 signal or the MST-IDX2 signal, for example, is used alternately as the reference IDX signal during phase control of the polygon mirror 42Y or the like. The MST-IDX2 signal is used as a reference IDX signal for phase control of the polygon mirror 42Y and the like during back surface image formation.

  In the image writing unit 3Y and the like, phase control is executed with reference to the pseudo MST-IDX1 signal and MST-IDX2 signal. The Y color STT signal (image formation start signal) at the time of surface image formation is latched by the MST-IDX1 signal, and is input to the Y-VV creation circuit 41Y of the image writing unit 3Y. Determine the start timing of the signal. Based on this Y color STT signal (image forming start signal), the YIDX signal of the image writing unit 3Y is counted to create a YVV signal. Hereinafter, the operation at the time of front / back switching will be described.

  Under these operating conditions, at time t1 shown in FIG. 5H, in synchronization with the MST-IDX1 signal, the VTOP signal (image leading edge signal) indicating surface image formation rises in FIG. A signal is output from the CPU 55 to the timing signal generator 40, the Y-VV generation circuit 41Y, and the like.

  Thereafter, the timing signal generator 40 counts the number of pulses of the MST-IDX1 signal shown in FIG. 5 (H), and at time t2, the STT signal for Y color (hereinafter referred to as SST-Y signal) shown in FIG. 5 (D). ) Stand up. This STT-Y signal is an image formation start signal that instructs the start of surface image formation of the Y color image forming unit 10Y. The STT-Y signal falls at time t3, and the Y-VV generation circuit 41Y counts the number of pulses of the MST-IDX1 signal based on the STT-Y signal. The Y-VV generation circuit 41Y To raise the YVV signal.

  The CPU 55 detects the fall of the YVV signal at time t5, and raises the selection control signal SS1 to “H” level at time t6 shown in FIG. This “H” level selection control signal SS1 is output from the CPU 55 to the polygon drive CLK generation circuit 39Y and the like.

  When the Y color image formation is completed at time t5 and the YVV signal shown in FIG. 5E falls, the image writing unit 3Y performs the Y color image formation on the back side of the paper in FIG. The rotational speed is changed based on the YIDX signal shown, and then the phase change control described in FIGS. 9 and 10 is performed.

  At time t7, the CPU 55 outputs the selection control signal SS2 to the timing signal generator 40 based on the sequence program. At time t8, the CPU 55 detects that the phase change control is completed, and at the same time, raises the paper back surface image formation signal (VTOP signal) based on the MST-IDX2 signal, and based on this VTOP signal, the MST-IDX2 signal The number of pulses is counted, the image forming start timing on the back side of the paper is determined based on the pulse count number, and the image forming process on the back side of the paper is performed from this image forming start timing.

  The CPU 55 operates so as to supply the speed setting signal Sv to the Y-PLL & frequency dividing circuit 61 by referring to the data for speed transition from the N frequency-divided data tables in the ROM 53 at the time of front / back switching. For example, when the CPU 55 determines that the front surface image formation by the image writing unit 3Y has been completed, the value obtained by multiplying the polygon drive CLK frequency of the YP-CLK signal at the time of front surface image formation by L ′ / L is the value at the back side image formation time. The polygon drive CLK frequency of the YP-CLK signal is set, and a speed setting signal (frequency control signal) Sv is output to the polygon drive CLK generation circuit 39Y.

  In the polygon drive CLK generation circuit 39Y, for example, a YP-CLK signal for back side image generation is generated according to the speed setting signal Sv output from the CPU 55, and the YP-CLK signal whose frequency and phase are adjusted is used as the image writing unit 3Y. It operates so as to output to the motor drive circuit 37 in the inside. The motor drive circuit 37 drives the polygon motor 36 based on the YP-CLK signal. The polygon motor 36 operates to rotate the polygon mirror 42Y. The laser diode connected to the LD driving circuit 35 radiates a laser beam LY, and the laser beam LY is main-scanned by rotating the polygon mirror 42Y with respect to the photosensitive drum 1Y rotating in the sub-scanning direction. The By this main scanning, an electrostatic latent image is written on the photosensitive drum 1Y. The electrostatic latent image written on the photosensitive drum 1Y is developed by a Y-color toner member. The Y color toner image on the photosensitive drum 1Y is transferred to the intermediate transfer belt 6 that rotates in the sub-scanning direction (primary transfer).

  The CPU 55 supplies the frequency control signal Sg to the pixel CLK generation circuit 32 at the time of front / back switching, and the pixel CLK generation circuit 32 generates a G-CLK signal (Y color pixel clock signal) based on the frequency control signal Sg. So as to output to the horizontal synchronizing circuit 33. For example, a value obtained by multiplying the frequency f0 of the G-CLK signal at the time of front surface imaging by (L ′ / L) · (W / W ′) is set as the Y-color pixel CLK frequency f at the time of rear surface image formation. When the YVV signal shown in FIG. 5 (E) is output to the Y color image memory 83 or the like, the horizontal synchronization circuit 33 detects the horizontal synchronization signal Sh based on the YIDX signal and sends it to the PWM signal generation circuit 34. Operates to output. The YIDX signal shown in FIG. 5F is output to the polygon drive CLK generation circuit 39Y in addition to being output from the Y color index sensor 38 to the horizontal synchronization circuit 33. The PWM signal generation circuit 34 receives the horizontal synchronization signal Sh and the Y color image data Dy, performs pulse width modulation on the image data Dy, and outputs the Y color laser drive signal Sy to the LD drive circuit 35. Operate. The LD drive circuit 35 drives the laser diode based on the laser drive signal Sy, generates a Y-color laser beam LY having a predetermined intensity, and radiates it toward the polygon mirror 42Y.

  FIG. 6 is a graph showing an example of speed characteristics of the polygon motor 36 at the time of switching between front and back image formation.

  In FIG. 6, the horizontal axis is time t, and the vertical axis is the rotational speed V of the polygon mirror 42Y and the like. In this example, it is assumed that the rotation speed of the polygon mirror 42Y or the like at the time of image formation on the paper surface is V1, and the rotation speed of the polygon mirror 42Y or the like at the time of image formation on the paper back surface is V2. The relationship between the rotational speeds V1 and V2 is set to V2> V1.

  Therefore, for example, speed control that gradually increases the rotation speed can be executed when shifting from the first sheet surface image formation to the sheet rear surface image formation (hereinafter referred to as speed transition). In the drawing, the speed data at the time of speed transition indicated by a broken line circle is stored in the ROM 53 as a divided data table, and this divided data table is referred to. N types of frequency division data tables are prepared and stored in the ROM 53 shown in FIG. The frequency-divided data Dv is decoded by the CPU 55, for example, and is output to the Y-polygon phase control circuits 62, 64, 66, and 68 shown in FIG. 4 as the speed setting signal Sv.

  In addition, when the image formation on both sides of the first sheet is completed and both surfaces of the second sheet are formed, the process proceeds to the image formation on the second sheet surface from the time of image formation on the back side of the first sheet. Speed control is performed such that the rotational speed is gradually decreased. The frequency division data Dv at the time of speed transition in this case is also stored in the ROM 53 as a frequency division data table, and this frequency division data table is referred to. Thereby, the rotation speed of the polygon mirror 42Y and the like can be controlled at the time of switching the front and back image formation.

  7A to 7D are time charts showing examples of phase control in the Y-polygon phase control circuit 62 and the like. In FIG. 7, the horizontal axis represents time t, and the vertical axis represents the amplitude of a polygon drive clock signal (YP-CLK signal or the like). An example of inverting the phase by controlling the phase of the YP-CLK signal by increasing or decreasing the frequency division value (= 6CLK1 signal) of the YP-CLK signal in FIG.

  The YP-CLK signal shown in FIG. 7A is obtained by dividing the reference clock signal (CLK1 signal) shown in FIG. 7D by 6 (divided value = 6 CLK1 signal). That is, one cycle of the YP-CLK signal in FIG. 7A corresponds to six cycles of the CLK1 signal, and one cycle of the YP-CLK signal becomes the 6CLK1 signal. Similarly, one cycle of the YP-CLK signal obtained by dividing the CLK1 signal by n is the nCLK1 signal. The frequency of the YP-CLK signal shown in FIG. 7A is three frequencies from the start of the phase change at t1 to the end of the phase change at t2.

  The YP-CLK ′ signal shown in FIG. 7B is obtained by dividing the CLK1 signal by 5 (frequency division value = 5 CLK1 signal). One cycle of the YP-CLK ′ signal in FIG. 7B is a 5CLK1 signal that is smaller than the YP-CLK signal shown in FIG. 7A by 1CLK1 signal. The YP-CLK 'signal in FIG. 7B is obtained by accelerating the polygon motor 36 and controlling the phase by dividing the frequency by 1CLK1 signal. From the start of the phase change at t1 to the end of the phase change at t2, the frequency of the YP-CLK ′ signal is 3.5 frequencies, which is about 0.5 frequency higher than the frequency of the YP-CLK signal, and the phase is inverted. ing.

  The YP-CLK ″ signal shown in FIG. 7C is obtained by dividing the CLK1 signal by 7 (divided value = 7 CLK1 signal). One cycle of the YP-CLK ″ signal in FIG. 7C is a 7CLK1 signal that is larger than the YP-CLK signal shown in FIG. The YP-CLK ″ signal in FIG. 7C is obtained by controlling the phase by decelerating the polygon motor 36 by dividing the frequency by 1CLK1 signal. From the start of the phase change at t1 to the end of the phase change at t2, the frequency of the YP-CLK ″ signal is 2.5, and the phase is set back by about 0.5 frequency compared to the frequency of the YP-CLK signal. Inverted.

  The YP-CLK signal 'in FIG. 7B described above is an example in which the phase is controlled by accelerating the polygon motor 36 by decreasing the frequency division value of the YP-CLK signal in FIG. 7A. (C) YP-CLK signal ″ is an example in which the phase is controlled by increasing the frequency division value of the YP-CLK signal to decelerate the polygon motor 36. Application examples of phase control are shown in FIGS. 9 and 10 by using the method of the phase control example shown in FIGS. 7B and 7C.

  FIG. 8 is a waveform diagram showing an example of the phase control time by the Y-polygon phase control circuit 62. The waveform shown in FIG. 8 is obtained by measuring the rotation direction and control time of the polygon motor 36 during acceleration and deceleration using an oscilloscope, for example. The horizontal axis in FIG. 8 is time (S), and the vertical axis is time interval (μsec). For example, the phase shift amount of the polygon motor 36 during acceleration and deceleration is set to a half cycle of the YP-CLK signal.

  Q1 shown in FIG. 8 is a waveform when the polygon motor 36 is accelerated to control the phase. In the waveform Q1, the polygon motor 36 rotates in the acceleration direction until the time interval value = 142.7, and thereafter the rotational force in the acceleration direction is weakened and returns to the normal rotation speed of 141.9, from 141.9. The motor rotates in the deceleration direction up to 141.7, and then the rotational force in the deceleration direction is weakened, returning to the normal rotational speed with a slight acceleration / deceleration blur. T1 = 235 msec indicates the time required for accelerating the polygon motor 36 and controlling the phase shift.

  Q2 shown in FIG. 8 is a waveform when the polygon motor 36 is decelerated to control the phase. In the waveform Q2, the polygon motor 36 rotates in the decelerating direction until the time interval value = 141.0, and thereafter the rotational force in the acceleration direction increases, returning to 141.9, which is the normal rotation speed, and 141 .9 to 142.5, and then the rotational force in the acceleration direction is weakened, returning to the normal rotational speed with a slight acceleration / deceleration blur. T2 = 365 msec indicates the time required to decelerate the polygon motor 36 and perform phase shift control.

  Here, when T1 and T2 which are phase shift control times of the polygon motor 36 are compared, T2 takes about 130 msec. This is because the polygon motor 36 is temporarily accelerated to perform phase shift control, and after the phase shift control is completed, the polygon motor 36 is once decelerated to perform phase shift control compared to the case where the polygon motor 36 is decelerated again. After the phase shift control is completed, it takes about 130 msec to accelerate the polygon motor 36 again.

  Subsequently, Example 1 and Example 2 are shown below as examples for shortening 130 msec, which is the difference in the phase shift control time. In the first embodiment, the phase shift control of the polygon drive CLK signal using the threshold value Dw at which the stabilization times in the acceleration and deceleration directions of the polygon motor 36 at a predetermined phase shift amount are equal will be described. In the second embodiment, phase shift control for setting the phase control width Dx in the YP-CLK signal of the polygon motor 36 to different values for acceleration and deceleration will be described.

  FIGS. 9A to 9E are time charts showing phase control examples (acceleration) of the polygon drive CLK signal in the image writing unit 3Y and the like. In FIG. 9, the horizontal axis represents time t, and the vertical axis represents the amplitude of a polygon drive clock signal (YP-CLK signal or the like). This example shows an example in which the phase control shown in FIG. 7 is applied. The pseudo index signal will be described using MST-IDX2 used at the time of rear surface image formation. The reference clock signal (CLK1 signal) shown in FIG. 9A is output by the crystal oscillator 11 shown in FIG. In the case of phase control, the Y-polygon phase control circuit 62 measures the phase difference between the MST-IDX2 signal shown in FIG. 9B and the YIDX signal shown in FIG.

  The threshold value Dw is, for example, the phase shift amount corresponding to one surface of the polygon mirror 42Y, the time required to move the phase shift amount by accelerating the polygon motor 36, and the phase shift amount by decelerating the polygon motor 36. The time required to move the vehicle is measured, and from each measured time, the stabilization time in the acceleration and deceleration directions is set to be equal.

  Specifically, when the YP-CLK signal obtained by dividing the CLK1 signal by 10 is used and one surface of the polygon mirror 42Y is driven by one cycle of the YP-CLK signal (10CLK1 signal), the polygon motor 36 is temporarily accelerated. Assume that the time required to move one surface of the polygon mirror 42Y is 200 msec, and the time required to move the one surface of the polygon mirror 42Y by decelerating the polygon motor 36 is 300 msec. At this time, the threshold value Dw at which the stabilization time in the acceleration and deceleration directions becomes equal from each measured time is a point where the phase shift amount during acceleration becomes the 6CLK signal and the phase shift amount during deceleration becomes the 4CLK signal. . For example, the calculated threshold value Dw is stored in the ROM 53 before the device is shipped. The threshold value Dw stored in the ROM 53 is used as a reference value for comparing the phase difference between the MST-IDX2 signal and the YIDX signal, for example.

The Y-polygon phase control circuit 62 uses the threshold value Dw at which the stabilization time in the acceleration and deceleration directions of the polygon motor 36 is equal to the phase shift amount of one surface of the polygon mirror 42Y, for example, the MST-IDX2 signal and the YIDX signal. Judgment is made by comparing with the phase difference of. Then, the Y-polygon phase control circuit 62 controls the phase by accelerating and decelerating the rotational speed of the polygon motor 36 based on the determination result.

  For example, when the phase difference is greater than or equal to the threshold value Dw (= 4CLK1 signal), the Y-polygon phase control circuit 62 decreases the frequency division value of the CLK1 signal that generates the YP-CLK signal of the polygon motor 36, The rotational speed of the polygon motor 36 is accelerated, and the phase is moved by a value obtained by subtracting the phase difference from a predetermined period in the MST-IDX2 signal. When the phase difference is smaller than the threshold value Dw, the division value of the CLK1 signal generating the YP-CLK signal of the polygon motor 36 is increased, and the rotational speed of the polygon motor 36 is reduced to move the phase. Control. Thereby, the phase control time in the YP-CLK signal can be reduced.

  The phase difference between the point c of the YIDX signal shown in FIG. 9C and the point b of the MST-IDX2 signal shown in FIG. 9B is 8CLK1 signal. When the measured threshold value Dw (= 4 CLK1 signal (α)) is used, the relationship between the threshold value Dw and the phase difference (β) is β> α, so that the YP-CLK signal of the polygon motor 36 is generated. The frequency division value of the signal is reduced, the polygon motor 36 is accelerated, and control is performed so that the point c of the YIDX signal is phase-shifted to the point a of the MST-IDX2.

  That is, the rotational speed of the polygon motor 36 is accelerated, and the phase is shifted by 2CLK1 signal obtained by subtracting the phase difference (= 8CLK1 signal) from one cycle (= 10CLK1 signal) in the MST-IDX2 signal. Thereby, the phase shift time in the YP-CLK signal can be reduced.

  Conventionally, since the threshold value Dw is not set and there is no means for comparing the phase difference and the threshold value Dw, the polygon motor 36 is moved in a constant direction of acceleration or deceleration to perform phase control. Therefore, for example, the polygon motor 36 is decelerated and the phase shift is performed by about 8 CLK1 signals.

  10A to 10E are time charts showing a phase control example (deceleration) of the polygon drive CLK signal in the image writing unit 3Y and the like. In FIG. 10, the horizontal axis is time t, and the vertical axis is the amplitude of a polygon drive clock signal (YP-CLK signal or the like). In this example, the phase control shown in FIG. 7 is applied to the Y color YP-CLK signal. The pseudo index signal will be described using MST-IDX2 used at the time of rear surface image formation. The reference clock signal (CLK1 signal) shown in FIG. 10A is output by the crystal oscillator 11. In the case of phase control, the Y-polygon phase control circuit 62 measures the phase difference between the MST-IDX2 signal shown in FIG. 10 (B) and the YIDX signal shown in FIG. 10 (C).

  The phase difference between the point c of the YIDX signal shown in FIG. 10C and the point b of the MST-IDX2 signal shown in FIG. 10B is 2CLK1 signal. For example, as calculated in FIG. 9, when the threshold value Dw is 4CLK1 signal (α), the relationship between the threshold value Dw and the phase difference (β) is β <α, so the YP-CLK signal of the polygon motor 36 is generated. By increasing the frequency dividing value of the CLK1 signal, the polygon motor is decelerated, and control is performed such that the point c of the YIDX signal is phase-shifted to the point b of the MST-IDX2. Thereby, the phase shift time in the YP-CLK signal can be reduced. The YP-CLK signal shown in FIG. 10D is phase-shifted by 2CLK1 signal by decelerating the polygon motor 36, and the phase-shifted YP-CLK signal is the YP-CLK ′ signal shown in FIG. It is.

  Next, a control method of the color image forming apparatus will be described using a control example of the color copying machine 100.

  FIG. 11 is a flowchart illustrating an example of phase control by changing the phase shift amount in the first embodiment.

  In this embodiment, the MST-IDX1 signal, the MST-IDX2 signal and the YIDX signal, etc. are used when the rotation speed of the polygon motor 36 and the phase of the YP-CLK signal are controlled to adjust the magnification of the image to form a color image. And the phase of the polygon motor 36, such as the YP-CLK signal, is controlled based on the phase difference to accelerate and decelerate the polygon motor 36.

  The color copying machine 100 forms a color image on one side (front side) of the paper P and forms a color image on the other side (back side). To set the phase control. Further, it is assumed that the CPU 55 reads out the threshold value Dw stored in the ROM 53 and supplies it to the Y-polygon phase control circuit 62. Furthermore, the values used in FIG. 9 or FIG. 10 are used for the MST-IDX2 signal and the YIDX frequency division value and threshold value Dw used in the flowchart. Furthermore, although the phase control of the polygon mirror 42Y in the Y-image writing unit 3Y is described, the same processing is performed for the M-image writing unit 3M, the C-image writing unit 3C, and the K-image writing unit 3K. .

  With these as conditions for phase control when adjusting the front / back magnification, the Y-polygon phase control circuit 62 uses the MST-IDX2 signal created by the pseudo index creation circuit 12 and the index sensor 38 in step S1 of the flowchart shown in FIG. The phase difference from the detected YIDX signal is measured using the CLK1 signal. As shown in FIG. 9, for example, one cycle of the MST-IDX2 signal is a 10CLK1 signal and a phase difference is an 8CLK1 signal.

  Subsequently, in step S2, the Y-polygon phase control circuit 62 compares the threshold value Dw (= 4CLK1 signal) shown in FIG. As shown in FIG. 9, for example, when the phase difference is the 8CLK1 signal, the phase difference is large with respect to the threshold value Dw (= 4CLK1 signal), and the process proceeds to step S3. In step S3, the dividing value of the CLK1 signal that generates the YP-CLK signal of the polygon motor 36 is decreased, the rotational speed of the polygon motor 36 is accelerated, and from one cycle (10CLK1 signal) in the MST-IDX2 signal. Control is performed so that the phase is shifted by the 2CLK1 signal obtained by subtracting the phase difference (8CLK1 signal). Thereby, the phase shift time in the YP-CLK signal can be reduced.

  In step S4, the Y-polygon phase control circuit 62 reduces the frequency division value of the CLK1 signal generating the YP-CLK signal, and controls the polygon motor 36 to accelerate and phase shift.

  For example, as shown in FIG. 9, the CLK1 signal divided by 10 is defined as a YP-CLK signal, and one frequency of the YP-CLK signal is defined as one step. Then, the divided value of the CLK1 signal generating the YP-CLK signal is reduced by 1CLK1 signal to obtain a divided value = 9CLK1 signal, and the obtained phase shift amount (2CLK1 signal) is phase-shifted. In the first step, the phase advances by 1 CLK1 signal, the remaining phase shift amount becomes 1 CLK1 signal, and the process proceeds to step S5.

  In step S5, it is determined whether the phase shift amount is zero. If the phase shift amount is zero, the phase control processing flow ends. If not, the process returns to step S4 and the phase shift processing described above is performed. In the second step, the remaining phase shift amount of the YP-CLK signal becomes the 0CLK1 signal and the phases match, and the process ends as shown in step S5.

  In step S2, as shown in FIG. 10, for example, when the phase difference is the 2CLK1 signal, the phase difference is small with respect to the threshold value Dw (= 4CLK1 signal), and the process proceeds to step S6. In step S6, as shown in FIG. 10, since the phase difference (= 2CLK1 signal) is smaller than the threshold value Dw (= 4CLK1 signal), the phase shift amount is 2CLK1 signal.

  In step S7, the Y-polygon phase control circuit 62 increases the frequency division value of the CLK1 signal generating the YP-CLK signal to decelerate the polygon motor 36 and shift the phase. Control. For example, as shown in FIG. 10, the CLK1 signal divided by 10 is defined as a YP-CLK signal, and one frequency of the YP-CLK signal is defined as one step. Then, the divided value of the CLK1 signal generating the YP-CLK signal is increased by 1CLK1 signal to obtain a divided value = 11CLK1 signal, and the obtained phase shift amount (2CLK1 signal) is phase-shifted. At the first step, the phase is delayed by 1 CLK1 signal, the remaining phase shift amount becomes 1 CLK1 signal, and the process proceeds to step S8.

  In step S8, it is determined whether the phase shift amount is zero. If it is zero, the phase control processing flow ends. If it is not zero, the process returns to step S7 and the phase shift processing described above is performed.

  In the second step, the remaining phase shift amount of the YP-CLK signal becomes the 0CLK1 signal and the phases match, and the process ends as shown in step S8.

As described above, according to the color copying machine 100 and the control method therefor according to the first embodiment, the rotation speed of the polygon motor 36 and the phase of the YP-CLK signal are controlled to adjust the magnification of the image, thereby producing a color image. When forming, the threshold value Dw at which the stabilization time in the acceleration and deceleration directions of the polygon motor 36 is equal for one surface of the polygon mirror 42Y and the phase difference between the MST-IDX2 signal and the YIDX signal are compared and determined. Based on the determination result, the rotational speed of the polygon motor 36 is accelerated and decelerated to control the phase.

  Thereby, the phase control time in the YP-CLK signal can be reduced. Therefore, the time until the polygon motor 36 rotates stably is shortened, and a color image can be formed at high speed. As a result, the number of color image formations per unit time is increased and the productivity is improved.

  FIG. 12 is a flowchart illustrating an example of phase control by changing the phase shift rate in the second embodiment.

  In this embodiment, the MST-IDX1 signal, the MST-IDX2 signal and the YIDX signal, etc. are used when the rotation speed of the polygon motor 36 and the phase of the YP-CLK signal are controlled to adjust the magnification of the image to form a color image. And the phase of the polygon motor 36, such as the YP-CLK signal, is controlled based on the phase difference to accelerate and decelerate the polygon motor 36.

  The color copying machine 100 forms a color image on one side (front side) of the paper P and forms a color image on the other side (back side). To set the phase control. Further, it is assumed that the CPU 55 reads out the threshold value Dw stored in the ROM 53 and supplies it to the Y-polygon phase control circuit 62. Furthermore, the frequency division value used in FIGS. 9 and 10 (= 10 CLK1 signal) is used as the MST-IDX2 signal and the YIDX division value used in the flowchart, and the threshold value Dw is, for example, this division value. Set to half (= 5 CLK1 signal). Furthermore, although the phase control of the polygon mirror 42Y in the Y-image writing unit 3Y is described, the same processing is performed for the M-image writing unit 3M, the C-image writing unit 3C, and the K-image writing unit 3K. .

  Using these as conditions for phase control when adjusting the front / back magnification, in step W1 of the flowchart shown in FIG. 12, the Y-polygon phase control circuit 62 generates the MST-IDX2 signal (= 10CLK1 signal) created by the pseudo index creation circuit 12. And the YIDX signal detected by the index sensor 38 is measured using the CLK1 signal. As shown in FIG. 9, for example, the phase difference is 8CLK1 signal.

  In step W2, the Y-polygon phase control circuit 62 determines the phase shift direction by comparing the determined threshold value Dw (5CLK1 signal based on the precondition) with the magnitude of the phase difference. As shown in FIG. 9, for example, when the phase difference is an 8CLK1 signal, the phase difference is larger than the threshold value Dw (5CLK1 signal), so the process proceeds to step W3 and the phase control width per step is set.

  In step W3, the phase control width Dx of the YP-CLK signal during acceleration and deceleration of the polygon motor 36 is set to a different value. According to the example of the phase control time shown in FIG. 8, since it takes more time for the polygon motor 36 to stabilize when decelerating than accelerating, YP− during deceleration is greater than the phase control width Dx of the YP-CLK signal during accelerating the polygon motor 36. The phase control width Dx of the CLK signal is set large.

  For example, when the polygon motor 36 is accelerated, the divided value of the CLK1 signal generating the YP-CLK signal is reduced by 1CLK1 signal to obtain a divided value = 9CLK1 signal, and when the polygon motor 36 is decelerated, the YP The frequency dividing value of the CLK1 signal generating the −CLK signal is increased by 2 CLK1 signals to obtain a frequency dividing value = 12 CLK1 signal. As a result, the phase control time difference in the YP-CLK signal during acceleration and deceleration can be reduced, so that the phase control time can be reduced.

  Shifting to step W4, for example, as shown in FIG. 9, a signal obtained by dividing the CLK1 signal by 10 is defined as a YP-CLK signal, and one frequency of the YP-CLK signal is defined as one step. Then, the divided value of the CLK1 signal generating the YP-CLK signal is reduced by 1CLK1 signal to obtain a divided value = 9CLK1 signal, and the obtained phase shift amount (2CLK1 signal) is phase-shifted. At the first step, the phase advances by 1CLK1 signal, the remaining phase shift amount becomes 1CLK1 signal, and the process proceeds to step W5.

  The process proceeds to step W5, where it is determined whether the phase shift amount is zero. If the phase shift amount is zero, the phase control process flow ends. If not, the process returns to step W4 and the phase shift process described above is performed. In the second step, the remaining phase shift amount of the YP-CLK signal becomes the 0CLK1 signal and the phase is matched, and the phase control process is completed.

  Further, at step W2, as shown in FIG. 10, for example, when the phase difference is the 2CLK1 signal, the phase difference is small with respect to the threshold value Dw (= 5CLK1 signal), and the process proceeds to step W6. In step W6, when the polygon motor 36 is decelerated, a phase control width Dx (2CLK1 signal) larger than the phase control width Dx (1CLK1 signal) of the YP-CLK signal in acceleration is set.

  Subsequently, the process proceeds to step W7, and according to the phase control time example shown in FIG. 8, since it takes more time for the polygon motor 36 to stabilize during deceleration than the acceleration, the YP-CLK signal is generated as described above. When the polygon motor 36 is decelerated, the divided value of the CLK1 signal generating the YP-CLK signal is reduced when the divided value of the CLK1 signal is reduced by 1CLK1 signal and the divided value = 9CLK1 signal. The value is increased by 2CLK1 signal to obtain a divided value = 12CLK1 signal. As a result, the phase control time difference in the YP-CLK signal during acceleration and deceleration can be reduced, so that the phase control time can be reduced.

  Here, one frequency of the YP-CLK signal is set as one step, and the divided value of the CLK1 signal generating the YP-CLK signal is increased by 2 CLK1 signals to obtain a divided value = 12 CLK1 signal. 2CLK1 signal). At the first step, the phase retreats by 2CLK1 signal, the remaining phase shift amount becomes 0CLK1 signal, and the process proceeds to Step W8.

  The process proceeds to step W8, where it is determined whether the phase shift amount is zero. If the phase shift amount is zero, the phase control process flow ends. If not, the process returns to step W7 and the phase shift process described above is performed. In the first step, the remaining phase shift amount of the YP-CLK signal becomes the 0CLK1 signal, the phases match, and the phase control process ends. That is, when the polygon motor 36 is phase shifted by accelerating and decelerating, it takes two steps to perform the phase shift control by 2 CLK1 signals during acceleration, and one step during deceleration.

  As described above, according to the color copying machine 100 and the control method thereof according to the second embodiment, the rotational speed of the polygon motor 36 and the phase of the YP-CLK signal are controlled to adjust the magnification of the image, thereby producing a color image. When forming, the Y-polygon phase control circuit 62 is provided, and the phase control width Dx of the YP-CLK signal in the acceleration and deceleration of the polygon motor 36 is set to a different value.

  Thereby, the difference in the phase control time in the YP-CLK signal during acceleration and deceleration can be reduced. Therefore, the time until the polygon motor 36 rotates stably is shortened, and a color image can be formed at high speed. As a result, the number of color image formations per unit time is increased and the productivity is improved.

  The present invention is extremely suitable when applied to a color printer having a function capable of forming an image on a sheet, the same facsimile machine, the same digital copying machine, and a multifunction machine thereof.

1 is a conceptual diagram illustrating a configuration example of a color copying machine 100 as an embodiment of the present invention. 2 is a block diagram illustrating a configuration example of a control system of the color copying machine 100. FIG. FIG. 3 is a block diagram showing a configuration example of a Y color image writing unit 3Y extracted from FIG. 2 and its peripheral circuits. It is a block diagram showing a configuration example in which a polygon drive CLK generation circuit 39Y for Y color and its peripheral circuits are extracted. (A)-(H) are time charts which show the operation example at the time of Y-color front and back magnification adjustment. It is a graph which shows the example of the speed characteristic of the polygon motor 36 at the time of front and back surface image formation switching. (A)-(D) are time charts showing examples of phase control in the Y-polygon phase control circuit 62 and the like. 6 is a waveform diagram showing an example of a phase control time by a Y-polygon phase control circuit 62. FIG. (A)-(E) are time charts showing a phase control example (acceleration) of a polygon drive CLK signal in the image writing unit 3Y and the like. (A)-(E) are time charts showing a phase control example (deceleration) of a polygon drive CLK signal in the image writing unit 3Y and the like. It is a flowchart which shows the phase control example by the phase shift amount change in a 1st Example. It is a flowchart which shows the phase control example by the phase shift rate change in a 2nd Example. (A) And (B) is a figure explaining the shrinkage | contraction example of the paper size at the time of double-sided image formation.

Explanation of symbols

1Y, 1M, 1C, 1K Photosensitive drum (image forming body)
3Y, 3M, 3C, 3K Image writing unit 4Y, 4M, 4C, 4K Developing means 6 Intermediate transfer belt 10Y, 10M, 10C, 10K Image forming unit 11 Crystal oscillator (signal source)
12 pseudo index creation circuit 13 image memory 14 operation means 15 control means 16 image processing means 39Y polygon drive CLK generation circuit (determination means, phase control means, phase control width setting means)
55 CPU
60 Image forming means 62 Y-polygon phase control circuit 100 Color copier (color image forming apparatus)
DESCRIPTION OF SYMBOLS 101 Copier main body 102 Image reading apparatus 201 Automatic document feeder 202 Document image scanning exposure apparatus

Claims (6)

When forming a color image by controlling the rotation speed of the polygon motor and the phase of the drive clock signal to adjust the magnification of the image, the predetermined pseudo main scanning reference signal having a fixed period and the rotation speed and phase of the polygon motor Means for detecting a phase difference from a main scanning reference signal whose period varies under control of the control, and means for accelerating and decelerating the polygon motor by controlling the phase of the drive clock signal of the polygon motor based on the phase difference In a color image forming apparatus having
The phase difference reference value at which the stabilization time in the acceleration and deceleration directions of the polygon motor is equal to a predetermined phase shift amount is compared with the phase difference between the pseudo main scanning reference signal and the main scanning reference signal. Determination means for determining
When the determination means determines that the phase difference is greater than or equal to the phase difference reference value, the dividing value of the reference clock signal that generates the driving clock signal of the polygon motor is decreased, and the polygon motor And the phase is shifted by a value obtained by subtracting the phase difference from a predetermined period in the pseudo main scanning reference signal, and
When it is determined that the phase difference is smaller than the phase difference reference value, the frequency division value of the reference clock signal generating the driving clock signal of the polygon motor is increased, and the rotation speed of the polygon motor is reduced. And a phase control means for controlling the phase to move. The predetermined phase shift amount is one polygon mirror,
The phase difference reference value is
The time required to accelerate the polygon motor and move the phase shift amount;
The time required to decelerate the polygon motor and move the phase movement amount is measured,
2. The color image forming apparatus according to claim 1, wherein a stable time in the acceleration and deceleration directions is set to be equal from each measured time. When forming a color image by controlling the rotation speed of the polygon motor and the phase of the driving clock signal to adjust the magnification of the image, the predetermined pseudo main scanning reference signal having a fixed period and the rotation speed and phase of the polygon motor Color image formation for detecting the phase difference from the main scanning reference signal whose cycle varies under the control, and controlling the phase of the driving clock signal of the polygon motor based on the phase difference to accelerate and decelerate the polygon motor In the device control method,
The color image forming apparatus includes a determination unit and a phase control unit,
The determination means is
Comparing the phase difference reference value at which the stabilization time in the acceleration and deceleration directions of the polygon motor is equal to a predetermined phase movement amount, and the magnitude of the phase difference between the pseudo main scanning reference signal and the main scanning reference signal Judgment,
The phase control means is
If the determined phase difference is greater than or equal to the phase difference reference value, the frequency division value of the reference clock signal that generates the polygon motor drive clock signal is decreased to accelerate the rotation speed of the polygon motor. Calculating a phase shift amount by subtracting the phase difference from a predetermined period in the pseudo main scanning reference signal,
If the determined phase difference is smaller than the phase difference reference value, the frequency division value of the reference clock signal that generates the driving clock signal of the polygon motor is increased, and the rotational speed of the polygon motor is reduced. A method for controlling a color image forming apparatus, wherein the phase is controlled to move. The predetermined phase shift amount is one polygon mirror,
The phase difference reference value is
The time required to accelerate the polygon motor and move the phase shift amount;
The time required to decelerate the polygon motor and move the phase movement amount is measured,
4. The method of controlling a color image forming apparatus according to claim 3, wherein a stable time in the acceleration and deceleration directions is set to be equal from each measured time. According to claim 1, further comprising a phase control range setting means for setting a larger value the phase control width of the drive clock signal in the deceleration than the phase control width of the drive clock signal definitive to accelerate before Symbol polygon motor color image forming apparatus. Before Symbol color image forming apparatus includes a phase control range setting means,
The phase control width setting means is
Control method of the color image forming apparatus according to claim 3, characterized in that setting the phase control width of the drive clock signal in the deceleration than the phase control width of the drive clock signal definitive to accelerate the polygon motor to a larger value .

Images