JP2005183780A - Manufacturing method of nitride-based iii group compound semiconductor light emitting element - Google Patents

Manufacturing method of nitride-based iii group compound semiconductor light emitting element Download PDF

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JP2005183780A
JP2005183780A JP2003424595A JP2003424595A JP2005183780A JP 2005183780 A JP2005183780 A JP 2005183780A JP 2003424595 A JP2003424595 A JP 2003424595A JP 2003424595 A JP2003424595 A JP 2003424595A JP 2005183780 A JP2005183780 A JP 2005183780A
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JP2005183780A5 (en
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Jun Ito
潤 伊藤
Toshiaki Sato
壽朗 佐藤
Naoki Wada
直樹 和田
Shiro Sakai
士郎 酒井
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Toyoda Gosei Co Ltd
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<P>PROBLEM TO BE SOLVED: To improve light emission output of a nitride-based III group compound semiconductor light emitting element by improving crystallinity of a p-layer formed in contact with a light emitting layer. <P>SOLUTION: The semiconductor light emitting element 1000 is formed of a GaN buffer layer 101, an n-type contact layer 102 formed of GaN, an n-layer 103 formed of Al<SB>0.12</SB>Ga<SB>0.88</SB>N, a light emission layer 104 of a single quantum well structure (SQW) holding a 2 nm-thick nondoped well layer consisting of Al<SB>0.005</SB>In<SB>0.045</SB>Ga<SB>0.95</SB>N between barrier layers, a block layer 105 consisting of Al<SB>0.16</SB>Ga<SB>0.84</SB>N, a p-type contact layer 106 consisting of Al<SB>0.02</SB>Ga<SB>0.98</SB>N, electrodes 110, 120, 140, a protecting film 130, and a reflection film 150 on a sapphire substrate 100. The relation of the epitaxial growth temperature T<SB>p</SB>of a p-side layer (105) in contact with the light emission layer, the epitaxial growth temperature T<SB>n</SB>of an n-side layer (103) in contact with the light emission layer and the epitaxial growth temperature T<SB>L</SB>(800°C or higher) of the light emission layer 106 is made 0<T<SB>n</SB>-T<SB>p</SB>≤(T<SB>n</SB>-T<SB>L</SB>)/5. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明はIII族窒化物系化合物半導体発光素子に関する。本発明は特に紫外線領域発光のIII族窒化物系化合物半導体発光素子に特に有効である。   The present invention relates to a group III nitride compound semiconductor light emitting device. The present invention is particularly effective for a group III nitride compound semiconductor light emitting device emitting in the ultraviolet region.

主として紫外線領域に発光波長が存在するような短波長の発光素子の開発が進められており、次のような出願がなされている。
特開平6−268259 特開2001−024223
Development of a light emitting element having a short wavelength in which an emission wavelength exists mainly in the ultraviolet region has been advanced, and the following applications have been filed.
JP-A-6-268259 JP 2001-024223 A

単一量子井戸構造又は多重量子井戸構造を有する発光素子において、障壁層を組成にアルミニウムを含むAlGaN、井戸層を組成にアルミニウム及びインジウムを含むAlInGaNで形成する際、当該発光層に接して形成されるp層の結晶性が悪いと、発光出力の向上が困難であることが分かった。   In a light emitting device having a single quantum well structure or a multiple quantum well structure, when the barrier layer is made of AlGaN containing aluminum in the composition and the well layer is made of AlInGaN containing aluminum and indium in the composition, it is formed in contact with the light emitting layer. It has been found that if the p layer has poor crystallinity, it is difficult to improve the light emission output.

そこで本発明の目的は、発光層に接して形成されるp層の結晶性を向上させることにより、III族窒化物系化合物半導体発光素子の発光出力を向上させることである。   Accordingly, an object of the present invention is to improve the light emission output of the group III nitride compound semiconductor light emitting device by improving the crystallinity of the p layer formed in contact with the light emitting layer.

上記の課題を解決するため、本発明の特徴は、エピタキシャル成長によりIII族窒化物系化合物半導体を積層して形成された発光素子の製造方法において、実質的に発光に寄与し、その組成に少なくともインジウム(In)を含む発光層の成長温度TL(但し800℃以上)と、発光層に接するn型半導体層の成長温度Tnと、発光層に接するp型半導体層の成長温度Tpとが、
n−Tpが正で、且つTn−TLの1/3以下、或いは1/4以下、或いは1/5以下とすることである(請求項1乃至3)。尚、ここで成長温度とは、エピタキシャル成長における基板の温度を言うものとする。
In order to solve the above-described problems, the present invention is characterized in that, in a method for manufacturing a light-emitting element formed by stacking group III nitride compound semiconductors by epitaxial growth, it substantially contributes to light emission, and the composition has at least indium. The growth temperature T L of the light emitting layer containing (In) (800 ° C. or higher), the growth temperature T n of the n-type semiconductor layer in contact with the light emitting layer, and the growth temperature T p of the p-type semiconductor layer in contact with the light emitting layer ,
T n −T p is positive and T n −T L is 1/3 or less, or 1/4 or less, or 1/5 or less (Claims 1 to 3). Here, the growth temperature refers to the temperature of the substrate in the epitaxial growth.

また、他の特徴は、少なくとも発光層と、前記n型半導体層と、前記p型半導体層を、有機金属気相成長法により形成することを特徴とする。或いは、温度Tpが、1000℃以上であることを特徴とする。 Another feature is that at least the light emitting layer, the n-type semiconductor layer, and the p-type semiconductor layer are formed by metal organic vapor phase epitaxy. Alternatively, the temperature T p is 1000 ° C. or higher.

また、他の特徴は、発光層の発光波長のピークが、380nm以下であることを特徴とする。更には、発光層は、単一量子井戸又は多重量子井戸であることを特徴とする。   Another feature is that the emission wavelength peak of the light emitting layer is 380 nm or less. Furthermore, the light emitting layer is a single quantum well or a multiple quantum well.

通常、n型層は発光層直下までの各層はその結晶性を良くするため1000〜1150℃程度でエピタキシャル成長により形成されている。一方、発光層にインジウムを含む場合などは、p型層のエピタキシャル成長を余り高温で行っていなかった。即ちp型層のエピタキシャル成長を余り高温で行うと、インジウムを含む発光層の結晶性が劣化し、また、p型層を形成するためのマグネシウムなどのドーパントが発光層へ拡散することにより、発光層が著しく悪化すると考えられていたからである。発光層への影響を除けば、アルミニウムを組成に含むp型層は、その成長温度はできるだけ高く、即ち、n側層と同じまで上げられ得る。   Usually, the n-type layer is formed by epitaxial growth at about 1000 to 1150 ° C. in order to improve the crystallinity of each layer immediately below the light emitting layer. On the other hand, when the light emitting layer contains indium, the epitaxial growth of the p-type layer was not performed at a very high temperature. That is, if epitaxial growth of the p-type layer is performed at an excessively high temperature, the crystallinity of the light-emitting layer containing indium is deteriorated, and a dopant such as magnesium for forming the p-type layer is diffused into the light-emitting layer. It was because it was thought that it deteriorated remarkably. Except for the influence on the light emitting layer, the p-type layer containing aluminum in its composition can have its growth temperature as high as possible, that is, as high as the n-side layer.

これに対し本発明者は、p型層のエピタキシャル成長温度をn型層のエピタキシャル成長温度よりは低くしつつ、その温度差が、n型層のエピタキシャル成長温度と発光層のエピタキシャル成長温度との差の1/3以下、或いは1/4以下、或いは1/5以下とすることで発光出力が向上できることを見出した。これは、p層の結晶性が向上することにより、p層から発光層へのホールの注入が理想的となるからと考えられる。一方、発光層への影響、即ち発光層の結晶性の劣化やドーパントの拡散は、p層の成長時間の短縮(薄膜化)により、p層の結晶性が向上することに比較すれば大きな影響はなかった。   In contrast, the inventor of the present invention makes the temperature difference lower than the epitaxial growth temperature of the n-type layer while making the epitaxial growth temperature of the p-type layer lower than the epitaxial growth temperature of the n-type layer and the epitaxial growth temperature of the light emitting layer. It has been found that the light emission output can be improved by setting it to 3 or less, 1/4 or less, or 1/5 or less. This is presumably because hole injection from the p layer into the light emitting layer becomes ideal as the crystallinity of the p layer improves. On the other hand, the influence on the light emitting layer, that is, the deterioration of the crystallinity of the light emitting layer and the diffusion of the dopant are more significant than the improvement of the crystallinity of the p layer by shortening the growth time (thinning of the p layer) There was no.

p型層は一般的にアルミニウムを組成に含むので、例えば発光層への影響を除外すれば、その成長温度Tpは、n型層の成長温度Tnに近いもので良い。一方、成長温度Tpの下限を示すものとして、発光層の成長温度をTLとして、Tn−TpがTn−TLの1/3を超えると、アルミニウムを組成に含むp型層は結晶性が悪くなり、発光素子の製造方法としては使用できないものとなる。 Since the p-type layer generally contains aluminum in its composition, the growth temperature T p may be close to the growth temperature T n of the n-type layer, for example, if the influence on the light emitting layer is excluded. On the other hand, as indicating the lower limit of the growth temperature T p, the growth temperature of the light emitting layer as a T L, if T n -T p exceeds 1/3 of T n -T L, p-type layer including aluminum on the composition Becomes poor in crystallinity and cannot be used as a method for manufacturing a light-emitting element.

本発明に係るIII族窒化物系化合物半導体発光素子は、上記の発明の主たる構成に係る限定の他は、任意の構成を取ることができる。また、発光素子は発光ダイオード(LED)、レーザダイオード(LD)、フォトカプラその他の任意の発光素子として良い。特に本発明に係るIII族窒化物系化合物半導体発光素子の製造方法としては任意の製造方法を用いることができる。   The group III nitride compound semiconductor light-emitting device according to the present invention can have any configuration other than the limitation related to the main configuration of the present invention. The light emitting element may be a light emitting diode (LED), a laser diode (LD), a photocoupler, or any other light emitting element. In particular, any manufacturing method can be used as a method for manufacturing a group III nitride compound semiconductor light emitting device according to the present invention.

具体的には、結晶成長させる基板としては、サファイヤ、スピネル、Si、SiC、ZnO、MgO或いは、III族窒化物系化合物単結晶等を用いることができる。III族窒化物系化合物半導体層を結晶成長させる方法としては、有機金属気相成長法(MOVPE)が好ましいが、分子線気相成長法(MBE)、ハイドライド気相成長法(HVPE)を用いても良い。   Specifically, sapphire, spinel, Si, SiC, ZnO, MgO, a group III nitride compound single crystal, or the like can be used as a substrate for crystal growth. As a method for crystal growth of the group III nitride compound semiconductor layer, metal organic vapor phase epitaxy (MOVPE) is preferable, but molecular beam vapor phase epitaxy (MBE) and hydride vapor phase epitaxy (HVPE) are used. Also good.

電極形成層その他のIII族窒化物半導体層は、少なくともAlxGayIn1-x-yN(0≦x≦1, 0≦y≦1, 0≦x+y≦1)にて表される2元系、3元系若しくは4元系の半導体から成るIII族窒化物系化合物半導体で形成することができる。また、これらのIII族元素の一部は、ボロン(B)、タリウム(Tl)で置き換えても良く、また、窒素(N)の一部をリン(P)、砒素(As)、アンチモン(Sb)、ビスマス(Bi)で置き換えても良い。 Electrode forming layer other Group III nitride semiconductor layer is expressed by at least Al x Ga y In 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) 2 A group III nitride compound semiconductor made of a ternary, ternary, or quaternary semiconductor can be used. Some of these group III elements may be replaced by boron (B) and thallium (Tl), and part of nitrogen (N) may be phosphorus (P), arsenic (As), antimony (Sb ) Or bismuth (Bi).

更に、これらの半導体を用いてn型のIII族窒化物系化合物半導体層を形成する場合には、n型不純物として、Si、Ge、Se、Te、C等を添加し、p型不純物としては、Zn、Mg、Be、Ca、Sr、Ba等を添加することができる。   Further, when an n-type group III nitride compound semiconductor layer is formed using these semiconductors, Si, Ge, Se, Te, C, etc. are added as n-type impurities, and p-type impurities are used as p-type impurities. Zn, Mg, Be, Ca, Sr, Ba and the like can be added.

以上の本発明の手段により、前記の課題を効果的、或いは合理的に解決することができる。   By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.

図1は本発明の具体的な一実施例に係るIII族窒化物系化合物半導体発光素子1000の断面図である。半導体発光素子1000では、図1に示す様に、厚さ約100μmのサファイヤ基板100の上に、窒化ガリウム(GaN)から成る膜厚約25nmのバッファ層101が成膜され、その上にシリコン(Si)をドープして電子濃度5×1018/cm3としたGaNから成る膜厚約4μmのn型コンタクト層102(高キャリヤ濃度n+層)が形成されている。 FIG. 1 is a cross-sectional view of a group III nitride compound semiconductor light emitting device 1000 according to a specific embodiment of the present invention. In the semiconductor light emitting device 1000, as shown in FIG. 1, a buffer layer 101 made of gallium nitride (GaN) and having a thickness of about 25 nm is formed on a sapphire substrate 100 having a thickness of about 100 μm, and silicon ( An n-type contact layer 102 (high carrier concentration n + layer) having a film thickness of about 4 μm made of GaN having an electron concentration of 5 × 10 18 / cm 3 by doping Si) is formed.

また、このn型コンタクト層102の上には、シリコン(Si)をドープして電子濃度5×1018/cm3としたAl0.12Ga0.88Nから成る膜厚約200nmのn層103が形成されている。 On the n-type contact layer 102, an n-layer 103 having a thickness of about 200 nm made of Al 0.12 Ga 0.88 N doped with silicon (Si) to an electron concentration of 5 × 10 18 / cm 3 is formed. ing.

n層103の上には、単一量子井戸構造(SQW)の発光層104が形成されている。単一量子井戸構造(SQW)の発光層104は、膜厚12nmのノンドープのAl0.13Ga0.87Nから成る障壁層1041と、膜厚2nmのノンドープのAl0.005In0.045Ga0.95Nから成る井戸層1042と、膜厚12nmのノンドープのAl0.13Ga0.87Nから成る障壁層1043とを積層して形成される。 A light emitting layer 104 having a single quantum well structure (SQW) is formed on the n layer 103. The light emitting layer 104 having a single quantum well structure (SQW) includes a barrier layer 1041 made of non-doped Al 0.13 Ga 0.87 N having a thickness of 12 nm and a well layer 1042 made of non-doped Al 0.005 In 0.045 Ga 0.95 N having a thickness of 2 nm. And a barrier layer 1043 made of non-doped Al 0.13 Ga 0.87 N having a thickness of 12 nm.

単一量子井戸構造(SQW)の発光層104の上には、マグネシウム(Mg)をドープしてホール濃度5×1017/cm3としたAl0.16Ga0.84Nから成る膜厚40nmのp型ブロック層105が形成されている。p型ブロック層105の上には、マグネシウム(Mg)をドープしてホール濃度5×1017/cm3としたAl0.02Ga0.98Nから成る膜厚約60nmのp型コンタクト層106を形成した。 A 40 nm-thick p-type block made of Al 0.16 Ga 0.84 N doped with magnesium (Mg) to a hole concentration of 5 × 10 17 / cm 3 on the light emitting layer 104 having a single quantum well structure (SQW) Layer 105 is formed. On the p-type block layer 105, a p-type contact layer 106 having a film thickness of about 60 nm made of Al 0.02 Ga 0.98 N doped with magnesium (Mg) to a hole concentration of 5 × 10 17 / cm 3 was formed.

又、p型コンタクト層106の上には金属蒸着による透光性薄膜p電極110が、n型コンタクト層102上にはn電極140が形成されている。透光性薄膜p電極110は、p型コンタクト層106に直接接合する膜厚約1.5nmのコバルト(Co)より成る第1層111と、このコバルト膜に接合する膜厚約6nmの金(Au)より成る第2層112とで構成されている。   Further, a translucent thin film p-electrode 110 formed by metal vapor deposition is formed on the p-type contact layer 106, and an n-electrode 140 is formed on the n-type contact layer 102. The translucent thin film p-electrode 110 includes a first layer 111 made of cobalt (Co) having a thickness of about 1.5 nm directly bonded to the p-type contact layer 106 and gold (Au) having a thickness of about 6 nm bonded to the cobalt film. ) And the second layer 112.

厚膜p電極120は、膜厚約18nmのバナジウム(V)より成る第1層121と、膜厚約15μmの金(Au)より成る第2層122と、膜厚約10nmのアルミニウム(Al)より成る第3層123とを透光性薄膜p電極110の上から順次積層させることにより構成されている。   The thick p-electrode 120 includes a first layer 121 made of vanadium (V) having a thickness of about 18 nm, a second layer 122 made of gold (Au) having a thickness of about 15 μm, and aluminum (Al) having a thickness of about 10 nm. The third layer 123 is formed by sequentially laminating the translucent thin film p-electrode 110 from above.

多層構造のn電極140は、n型コンタクト層102の一部露出された部分の上から、膜厚約18nmのバナジウム(V)より成る第1層141と膜厚約100nmのアルミニウム(Al)より成る第2層142とを積層させることにより構成されている。   The n-electrode 140 having a multilayer structure is formed of a first layer 141 made of vanadium (V) having a thickness of about 18 nm and an aluminum (Al) having a thickness of about 100 nm from above a part of the n-type contact layer 102 exposed. It is comprised by laminating | stacking the 2nd layer 142 which consists.

また、最上部には、SiO2膜より成る保護膜130が形成されている。
サファイヤ基板100の底面に当たる外側の最下部には、膜厚約500nmのアルミニウム(Al)より成る反射金属層150が、金属蒸着により成膜されている。尚、この反射金属層150は、Rh、Ti、W等の金属の他、TiN、HfN等の窒化物でも良い。
A protective film 130 made of a SiO 2 film is formed on the top.
A reflective metal layer 150 made of aluminum (Al) with a film thickness of about 500 nm is formed on the lowermost part of the outer side corresponding to the bottom surface of the sapphire substrate 100 by metal deposition. The reflective metal layer 150 may be a metal such as Rh, Ti, or W, or a nitride such as TiN or HfN.

上記の構成の発光素子1000は次のように製造された。発光素子1000は、有機金属気相成長法(以下「MOVPE」と略す)にり製造された。用いられたガスは、アンモニア(NH3)、キャリアガス(H2及びN2)、トリメチルガリウム(Ga(CH3)3)(以下「TMG」と記す)、トリメチルアルミニウム(Al(CH3)3)(以下「TMA」と記す)、トリメチルインジウム(In(CH3)3)(以下「TMI」と記す)、シラン(SiH4)とシクロペンタジエニルマグネシウム(Mg(C5H5)2)(以下「CP2Mg」と記す)である。 The light emitting device 1000 having the above-described configuration was manufactured as follows. The light-emitting element 1000 was manufactured by metal organic chemical vapor deposition (hereinafter abbreviated as “MOVPE”). The gases used were ammonia (NH 3 ), carrier gas (H 2 and N 2 ), trimethylgallium (Ga (CH 3 ) 3 ) (hereinafter referred to as “TMG”), trimethylaluminum (Al (CH 3 ) 3 ) (Hereinafter referred to as “TMA”), trimethylindium (In (CH 3 ) 3 ) (hereinafter referred to as “TMI”), silane (SiH 4 ) and cyclopentadienyl magnesium (Mg (C 5 H 5 ) 2 ) (Hereinafter referred to as “CP 2 Mg”).

まず、有機洗浄及び熱処理により洗浄したC面を主面とした単結晶の基板100をMOVPE装置の反応室に載置されたサセプタに装着する。次に、常圧でH2を反応室に流しながら温度1100℃で基板100をベーキングした。
次に、基板100の温度を500℃まで低下させて、H2、NH3及びTMGを供給してGaNのバッファ層101を約25nmの膜厚に形成した。
First, a single crystal substrate 100 having a C-plane main surface cleaned by organic cleaning and heat treatment is mounted on a susceptor mounted in a reaction chamber of a MOVPE apparatus. Next, the substrate 100 was baked at a temperature of 1100 ° C. while flowing H 2 into the reaction chamber at normal pressure.
Next, the temperature of the substrate 100 was lowered to 500 ° C., and H 2 , NH 3 and TMG were supplied to form a GaN buffer layer 101 with a film thickness of about 25 nm.

次に、基板100の温度を1075℃に保持し、H2、NH3、TMG、シランを供給して、膜厚約4μm、キャリア濃度5×1018/cm3のGaNから成るn型コンタクト層102を形成した。この後、H2、NH3、TMG、TMA、シランの供給量を制御しながら、電子濃度5×1018/cm3としたAl0.12Ga0.88Nから成る膜厚約200nmのn層103を形成した。 Next, the temperature of the substrate 100 is kept at 1075 ° C., H 2 , NH 3 , TMG, and silane are supplied, and an n-type contact layer made of GaN having a film thickness of about 4 μm and a carrier concentration of 5 × 10 18 / cm 3 102 was formed. Thereafter, an n layer 103 having a film thickness of about 200 nm made of Al 0.12 Ga 0.88 N with an electron concentration of 5 × 10 18 / cm 3 is formed while controlling the supply amount of H 2 , NH 3 , TMG, TMA, and silane. did.

次に、基板100の温度を825℃にまで低下させて、N2又はH2、NH3、TMG、TMA及びTMIの供給量を制御して、膜厚12nmのノンドープのAl0.13Ga0.87Nから成る障壁層1041と、膜厚2nmのノンドープのAl0.005In0.045Ga0.95Nから成る井戸層1042と、膜厚12nmのノンドープのAl0.13Ga0.87Nから成る障壁層1043とを順次積層し、単一量子井戸構造の発光層104を形成した。 Next, the temperature of the substrate 100 is lowered to 825 ° C., and the supply amount of N 2 or H 2 , NH 3 , TMG, TMA, and TMI is controlled, and from 12 nm thick non-doped Al 0.13 Ga 0.87 N A barrier layer 1041 composed of non-doped Al 0.005 In 0.045 Ga 0.95 N with a thickness of 2 nm, and a barrier layer 1043 composed of non-doped Al 0.13 Ga 0.87 N with a thickness of 12 nm. A light emitting layer 104 having a quantum well structure was formed.

次に、基板100の温度を1025℃に保持し、N2又はH2、NH3、TMG、TMA及びCP2Mgを制御しながら供給して、マグネシウム(Mg)をドープしたAl0.16Ga0.84Nから成る膜厚40nmのp型ブロック層105、マグネシウム(Mg)をドープしたAl0.02Ga0.98Nから成る膜厚約60nmのp型コンタクト層106を順次形成した。 Next, the temperature of the substrate 100 is maintained at 1025 ° C., and N 2 or H 2 , NH 3 , TMG, TMA, and CP 2 Mg are supplied while being controlled, and Al 0.16 Ga 0.84 N doped with magnesium (Mg). A p-type block layer 105 having a thickness of 40 nm and a p-type contact layer 106 having a thickness of about 60 nm made of Al 0.02 Ga 0.98 N doped with magnesium (Mg) were sequentially formed.

この後、p側層であるp型ブロック層105及びp型コンタクト層106をp型化して、各々ホール濃度を5×1017/cm3、5×1017/cm3のp型層としたのち、各電極(110、120、140)及び保護膜130及び反射金属層150を形成した。 Thereafter, the p-type block layer 105 and the p-type contact layer 106, which are p-side layers, are made p-type to form p-type layers having hole concentrations of 5 × 10 17 / cm 3 and 5 × 10 17 / cm 3 , respectively. After that, each electrode (110, 120, 140), protective film 130 and reflective metal layer 150 were formed.

上記実施例において、p側層であるp型ブロック層105及びp型コンタクト層106のエピタキシャル成長における成長温度を、975℃、1000℃、1025℃、1050℃と変えて、発光素子1000を形成し、そのエレクトロルミネッセンス強度を測定した。これを図2に示す。図2に示されるように、p側層のエピタキシャル成長温度を975℃とした場合は、エレクトロルミネッセンス(EL)強度がばらつき、且つEL強度が小さい。p側層のエピタキシャル成長温度を1000℃、1025℃、1050℃と高くするにつれて、エレクトロルミネッセンス(EL)強度のばらつきが小さくなり、且つEL強度が大きくなっていく。この時、発光層104のエピタキシャル成長温度TLが825℃、n側層のエピタキシャル成長温度Tnが1075℃であるので、Tn−TLは250℃である。p側層のエピタキシャル成長温度Tpが1000℃のときは、Tn−Tpは75℃でTn−TLの1/3以下である。p側層のエピタキシャル成長温度Tpが1025℃のときは、Tn−Tpは50℃でTn−TLの1/5以下である。p側層のエピタキシャル成長温度Tpが1050℃のときは、Tn−Tpは25℃でTn−TLの1/8以下である。これは、n側層と同様の温度でp側層をエピタキシャル成長させることにより、p側層の結晶性が向上し、発光強度が向上することを意味する。この現象の技術的理由としては、p層の結晶性が向上することにより、p層から発光層へのホールの注入が理想的となるからと考えられる。 In the above embodiment, the growth temperature in the epitaxial growth of the p-type block layer 105 and the p-type contact layer 106 which are p-side layers is changed to 975 ° C., 1000 ° C., 1025 ° C., and 1050 ° C. The electroluminescence intensity was measured. This is shown in FIG. As shown in FIG. 2, when the epitaxial growth temperature of the p-side layer is 975 ° C., the electroluminescence (EL) intensity varies and the EL intensity is small. As the epitaxial growth temperature of the p-side layer is increased to 1000 ° C., 1025 ° C., and 1050 ° C., the variation in electroluminescence (EL) intensity decreases and the EL intensity increases. At this time, the epitaxial growth temperature T L of the light emitting layer 104 is 825 ° C., since the epitaxial growth temperature T n of the n-side layer is 1075 ° C., T n -T L is 250 ° C.. When the epitaxial growth temperature T p of the p-side layer is 1000 ° C., the T n -T p is less than or equal to 1/3 of the T n -T L at 75 ° C.. When the epitaxial growth temperature T p of the p-side layer is 1025 ° C., the T n -T p is less than or equal to 1/5 of the T n -T L at 50 ° C.. When the epitaxial growth temperature T p of the p-side layer is 1050 ℃, T n -T p is 1/8 or less of T n -T L at 25 ° C.. This means that the crystallinity of the p-side layer is improved and the emission intensity is improved by epitaxially growing the p-side layer at the same temperature as the n-side layer. The technical reason for this phenomenon is considered to be the ideal injection of holes from the p layer to the light emitting layer by improving the crystallinity of the p layer.

本発明は、紫外線領域に発光波長が存在するような短波長の発光素子に好適である。短波長の発光素子の用途としては、光励起触媒を用いる光化学分野、蛍光体を励起させるために用いる照明分野、誘蛾灯に代表されるバイオ関連分野の他、蛍光ランプに用いてブラックライトに用いることができる。   The present invention is suitable for a light emitting element having a short wavelength in which an emission wavelength exists in the ultraviolet region. Short-wavelength light-emitting elements can be used for fluorescent lamps as well as photochemical fields using photoexcitation catalysts, lighting fields used to excite phosphors, bio-related fields such as kidnapping lights, and black lights. it can.

本発明の実施例に係る半導体発光素子1000の断面図。Sectional drawing of the semiconductor light-emitting device 1000 which concerns on the Example of this invention. p側層の成長温度と、発光強度の関係を示すグラフ図。The graph which shows the growth temperature of p side layer, and the relationship of emitted light intensity.

符号の説明Explanation of symbols

1000:半導体発光素子
100:サファイヤ基板
101:バッファ層
102:n型コンタクト層
103:n層
104:単一量子井戸発光層(SQW)
105:p型ブロック層
106:p型コンタクト層
110:透光性薄膜p電極
120:p電極
130:保護膜
140:n電極
150:反射金属層
1000: Semiconductor light emitting device 100: Sapphire substrate 101: Buffer layer 102: n-type contact layer 103: n layer 104: single quantum well light emitting layer (SQW)
105: p-type block layer 106: p-type contact layer 110: translucent thin film p-electrode 120: p-electrode 130: protective film 140: n-electrode 150: reflective metal layer

Claims (7)

エピタキシャル成長によりIII族窒化物系化合物半導体を積層して形成された発光素子の製造方法において、
実質的に発光に寄与し、その組成に少なくともインジウム(In)を含む発光層の成長温度TL(但し800℃以上)と、
発光層に接するn型半導体層の成長温度Tnと、
発光層に接するp型半導体層の成長温度Tpとが、
0<Tn−Tp≦(Tn−TL)/3
を充たすことを特徴とするIII族窒化物系化合物半導体発光素子の製造方法。
In a method for manufacturing a light emitting device formed by stacking group III nitride compound semiconductors by epitaxial growth,
A growth temperature T L (however, 800 ° C. or higher) of a light emitting layer that substantially contributes to light emission and contains at least indium (In) in its composition;
A growth temperature T n of the n-type semiconductor layer in contact with the light emitting layer;
The growth temperature T p of the p-type semiconductor layer in contact with the light emitting layer is
0 <T n −T p ≦ (T n −T L ) / 3
A method for producing a group III nitride compound semiconductor light-emitting device, characterized by comprising:
エピタキシャル成長によりIII族窒化物系化合物半導体を積層して形成された発光素子の製造方法において、
実質的に発光に寄与し、その組成に少なくともインジウム(In)を含む発光層の成長温度TL(但し800℃以上)と、
発光層に接するn型半導体層の成長温度Tnと、
発光層に接するp型半導体層の成長温度Tpとが、
0<Tn−Tp≦(Tn−TL)/4
を充たすことを特徴とするIII族窒化物系化合物半導体発光素子の製造方法。
In a method for manufacturing a light emitting device formed by stacking group III nitride compound semiconductors by epitaxial growth,
A growth temperature T L (however, 800 ° C. or higher) of a light emitting layer that substantially contributes to light emission and contains at least indium (In) in its composition;
A growth temperature T n of the n-type semiconductor layer in contact with the light emitting layer;
The growth temperature T p of the p-type semiconductor layer in contact with the light emitting layer is
0 <T n −T p ≦ (T n −T L ) / 4
A method for producing a group III nitride compound semiconductor light-emitting device, characterized by comprising:
エピタキシャル成長によりIII族窒化物系化合物半導体を積層して形成された発光素子の製造方法において、
実質的に発光に寄与し、その組成に少なくともインジウム(In)を含む発光層の成長温度TL(但し800℃以上)と、
発光層に接するn型半導体層の成長温度Tnと、
発光層に接するp型半導体層の成長温度Tpとが、
0<Tn−Tp≦(Tn−TL)/5
を充たすことを特徴とするIII族窒化物系化合物半導体発光素子の製造方法。
In a method for manufacturing a light emitting device formed by stacking group III nitride compound semiconductors by epitaxial growth,
A growth temperature T L (however, 800 ° C. or higher) of a light emitting layer that substantially contributes to light emission and contains at least indium (In) in its composition;
A growth temperature T n of the n-type semiconductor layer in contact with the light emitting layer;
The growth temperature T p of the p-type semiconductor layer in contact with the light emitting layer is
0 <T n −T p ≦ (T n −T L ) / 5
A method for producing a group III nitride compound semiconductor light-emitting device, characterized by comprising:
少なくとも前記発光層と、前記n型半導体層と、前記p型半導体層を、有機金属気相成長法により形成することを特徴とする請求項1乃至請求項3のいずれか1項に記載のIII族窒化物系化合物半導体発光素子の製造方法。 4. The III according to claim 1, wherein at least the light emitting layer, the n-type semiconductor layer, and the p-type semiconductor layer are formed by metal organic vapor phase epitaxy. A method for manufacturing a group nitride compound semiconductor light emitting device. 前記温度Tpが、1000℃以上であることを特徴とする請求項1乃至請求項4のいずれか1項に記載のIII族窒化物系化合物半導体発光素子の製造方法。 5. The method for producing a group III nitride compound semiconductor light-emitting element according to claim 1, wherein the temperature T p is 1000 ° C. or higher. 前記発光層の発光波長のピークが、380nm以下であることを特徴とする請求項1乃至請求項5のいずれか1項に記載のIII族窒化物系化合物半導体発光素子の製造方法。 The method for producing a group III nitride compound semiconductor light-emitting device according to any one of claims 1 to 5, wherein a peak of an emission wavelength of the light-emitting layer is 380 nm or less. 前記発光層は、単一量子井戸又は多重量子井戸であることを特徴とする請求項1乃至請求項6のいずれか1項に記載のIII族窒化物系化合物半導体発光素子の製造方法。 The method for manufacturing a group III nitride compound semiconductor light-emitting device according to any one of claims 1 to 6, wherein the light-emitting layer is a single quantum well or a multiple quantum well.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101613958B1 (en) 2014-09-04 2016-04-20 엘지전자 주식회사 Manufacturing method for display device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101613958B1 (en) 2014-09-04 2016-04-20 엘지전자 주식회사 Manufacturing method for display device

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