JP2005183779A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a good semiconductor device wherein the occurrence of peeling and cracks of a low dielectric film is restrained in a semiconductor device using a porous low dielectric film as a layer insulating film. <P>SOLUTION: In the part B and the part D of a layer insulating film which do not include a wiring pattern on a semiconductor substrate, dummy patterns 13b and 13d dividing the low dielectric film into a plurality of isolated regions E are formed. In a CMP of buried wiring formation, since the low dielectric film of the part B and the part D is divided into isolated regions, shearing stress of the CMP to the low dielectric film of a part A and a part C including the wiring pattern is relaxed. Furthermore, even if peeling and cracks are caused in the low dielectric film of the part B and the part D, propagation of peeling and cracks is restrained in the part A and the part C. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure.

  With the high integration of LSIs (Large Scale Integrated Circuits) such as microprocessors and memories, which are known as representative semiconductor devices, element dimensions such as transistor gate lengths and film thicknesses constituting each element have been miniaturized. It was. In addition, with these miniaturization, the wiring pitch and the size of vias for connecting wirings have also been reduced.

  However, if simple miniaturization is performed, the wiring resistance increases due to the reduction of the wiring width and the thickness of the wiring film, and the parasitic capacitance between wirings increases due to the reduction of the wiring pitch. These increases in wiring resistance and inter-wiring parasitic capacitance both increase the signal transmission delay, which is a major obstacle to increasing the speed of semiconductor devices. Therefore, in recent multilayer wiring technology, various methods are taken as a workaround.

  First, regarding the wiring resistance, a shift to a copper wiring having a resistance lower than that of a conventional aluminum wiring has been studied. Since it is extremely difficult to process copper into a wiring shape by dry etching as in the past, so-called damascene, in which wiring grooves are formed in the interlayer insulating film and copper wiring is formed in the grooves. Embedded wiring structures called wiring have come to be used in products (for example, see Patent Document 1).

  Here, a general method for forming a buried wiring is to form a groove for wiring in an interlayer insulating film, and to form a metal film such as a copper film on the entire surface so as to fill the groove, and to form outside the groove for wiring. The metal film is removed by chemical mechanical polishing (hereinafter referred to as CMP).

However, since the polishing rate of CMP differs greatly between the copper film and the interlayer insulating film, a phenomenon called erosion, where the wiring film thickness and the interlayer insulating film are locally thinned, is likely to occur at a portion where the wiring density is high. On the other hand, in a portion where the interval between adjacent wiring patterns is large and the wiring density is small, a phenomenon called “dishing” in which the interlayer insulating film is thinned easily occurs.
For these reasons, the film thickness of the wiring and the interlayer insulating film becomes non-uniform depending on the wiring density and the wiring width, resulting in a drawback that the wiring resistance is increased and the parasitic capacitance between the wirings is increased. In order to eliminate the above-described drawbacks, a technique for forming a dummy pattern so as to reduce the density difference of wiring density has been provided (for example, see Patent Document 2).

On the other hand, in order to reduce the inter-wiring parasitic capacitance, it is indispensable to introduce a so-called low dielectric constant film having a relative dielectric constant lower than that of the silicon oxide film as a material for the interlayer insulating film, instead of the conventional silicon oxide film. .
Among them, a porous film having a low relative dielectric constant has a lower mechanical strength and adhesion than conventional silicon oxide films, so that the film may be peeled off due to friction during CMP or the film may be cracked. Is inevitable. However, the conventional dummy pattern formation technique has not been sufficient in measures for reducing such damage to the low dielectric constant film (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 10-284600 Japanese Patent Laid-Open No. 10-027799

  As described above, when a buried wiring structure is formed in a semiconductor device using a low dielectric constant film as an interlayer insulating film, CMP is performed to remove the metal film formed outside the wiring trench. At this time, due to the difference in density of the wiring density or the wiring width, the thickness of the wiring after the CMP or the interlayer insulating film becomes non-uniform, the low dielectric constant film used as the interlayer insulating film peels off, or the film is cracked. There was a problem of entering.

  The present invention has been made to solve the above problems, and in a semiconductor device using a low dielectric constant film as an interlayer insulating film, variations in the wiring film thickness after the formation of embedded wiring and the film thickness of the interlayer insulating film are suppressed. An object of the present invention is to provide an excellent semiconductor device in which peeling of a low dielectric constant film and generation of cracks are suppressed.

According to another aspect of the present invention, there is provided a semiconductor device including an interlayer insulating film having a portion including a wiring pattern and a portion not including a wiring pattern on a substrate, wherein a plurality of interlayer insulating films not including the wiring pattern are provided. This is characterized in that a dummy pattern for partitioning into isolated regions is formed.
Other features of the present invention are described in detail below.

  According to the present invention, in a semiconductor device using a low dielectric constant film as an interlayer insulating film, variations in the wiring film thickness after the formation of the embedded wiring and the film thickness of the interlayer insulating film are suppressed, and peeling or cracking of the low dielectric constant film is generated. It is possible to obtain an excellent semiconductor device that suppresses the above.

Embodiment 1 FIG.
1 to 4 are process explanatory views for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention step by step through the cross section of the semiconductor device.

First, as shown in FIG. 1, element isolation 2 having a depth of 300 nm to 400 nm is formed on the main surface of a semiconductor substrate 1 by STI (Shallow Trench Isolation).
Next, a gate insulating film 3 made of a silicon nitride oxide film or the like is formed on the main surface of the semiconductor substrate 1 with a thickness of about 2 to 3 nm. Next, a gate electrode 4 made of polycrystalline silicon or the like is formed on the gate insulating film 3 with a thickness of about 100 nm. Further, the diffusion layer 5 is formed using the gate electrode 4 and the gate insulating film 3 as a mask.
Further, a lower insulating film 6 is formed on the element isolation 2, the diffusion layer 5, and the gate electrode 4, that is, on the entire surface.

  Next, as shown in FIG. 2, a first stopper film 7 made of SiC is formed on the lower insulating film 6 with a film thickness of about 50 nm by plasma CVD (Chemical Vapor Deposition). Further, a first intermediate film 8 made of a low dielectric constant film such as an organic siloxane film is formed on the first stopper film 7 with a film thickness of about 200 nm by an SOD (Spin On Dielectrics) method. Further, a first cap film 9 made of a silicon oxide film is formed on the first intermediate film 8 with a film thickness of about 50 nm by plasma CVD.

  At this time, the first stopper film 7 is used as a dry etching stopper film when a groove shape to be formed later is formed.

The first intermediate film 8 is a so-called porous low dielectric constant film having a relative dielectric constant lower than that of a silicon oxide film widely used as an interlayer insulating film in order to reduce the parasitic capacitance between wirings. The relative dielectric constant of the film used here is about 2.2, which is a sufficiently low value compared to 3.9 of the silicon oxide film.
In general, in order to reduce the parasitic capacitance between wirings, the lower the relative dielectric constant, the better. However, if the dielectric constant is too low, the mechanical strength as the insulating film becomes weak. For this reason, it is preferable to use a low dielectric constant film having a relative dielectric constant of 3.0 or less in consideration of the low dielectric constant and the balance of mechanical strength as an insulating film.

  Further, the first cap film 9 is a film for preventing the first intermediate film 8 from being peeled off or cracked when performing CMP in the formation of an upper-layer buried wiring to be formed later.

  In the present embodiment, a film in which three films of the first stopper film 7, the first intermediate film 8, and the first cap film 9 are laminated is referred to as an interlayer insulating film 10 as a whole.

  Next, although not shown, a resist pattern is formed on the first cap film 9, and the first cap film 9, the first intermediate film 8, and the first stopper film 7, that is, the interlayer insulating film 10 are formed using the resist pattern as a mask. A wiring trench is formed by dry etching.

Next, as shown in FIG. 3, a barrier metal film 11 made of TaN or TiN is formed on the inner surface of the wiring trench 10a by the PVD method or the atomic chemical vapor deposition method (hereinafter referred to as the ALD method). It is formed with a film thickness of 20-30 nm. At this time, the barrier metal film 11 leaves a groove on the inner surface of the wiring groove 10a.
Further, the copper film 12 is embedded in the inner surface of the groove formed by the barrier metal film 11 with a film thickness of about 300 to 500 nm.

Next, the barrier metal film 11 and the copper film 12 (see FIG. 3) formed outside the wiring trench 10a are removed by CMP, and as shown in FIG. 4, a high-density wiring pattern 13a, a dummy pattern 13b, an isolated wiring pattern 13c and a dummy pattern 13d are formed.
At this time, the high-density wiring pattern 13 a is formed in the portion A of the interlayer insulating film 10, and the isolated wiring pattern 13 c is formed in the portion C of the interlayer insulating film 10. The dummy pattern 13b is formed in a portion B between the portion A and the portion C of the interlayer insulating film 10, and the dummy pattern 13d is formed in a portion D on the right side of the portion C of the interlayer insulating film 10. .
That is, the wiring patterns of the high-density wiring pattern 13a and the isolated wiring pattern 13c are respectively formed in the portion A and the portion C of the interlayer insulating film 10, and are portions including the wiring pattern. On the other hand, only the dummy pattern 13b and the dummy pattern 13d are formed in the portion B and the portion D of the interlayer insulating film 10, respectively, and do not include the wiring pattern.

Here, the high-density wiring pattern 13a formed in the portion A of the interlayer insulating film 10 in FIG. 4 is used for, for example, internal circuit signal transmission of an integrated circuit (hereinafter referred to as an IC), etc. They are arranged with a spacing of about 0.1 μm and between adjacent wirings of about 0.1 μm.
The isolated wiring pattern 13c formed in the portion C of the interlayer insulating film 10 is used, for example, for application of a well voltage at a specific location of the IC, and has a line width of about 0.1 μm.

Here, in FIG. 4, a dummy pattern 13b and a dummy pattern 13d are arranged in a portion B and a portion D that do not include the wiring pattern of the interlayer insulating film 10, respectively. As a result, the density deviation between the wiring patterns of the portions A and C including the wiring pattern of the interlayer insulating film 10 and the dummy patterns of the portions B and D not including the wiring pattern of the interlayer insulating film 10 is The portions A to D are smaller as a whole.
Accordingly, CMP erosion and dishing in forming the embedded wiring can be suppressed.

Hereinafter, a dummy pattern arranging method according to the present embodiment will be described.
FIG. 5 shows a planar structure including portions A and C including the wiring pattern of the interlayer insulating film 10 and portions B and D not including the wiring pattern of the interlayer insulating film 10 in FIG. In this figure, the line width, the number of wirings, the interval, etc. of each wiring pattern and dummy pattern do not correspond to FIG.

As shown in FIG. 5, high-density wiring patterns 13a having a wiring width of 0.1 μm are formed at intervals of 0.1 μm in the portion A of the interlayer insulating film 10 (see FIG. 4). In addition, a dummy pattern 13b having an overall width of about 20 μm is formed in the portion B of the interlayer insulating film 10 and is about 4 μm from the right end of the rightmost high-density wiring pattern 13a of the portion A of the interlayer insulating film 10. Arranged at intervals.
Further, an isolated wiring pattern 13c having a wiring width of 0.1 μm is formed in the portion C of the interlayer insulating film 10, and is arranged at an interval of about 2 μm from the right end of the dummy pattern 13b of the portion B of the interlayer insulating film 10. ing.
Further, a dummy pattern 13d having a total width of about 10 μm is formed in the portion D of the interlayer insulating film 10, and is arranged at an interval of about 2 μm from the right end of the isolated wiring pattern 13c in the portion C of the interlayer insulating film 10. Has been.
That is, in the present embodiment, the portion A and the portion C including the wiring pattern of the interlayer insulating film 10 such as the high-density wiring pattern 13a and the isolated wiring pattern 13c, and the portion B including no wiring pattern of the interlayer insulating film 10 and In the semiconductor device including the interlayer insulating film 10 having the portion D, the dummy patterns 13b and 13d that partition the portion B of the interlayer insulating film 10 and the interlayer insulating film 10 of the portion D into a plurality of isolated regions E are formed.

Here, in the portion B not including the wiring pattern of the interlayer insulating film 10 (see FIG. 4) shown in FIG. 5, the dummy pattern 13b is formed so as to partition the plurality of isolated regions E into a mesh shape (interlayer). The same applies to the dummy pattern 13d in the portion D of the insulating film 10). In this case, the plurality of isolated regions E are arranged at a constant interval in a direction parallel to and perpendicular to the wiring directions of the high-density wiring pattern 13a and the isolated wiring pattern 13c in FIG. 5, that is, the plurality of isolated regions E are fixed. They are arranged in a matrix at intervals.
Further, since the surface of the first cap film 9, that is, the interlayer insulating film 10 is exposed on the surface of the isolated region E (see FIG. 4), the dummy pattern 15 causes the interlayer insulating film 10 to be in a plurality of isolated regions E. It is a dummy pattern to partition.

  As described above, since the dummy patterns 13b and 13d partition the interlayer insulating film 10 into a plurality of isolated regions E, the shear stress on the interlayer insulating film 10 can be relaxed in the CMP for forming the embedded wiring. Further, even in the portion B and the portion D that do not include the wiring pattern of the interlayer insulating film 10, even when cracks or peeling occurs in the interlayer insulating film 10 in the portion partitioned by the isolated region E, the wiring pattern of the interlayer insulating film 10 is changed. It is possible to prevent cracks and peeling from spreading to the included part A and part C.

FIG. 6 shows an enlarged view of the dummy pattern 13b including the isolated region E of the portion B of the interlayer insulating film 10 (see FIG. 4) in FIG. The isolated region E is a square whose side (W) is 3 μm, and is formed in the same shape and size. The line width (L) of the dummy pattern 13b that partitions the isolated region E is all 1 μm.
Although an enlarged view of the portion D of the interlayer insulating film 10 is not shown, it is formed in the same manner as the portion B of the interlayer insulating film 10.

  As described above, the portions B and D that do not include the wiring pattern of the interlayer insulating film 10 are all formed to have the same shape and size of the isolated region E. Since the polishing pressure applied to the insulating film is made uniform, peeling and cracking of the interlayer insulating film due to a local increase in the polishing pressure can be suppressed.

  Further, as shown in FIG. 5, in the portion B and the portion D of the interlayer insulating film 10 (see FIG. 4), each isolated region E is shifted by a half block for each column. With such an arrangement, the interlayer insulating film 10 is structurally stronger than in the case where the shift is not caused to the shear stress applied to the interlayer insulating film 10 in the isolated region E in the CMP for forming the buried wiring. Therefore, peeling and cracking of the interlayer insulating film 10 can be suppressed in the CMP for forming the embedded wiring.

In the present embodiment, the isolated regions E are arranged at a constant interval in a direction parallel to and perpendicular to the wiring directions of the high-density wiring pattern 13a and the isolated wiring pattern 13c in FIG. It was arranged in a matrix at regular intervals.
As a modification of this arrangement method, for example, a regular hexagonal isolated region F is formed as shown in FIG. 7, or a circular isolated region G is formed as shown in FIG. An effect can be obtained.
That is, even in an isolated region having a shape as shown in FIGS. 7 and 8, since the shear stress exerted by CMP on the interlayer insulating film 10 (see FIG. 4) can be reduced in the formation of the buried wiring, the interlayer insulation Separation and cracking of the film can be suppressed. Thus, the shape of the isolated region can be variously modified.

  As shown in FIG. 7, when the isolated region is a regular hexagon, the density of the partitioned isolated region can be made the closest. Therefore, for the purpose of reducing the wiring capacitance, when securing a low dielectric constant film of the same area in the same region, the line width L of the dummy pattern is relatively larger than when forming isolated regions of other shapes. Is possible. Thereby, since the mechanical strength of the dummy pattern can be improved, peeling of the interlayer insulating film and occurrence of cracks can be more effectively suppressed.

Next, as a dummy pattern arrangement method, another modification will be described.
As described above, in FIG. 5, the distance between the rightmost high-density wiring pattern 13a of the portion A of the interlayer insulating film 10 and the dummy pattern 13b of the portion B of the interlayer insulating film 10 is about 4 μm. That is, a region of the interlayer insulating film 10 having a width of about 4 μm exists in the portion A and the portion B of the interlayer insulating film 10.
At this time, in order to reduce the influence of dishing and erosion in the CMP for forming the embedded wiring, the distance between the high-density wiring pattern 13a in the portion A of the interlayer insulating film 10 and the dummy pattern 13b in the portion B of the interlayer insulating film 10 Is preferably as narrow as possible within the range where the pattern can be processed. However, if the space is narrowed by inserting a square isolated region E having a side of 3 μm on the left side of the dummy pattern 13b, the rightmost high-density wiring pattern 13a and the dummy pattern 13b of the portion A of the interlayer insulating film 10 are reduced. As a result, the left-hand side portion overlaps and a desired wiring pattern and dummy pattern cannot be obtained.
Therefore, by inserting an isolated region relatively smaller than the isolated region E on the left side of the dummy pattern 13b, the interval between the high-density wiring pattern 13a and the dummy pattern 13b can be reduced.

FIG. 9 shows an example in which an isolated region H relatively smaller than the isolated region E is added to the left side at equal intervals in the dummy pattern 13b of the portion B of the interlayer insulating film 10 (see FIG. 4) shown in FIG. 4 is a diagram showing an example of the arrangement of dummy patterns in which the distance between the portion A and the portion B of the interlayer insulating film 10 is made small. FIG.
FIG. 10 is an enlarged view of the left end portion of the dummy pattern 13b of the portion B of the interlayer insulating film 10 of FIG. For example, the wiring width (L) of the dummy pattern is 1 μm, the newly added isolated region H is a square with 1 μm on each side (W2), and the isolated region E in the other columns is a square with 3 μm on each side (W1). At this time, the distance between the rightmost high-density wiring pattern 13a and the dummy pattern 13b in the portion A of the interlayer insulating film 10 is 2 μm smaller than that in FIG. 5, and the distance is 2 μm in FIG. .

In other words, in the present embodiment, in FIG. 9, it is formed in the portion B of the interlayer insulating film 10 so as to face the rightmost high-density wiring pattern 13a of the portion A of the interlayer insulating film 10 (see FIG. 4). The isolated region H is formed to be relatively smaller than the isolated region E. By doing so, the distance between the rightmost high-density wiring pattern 13a and the dummy pattern 13b in the portion A of the interlayer insulating film 10 can be reduced.
In this manner, dishing at this location and erosion that occurs in the high-density wiring pattern in the portion A of the interlayer insulating film 10 can be effectively suppressed.

  In the present embodiment, the isolated region H is formed so as to be a square having a side of 1 μm. However, as described above, in order to suppress the influence of dishing and erosion in the CMP of the embedded wiring, a pattern processing range is possible. In this case, it may be adjusted as appropriate. Alternatively, a column having a relatively small isolated area may be formed in another column, such as a column at the right end.

  Thereafter, although not shown, vias, wiring layers, and the like are formed on the high-density wiring pattern 13a, the dummy pattern 13b, the isolated wiring pattern 13c, and the dummy pattern 13d as necessary. Since these steps are known in this field, a detailed description is omitted.

  In the present embodiment, the interlayer insulating film 10 is an example of a three-layer film including the first intermediate film 8 which is a low dielectric constant film having a relative dielectric constant of 3 or less. May be a single-layer film of a low dielectric constant film having a relative dielectric constant of 3 or less. The first stopper film 7 or the first cap film 9 may be a low dielectric constant film having a relative dielectric constant of 3 or less.

As described above, in the present embodiment, in a semiconductor device including an interlayer insulating film having a portion including a wiring pattern and a portion not including a wiring pattern, the interlayer insulating film in a portion not including the wiring pattern is provided. A dummy pattern is formed so as to partition into a plurality of mesh-like isolated regions.
In addition, the shape and size of the isolated regions are all the same and are formed in a matrix.
Furthermore, the isolated region at the position facing the wiring pattern is formed to be relatively smaller than the other isolated regions.

In this way, by forming a dummy pattern that partitions a portion of the interlayer insulating film that does not include the wiring pattern into a plurality of network-like isolated regions, the shear stress on the interlayer insulating film can be reduced in the CMP for forming the embedded wiring. It is possible to suppress the peeling and cracking of the interlayer insulating film. Further, even when a crack or peeling occurs in the interlayer insulating film in a portion not including the wiring pattern, it is possible to prevent the crack or peeling from spreading to the portion including the wiring pattern.
Further, by forming the isolated regions in the same shape and size in the form of a matrix, the polishing pressure applied to the insulating film is made uniform in the CMP for forming the embedded wiring, so that the interlayer insulation is increased by increasing the local polishing pressure. Separation and cracking of the film can be suppressed.
Furthermore, local dishing and erosion can be more effectively suppressed by forming an isolated region at a position facing the wiring pattern relatively smaller than other isolated regions.
In addition, a dummy pattern is arranged in a portion not including the wiring pattern of the interlayer insulating film so that the total density of the wiring pattern and the dummy pattern is made uniform on the substrate. CMP erosion and dishing caused by wiring width and pattern density difference can be suppressed.

By forming in this way, it is possible to suppress the occurrence of peeling and cracking of the interlayer insulating film in the CMP for forming the buried wiring, and even if cracks and peeling occur, the portion including the wiring pattern of the interlayer insulating film can be suppressed. It is possible to prevent the cracks and peeling from spreading.
In addition, variations in the film thickness of the wiring and the interlayer insulating film due to CMP erosion and dishing due to the difference in density of the wiring width and pattern can be suppressed. Therefore, the problem of increasing the wiring resistance and increasing the inter-wiring parasitic capacitance due to the non-uniform thickness of the wiring and the interlayer insulating film depending on the wiring density and the wiring width is solved. Therefore, a highly reliable semiconductor device can be obtained.

Embodiment 2. FIG.
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS.
In the second embodiment, the process from the step of forming element isolation 2 on the main surface of the semiconductor substrate 1 to the formation of the high-density wiring pattern 13a, dummy pattern 13b, isolated wiring pattern 13c, and dummy pattern 13d (FIG. 1 to 4) are formed by the same method as the steps shown in the first embodiment.

Next, as shown in FIG. 11, an anti-diffusion film 14 made of SiC is formed on the first cap film 9 by plasma CVD as an etching stopper film for dummy vias and a copper anti-diffusion film to be formed later. It is formed with a film thickness. Further, a via insulating film 14a made of a silicon oxide film is formed on the diffusion preventing film 14 with a film thickness of about 200 nm by plasma CVD.
Next, in each of the portions A, B, C, and D of the interlayer insulating film 10, the high-density wiring pattern 13a, the dummy pattern 13b, the isolated wiring pattern 13c, and the dummy pattern 13d (see FIG. 4). A via 15a, a dummy via 15b, a via 15c, and a dummy via 15d are formed thereon.

  Next, as shown in FIG. 12, a second stopper film 16 made of SiC is formed on the via insulating film 14a, the via 15a, the dummy via 15b, the via 15c, and the dummy via 15d to a thickness of about 50 nm by plasma CVD. Form. Further, a second intermediate film 17 made of a low dielectric constant film such as an organic siloxane film is formed on the second stopper film 16 with a film thickness of about 200 nm by the SOD method. Further, a second cap film 18 made of a silicon oxide film is formed on the second intermediate film 17 with a film thickness of about 50 nm by plasma CVD.

  At this time, the second stopper film 16 is used as a film for preventing diffusion of metal contained in a metal wiring to be formed later.

The second intermediate film 17 is a so-called porous low dielectric constant film having a relative dielectric constant lower than that of a silicon oxide film widely used as an interlayer insulating film in order to reduce the parasitic capacitance between wirings. The relative dielectric constant of the film used here is about 2.2, which is a sufficiently low value compared to 3.9 of the silicon oxide film.
In general, in order to reduce the parasitic capacitance between wirings, the lower the relative dielectric constant, the better. However, if the dielectric constant is too low, the mechanical strength as the insulating film becomes weak. For this reason, it is preferable to use a low dielectric constant film having a relative dielectric constant of 3.0 or less in consideration of the low dielectric constant and the balance of mechanical strength as an insulating film.

  Furthermore, the second cap film 18 is a film for preventing the second intermediate film 17 from being peeled off or cracked when performing CMP in the formation of an upper-layer buried wiring to be formed later.

  In the present embodiment, the laminated film (multilayer film) of the three films of the second stopper film 16, the second intermediate film 17, and the second cap film 18 is referred to as an upper insulating film 19 as a whole. I will do it.

  Further, although not shown, a resist pattern is formed on the second cap film 18, and the second cap film 18, the second intermediate film 17, and the second stopper film 16, that is, the upper insulating film 19 are dried using the resist pattern as a mask. Etching is performed to form wiring trenches.

Next, as shown in FIG. 13, an upper barrier metal film 20 made of TaN or TiN is formed on the inner surface of the wiring trench 19a to a thickness of 20 to 30 nm by the PVD method or the ALD method. At this time, the upper barrier metal film 20 leaves a groove on the inner surface of the wiring groove 19a.
Furthermore, the upper copper film 21 is embedded in the inner surface of the groove formed by the upper barrier metal film 20 with a film thickness of about 300 to 500 nm.

  Next, as shown in FIG. 14, the upper barrier metal film 20 and the upper copper film 21 (see FIG. 13) formed outside the wiring groove 19a are removed by CMP, and the upper high-density wiring pattern 22a and the upper layer dummy are removed. A pattern 22b, an upper layer isolated wiring pattern 22c, and an upper layer dummy pattern 22d are formed.

  At this time, in the portion A of the upper insulating film 19, the upper high-density wiring pattern 22a formed on the upper insulating film 19 passes through the high-density wiring pattern 13a (see FIG. 4) formed on the interlayer insulating film 10 and the via 15a. It is connected. Similarly, in the portion C of the upper insulating film 19, the upper isolated wiring pattern 22c formed in the upper insulating film 19 is connected to the isolated wiring pattern 13c (see FIG. 4) formed in the interlayer insulating film 10 via the via 15c. ing.

  In the portion B of the upper insulating film 19, the upper dummy pattern 22b formed on the upper insulating film 19 is connected to the dummy pattern 13b (see FIG. 4) formed on the interlayer insulating film 10 via the dummy via 15b. Similarly, in the portion D of the upper insulating film 19, the upper dummy pattern 22d formed on the upper insulating film 19 is connected to the dummy pattern 13d (see FIG. 4) formed on the interlayer insulating film 10 through the dummy via 15d. .

Next, a method for arranging dummy patterns in the present embodiment will be described.
FIG. 15 shows a planar structure of portions A and C which are portions including the wiring pattern of the upper insulating film 19 and portions B and D which are portions not including the wiring pattern of the upper insulating film 19 in FIG. In this figure, the line width, the number of wirings, the interval, etc. of each wiring pattern and dummy pattern do not correspond to FIG.

As shown in FIG. 15, in the portion A of the upper insulating film 19 (see FIG. 14), the upper layer high-density wiring pattern 22a having a wiring width of 0.1 μm is spaced by 0.1 μm, and the high-density wiring pattern shown in FIG. It is formed so as to overlap from above 13a. The upper layer high-density wiring pattern 22a is connected to the high-density wiring pattern 13a (see FIG. 5) through the via 15a.
Further, an upper layer dummy pattern 22b having a total width of about 20 μm is formed in the portion B of the upper layer insulating film 19, and it is approximately from the right end of the rightmost upper layer high-density wiring pattern 22a of the portion A of the upper layer insulating film 19. They are arranged with an interval of 4 μm. The upper layer dummy pattern 22b is connected to the dummy pattern 13b (see FIG. 5) through the dummy via 15b.
Further, an upper isolated wiring pattern 22c having a wiring width of 0.1 μm is formed in the portion C of the upper insulating film 19, and is spaced by about 2 μm from the right end of the upper dummy pattern 22b of the portion B of the upper insulating film 19. Has been placed. The upper layer isolated wiring pattern 22c is connected to the isolated wiring pattern 13c (see FIG. 5) through the via 15c.
Further, an upper layer dummy pattern 22d having an overall width of about 10 μm is formed in the portion D of the upper insulating film 19, and is spaced by about 2 μm from the right end of the upper isolated wiring pattern 22c of the portion C of the upper insulating film 19. Are arranged. The upper layer dummy pattern 22d is connected to the dummy pattern 13d (see FIG. 5) through the dummy via 15d.

14 and 15, in the portion B of the upper insulating film 19, the upper dummy pattern 22 b formed in the upper insulating film 19 is connected to the dummy via 15 b, and the dummy via 15 b is a dummy pattern 13 b formed in the interlayer insulating film 10 ( (See FIG. 4). Thus, the upper layer dummy pattern 22b of the portion B of the upper layer insulating film 19 is connected to the dummy via 15b and the dummy pattern 13b, so that the upper layer dummy pattern 22b and the isolated region E partitioned by the dummy pattern are reinforced. Has been.
The same applies to the portion D of the upper insulating film 19, and since the upper dummy pattern 22d is connected to the dummy via 15d and the dummy pattern 13d, the upper dummy pattern 22d and the isolated region E partitioned by the dummy pattern are separated. It is reinforced.
By reinforcing in this way, the upper insulating film 19 is peeled off in the CMP for forming the upper high-density wiring pattern 22a, the upper dummy pattern 22b, the upper isolated wiring pattern 22c, and the upper dummy pattern 22d shown in FIG. And cracks can be more effectively suppressed.

  In the present embodiment, the dummy pattern formed in the lower interlayer insulating film 10 and the dummy pattern formed in the upper upper insulating film 19 have the same size and shape as projected. Although described, it is not necessary to have the same shape and size that overlap each other.

  As a modification of the present embodiment, the upper layer dummy pattern 22b is connected to a wiring pattern other than the dummy pattern 13b via the dummy via 15b or connected to the dummy via 15b even if it is not connected to any pattern. Since it is reinforced by doing, it has the same effect.

In the present embodiment, an upper insulating film 19 (see FIG. 14) in which another pattern is formed is formed in the upper layer of the interlayer insulating film 10, and the dummy pattern 13b and the upper insulating film formed in the interlayer insulating film 10 are formed. A dummy via 15b is formed to connect the upper layer dummy pattern 22b formed in FIG.
As a modified example, another insulating film in which another pattern is formed is formed under the interlayer insulating film 10 in which the dummy pattern 13b is formed, and the dummy pattern 13b is connected to the other pattern formed in the other insulating film. A via may be formed.
In this case, the dummy pattern formed in the interlayer insulating film 10 and the interlayer insulating film 10 partitioned by the dummy pattern are reinforced.

Here, in the portion B not including the wiring pattern of the upper insulating film 19 shown in FIG. 15, the upper dummy pattern 22b is formed so as to partition the plurality of isolated regions E into a mesh shape (the upper insulating film 19 The same applies to the upper layer dummy pattern 22d in the portion D). In this case, the plurality of isolated regions E are arranged at a constant interval in a direction parallel to and perpendicular to the wiring direction of the upper layer high-density wiring pattern 22a and the upper layer isolated wiring pattern 22c in FIG. They are arranged in a matrix at regular intervals.
Further, since the surface of the second cap film 18, that is, the upper insulating film 19 is exposed on the surface of the isolated region E (see FIG. 14), the upper layer dummy patterns 22b and 22d form the upper insulating film 19 with a plurality of isolated layers. This is a dummy pattern that partitions the region E.

  As described above, since the upper layer dummy patterns 22b and 22d partition the upper layer insulating film 19 into a plurality of isolated regions E, the shear stress on the upper layer insulating film 19 can be relieved in the CMP for forming the embedded wiring. . In addition, in the portion B and the portion D that do not include the wiring pattern of the upper insulating film 19, even when cracks or peeling occur in the upper insulating film 19 that is partitioned by the isolated region E, the wiring pattern of the upper insulating film 19 is changed. It is possible to prevent cracks and peeling from spreading to the included part A and part C.

  FIG. 16 is an enlarged view of the upper layer dummy pattern 22b including the isolated region E of the portion B of the upper layer insulating film 19 (see FIG. 14) in FIG. The isolated region E is a square whose side (W) is 3 μm, and is formed in the same shape and size. Further, the line width (L) of the upper layer dummy pattern 22b partitioning the isolated region E is all 1 μm.

Further, the dummy pattern 13b (see FIG. 4) formed in the interlayer insulating film 10 in the portion B of the upper insulating film 19 and the upper dummy pattern 22b (see FIG. 14) formed in the upper insulating film 19 are connected by the dummy via 15b. ing. The dummy via 15b is formed with a via diameter of about 0.75 μm.
Although not shown in the drawing, the enlarged view and dimensions of the portion D of the upper insulating film 19 are the same as those of the portion B of the upper insulating film 19, and detailed description thereof is omitted.

  As described above, the portions B and D that do not include the wiring pattern of the upper insulating film 19 are all formed to have the same shape and size of the isolated region E. Since the polishing pressure applied to the insulating film is made uniform, peeling and cracking of the interlayer insulating film due to a local increase in the polishing pressure can be suppressed.

  Further, as shown in FIG. 15, in the portion B and the portion D of the upper insulating film 19 (see FIG. 14), the isolated regions E are shifted by a half block for each column. With this arrangement, the upper insulating film 19 is compared to the case where the shear stress applied to the upper insulating film 19 in the isolated region E is not shifted in the CMP for forming the embedded wiring, as in the first embodiment. Is structurally strong. Therefore, peeling and cracking of the upper insulating film 19 can be suppressed in the CMP for forming the embedded wiring.

In the present embodiment, the isolated region E has a plurality of intervals in a direction parallel to and perpendicular to the wiring direction of the upper layer high-density wiring pattern 22a and the upper layer isolated wiring pattern 22c in FIG. The isolated regions E are arranged in a matrix at regular intervals.
In place of this, as shown in FIG. 17, in the portion B (see FIG. 14) of the upper insulating film 19, a dummy pattern 13b having a hexagonal isolated region F is formed in the interlayer insulating film 10 (see FIG. 4). An upper layer dummy pattern 22b having a hexagonal isolated region F is formed on the upper layer insulating film 19 (see FIG. 14) so as to overlap with the dummy pattern 13b, and the lower layer dummy pattern 13b and the upper layer dummy pattern are formed. 22b may be connected by a dummy via 15b. The same applies to the portion D of the upper insulating film 19.
That is, even in an isolated region having a shape as shown in FIGS. 17 and 18, since the shear stress of CMP exerted on the upper insulating film 19 can be relaxed in the formation of the embedded wiring, peeling or cracking of the upper insulating film is possible. Can be suppressed. Thus, the shape of the isolated region can be variously modified.

  As shown in FIG. 17, when the isolated area is a regular hexagon, the density of the partitioned isolated areas can be made the closest. Therefore, for the purpose of reducing the wiring capacitance, when securing a low dielectric constant film of the same area in the same region, the line width L of the dummy pattern is relatively larger than when forming isolated regions of other shapes. Is possible. Thereby, since the mechanical strength of the dummy pattern can be improved, peeling of the upper insulating film and occurrence of cracks can be more effectively suppressed.

Next, as a dummy pattern arrangement method, another modification will be described.
As described above, in FIG. 15, the distance between the uppermost high-density wiring pattern 22a at the right end of the portion A of the upper insulating film 19 (see FIG. 14) and the upper dummy pattern 22b of the portion B of the upper insulating film 19 is about 4 μm. It is. In other words, the region of the upper insulating film 19 having a width of about 4 μm exists in the portion A and the portion B of the upper insulating film 19.
At this time, in order to reduce the influence of dishing and erosion in CMP for forming the embedded wiring, the upper layer high-density wiring pattern 22a of the portion A of the upper insulating film 19 and the upper dummy pattern 22b of the portion B of the upper insulating film 19 It is preferable to keep the interval as small as possible within a range where the pattern can be processed. However, if the space is narrowed by inserting a square isolated region E having a side of 3 μm on the left side of the upper layer dummy pattern 22b, the rightmost upper layer high density wiring pattern 22a and the upper layer of the portion A of the upper layer insulating film 19 are reduced. Since the left portion of the dummy pattern 22b overlaps, a desired wiring pattern and dummy pattern cannot be obtained.
Thus, by inserting an isolated region relatively smaller than the isolated region E on the left side of the upper layer dummy pattern 22b, the interval between the upper layer high-density wiring pattern 22a and the upper layer dummy pattern 22b can be reduced.

FIG. 19 shows an upper region of the upper layer dummy pattern 22b of the upper insulating film 19 (see FIG. 14) shown in FIG. FIG. 6 is a diagram showing an example of arrangement of dummy patterns in which the distance between the portion A and the portion B of the upper insulating film 19 is made small.
20 is an enlarged view of the left end portion of the upper layer dummy pattern 22b of the portion B of the upper insulating film 19 (see FIG. 14) in FIG. For example, the wiring width (L) of the dummy pattern is 1 μm, the newly added isolated region H is a square with 1 μm on each side (W2), and the isolated region E in the other columns is a square with 3 μm on each side (W1). At this time, the distance between the uppermost high-density wiring pattern 22a and the upper-layer dummy pattern 22b at the rightmost end of the portion A of the upper insulating film 19 is 2 μm smaller than that in FIG. 15, and the distance is 2 μm in FIG. Yes.

That is, also in the present embodiment, in FIG. 19, the isolated region H facing the uppermost high-density wiring pattern 22 a at the right end of the portion A of the upper insulating film 19 (see FIG. 14) is relative to the isolated region E. It was made to form small. By doing so, the distance between the uppermost high-density wiring pattern 22a at the right end of the portion A of the upper insulating film 19 and the upper dummy pattern 22b can be reduced.
In this manner, dishing at this location and erosion that occurs in the high-density wiring pattern in the portion A of the upper insulating film 19 can be effectively suppressed.

  In the present embodiment, the isolated region H is a square having a side of 1 μm. However, as described above, in order to suppress the influence of dishing and erosion in the CMP of the embedded wiring, in the range where pattern processing is possible, You may make it adjust suitably. Alternatively, a column having a relatively small isolated area may be formed in another column, such as a column at the right end.

  Thereafter, although not shown, vias, wiring layers, and the like are formed on the upper layer high-density wiring pattern 22a, the upper layer isolated wiring pattern 22c, the upper layer dummy pattern 22b, and the upper layer dummy pattern 22d as necessary. Since these steps are known in this field, a detailed description is omitted.

  In the present embodiment, the upper insulating film 19 is an example of a three-layer film including the second intermediate film 17 which is a low dielectric constant film having a relative dielectric constant of 3 or less. May be a single-layer film of a low dielectric constant film having a relative dielectric constant of 3 or less. The second stopper film 16 or the second cap film 18 may be a low dielectric constant film having a relative dielectric constant of 3 or less.

As described above, in the present embodiment, in a semiconductor device including an interlayer insulating film having a portion including a wiring pattern and a portion not including a wiring pattern, the interlayer insulating film in a portion not including the wiring pattern is provided. A dummy pattern is formed so as to partition into a plurality of mesh-like isolated regions.
Further, the shape and size of the isolated regions are all the same and are formed in a matrix.
Further, the isolated region at a position facing the wiring pattern is formed to be relatively smaller than other isolated regions.

  Further, in a semiconductor device having an interlayer insulating film having a portion including a wiring pattern and a portion not including a wiring pattern, a dummy pattern is formed to partition the interlayer insulating film in a portion not including the wiring pattern into a plurality of isolated regions. Furthermore, a dummy pattern for partitioning the upper insulating film formed on the upper layer of the interlayer insulating film into a plurality of isolated regions is formed, and these dummy patterns are connected via dummy vias.

In this way, by forming a dummy pattern that divides a portion of the interlayer insulating film that does not include the wiring pattern into a plurality of isolated regions, the shear stress on the interlayer insulating film can be relieved in the CMP for forming the embedded wiring. The insulating film can be prevented from peeling and cracking. Further, even when a crack or peeling occurs in the interlayer insulating film in a portion not including the wiring pattern, it is possible to prevent the crack or peeling from spreading to the portion including the wiring pattern.
Further, by forming the isolated regions in the same shape and size in the form of a matrix, the polishing pressure applied to the insulating film is made uniform in the CMP for forming the embedded wiring, so that the interlayer insulation is increased by increasing the local polishing pressure. Separation and cracking of the film can be suppressed.
Furthermore, local dishing and erosion can be more effectively suppressed by forming an isolated region at a position facing the wiring pattern relatively smaller than other isolated regions.

  In addition, a dummy pattern is arranged in a portion not including the wiring pattern so that the total density of the wiring pattern and the dummy pattern is made uniform on the substrate. It is possible to suppress erosion and dishing of CMP due to the difference in density between the two.

  Further, since the upper insulating film is reinforced by connecting the upper insulating film to the dummy via, in the CMP for forming the embedded wiring formed in the upper insulating film, the peeling of the upper insulating film and the generation of cracks are more effectively performed. Can be suppressed.

By forming in this way, it is possible to suppress the occurrence of peeling and cracking of the interlayer insulating film and the upper insulating film formed in the upper layer in the CMP for forming the buried wiring. Even when cracks and peeling occur, the wiring It is possible to prevent cracks and peeling from spreading to the portion including the pattern.
In addition, variations in the film thickness of the wiring and the interlayer insulating film due to CMP erosion and dishing due to the difference in density of the wiring width and pattern can be suppressed. Therefore, the problem of increasing the wiring resistance and increasing the inter-wiring parasitic capacitance due to the non-uniform thickness of the wiring and the interlayer insulating film depending on the wiring density and the wiring width is solved. Therefore, a highly reliable semiconductor device can be obtained.

Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 1 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 1 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 1 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 1 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 1 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 1 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 1 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. Sectional drawing which shows the manufacturing method of the semiconductor device of Embodiment 2 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 2 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 2 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 2 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 2 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 2 of this invention. The top view which shows arrangement | positioning of the dummy pattern of Embodiment 2 of this invention.

Explanation of symbols

  1 semiconductor substrate, 7 first stopper film, 8 first intermediate film, 9 first cap film, 10 interlayer insulating film, 11a barrier metal, 12a buried copper film, 13a high density wiring pattern, 13b dummy pattern, 13c isolated wiring pattern 13d dummy pattern, 14a via insulating film, 15a via, 15b dummy via, 15c via, 15d dummy via, 16 second stopper film, 17 second intermediate film, 18 second cap film, 19 upper insulating film, 20a upper barrier metal, 21a Upper layer embedded copper film, 22a Upper layer high-density wiring pattern, 22b Upper layer dummy pattern, 22c Upper layer isolated pattern, 22d Upper layer dummy pattern

Claims (8)

In a semiconductor device including an interlayer insulating film having a portion including a wiring pattern and a portion not including a wiring pattern on a substrate,
A semiconductor device, wherein a dummy pattern is formed to partition a portion of the interlayer insulating film not including the wiring pattern into a plurality of isolated regions.   2. The semiconductor device according to claim 1, wherein the dummy pattern is formed in a net shape having the plurality of isolated regions in a net.   3. The semiconductor device according to claim 1, wherein the plurality of isolated regions have the same shape and size.   The semiconductor device according to claim 1, wherein the plurality of isolated regions are arranged in a matrix at regular intervals.   5. The semiconductor device according to claim 1, wherein among the plurality of isolated regions, an isolated region at a position facing the wiring pattern is formed to be relatively small.   6. The semiconductor device according to claim 1, further comprising another insulating film in which another pattern is formed in an upper layer or a lower layer of the interlayer insulating film, and a dummy via connecting the dummy pattern and the other pattern. The semiconductor device according to any one of the above.   The interlayer insulating film is a single layer film of a low dielectric constant film having a relative dielectric constant of 3 or less, or a multilayer film including at least one low dielectric constant film having a relative dielectric constant of 3 or less. The semiconductor device according to claim 1.   The semiconductor device according to claim 7, wherein the low dielectric constant film is a porous film.

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