JP2010004085A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique that suppresses the propagation of cracking generated at the time of dicing to improve reliability in semiconductor device even in the semiconductor device using a low-k film as an interlayer insulating film. <P>SOLUTION: Dummy vias 125, 135, 145, 155, and 165 are formed in each layer on dicing region sides. The vias 125, 135, 145, 155, and 165 are formed so as to be disposed at equal distances vertically and horizontally or zigzag as viewed from the top face. Even if cracking occurs at the dicing, the cracking propagating up to a seal ring section 190 is suppressed by the vias 125, 135, 145, 155, and 165. This consequently improves moisture absorption resistance in circuit formation region, thereby preventing deterioration in reliability. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a seal ring which is a protective structure for a semiconductor device.

  In order to protect the circuit formation region of the semiconductor device from the influence of moisture and ions from the ambient atmosphere, a seal ring or die edge seal is provided inside the dicing line, that is, near the edge of the chip (die). A protective structure called a guard ring is provided. The seal ring is formed by a wiring layer and contacts similar to the circuit formation region, and is formed so as to surround the circuit formation region of the semiconductor device.

  The presence of the seal ring protects the circuit formation region of the semiconductor device from the influence of moisture and ions from the ambient atmosphere, and can stabilize the characteristics of the semiconductor device over a long period of time.

  The seal ring also has an effect of suppressing the occurrence of cracks in the circuit formation region when dicing the dicing region. When dicing, cracks may occur in the dicing area, but since a seal ring exists between the dicing area and the circuit forming area, the crack is prevented from reaching the circuit forming area. is there.

  For example, in Patent Document 1, a seal ring is formed, and a plurality of dummy patterns are provided in a circuit formation region. In addition, an invention that can improve the flatness of a chip edge portion in a flattening process by a CMP (Chemical Mechanical Polishing) method is disclosed.

JP 2002-208676 A

  By the way, in recent years, as the structure of semiconductor devices is miniaturized, highly integrated, and the operation speed is increased, the importance of reducing the resistance of wiring is increasing. Accordingly, Cu (copper) having a relatively small resistance is often used as a wiring material. That is, the number of cases in which copper is also used in the above seal ring structure is increasing. In addition, a so-called Low-k film (k <3.0) having a low relative dielectric constant k is often used as an interlayer insulating film.

  When such a Low-k film is used as an interlayer insulating film, there is a problem that cracks generated during dicing easily reach the circuit formation region beyond the seal ring and adversely affect the circuit formation region. Even if the crack does not reach the circuit formation region, if it reaches the seal ring, there arises a problem of deteriorating the moisture absorption resistance of the semiconductor device.

  Therefore, the present invention provides a technique for improving the reliability of a semiconductor device by suppressing cracks generated during dicing from reaching a seal ring even when a low-k film is used as an interlayer insulating film.

  A semiconductor device according to the present invention includes a first interlayer insulating film having a relative dielectric constant of 3 or less, a second interlayer insulating film formed on the first interlayer insulating film and having a relative dielectric constant of 3 or less, and a circuit of a semiconductor chip A seal ring formed in the first and second interlayer insulating films so as to surround a formation region, and a plurality of dummy patterns formed in a dicing region of the semiconductor chip. Each of the plurality of dummy patterns includes a first dummy metal formed in the first interlayer insulating film, a second dummy metal formed in the second interlayer insulating film, and the second interlayer insulating film And a dummy via for connecting the first dummy metal and the second dummy metal. The seal ring is disposed in the vicinity of the edge portion of the semiconductor chip, and the dicing region is disposed outside the seal ring. The plurality of first dummy metals, the plurality of second dummy metals, and the plurality of dummy vias are disposed so as to surround the seal ring. The dummy vias are arranged along a plurality of rows in a plan view, and the dummy vias arranged in adjacent rows are arranged in a staggered manner by being alternately arranged.

  In the present invention, a dummy pattern is formed on the dicing region side of the semiconductor chip so as to surround the seal ring portion. Therefore, even if a crack occurs during dicing, the progress of the crack is prevented by the dummy pattern, and the crack can be prevented from reaching the seal ring portion. Moreover, since the dummy vias arranged in adjacent rows are alternately arranged, the possibility of cracks being transmitted between the dummy patterns can be further reduced. As a result, propagation of cracks that occur during dicing can be further suppressed.

1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment. 1 is a top view showing a configuration of a semiconductor device according to a first embodiment. 6 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a second embodiment. FIG. 6 is a top view showing a configuration of a semiconductor device according to a second embodiment. FIG. 10 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment. FIG. 10 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment. FIG. 10 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment. FIG. 10 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment. FIG. 10 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment. FIG. 10 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment. FIG. 10 is a diagram for explaining a manufacturing process for the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a third embodiment. FIG. 6 is a top view illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 6 is a cross-sectional view showing a configuration of a semiconductor device according to a fourth embodiment. FIG. 6 is a top view illustrating a configuration of a semiconductor device according to a fourth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a fifth embodiment. FIG. 10 is a top view showing a configuration of a semiconductor device according to a fifth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a sixth embodiment. FIG. 10 is a top view showing a configuration of a semiconductor device according to a sixth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a seventh embodiment. FIG. 10 is a top view showing a configuration of a semiconductor device according to a seventh embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to an eighth embodiment. FIG. 10 is a top view showing a configuration of a semiconductor device according to an eighth embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a semiconductor device according to a ninth embodiment. FIG. 10 is a top view showing a configuration of a semiconductor device according to a ninth embodiment. FIG. 10 is a cross-sectional view showing a configuration of a semiconductor device according to a tenth embodiment. FIG. 16 is a top view showing a configuration of a semiconductor device according to a tenth embodiment. FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to an eleventh embodiment. FIG. 38 is a top view showing a configuration of a semiconductor device according to an eleventh embodiment. FIG. 22 is a cross-sectional view showing a configuration of a semiconductor device according to a twelfth embodiment. FIG. 38 is a top view showing a configuration of a semiconductor device according to a twelfth embodiment.

<Embodiment 1>
FIG. 1 is a diagram showing the configuration of the semiconductor device according to the first embodiment, and is an enlarged cross-sectional view of a region where a seal ring is formed. FIG. 2 corresponds to a top view taken along line A1-A1 of FIG. 1 corresponds to a cross-sectional view taken along line B1-B1 of FIG. A circuit forming area is present on the right side of the area shown in FIG. 1, and a dicing area is present on the left side.

  Here, semiconductor chips are arranged vertically and horizontally on the semiconductor wafer, and each semiconductor chip is divided by a dicing region. A circuit formation region is formed in the semiconductor chip, and a seal ring is disposed around the circuit formation region. That is, a seal ring is formed so as to surround the circuit formation region. FIG. 1 shows a view corresponding to the end view of the semiconductor chip and corresponding to the vicinity of the edge portion of the semiconductor chip (region where the seal ring is formed).

  In the figure, the circuit portion of the semiconductor device is not shown. FIG. 1 shows the case of a semiconductor device having a six-layer Cu wiring and a one-layer Al wiring structure.

  An interlayer insulating film 113 is formed on the silicon substrate 101 on which the trench isolation 102 is formed. The trench isolation (element isolation film) 102 is formed with an oxide film of 300 nm, for example. The interlayer insulating film 113 includes an interlayer insulating film 113a and a first wiring interlayer insulating film 113b. The interlayer insulating film 113a is formed of, for example, a USG (Undoped Silicon Glass) film of 500 nm, and the first wiring interlayer insulating film 113b is formed of, for example, a plasma TEOS (Tetrahethyl orthosilicate) film of 300 nm.

  Slit W (tungsten) plugs 114 are formed in the interlayer insulating film 113a. In the W plug 114, a barrier metal having a TiN (titanium nitride) / Ti (titanium) structure is formed and W is buried. A wiring layer 111 is formed on the W plug 114. In the wiring layer 111, Cu is embedded in a barrier metal having a Ta (tantalum) / TaN (tantalum nitride) structure.

  A Cu diffusion prevention insulating film (also referred to as an etching stopper film or a liner film; hereinafter simply referred to as a diffusion prevention film) 122 is formed on the interlayer insulating film 113. An interlayer insulating film 123 is formed on the diffusion prevention film 122. In the interlayer insulating film 123, a plurality of dummy vias 125 and slit-like slit vias 124 are formed. The slit via 124 is formed on the wiring layer 111. The dummy via 125 is formed on the dicing region side.

  A diffusion prevention film 132 is formed on the interlayer insulating film 123. An interlayer insulating film 133 in which a plurality of dummy vias 135 and slit-like slit vias 134 are formed is formed on the diffusion prevention film 132. The slit via 134 is formed on the slit via 124. The dummy via 135 is formed on the dummy via 125.

  A diffusion prevention film 142 is formed on the interlayer insulating film 133. An interlayer insulating film 143 in which a plurality of dummy vias 145 and slit-like slit vias 144 are formed is formed on the diffusion prevention film 142. The slit via 144 is formed on the slit via 134. The dummy via 145 is formed on the dummy via 135.

  A diffusion prevention film 152 is formed on the interlayer insulating film 143. On the diffusion prevention film 152, an interlayer insulating film 153 in which a plurality of dummy vias 155 and slit-like slit vias 154 are formed is formed. The slit via 154 is formed on the slit via 144. The dummy via 155 is formed on the dummy via 145.

  A diffusion prevention film 162 is formed on the interlayer insulating film 153. An interlayer insulating film 163 in which a plurality of dummy vias 165 and slit-like slit vias 164 are formed is formed on the diffusion prevention film 162. The slit via 164 is formed in contact with the slit via 154. Further, the dummy via 165 is formed in contact with the dummy via 155.

  As shown in FIG. 2, the diameter of the fifth-layer dummy vias 155 is, for example, 0.14 μm, and is arranged at regular intervals vertically and horizontally at, for example, a 1 μm pitch. The dummy vias formed from the second layer to the fourth layer are similarly formed. The diameters of the dummy vias 165 are 0.28 μm, and are arranged at regular intervals vertically and horizontally at a pitch of 2 μm, for example.

  The diffusion prevention films 122, 132, 142, 152, 162 are made of, for example, a SiC (silicon carbide) film (k to 4.8) 50 nm. The interlayer insulating films 123, 133, 143, and 153 are made of SiOC (carbon-containing silicon oxide film) (k to 2.8), which is a low-k film, and has a thickness of 500 nm. The interlayer insulating film 163 is a USG film (k to 4.1) and is formed with a thickness of about 1000 nm.

  In the slit vias 124, 134, 144, 154, 164 and the dummy vias 125, 135, 145, 155, 165, Cu is embedded in a barrier metal having a Ta (tantalum) / TaN (tantalum nitride) structure.

  A passivation film 173 is formed on the interlayer insulating film 163. The passivation film 173 is formed of, for example, a plasma SiN (silicon nitride) film (k to 7) of 500 nm. A hole 174 is formed in the first passivation film 173. An Al (aluminum) wiring layer 171 is formed on the first passivation film 173.

  The Al wiring layer 171 is formed of an AL (aluminum) laminated film including a barrier metal TiN / Ti film. The thickness of the Al wiring layer 171 is 1000 nm. A second passivation film 183 is formed so as to cover the Al wiring layer 171. The second passivation film 183 is formed with a thickness of 1000 nm using, for example, a plasma SiN film.

  The W plug 114, the wiring layer 111, the slit vias 124, 134, 144, 154, 164, and the Al wiring layer 171 form a seal ring portion 190.

  The dummy vias 125, 135, 145, 155, and 165 are disposed around the seal ring portion 190. That is, the dummy vias 125, 135, 145, 155, 165 (dummy pattern) are formed so as to surround the seal ring portion 190.

  3 to 9 are diagrams showing manufacturing steps of the semiconductor device shown in FIG. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to these drawings.

  In the process shown in FIG. 3, for example, a trench isolation 102 having a thickness of 300 nm is formed on the silicon substrate 101 by STI (Shallow Trench Isolation). Next, an interlayer insulating film 113a is formed, for example, by depositing a high density plasma (HDP) oxide film having a thickness of 800 nm and polishing it by a CMP (Chemical Mechanical Polishing) method to a thickness of 300 nm. Then, a slit-like opening is formed in the interlayer insulating film 113a at a position corresponding to the seal ring 190 by dry etching using a resist mask having a width of 0.10 μm, for example. At this time, the silicon substrate 101 and the interlayer insulating film 113a are etched under conditions having a sufficient etching selectivity.

  Subsequently, a barrier metal (not shown) in which, for example, 20 nm each of TiN and Ti are deposited is formed by CVD (Chemical Vapor Deposition), and then tungsten is deposited by 200 nm in the same manner. Thereafter, the tungsten and the barrier metal on the interlayer insulating film 113a are removed by CMP to form a slit-shaped W plug 114.

  Next, a 300 nm thick plasma TEOS film is deposited on the interlayer insulating film 113a to form a first wiring interlayer insulating film 113b. A resist mask R1 is formed on the first wiring interlayer insulating film 113b, and the plasma TEOS film is etched using the resist mask R1, thereby forming an opening K1 for forming the wiring layer 111 on the W plug 114. (FIG. 4).

  Next, after removing the resist mask R1, a barrier metal (not shown) is formed by forming a TaN film and a Ta film by 10 nm each by sputtering, and then Cu is deposited by sputtering to a thickness of 100 nm. (Not shown). Then, 1000 nm of Cu as a material of the wiring layer 111 is deposited by a plating method. Thereafter, the Cu and the barrier metal on the interlayer insulating film 113 are removed using the CMP method, thereby forming the wiring layer 111 (FIG. 5).

  Next, a diffusion prevention film 122 is formed by depositing a plasma SiC film by 50 nm. Subsequently, for example, a plasma SiOC film is deposited by 600 nm and polished by 200 nm using a CMP method, thereby forming an interlayer insulating film 123. Thereafter, an opening K2 for forming the dummy via 125 and the slit via 124 constituting the seal ring portion 190 is formed in the interlayer insulating film 123 by dry etching using the resist mask R2 (FIG. 6).

  At this time, in a circuit formation region (not shown), an opening (not shown) for forming the second via is formed at the same time as the opening K2 of the dummy via 125 and the slit via 124.

  Next, an opening (not shown) for forming the second wiring layer is formed in the circuit formation region, and Ta and TaN are deposited by 10 nm each by sputtering. Then, a seed is formed by depositing 100 nm of Cu by sputtering (not shown). Thereafter, Cu is deposited to 1000 nm by a plating method, and Cu and barrier metal on the interlayer insulating film 123 are removed by a CMP method. Thus, dummy vias 125 and slit vias 124 are formed (FIG. 7). In the circuit formation region, the second via and the second wiring layer are simultaneously formed.

  Next, a diffusion preventive film 132 is formed by depositing a plasma SiC film by 50 nm. Subsequently, for example, a plasma SiOC film is deposited to 600 nm, and the interlayer insulating film 133 is formed by polishing 200 nm using a CMP method. Thereafter, an opening for forming the slit via 134 constituting the dummy via 135 and the seal ring portion 190 is formed in the interlayer insulating film 133 by dry etching using a resist mask.

  At this time, in a circuit formation region (not shown), an opening (not shown) for forming the third via is formed simultaneously with the openings of the dummy via 135 and the slit via 134.

  Next, an opening for forming the third wiring layer is formed in the circuit formation region. After that, Ta and TaN are deposited by 10 nm each by sputtering.

  Next, a seed is formed by depositing 100 nm of Cu by sputtering. Thereafter, Cu is deposited to a thickness of 1000 nm by a plating method, and Cu and barrier metal on the interlayer insulating film 133 are removed by a CMP method. Thus, dummy vias 135 and slit vias 134 are formed (FIG. 8). In the circuit formation region, a third via and a third wiring layer are simultaneously formed.

  According to a similar procedure, dummy vias 145 and 155 and slit vias 144 and 154 of the fourth layer and the fifth layer are formed. In the circuit formation region, fourth and fifth vias and fourth and fifth wiring layers are formed simultaneously. Since the formation method is the same as that of the second layer and the third layer, description thereof is omitted.

  Next, in the process shown in FIG. 9, for example, a diffusion prevention film 162 is formed by depositing a plasma SiC film by 50 nm. Subsequently, for example, a plasma TEOS film is deposited to 1200 nm, and the interlayer insulating film 163 is formed by polishing 200 nm using a CMP method. Thereafter, a slit via 164 constituting the interlayer insulating film 163, the dummy via 165, and the seal ring portion 190 is formed. At the same time, a sixth via and a sixth wiring layer are formed in the circuit formation region.

  Here, the sixth layer corresponds to the layer where the semi-global wiring is formed. The semi-global process for forming the semi-global wiring is laid out with, for example, twice the size of the process for forming the first to fifth local wirings (fine process). Therefore, the dummy vias 165 are formed with a diameter of 0.28 μm as shown in FIG.

  Next, a plasma SiN film of 500 nm is deposited on the interlayer insulating film 163 to form a first passivation film 173. Thereafter, a hole 174 is formed in the first passivation film 173. Further, after depositing an AL laminated film including a TiN / Ti barrier metal, patterning is performed to form an Al wiring layer 171. Further, a second passivation film 183 is formed after the plasma SiN film 500 nm is deposited. Thus, the structure shown in FIG. 1 can be formed.

  As described above, in the semiconductor device according to the present embodiment, dummy vias are formed on the dicing region side. Therefore, even if a crack occurs during dicing, the progress of the crack is blocked by the dummy via, and the crack can be prevented from reaching the seal ring portion 190. Since cracks can be prevented from reaching the circuit formation region beyond the seal ring part 190 and further the seal ring part 190, it is possible to improve the moisture absorption resistance of the circuit formation region and to prevent deterioration of reliability.

  In addition, when the low-k film is used in a portion having a low Cu pattern ratio, such as a region where a seal ring is formed, the area occupied by the low-k film increases. Since the adhesion between the low-k film and the diffusion preventing film is not high, there is a problem that delamination (film peeling) is likely to occur.

  In this embodiment, the area occupied by the low-k film can be reduced by forming the dummy via. Therefore, even when the Low-k film is used, film peeling can be suppressed.

  In this embodiment, the case where a plasma SiOC film which is a low-k film is used as an interlayer insulating film has been described. However, a ULK (Ultra Low-k) film or a stacked film thereof has the same effect.

  Further, the case where the diffusion preventing films 122, 132, 142, 152, 162 are plasma SiC films has been described. However, a plasma SiC film (k: 3 to 4) having a lower dielectric constant, a plasma SiN film, or a laminated film thereof is used. There may be. Further, the same effect can be obtained even when the diffusion prevention film is not formed.

  Furthermore, although the case where the dummy via and the slit via are made of Cu has been described, W, TaN, TiN, Ta, Ti, or a laminated film thereof may be used.

  In the present embodiment, the case of dummy vias having a pitch of 1 μm and a diameter of 0.14 μm has been described, but the same can be said if the via diameter is about 1 to 100 times the minimum dimension. Also, the via pitch may be in the range of 0.01 to 20%.

  Here, the minimum dimension refers to a dimension defined by a via diameter and a wiring width in designing a via or wiring formed in each layer.

  Further, although the dummy via is shown as a square shape, it may be a rectangle as long as the aperture ratio is the same.

  In the present embodiment, the process of forming the dummy via at the same time as the via in the circuit formation region is shown. However, the dummy via may be formed before or after the via in the circuit formation region. Further, it may be formed separately from the slit via of the seal ring portion 190. Although the case where the layers are stacked with the same layout has been described, the same can be said when the upper layer layout is shifted by a half pitch compared to the lower layer layout. And each layer may have different via diameters and pitch layouts.

<Embodiment 2>
FIG. 10 is a diagram showing a configuration of the semiconductor device according to the second embodiment, and is an enlarged cross-sectional view of a region where a seal ring is formed. FIG. 11 corresponds to a top view taken along line A2-A2 of FIG. FIG. 10 corresponds to the sectional view taken along line B2-B2 of FIG. In this embodiment, a dummy metal and a wiring layer are further formed in each layer. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  A dummy metal 116 is formed on the same plane as the wiring layer 111. A dummy via 125 is formed on the dummy metal 116. A dummy metal 126 is formed on the dummy via 125. Dummy metals 136, 146, 156, and 166 are formed on the dummy vias 135, 145, 155, and 165, respectively. In addition, wiring layers 121, 131, 141, 151, and 161 are formed on the slit vias 124, 134, 144, 154, and 164, respectively.

  Further, as shown in FIG. 11, the plurality of dummy metals 156 are arranged in parallel so as to cover the upper end of the dummy via 155. Dummy metals formed in other layers are also arranged in the same manner. Here, the line width of the dummy metal is, for example, 2 μm width without using a width of 10 μm or more in order to suppress dishing generated in the CMP process after Cu deposition. A wiring layer 151 is formed on the slit via 154.

  In the dummy metals 116, 126, 136, 146, 156, 166 and the wiring layers 111, 121, 131, 141, 151, Cu is embedded in a Ta / TaN structure barrier metal.

  The W plug 114, the wiring layers 111, 121, 131, 141, 151, 161, the slit vias 124, 134, 144, 154, 164, and the Al wiring layer 171 form a seal ring portion 190.

  A method for manufacturing a semiconductor device according to the present embodiment will be described below with reference to FIGS. First, as described in the first embodiment (FIG. 3), the trench isolation 102, the interlayer insulating film 113, and the W plug 114 are formed on the silicon substrate 101.

  Next, in the step shown in FIG. 12, a plasma TEOS film is deposited to 300 nm. Then, the plasma TEOS film is etched using the resist mask R1, and openings corresponding to the dummy metal 116 and the wiring layer 111 are formed.

  Subsequently, in the process shown in FIG. 13, after removing the resist mask R1, a barrier metal (not shown) is formed by depositing TaN and Ta by 10 nm each by sputtering, and then Cu is sputtered. To deposit 100 nm to form a seed (not shown). Then, 1000 nm of Cu as the material of the wiring layer 111 is deposited by a plating method. Then, the wiring layer 111 and the dummy metal 116 are formed by removing Cu and the barrier metal on the interlayer insulating film 103 by using the CMP method.

  Next, a diffusion prevention film 122 is formed by depositing a plasma SiC film by 50 nm. Subsequently, for example, a plasma SiOC film is deposited by 600 nm and polished by 200 nm using a CMP method, thereby forming an interlayer insulating film 123. Thereafter, an opening K2 for forming the dummy via 125 and the slit via 124 is formed in the interlayer insulating film 123 by dry etching using the resist mask R2 (FIG. 14).

  At this time, in a circuit formation region (not shown), an opening (not shown) for forming the second via is formed at the same time as the opening K2 of the dummy via 125 and the slit via 124.

  Subsequently, in the step shown in FIG. 15, the region for forming the dummy metal 126 and the wiring layer 121 is opened by etching the interlayer insulating film 123 using the resist mask R3. At this time, an opening (not shown) for forming the second wiring layer is also formed in a circuit formation region (not shown).

  Next, in the step shown in FIG. 16, after removing the resist mask R3, Ta and TaN are deposited by 10 nm each by sputtering. A seed is formed by depositing Cu to a thickness of 100 nm by sputtering (not shown). Thereafter, Cu is deposited to 1000 nm by a plating method, and Cu and barrier metal on the interlayer insulating film 123 are removed by a CMP method. Thus, the dummy via 125, the slit via 124, the dummy metal 125, and the wiring layer 121 are formed at the same time. A second via and a second wiring layer (not shown) are also formed in the circuit formation region at the same time.

  Dummy vias 135, 145, 155, slit vias 134, 144, 154, dummy metals 136, 146, 156 and wiring layers 131, 141, 151 of the third to fifth layers are formed according to the same procedure (FIG. 17). Also in the circuit formation region, the third to fifth vias and the third to fifth wiring layers are formed simultaneously. Since the formation method is the same as that of the second layer, the description is omitted.

  Next, in the step shown in FIG. 18, for example, a diffusion prevention film 162 is formed by depositing a plasma SiC film by 50 nm. Subsequently, for example, a plasma TEOS film is deposited to 1200 nm, and the interlayer insulating film 163 is formed by polishing 200 nm using a CMP method.

  Then, a slit via 164, a dummy via 165, a dummy metal 166, and a wiring layer 161 are formed in the interlayer insulating film 163 according to the same procedure as described in FIGS. 14 and 15. At the same time, a sixth via and a sixth wiring layer are formed in the circuit formation region.

  Here, the sixth layer corresponds to the layer where the semi-global wiring is formed. The semi-global process for forming the semi-global wiring is laid out with, for example, twice the size of the process for forming the first to fifth local wirings (fine process). Accordingly, as shown in FIG. 18, the dummy vias 165 are formed with a diameter of 0.28 μm, and are laid out so as to be aligned vertically and horizontally, for example, with a 2 μm pitch.

  Next, a plasma SiN film of 500 nm is deposited on the interlayer insulating film 163 to form a first passivation film 173. Thereafter, a hole 174 is formed in the first passivation film 173. Further, after depositing an AL laminated film including a TiN / Ti barrier metal, patterning is performed to form an Al wiring layer 171. Further, a second passivation film 183 is formed after the plasma SiN film 500 nm is deposited. Thus, the structure shown in FIG. 10 can be formed.

  In this embodiment, a dummy metal is formed in each layer. Therefore, propagation of cracks and the like generated during dicing can be further suppressed. Since the seal ring portion 190 can be prevented from being exposed due to cracks or the like, the hygroscopicity of the circuit formation region can be improved.

  Moreover, there is a difference in the coefficient of thermal expansion between the low-k film and the diffusion prevention film. Therefore, stress is generated between the low-k film and the diffusion prevention film. In the present embodiment, the provision of the dummy metal reduces the area in contact with the low-k film and the diffusion prevention film. As a result, stress between the low-k film and the diffusion prevention film can be relieved.

  Furthermore, by providing the dummy metal, the contact area between the dummy metal and the diffusion prevention film provided in the upper layer is increased. Since the adhesion between the dummy metal and the diffusion prevention film is higher than the adhesion between the low-k film and the diffusion prevention film, the adhesion between the respective layers can be improved by increasing the area of the dummy metal. .

  Further, when a wide wiring is used for the dummy metal or wiring layer, there is a problem that the dummy metal or wiring layer is disconnected by dishing in the CMP process after Cu filling.

  Further, when a thick wiring is used, a void (SIV) after high-temperature storage (SM test: stress migration test) is performed at the junction between the upper dummy via and the lower dummy metal (for example, the junction between the dummy via 125 and the dummy metal 116). : Stress Induced Voice) occurs, and there is a problem that reliability is lowered. In the present embodiment, since the layout is made so that the dummy metal and the wiring layer do not use the wide wiring, these problems can be prevented.

<Embodiment 3>
FIG. 19 is a diagram showing a configuration of the semiconductor device according to the third embodiment, and is an enlarged cross-sectional view of a region where a seal ring is formed. FIG. 20 corresponds to the top view along line A3-A3 of FIG. FIG. 19 corresponds to a cross-sectional view taken along line B3-B3 of FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  In the semiconductor device according to the present embodiment, the arrangement pattern of the dummy vias 155 is staggered as shown in the top view of FIG. That is, the dummy vias formed in adjacent rows are formed with a half pitch shift. In other words, the dummy vias 155 are arranged along a plurality of columns in a plan view, and the dummy vias 155 arranged in adjacent columns are alternately arranged to form a staggered arrangement. The dummy vias formed in the other layers have the same arrangement. Since the manufacturing method is the same as that of Embodiment 1, it is omitted.

  Since the configuration as described above is provided, the same effect as in the first embodiment is obtained. Further, in the first embodiment, since the dummy vias are arranged at equal intervals in the vertical and horizontal directions, there is a possibility that cracks are transmitted between the dummy vias and reach the seal ring. In the present embodiment, since the dummy vias are arranged in a staggered manner as viewed from above, the possibility that the cracks are transmitted between the dummy vias is reduced. As a result, propagation of cracks that occur during dicing can be further suppressed.

<Embodiment 4>
FIG. 21 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged sectional view of a region where a seal ring is formed. The fourth embodiment is a combination of the second embodiment and the third embodiment. The same components as those in the second embodiment or the third embodiment are denoted by the same reference numerals, and redundant description is omitted. .

  22 corresponds to a top view taken along line A4-A4 of FIG. 21, and FIG. 21 corresponds to a cross-sectional view taken along line B4-B4 of FIG. As shown in FIG. 22, the arrangement pattern of the dummy vias 155 is staggered. In other words, the dummy vias 155 formed in adjacent rows are formed with a half pitch shift. Further, a dummy metal 156 is formed on the dummy via 155. The other layers have the same configuration. Further, the manufacturing method is the same as that of the second embodiment, so that the description is omitted.

  As described above, in the present embodiment, dummy vias are arranged in a staggered manner, and a dummy metal is formed in each layer. The dummy metal is arranged so as to cover the dummy via. As a result, propagation of cracks that occur during dicing can be further suppressed. Further, by forming the dummy metal, the stress of the low-k film and the diffusion preventing film can be relieved and the adhesion can be improved.

<Embodiment 5>
FIG. 23 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged sectional view of a region where a seal ring is formed. 24 corresponds to a top view taken along line A5-A5 in FIG. 23, and FIG. 23 corresponds to a cross-sectional view taken along line B5-B5 in FIG.

  In this embodiment, as shown in FIG. 24, a dummy slit via 557 is formed in place of the dummy via 155. The slit width of the dummy slit via 557 is formed with a minimum dimension of, for example, 0.14 μm. The layers from the second layer to the fourth layer have the same configuration, and dummy slit vias 527, 537, and 547 are formed. The sixth-layer dummy slit via 567 is formed with a slit width of 0.28 μm.

  Other configurations are the same as those of the first embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted. Since the manufacturing method is the same as that of the first embodiment except that a dummy slit via is formed instead of the dummy via, the manufacturing method is omitted.

  As described above, in the present embodiment, dummy slit vias are formed on the dicing region side instead of dummy vias. By forming the dummy slit via on the dicing region side, it is possible to suppress the propagation of cracks that occur during dicing compared to the case where the dummy via is formed. By disposing the dummy slit, it is possible to prevent cracks from propagating to the seal ring portion 190, so that the moisture absorption resistance of the circuit forming region can be improved.

  Furthermore, by using a slit-like structure like a dummy slit via, the area occupied by the low-k film can be reduced compared to a dummy via. Therefore, the stress of the low-k film and the diffusion prevention film can be relieved.

  Further, by providing the dummy slit via, the contact area between the Low-k film and the diffusion prevention film is reduced, and thus the adhesion can be improved.

<Embodiment 6>
FIG. 25 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged sectional view of a region where a seal ring is formed. 26 corresponds to a top view taken along line A6-A6 of FIG. 25, and FIG. 25 corresponds to a cross-sectional view taken along line B6-B6 of FIG.

  The sixth embodiment is a combination of the second embodiment and the fifth embodiment, and the same components as those in the second embodiment or the fifth embodiment are denoted by the same reference numerals, and redundant description is omitted. To do.

  In the present embodiment, a dummy metal is further formed in each of the first to sixth layers in addition to the dummy slit via.

  As shown in FIG. 26, for example, the dummy metal 156 formed in the fifth layer is formed on the dummy slit via 557 at equal intervals so as to be orthogonal to each other. Similarly, dummy slit vias 527, 537, 547, 567 and dummy metals 126, 136, 146, 156, 166 are formed in the second to fourth layers and the sixth layer. For the first layer, only the dummy metal 116 is formed.

  Since the manufacturing method is the same as the manufacturing method shown in the second embodiment, detailed description thereof is omitted.

  By forming a dummy metal on the dummy slit, it is possible to suppress the propagation of cracks that occur during dicing compared to a configuration with only a dummy slit via.

  Further, since the dummy metal is further formed in the dummy slit via, the area occupied by the low-k film is reduced, the stress of the low-k film and the diffusion prevention film can be relieved, and the adhesion can be improved.

<Embodiment 7>
FIG. 27 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged sectional view of a region where a seal ring is formed. 28 corresponds to a top view taken along line A7-A7 in FIG. 27, and FIG. 27 corresponds to a cross-sectional view taken along line B7-B7 in FIG.

  In the present embodiment, as shown in FIG. 28, the dummy slit via 557 is formed to have a large line width. Other configurations are the same as those of the fifth embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted.

  The line width of the dummy slit via is, for example, 1 μm. Similarly, dummy slit vias 527, 537, and 547 having a thick line width are formed in the second to fourth layers. In the sixth layer, for example, a dummy slit via 567 having a line width of 2 μm is formed.

  The manufacturing method is the same as the manufacturing method shown in the first embodiment except that a dummy slit via is formed instead of the dummy via, and the description thereof is omitted.

  As described above, by using the thick dummy slit via structure formed with a large line width, propagation of cracks generated during dicing can be further suppressed as compared with a case where the line width is small.

  Moreover, the area occupied by the low-k film is reduced by forming the thick dummy slit via. Therefore, the stress of the low-k film and the diffusion prevention film can be relieved.

  Furthermore, since the contact area between the dummy slit via and the diffusion prevention film formed in the upper layer is larger than when a narrow dummy slit via is used, the adhesion can be improved.

The line width of the dummy slit via is not limited to 1 μm, and the same effect can be obtained if it is 0.8 μm to 2 μm. More generally, the same effect can be obtained if the vias are formed in the respective layers, and the vias are designed to have a design via diameter of 5 to 20 times the minimum dimension defined by the wiring width.
However, it is necessary to optimize manufacturing process conditions such as etching conditions and Cu plating film thickness for embedding dummy slit vias according to the line width.

<Eighth embodiment>
FIG. 29 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged cross-sectional view of a region where a seal ring is formed. 30 corresponds to a top view taken along line A8-A8 in FIG. 29, and FIG. 30 corresponds to a cross-sectional view taken along line B8-B8 in FIG.

  In the present embodiment, the line width of the dummy slit via is thickened in the sixth embodiment. The line width of the dummy slit via is, for example, 1 μm. Other configurations are the same as those in the sixth embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted.

  As described above, by using dummy metal in each layer and using a thick dummy slit via structure with a wider line width, the propagation of cracks that occur during dicing can be further suppressed compared to when the line width is small. can do.

  In addition, since the area occupied by the low-k film is reduced, the stress of the low-k film and the diffusion prevention film can be alleviated.

  Furthermore, since the contact area between the low-k film and the diffusion prevention film is smaller than that in the case where the dummy slit via having a narrow line width is formed, the adhesion can be improved.

  The line width of the dummy slit via is not limited to 1 μm, and the same effect can be obtained if it is 0.8 μm to 2 μm. More generally, the same effect can be obtained if the vias are formed in the respective layers, and the vias are designed to have a design via diameter of 5 to 20 times the minimum dimension defined by the wiring width. However, it is necessary to optimize manufacturing process conditions such as etching conditions and Cu plating film thickness for embedding dummy slit vias according to the line width.

<Embodiment 9>
FIG. 31 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged cross-sectional view of a region where a seal ring is formed. 32 corresponds to the sectional view taken along line A9-A9 in FIG. 31, and FIG. 31 corresponds to the sectional view taken along line B9-B9 in FIG.

  The ninth embodiment is a combination of the first embodiment and the fifth embodiment, and the same components as those in the first embodiment or the fifth embodiment are denoted by the same reference numerals, and redundant description is omitted. To do.

  In the present embodiment, dummy vias and dummy slit vias are formed in each of the second to sixth layers on the dicing region side.

  As shown in FIG. 32, dummy vias 155 are formed on both sides of the dummy slit via 557 at equal intervals vertically and horizontally. The other layers have the same structure.

  Since the structure as described above is provided, even if a crack generated during dicing propagates between the dummy vias, the propagation of the cracks can be prevented by the dummy slit via. Therefore, propagation of cracks can be reduced as compared with the structure shown in the first embodiment.

  In addition, since the structure including the dummy via and the dummy slit via is provided, the area occupied by the low-k film can be reduced as compared with the structure of the first embodiment including only the dummy via. Therefore, the stress between the low-k film and the diffusion prevention film can be relieved.

  Furthermore, since the contact area between the Low-k film and the diffusion prevention film is reduced, the adhesion can be improved.

<Embodiment 10>
FIG. 33 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged sectional view of a region where a seal ring is formed. 34 corresponds to a top view taken along line A10-A10 in FIG. 33, and FIG. 33 corresponds to a cross-sectional view taken along line B10-B10 in FIG.

  The tenth embodiment is a combination of the second embodiment and the ninth embodiment, and the same components as those in the second embodiment or the ninth embodiment are denoted by the same reference numerals, and redundant description is omitted. To do.

  As shown in FIG. 33, dummy slit vias and dummy vias are formed on the dicing region side, and dummy metals are formed in the first to sixth layers. Further, as shown in FIG. 34, dummy vias 155 are formed on both sides of the dummy slit via 557 at equal intervals vertically and horizontally. A dummy metal 156 is formed so as to cover the dummy slit via 557 and the dummy via 155. The second to fourth layers and the sixth layer are configured in the same manner.

  Note that the manufacturing method is substantially the same as that of the second embodiment, and therefore will be omitted.

  By forming the dummy metal in each layer so as to cover the dummy slit via and the dummy via, it is possible to further suppress the propagation of cracks generated during dicing as compared with the structure of the ninth embodiment.

  Further, by providing the dummy metal, the area where the low-k film is in contact with the diffusion prevention film is reduced. As a result, stress between the low-k film and the diffusion prevention film can be relieved. Furthermore, the adhesion between each layer can be enhanced.

<Embodiment 11>
FIG. 35 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged cross-sectional view of a region where a seal ring is formed. 36 corresponds to the top view along the line A11-A11 in FIG. FIG. 35 corresponds to a cross-sectional view taken along line B11-B11 of FIG.

  In the present embodiment, as shown in FIG. 36, a dummy via 155 is formed with a dummy slit via 557 interposed therebetween. The dummy vias 155 are staggered. The other layers have the same configuration.

  Other configurations are the same as those in the ninth embodiment, and the same components are denoted by the same reference numerals, and redundant description is omitted. The manufacturing method is the same as the manufacturing method described in the first embodiment, and thus the description thereof is omitted.

  In this embodiment, since the dummy vias are staggered, cracks reaching the dummy slit vias can be reduced. Even when the crack progresses beyond the dummy slit via, the staggered dummy via is further formed between the dummy slit and the seal ring part 190, so that the crack reaches the seal ring part 190. Can be reduced as compared with the configuration of the ninth embodiment.

<Embodiment 12>
FIG. 37 is a diagram showing a configuration of the semiconductor device according to the present embodiment, and is an enlarged cross-sectional view of a region where a seal ring is formed. The present embodiment 12 is a combination of the second embodiment and the eleventh embodiment, and the same components as those in the second embodiment or the eleventh embodiment are denoted by the same reference numerals, and redundant description is omitted. To do.

  Note that the manufacturing method is the same as the manufacturing method described in the second embodiment, and a description thereof will be omitted.

  FIG. 38 corresponds to a top view of the fifth layer. As shown in FIG. 38, a dummy metal 156 is formed so as to cover the dummy slit via 557 and the dummy via 155. The second to fourth layers and the sixth layer are configured in the same manner. Only the dummy metal 116 is formed in the first layer.

  In this embodiment, a dummy metal is formed so as to cover the dummy slit via and the dummy via. Therefore, propagation of cracks that occur during dicing can be further suppressed as compared with the structure of the eleventh embodiment.

  Furthermore, by providing the dummy metal, the area where the low-k film is in contact with the diffusion prevention film is reduced. As a result, stress between the low-k film and the diffusion prevention film can be relieved. And the adhesiveness between each layer can also be improved.

  111 Wiring layer, 114 W plug, 124, 134, 144, 154, 164 Slit via, 125, 135, 145, 155, 165 Dummy via, 171 Al wiring layer, 190 Seal ring part.

Claims (4)

A first interlayer insulating film having a relative dielectric constant of 3 or less;
A second interlayer insulating film formed on the first interlayer insulating film and having a relative dielectric constant of 3 or less;
A seal ring formed in the first and second interlayer insulating films so as to surround a circuit formation region of the semiconductor chip;
A plurality of dummy patterns formed in a dicing region of the semiconductor chip,
Each of the plurality of dummy patterns is
A first dummy metal formed in the first interlayer insulating film;
A second dummy metal formed in the second interlayer insulating film;
A dummy via formed in the second interlayer insulating film and connecting the first dummy metal and the second dummy metal;
The seal ring is disposed in the vicinity of the edge portion of the semiconductor chip,
The dicing area is disposed outside the seal ring,
A plurality of the first dummy metals, a plurality of the second dummy metals, and a plurality of the dummy vias are disposed so as to surround the seal ring;
The dummy vias are arranged along a plurality of columns in a plan view, and the dummy vias arranged in adjacent columns are arranged in a staggered manner by being alternately arranged. The semiconductor device according to claim 1, further comprising a dummy slit via formed in the first and second interlayer insulating films so as to surround the seal ring.   The semiconductor device according to claim 2, wherein a line width of the dummy slit via is 5 to 20 times a minimum dimension.   4. The semiconductor device according to claim 1, wherein a diameter of the dummy via is 1 to 100 times a minimum dimension.

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