JP2005178116A - Liquid discharging head, liquid discharging apparatus, manufacturing method for liquid discharging head, integrated circuit, and manufacturing method for integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an increase of a chip area and a decrease of an operation speed by forming a high withstand voltage transistor for driving and a logic circuit for driving this transistor integrally on a substrate through application to, for example, an inkjet printer of a thermal system in relation to a liquid discharging head, a liquid discharging apparatus, a manufacturing method for a liquid discharging head, an integrated circuit and a manufacturing method for an integrated circuit. <P>SOLUTION: The high withstand voltage transistor for driving is formed by an offset LOCOS structure. A sacrifice oxide film is formed and removed before a gate oxide film of the transistor is formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a liquid discharge head, a liquid discharge apparatus, a method of manufacturing a liquid discharge head, an integrated circuit, and a method of manufacturing an integrated circuit, and can be applied to, for example, a thermal ink jet printer. According to the present invention, a high breakdown voltage driving transistor is formed with an offset LOCOS structure, and a sacrificial oxide film is formed and removed before forming a gate oxide film of the transistor. The logic circuit for driving the transistor is integrally formed on the substrate so that an increase in chip area and a decrease in operation speed can be prevented.

  In recent years, in the field of image processing and the like, there is an increasing need for color hard copy. In response to this need, color copy systems such as a sublimation thermal transfer system, a melt thermal transfer system, an ink jet system, an electrophotographic system, and a heat development silver salt system have been proposed.

  Among these methods, the inkjet method is a method in which droplets of recording liquid (ink) are ejected from nozzles provided on a printer head, which is a liquid discharge head, and are attached to a recording target to form dots. A high-quality image can be output depending on the configuration. This ink jet method is classified into an electrostatic attraction method, a continuous vibration generation method (piezo method), and a thermal method according to the difference in the method of causing ink droplets to fly from the nozzles.

  Among these methods, the thermal method is a method in which bubbles are generated by local heating of the ink, and the ink is pushed out from the nozzles by the bubbles to fly to a printing target, and a color image can be printed with a simple configuration. It has been made possible.

  In such a thermal type printer head, a heating element for heating ink is integrally formed on a semiconductor substrate together with a driving circuit by a logic integrated circuit for driving the heating element. As a result, in this type of printer head, the heating elements are arranged with high density so that they can be reliably driven.

  That is, in this thermal printer, it is necessary to arrange the heating elements at a high density in order to obtain a high-quality printing result. Specifically, in order to obtain a printing result equivalent to 600 [DPI], for example, it is necessary to arrange the heating elements at intervals of 42.333 [μm]. It is extremely difficult to arrange individual driving elements. As a result, in the printer head, a switching transistor or the like as a driving element is formed on a semiconductor substrate and connected to a corresponding heating element by integrated circuit technology, and each switching transistor is similarly connected by a logic circuit created on the semiconductor substrate. By driving, each heating element can be driven easily and reliably.

In the printer head, this type of switching transistor and a driving circuit for driving the switching transistor are formed by, for example, a MOS (Metal Oxide Semiconductor) type field effect transistor (metal oxide field effect transistor), and the heating element is, for example, tantalum ( Ta), tantalum nitride (TaN _x ), tantalum aluminum (TaAl), polysilicon (Poly-Silicon), or the like. Further, a pulse voltage having a rectangular shape is applied to the heat generating element to drive the heat generating element, and heat generated by driving the heat generating element is propagated to the ink to eject ink droplets.

  Regarding such a printer head, in a top shooter (face shooter) type printer head that pushes ink droplets vertically from a nozzle provided on a heating element, tantalum nitride, tantalum aluminum, etc. using tantalum as a main material Thus, a heating element is created. These materials have a specific resistance of 270 to 300 [[mu] [Omega] -cm], and the printer head generates a power of about 0.8 to 1.1 [W] by driving the heating element with these materials. Thus, the power supply voltage is set to about 10 to 15 [V]. Such a power supply voltage is set in consideration of a voltage drop due to a parasitic resistance such as an on-resistance or wiring resistance of a transistor related to driving of the heating element.

  In such a printer head, when the heating element is driven, a voltage equivalent to the power supply voltage is also applied between the gate and drain of the MOS transistor used for driving the heating element. In contrast, MOS transistors are normally operated with a gate input voltage of 5 [V] or less. In such a MOS transistor operating with a gate input voltage of 5 [V] or less, when a voltage of 5 [V] or more is applied between the gate and the drain, electrons flowing out from the source pass through the channel formation region. Accelerated in the high electric field region near the drain, electrons and holes generated by impact ionization of the accelerated electrons are injected into the gate oxide film, which degrades the threshold voltage and turns on / off control. Becomes difficult.

  Therefore, conventionally, a MOS transistor having an LDD (Lightly Doped Drain) structure is applied to the MOS transistor of this type of printer head as shown in FIG. Here, in the MOS transistor having the LDD structure, a diffusion layer AR made of a low-concentration impurity layer is formed in the vicinity of the end of the drain D on the gate G side, and the high voltage between the channel formation region below the gate G and the drain D is used. The breakdown voltage is increased by relaxing the electric field by the diffusion layer AR.

  On the other hand, for example, Japanese Patent Laid-Open No. 2002-319631 proposes a printer head using a MOS transistor having a DDD (Double Diffused Drain) structure. Here, in the MOS transistor having the DDD structure, as shown in FIG. 10, a low-concentration diffusion layer AR is formed so as to surround the drain D, thereby relaxing the electric field and ensuring a withstand voltage.

  In Japanese Patent Laid-Open No. 10-71713, a MOS transistor having an offset / drain structure is applied to a printer head. Here, the MOS transistor having the offset drain structure is based on the LDD structure as shown in FIG. 11, and the gate G and the drain D are compared with the LDD structure by increasing the region of the diffusion layer AR in the horizontal direction. Are separated from each other, thereby relaxing the electric field and ensuring a withstand voltage. This offset / drain structure is also called an LD (Lateral Diffusion) structure.

  In a transistor that requires a higher breakdown voltage than a MOS transistor having an offset / drain structure, a MOS transistor having an offset LOCOS (LOCOS: Local Oxidation Of Silicon) structure is applied.

  Here, in the MOS transistor having the offset LOCOS structure, as shown in FIG. 12, in addition to the diffusion layer, an insulating layer is further formed in a part of the gate oxide film below the gate electrode.

Specifically, in the transistor 1, an N well and a P well, which are diffusion layers, are formed on a silicon substrate 2, and a silicon nitride film (Si ₃ N ₄ ) is formed on the silicon substrate 2 except at least a portion where an insulating layer is formed. Is deposited. In the transistor 1, an insulating layer 3 made of a LOCOS film for element isolation is subsequently formed by thermal oxidation using the silicon nitride film as a mask. In the transistor 1, the gate G is subsequently formed by the laminated structure of the gate oxide film 4 and the polysilicon 5. Subsequently, the silicon substrate 2 is processed by an ion implantation process and a heat treatment process, whereby a source S and a drain D are formed, and sidewalls 6 are formed at both ends of the gate G. Thereby, in the transistor 1, the insulating layer 3 provided on a part of the gate oxide film 4 on the drain D side widens the distance between the drain D and the electrode of the gate G, thereby relaxing the electric field and ensuring a withstand voltage. It is made to do.

  In such a transistor 1, when the silicon nitride film used as a mask at the time of the thermal oxidation process is removed with phosphoric acid, as shown in FIG. Cannot be completely removed, leaving residue 7. In the transistor 1, the gate oxide film 4 is formed on the residue 7, and in the silicon nitride film, the oxidation rate is two orders of magnitude lower than that of silicon. Many pinholes are generated. When such a pinhole is generated, electrons easily pass through the pinhole in the transistor 1, and the threshold voltage deteriorates due to injection of the passed electrons into the gate oxide film 4, thereby making it difficult to control on / off. become.

  When the insulating layer 3 is formed by thermal oxidation, a field oxide film tailing portion is generated near the boundary surface between the insulating layer 3 and the gate oxide film 4 formation region. Immediately below the bottom portion of the field oxide film, as indicated by x, crystal defects due to silicon are likely to occur. In the transistor 1, the gate oxide film 4 is formed on the bottom portion. As a result, electrons also pass through the trailing portion, and this also makes on / off control difficult due to deterioration of the threshold voltage.

  As a result, in the transistor 1, the gate oxide film 4 is formed with a film thickness that can suppress such deterioration of the threshold voltage, thereby ensuring the insulation resistance of the gate oxide film 4.

  Thus, in the transistor 1, the thickness of the gate oxide film 4 is increased, and accordingly, the on-resistance value is increased in the normal 5 [V] gate input operation. As a method to eliminate such an increase in on-resistance, a booster circuit is installed in the gate input voltage section, and the booster circuit boosts the gate input voltage to increase the drain current of the MOS transistor, thereby reducing the on-resistance. It is made to let you.

  Incidentally, in recent years, in this type of printer head, it has been desired to efficiently drive the heating elements. Specifically, when ink droplets can be ejected by driving a heating element by a MOS transistor, electric power is consumed depending on the ON resistance value of the MOS transistor and the resistance value of the wiring pattern. As a result, the efficiency of driving the heating element is expressed by the resistance value of the heating element / (resistance value of the heating element + ON resistance value of the MOS transistor + wiring resistance). In the printer head, the resistance value of the heating element. If the height is increased, the heating element can be driven efficiently.

However, when the resistance value of the heating element is increased in this way, the power for driving the heating element is expressed by (voltage) ² / resistance value, so that in the MOS transistor used for driving the heating element, further between the gate and the drain It is necessary to increase the breakdown voltage.

  On the other hand, when the diffusion layer AR is simply provided as in the transistors shown in FIGS. 9 to 11, the breakdown voltage can be increased by increasing the area of the diffusion layer AR. As a result, the area occupied by the transistor increases. As a result, in a printer head, when this type of MOS transistor is applied to a high breakdown voltage driving transistor, there is a problem that the area of the head chip increases. In addition, in the LDD structure, it is necessary to thermally diffuse for a long time by forming the diffusion layer AR in the direction perpendicular to the semiconductor substrate and then forming the drain D. Further, in the offset drain structure, there is a problem in that the operating speed is lowered and the on-resistance is increased by increasing the region of the diffusion layer AR in the horizontal direction.

  On the other hand, in the case where the insulating layer 3 is further provided in addition to the diffusion layer as in the transistor 1 shown in FIG. 12, the region of the diffusion layer AR is increased by the amount of the electric field relaxed by the insulating layer 3. Therefore, if the transistor 1 is applied to a high breakdown voltage driving transistor in the printer head, an increase in chip area can be prevented even if the breakdown voltage is increased. It is done.

However, when this transistor 1 is applied to a driving transistor, the printer head performs on / off control of the high-breakdown-voltage driving transistor and the transistors constituting the logic circuit that drives the transistor with different gate input voltages. As a result, in the printer head, these transistors are integrally formed on the substrate, so that the configuration relating to driving of the heating elements becomes complicated, and the chip area is increased by installing a booster circuit in the gate input voltage section. There is also a problem to do.
Japanese Patent Laid-Open No. 2002-319631 JP-A-10-71713

  The present invention has been made in consideration of the above points. A high breakdown voltage driving transistor and a logic circuit for driving the transistor are integrally formed on a substrate, thereby increasing the chip area and operating speed. It is an object of the present invention to propose a liquid discharge head, a liquid discharge device, a method for manufacturing a liquid discharge head, an integrated circuit, and a method for manufacturing an integrated circuit, which can prevent the deterioration of the above.

  In order to solve this problem, in the first aspect of the present invention, a heat generating element, a field effect transistor for driving the heat generating element, and a logic circuit for driving the field effect transistor are integrally formed on the substrate, and the field effect is obtained. At least the field-effect transistor is applied to the gate oxide film under the gate electrode by applying the liquid holding head that heats the liquid held in the liquid chamber by driving the heating element by the type transistor and ejects the liquid droplet from the nozzle. An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the drain side. The insulating layer is formed by depositing a silicon nitride film on the substrate excluding at least a portion where the insulating layer is formed, and then the substrate. After the silicon nitride film is removed by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate. After the oxide film is removed by etching, to be formed by thermal oxidation of the substrate.

  According to a second aspect of the present invention, the liquid discharge head is applied to a liquid discharge apparatus that supplies a droplet ejected from the liquid discharge head to an object. The liquid discharge head includes a heating element, a field effect transistor that drives the heating element, A logic circuit for driving the field effect transistor is integrally formed on the substrate, the liquid held in the liquid chamber is heated by driving the heating element by the field effect transistor, and the liquid droplet is ejected from the nozzle. In the field effect transistor, an insulating layer that relaxes an electric field between the drain and the gate electrode is formed on a part of the drain side of the gate oxide film below the gate electrode, and the insulating layer is a portion that forms at least the insulating layer. After the silicon nitride film is deposited on the substrate except for the substrate, it is formed by thermal oxidation of the substrate, and the gate oxide film is removed by etching the silicon nitride film Sacrificial oxide film is formed by thermal oxidation of the substrate, after the sacrifice oxide film is removed by etching, to be formed by thermal oxidation of the substrate.

  According to a third aspect of the present invention, a heat generating element, a field effect transistor for driving the heat generating element, and a logic circuit for driving the field effect transistor are integrally formed on a substrate, and the heat generating element by the field effect transistor is formed. At least the field effect transistor is applied to the drain side of the gate oxide film under the gate electrode by applying to the method of manufacturing the liquid discharge head that heats the liquid held in the liquid chamber by driving and ejects liquid droplets from the nozzle. An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the substrate, and the method of manufacturing the liquid discharge head is performed after depositing a silicon nitride film on the substrate excluding at least a portion where the insulating layer is formed. After forming the insulating layer by thermal oxidation of the substrate and removing the silicon nitride film by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate. After removing by etching the film to form a gate oxide film by thermal oxidation of the substrate.

  According to a fourth aspect of the invention, when applied to an integrated circuit in which a field effect transistor and a logic circuit for driving the field effect transistor are integrally formed on a substrate, at least the field effect transistor has a gate An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the drain side of the gate oxide film under the electrode, and the insulating layer is formed of silicon nitride on the substrate excluding at least a portion where the insulating layer is formed. After the film is deposited, the gate oxide film is formed by thermal oxidation of the substrate, and after the silicon nitride film is removed by etching, the sacrificial oxide film is formed by thermal oxidation of the substrate, and the sacrificial oxide film is removed by etching. And formed by thermal oxidation of the substrate.

  According to a fifth aspect of the present invention, at least a field effect transistor is applied to a method of manufacturing an integrated circuit in which a field effect transistor and a logic circuit for driving the field effect transistor are integrally formed on a substrate. An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the drain side of the gate oxide film below the gate electrode, and an integrated circuit manufacturing method includes at least a portion for forming the insulating layer. After depositing a silicon nitride film on the substrate except the substrate, an insulating layer is formed by thermal oxidation of the substrate, and after removing the silicon nitride film by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate, and the sacrificial oxide film is etched. Then, a gate oxide film is formed by thermal oxidation of the substrate.

  According to the configuration of claim 1, the heat generating element, the field effect transistor for driving the heat generating element, and the logic circuit for driving the field effect transistor are integrally formed on the substrate, and the heat generating element is driven by the field effect transistor. Is applied to a liquid discharge head that heats the liquid held in the liquid chamber and ejects liquid droplets from the nozzle, and at least the field effect transistor has a portion on the drain side of the gate oxide film below the gate electrode. If an insulating layer that relaxes the electric field between the drain and the gate electrode is formed, the breakdown voltage between the drain and the gate electrode in the field effect transistor can be increased. The insulating layer is formed by depositing a silicon nitride film on a substrate excluding at least a portion where the insulating layer is to be formed and then thermally oxidizing the substrate, and the gate oxide film is formed by etching the silicon nitride film. Then, after the sacrificial oxide film is formed by thermal oxidation of the substrate, and after the sacrificial oxide film is removed by etching, the sacrificial oxide film is formed by thermal oxidation of the substrate. By forming a gate oxide film of a field effect transistor with a corresponding film thickness, it is possible to ensure insulation of the gate oxide film. Thus, a high breakdown voltage driving transistor and a logic circuit for driving the transistor are integrally formed on the substrate, thereby preventing an increase in chip area and a decrease in operating speed.

  Thus, according to the second and third aspects of the present invention, the high breakdown voltage driving transistor and the logic circuit for driving the transistor are integrally formed on the substrate, thereby increasing the chip area and operating speed. It is possible to provide a liquid ejecting apparatus and a liquid ejecting head manufacturing method that can prevent the deterioration of the liquid.

  According to the configurations of the fourth and fifth aspects, the high breakdown voltage driving transistor and the logic circuit for driving the transistor are integrally formed on the substrate, so that the chip area can be increased and the operation speed can be increased. It is possible to provide an integrated circuit and a method for manufacturing the integrated circuit that can prevent the degradation.

  According to the present invention, a high breakdown voltage driving transistor and a logic circuit for driving the transistor are integrally formed on a substrate, thereby preventing an increase in chip area and a decrease in operating speed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a perspective view showing a line printer according to the present invention. The line printer 11 is a full line type line printer, and a printer main body 12 is formed in a substantially rectangular shape. The line printer 11 can feed the paper 13 by attaching a paper tray 14 containing the paper 13 to be printed from a tray inlet / outlet formed on the front surface of the printer main body 12.

  In the line printer 11, when the paper tray 14 is attached to the printer main body 12 from the tray entrance / exit in this way, the paper tray 14 moves toward the back side of the printer main body 12 by the rotation of the paper feed roller provided in the printer main body 12. The paper 13 is fed out from the printer, and the feeding direction of the paper 13 is switched to the front direction by a reverse roller provided on the back side of the printer main body 12. In the line printer 11, the sheet 13 having the sheet feeding direction switched to the front direction is conveyed so as to cross the sheet tray 14, and is discharged to the tray 15 from the discharge port disposed on the front side of the line printer 11. Is done.

  The line printer 11 is provided with an upper lid 16 on the upper end surface, and the head cartridge 18 is disposed in a replaceable manner as indicated by an arrow A while the paper is being conveyed in the front direction of the inside of the upper lid 16.

  Here, the head cartridge 18 is a full-line type printer head with four colors of yellow, magenta, cyan, and black, and ink tanks 19Y, 19M, 19C, and 19K for each color are provided on the upper side. The head cartridge 18 is provided on the head assembly 20 which is an assembly of printer heads related to the ink tanks 19Y, 19M, 19C and 19K, and on the paper 13 side of the head assembly 20, and is provided in the head assembly 20 when not in use. And a head cap 21 that closes the nozzle row and prevents the ink from drying. As a result, in the line printer 11, by driving the head assembly 20 provided in the head cartridge 18, ink droplets of each color are attached to the paper 13 so that a desired image or the like can be printed in color. ing.

  FIG. 3 is an enlarged perspective view of the head assembly 20 as seen from the paper 13 side, with a portion related to the ejection of the ink droplets D being enlarged and a partial cross-sectional view. The head assembly 20 is formed by wiring the head chips 24 through the bonding terminals 26 after the head chips 24 that have created the partition walls 23 and the like of the ink liquid chamber 22 are sequentially attached to the head frame.

  Here, the head chip 24 is formed with a plurality of heat generating elements 27, a drive circuit for driving the plurality of heat generating elements 27, a pad 28 for inputting a power source for driving the drive circuit, and the like. The whole is formed in a rectangular shape as viewed from the side 25, and a plurality of heating elements 27 are arranged at a predetermined pitch along one side of the long side of the rectangular shape.

  In the head chip 24, the partition wall 23 of the ink liquid chamber 22 is formed by a comb tooth shape so that the one side is open, thereby forming an ink channel on the one side, The ink in the corresponding ink tanks 19Y, 19M, 19C, and 19K can be guided to the ink liquid chambers 22, and the ink thus guided to the ink liquid chambers 22 can be heated by driving the heating elements 27. Has been made.

  In the head chip 24, after the exposure curing type dry film resist is laminated on the side surface of the heat generating element 27 at the stage of the semiconductor wafer, the partition wall 23 is formed by removing a portion of the ink liquid chamber from the dry film resist by a photolithography process. It is designed to be formed.

  On the other hand, the nozzle sheet 25 is a sheet-like member in which rows of nozzles 29 having respective paper widths corresponding to yellow, magenta, cyan, and black inks are arranged in parallel, and is formed by an electroforming technique. The nozzle sheet 25 is formed in a staggered manner with the rows of the nozzles 29 interposed therebetween, and openings 30 for working when wire bonding the head chips 24 to the bonding terminals 26 are formed.

  FIG. 4 is a cross-sectional view showing a configuration in the vicinity of the head chip disposed in the head assembly 20. The head chip 24 is formed by scribing each chip after a plurality of chips are collectively formed on a semiconductor wafer made of a silicon substrate by a semiconductor manufacturing process.

  In this embodiment, a high-breakdown-voltage driving switching transistor 32 used for driving a heating element is formed by an N-channel MOS transistor having an offset LOCOS structure, and a logic circuit constituting a logic circuit for driving the switching transistor 32 The switching transistor 33 and the like are formed by N-channel MOS type and P-channel MOS type transistors. These transistors 32 and 33 are formed so as to operate with an equivalent gate input voltage.

  That is, as shown in FIG. 5A, after the P-type silicon substrate 34 is cleaned by the wafer, the head chip 24 is processed by a photolithography process, an ion implantation process, and a thermal diffusion process. An N well region and a P well region are formed in the silicon substrate 34.

Subsequently, after a silicon nitride film (Si ₃ N ₄ ) is deposited with a film thickness of 100 [nm], the silicon chip 34 is processed in the head chip 24 by a photolithography process and a reactive ion etching process. , 33 is removed from the region other than the predetermined region. As a result, in the head chip 24, a silicon nitride film is deposited on a region on the silicon substrate 34 where a transistor is to be formed. At this time, in the region where the transistor 32 is formed, the silicon nitride film is removed from the region where the insulating layer is formed so that the insulating layer having the offset LOCOS structure is formed in the subsequent process.

  Subsequently, in the head chip 24, a thermal silicon oxide film is formed with a film thickness of 770 [nm] in a region where the silicon nitride film is removed by the thermal oxidation process, and element isolation for isolating the transistor by this thermal silicon oxide film is performed. An insulating layer 36 having a region (LOCOS) 35 and a length of 4.0 [μm] is formed. As a result, the head chip 24 creates an insulating layer 36 having an offset LOCOS structure when the element isolation region 35 is created, thereby preventing an increase in the number of processes.

  In the head chip 24, the silicon substrate 34 is subsequently immersed in a heated phosphoric acid solution, and the silicon nitride film is removed by etching using the phosphoric acid. As a result, in the gate formation region of the transistor 32, as shown in FIG. 1A, a residue 37 is generated without the silicon nitride film being completely removed, and as shown by x, the bottom of the insulating layer 36 is formed. A crystal defect 38 of the silicon substrate 34 occurs near the pulling portion.

Subsequently, in the head chip 24, the silicon substrate 34 is processed by an ion implantation process, whereby the threshold voltages of the transistors 32 and 33 are adjusted. Subsequently, as shown in FIG. 5B, heat treatment is performed at 950 ° C. in a mixed gas (H ₂ / O ₂ ) atmosphere of hydrogen and oxygen in a heat treatment furnace, and a film thickness of 100 to 200 [ nm] to form a thermal oxide film 39 (hereinafter referred to as a sacrificial oxide film). At this time, in the gate formation region of the transistor 32, the residue 37 is absorbed in the sacrificial oxide film 39, and the crystal defect 38 at the bottom of the insulating layer 36 is repaired (FIG. 1B).

  Subsequently, after the element isolation region 35 and the insulating layer 36 are masked with a resist layer by a photolithography process, the head chip 24 is further continued for about 100: 1 for 100 to 150 seconds as shown in FIG. 6C. The silicon substrate 34 is immersed in a dilute hydrofluoric acid solution that is diluted to 1 and the sacrificial oxide film 39 is removed by etching using the dilute hydrofluoric acid. The head chip 24 is then washed with running water, whereby in the gate formation region of the transistor 32, the residue 37 is also removed and the clean surface of the silicon substrate 34 is exposed (FIG. 1C). .

When the surfaces of the gate forming regions of the transistors 32 and 33 are cleaned in this way, subsequently, as shown in FIG. 6D, again in the heat treatment furnace, a mixed gas (H ₂ / Heat treatment is performed at 900 degrees in an atmosphere of O ₂ ), and in these regions, a thermal oxide film 40 serving as a gate oxide film of the transistor 32 is formed with a desired film thickness (FIG. 1D). .

  Here, the thickness of the gate oxide film is set based on the gate input voltage and the gate length. Specifically, for example, in the case of a transistor with a gate input voltage of 5 [V] and a gate length of 2.0 [μm]. The film thickness is set to about 34 [nm]. In the case of a transistor with a gate input voltage of 5 [V] and a gate length of 1.0 [μm], the film thickness is set to about 20 [nm], and the gate input voltage is 5 [V] and the gate length is 0.7 [μm]. In the case of the transistor according to (1), the film thickness is set to about 16 [nm]. Incidentally, in recent years, the gate input voltage of a transistor has a tendency to shift from 5.0 [V] to 3.3 [V] and further to 2.5 [V] with the miniaturization of a MOS logic circuit. In order to cope with such a low voltage, the gate oxide film has a thickness of 8 [nm] in the case of a transistor with a gate input voltage of 3.3 [V] and a gate length of 0.7 [μm]. In the case of a transistor with a gate input voltage of 2.5 [V] and a gate length of 0.7 [μm], the film thickness is set to about 6 [nm].

  In this embodiment, the gate oxide film is formed with a thickness of about 34 [nm] so that the high breakdown voltage driving transistor 32 with a gate length of 2.0 [μm] operates with a gate input voltage of 5 [V]. On the other hand, the gate oxide film of the transistor 33 is formed with a film thickness of about 20 [nm] so that the logic circuit transistor 33 with a gate length of 1.0 [μm] operates with a gate input voltage of 5 [V]. Is done.

Therefore, in the head chip 24, the gate oxide film of the logic circuit transistor 33 is subsequently formed with a corresponding film thickness. That is, as shown in FIG. 7E, after the element isolation region 35, the insulating layer 36, and the formation region of the transistor 32 are masked with a resist layer by a photolithography process, dilute hydrofluoric acid is used as in FIG. A cleaning process using is performed. Subsequently, as shown in FIG. 7F, heat treatment is performed at 850 ° C. in a mixed gas (H ₂ / O ₂ ) atmosphere of hydrogen and oxygen in a heat treatment furnace, and the logic circuit transistor 33 is formed. A thermal oxide film 41 to be a gate oxide film is formed with a film thickness of about 20 nm.

Subsequently, after the silicon substrate 34 is cleaned in the head chip 24, as shown in FIG. 8G, polysilicon is deposited with a film thickness of 100 [nm] by a CVD (Chemical Vapor Deposition) method. Subsequently, a tungsten silicide film is deposited with a film thickness of 100 nm by a CVD method using a WF ₆ + SiH ₄ gas. Further, after the gate region is exposed by a lithography process, the excess thermal oxide films 40 and 41, the polysilicon film, and the tungsten silicide film are removed by dry etching using a mixed gas of SF ₆ + HBr. Thereby, in the formation region of the switching transistor 32, the electrode of the gate G is formed with a gate length of 2 [μm] by the polycide structure by the gate oxide film 42, the polysilicon film 44, and the tungsten silicide film 45. In FIG. 5, the gate G electrode is formed with a gate length of 1 [μm] by the polycide structure of the gate oxide film 43, the polysilicon film 44, and the tungsten silicide film 45.

Subsequently, in the head chip 24, the silicon substrate 34 is processed by an ion implantation process and a heat treatment process to form a source S and a drain D, and subsequently, a silicon oxide film (SiO ₂ ) is deposited and reactive using a CVD method. Sidewalls 46 are formed at both ends of the gate G by ion etching.

  When the MOS transistors 32 and 33 are formed in this way, the head chip 24 is formed by integrating a high breakdown voltage driving transistor having an offset LOCOS structure and a logic circuit transistor for driving the transistor into a silicon substrate. 34 is formed. Thereby, in the head chip 24, the breakdown voltage between the gate and the drain of the transistor 32 can be increased, and an increase in chip area due to the increase in breakdown voltage can be prevented as compared with a transistor having a structure in which a diffusion layer is simply provided. Yes.

  Further, in this embodiment, the gate oxide film 42 of the transistor 32 is formed with a film thickness corresponding to the gate input voltage equivalent to that of the transistor 33, and the sacrificial oxide film 39 is formed before the gate oxide film 42 is formed. As a result, the insulating property of the gate oxide film 42 is secured. Accordingly, in the head chip 24, the high-breakdown-voltage driving transistor 32 is controlled to be turned on / off by the gate input voltage equivalent to that of the logic circuit transistor 33, and insulation is not ensured by increasing the thickness of the gate oxide film. In order to prevent an increase in chip area and a decrease in operating speed.

  In this embodiment, the switching transistor 32 increases the breakdown voltage between the gate and the drain to about 40 [V]. Further, the sacrificial oxide film 39 used for removing the residue 37 is formed to have a thickness of about 180 [nm], which is larger than the thickness of the silicon nitride film 100 [nm], thereby reliably removing the residue 37 from the gate formation region. I did it.

  When the transistors 32 and 33 are formed in this way, the head chip 24 is then subjected to an NSG (Non-doped Silicate Glass) film, boron, which is a silicon oxide film by CVD, as shown in FIG. BPSG (Boron Phosphorus Silicate Glass) film, which is a silicon oxide film to which silicon and phosphorus are added, is sequentially formed with a film thickness of 100 [nm] and 500 [nm]. An interlayer insulating film 47 for the eyes is formed.

Subsequently, after the photolithography process, a contact hole 48 is formed on the silicon semiconductor diffusion layer (source / drain) by a reactive ion etching method using C ₄ F ₈ / CO / O ₂ / Ar-based gas.

  Furthermore, the head chip 24 is added with 1 [at%] of titanium with a film thickness of 30 [nm], titanium nitride oxide barrier metal with a film thickness of 70 [nm], titanium with a film thickness of 30 [nm], and silicon by sputtering. Aluminum with a thickness of 500 [nm] is sequentially deposited. Subsequently, on the head chip 24, titanium nitride oxide, which is an antireflection film, is deposited with a film thickness of 25 [nm], thereby forming a wiring pattern material layer.

  Subsequently, the formed wiring pattern material layer is selectively removed by a photolithography process and a dry etching process, and a first wiring pattern 49 is created. The head chip 24 is configured such that a logic integrated circuit is formed by connecting the logic circuit transistor 33 by the first-layer wiring pattern 49 thus created.

Next, a silicon oxide film, which is an interlayer insulating film, is deposited on the head chip 24 by a CVD method using TEOS (tetraethoxysilane: Si (OC ₂ H ₅ ) ₄ ) as a source gas. Subsequently, in the head chip 24, the silicon oxide film is flattened by applying and etching back a coating type silicon oxide film containing SOG (Spin On Glass), and these steps are repeated twice to form the first layer wiring. A second interlayer insulating film 50 is formed of a silicon oxide film having a thickness of 440 [nm] that insulates the pattern 49 from the second wiring pattern that follows.

Next, a β-tantalum film having a film thickness of 50 to 100 [nm] is deposited on the head chip 24 by a sputtering apparatus, whereby a resistor film is formed on the silicon substrate 34. The sputtering conditions were set to a wafer heating temperature of 200 to 400 degrees, a DC applied power of 2 to 4 [kW], and an argon gas flow rate of 25 to 40 [sccm]. Further, the resistor film is selectively removed from the head chip 24 by a photolithography process, a dry etching process using BCl ₃ / Cl ₂ gas, in a square shape or in a folded shape in which one end is connected by a wiring pattern. , A heating element 27 having a resistance value of 40 to 100 [Ω] is formed.

When the heating element 27 is formed in this way, a silicon nitride film having a film thickness of 300 [nm] is deposited on the head chip 24 by the CVD method, and the insulating protective layer 52 of the heating element 27 is formed. Subsequently, the silicon nitride film at a predetermined position is removed by a photoresist process and a dry etching process using CHF ₃ / CF ₄ / Ar gas, thereby exposing a portion connecting the heating element 27 to the wiring pattern. Further, via holes 53 are formed by forming openings in the interlayer insulating film 50 by a dry etching process using CHF ₃ / CF ₄ / Ar gas.

  Further, the head chip 24 is formed by sputtering using titanium having a film thickness of 200 [nm], aluminum added with 1 [at%] of silicon, or aluminum added with 0.5 [at%] of copper with a film thickness of 600 [ nm] are sequentially deposited. Subsequently, titanium nitride oxide having a film thickness of 25 [nm] is deposited on the head chip 24, thereby forming an antireflection film. Thus, the head chip 24 is formed with a wiring pattern material layer made of aluminum to which silicon or copper is added.

Subsequently, the wiring pattern material layer is selectively removed by a photolithography process and a dry etching process using BCl ₃ / Cl ₂ gas, and a second wiring pattern 54 is created. In the head chip 24, a wiring pattern for power supply and a wiring pattern for grounding are created by the wiring pattern 54 of the second layer, and a wiring pattern for connecting the driver transistor 32 to the heating element 27 is created. Note that the silicon nitride film 52 left on the upper layer of the heat generating element 27 functions as a protective layer for protecting the heat generating element 27 from chlorine radicals used for etching in the etching process when forming the wiring pattern. Further, in this silicon nitride film 52, the portion exposed to chlorine radicals in this etching step is reduced from a film thickness of 300 [nm] to a film thickness of 100 [nm].

  Subsequently, in the head chip 24, a silicon nitride film 55 functioning as an ink protective layer and an insulating layer is deposited with a film thickness of 400 [nm] by plasma CVD. Further, in a heat treatment furnace, heat treatment is performed at 400 ° C. for 60 minutes in an atmosphere of nitrogen gas added with 4% hydrogen or in a nitrogen gas atmosphere of 100%. As a result, in the head chip 24, the operations of the transistors 32 and 33 are stabilized, and the connection between the first-layer wiring pattern 49 and the second-layer wiring pattern 54 is stabilized, thereby reducing the contact resistance.

In the head chip 24, after a cavitation-resistant material layer is subsequently deposited with a film thickness of 200 nm, a cavitation-resistant layer 56 is formed by patterning using BCl ₃ / Cl ₂ gas. In this embodiment, the anti-cavitation layer 56 made of β-tantalum is formed by a DC magnetron sputtering apparatus using tantalum as a target. Here, the anti-cavitation layer 56 protects the heating element 27 by absorbing physical damage (cavitation) when bubbles generated in the ink chamber 22 disappear due to the driving of the heating element 27. This is a protective layer that protects the heating element 27 from the chemical action of ink that has become hot due to driving.

  Next, as shown in FIG. 4, the head chip 24 is coated with a photosensitive organic resin, and then the portions corresponding to the ink liquid chamber 22 and the ink flow path are removed by an exposure and development process, and then cured. Thus, the partition wall 23 of the ink liquid chamber 22, the partition wall 23 of the ink flow path, and the like are created. The head chip 24 is formed by scribing a plurality of head chips formed on the silicon substrate 34 in this way.

(2) Operation of Embodiment In the above-described configuration, in the line printer 11 (FIG. 2), the head cartridge 18 is driven by image data, text data, etc. used for printing, and the sheet 13 to be printed is fed to a predetermined sheet. While being transported by the mechanism, ink droplets are ejected from a head assembly 20 provided in the head cartridge 18, and the ink droplets adhere to the paper 13 being transported to print an image, text, or the like. Correspondingly, in the head assembly 20 of the head cartridge 18 (FIGS. 2 and 3), the ink in the ink tanks 19Y, 19M, 19C, and 19K is guided to the ink liquid chamber 22 formed in each head chip 24, Ink droplets L are ejected from the nozzles 29 provided on the nozzle sheet 25 by heating the ink in the ink liquid chamber 22 by driving the heating element 27. As a result, the line printer 11 can print a desired image or the like.

  In the head assembly 20, a plurality of heating elements 27, a transistor 32 that drives the plurality of heating elements 27, a transistor 33 that constitutes a logic circuit that drives the transistors 32, and the like are integrally formed. 24 (FIGS. 4 to 8), a nozzle row by nozzles 29 for discharging ink droplets, and a nozzle sheet 25 which is a sheet-like member formed by forming an opening 30 by electroforming. (Figure 3). Further, such a nozzle row by the nozzles 29 is formed by the width of the paper to be printed, thereby forming a full-line type line head, and a desired image etc. at a higher speed than in the case of a serial head printer head. Can be printed.

  In such a head assembly 20, a high breakdown voltage driving transistor 32 is formed with an offset LOCOS structure, whereby the breakdown voltage between the gate and drain for driving the heating element 27 is increased. In the transistor 32 having such an offset LOCOS structure, when the insulating layer 36 is formed, a residue 37 and a crystal defect 38 due to the silicon nitride film are generated in the formation region of the gate oxide film 42 (FIG. 1A). Normally, in this type of transistor, a gate oxide film is formed with a film thickness that suppresses deterioration of the threshold voltage due to these residues 37 and crystal defects 38, thereby ensuring insulation of the gate oxide film.

  Thus, in the case where the insulating property of the gate oxide film 42 is ensured in this way, the gate input voltage is boosted by the booster circuit provided in the gate input voltage portion of the transistor 32, thereby the head assembly 20. Then, the transistors 32 and 33 are controlled to be turned on / off by different gate input voltages, so that the configuration relating to driving of the heat generating element 27 becomes complicated, and the area of the head chip increases by the provision of the booster circuit.

  However, in this embodiment, a gate oxide film 42 is formed with a film thickness corresponding to the gate input voltage equivalent to that of the logic circuit transistor 33, and a sacrificial oxide film 39 is formed before the gate oxide film 42 is formed. By removing, the insulating property of the gate oxide film 42 is ensured.

  That is, in the formation region of the gate oxide film 42, the crystal defects 38 are repaired by thermal oxidation of the substrate 34 and the residue 37 is absorbed in the sacrificial oxide film 39 (FIG. 1B), and the sacrificial oxide film 39 by etching is obtained. The residue 37 is also removed by removing (FIG. 1C). As a result, a clean surface of the silicon substrate 34 is exposed, and then a gate oxide film 42 is formed by thermal oxidation of the clean surface (FIG. 1D).

  Thereby, in the head assembly 20, the transistors 32 and 33 are controlled to be turned on and off by the same gate input voltage, and the insulation of the gate oxide film 42 of the transistor 32 is not ensured, so that the area of the head chip is increased. It is possible to prevent a decrease in operating speed and an increase in on-resistance value.

  In practice, when a transistor having a breakdown voltage of about 20 [V] between the gate and the drain is formed by a conventional structure in which a diffusion layer is simply provided, the chip area is remarkably increased, the operation speed is further reduced, and the on-resistance value is increased. On the other hand, when a transistor having a breakdown voltage of about 40 [V] between the gate and the drain was formed by the configuration according to this example, the chip area was increased, the operation speed was decreased, and the on-resistance value was increased. Was not seen at all.

  In addition, the sacrificial oxide film 39 used to ensure the insulation of the gate oxide film 42 is reliably formed by being thicker than the silicon nitride film used for forming the insulating layer 36. In addition, the residue 37 can be removed from the gate formation region.

(3) Advantages of the embodiment According to the above configuration, the high breakdown voltage driving transistor is formed by the offset LOCOS structure, and the sacrificial oxide film is formed and removed before the gate oxide film of the transistor is formed. Thus, a high breakdown voltage driving transistor and a logic circuit for driving the transistor are integrally formed on the substrate, thereby preventing an increase in chip area and a decrease in operating speed.

  In the above-described embodiment, a case has been described in which a high breakdown voltage driving transistor and a transistor for driving this transistor are formed with different gate lengths to form a gate oxide film with a corresponding film thickness. The present invention is not limited to this, and can be widely applied to the case where these transistors are formed with the same gate length. In this case, the process for forming the gate oxide film can be simplified.

  In the above-described embodiment, a case has been described in which the present invention is applied to a full-line type printer head for color printing to create four nozzle arrays. However, the present invention is not limited to this, for example, monochrome printing. For example, when the present invention is applied to a full-line type printer head for producing a single nozzle array, the present invention can be widely applied to the production of nozzle arrays of various numbers.

  In the above-described embodiments, the case where the present invention is applied to a printer head to eject ink droplets has been described. However, the present invention is not limited to this, and instead of ink droplets, the droplets are liquids of various dyes. Droplets, liquid discharge heads that are droplets for forming a protective layer, etc., microdispensers where the droplets are reagents, various measuring devices, various test devices, and various types of droplets that are agents that protect members from etching The present invention can be widely applied to pattern drawing apparatuses and the like.

  In the above-described embodiments, the case where the present invention is applied to a thermal-type printer head has been described. However, the present invention is not limited to a thermal-type printer head, and includes, for example, an integrated circuit for driving a motor related to frequency control and various actuators. The present invention can be widely applied to an integrated circuit for driving to be driven.

  The present invention relates to a liquid discharge head, a liquid discharge apparatus, a method of manufacturing a liquid discharge head, an integrated circuit, and a method of manufacturing an integrated circuit, and can be applied to, for example, a thermal ink jet printer.

It is sectional drawing with which it uses for description of the transistor by the production process of the head chip of the head assembly applied to the line printer which concerns on Example 1 of this invention. 1 is a perspective view illustrating a line printer according to a first embodiment of the invention. FIG. 3 is an enlarged perspective view showing a portion related to ejection of ink droplets in the head assembly of FIG. 2. FIG. 3 is a cross-sectional view showing a portion related to ejection of ink droplets in the head assembly of FIG. 2. FIG. 5 is a cross-sectional view for explaining a head chip production process in the head assembly of FIG. 4. It is sectional drawing which shows the continuation of FIG. It is sectional drawing which shows the continuation of FIG. It is sectional drawing which shows the continuation of FIG. It is sectional drawing which shows the transistor applied to the conventional printer head. It is sectional drawing which shows the transistor by a DDD structure. It is sectional drawing which shows the transistor by an offset drain structure. It is sectional drawing which shows the transistor by an offset LOCOS structure. FIG. 13 is a cross-sectional view for explaining the vicinity of the gate electrode of the transistor in FIG. 12.

Explanation of symbols

1, 32, 33... Transistor 2, 34... Substrate 3, 36... Insulating layer 4, 42, 43... Gate oxide film 7, 37. ... head assembly, 24 ... head chip, 27 ... heating element

Claims (5)

A heating element, a field effect transistor for driving the heating element, and a logic circuit for driving the field effect transistor are integrally formed on a substrate, and a liquid chamber is formed by driving the heating element by the field effect transistor. In the liquid discharge head that heats the liquid held in the liquid and ejects the liquid droplets from the nozzle,
At least the field effect transistor is
An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the gate oxide film under the gate electrode on the drain side.
The insulating layer is
After depositing a silicon nitride film on the substrate excluding at least a portion where the insulating layer is formed, formed by thermal oxidation of the substrate,
The gate oxide film is
After removing the silicon nitride film by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate,
The liquid discharge head is formed by removing the sacrificial oxide film by etching and then thermally oxidizing the substrate. In a liquid ejection device that supplies liquid droplets ejected from a liquid ejection head to an object,
The liquid discharge head is
A heating element, a field effect transistor for driving the heating element, and a logic circuit for driving the field effect transistor are integrally formed on a substrate, and a liquid chamber is formed by driving the heating element by the field effect transistor. The liquid held in the container is heated to cause the liquid droplet to jump out of the nozzle,
At least the field effect transistor is
An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the gate oxide film under the gate electrode on the drain side.
The insulating layer is
After depositing a silicon nitride film on the substrate excluding at least a portion where the insulating layer is formed, formed by thermal oxidation of the substrate,
The gate oxide film is
After removing the silicon nitride film by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate,
The liquid discharging apparatus, wherein the sacrificial oxide film is formed by thermal oxidation of the substrate after the sacrificial oxide film is removed by etching. A heating element, a field effect transistor for driving the heating element, and a logic circuit for driving the field effect transistor are integrally formed on a substrate, and a liquid chamber is formed by driving the heating element by the field effect transistor. In a method of manufacturing a liquid discharge head that heats the liquid held in the liquid and ejects the liquid droplets from the nozzle,
At least the field effect transistor is
An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the gate oxide film under the gate electrode on the drain side.
The method of manufacturing the liquid discharge head is as follows:
After depositing a silicon nitride film on the substrate excluding at least a portion where the insulating layer is to be formed, the insulating layer is formed by thermal oxidation of the substrate,
After removing the silicon nitride film by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate,
A method of manufacturing a liquid discharge head, comprising: removing the sacrificial oxide film by etching; and forming the gate oxide film by thermal oxidation of the substrate. In an integrated circuit in which a field effect transistor and a logic circuit for driving the field effect transistor are integrally formed on a substrate,
At least the field effect transistor is
An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the gate oxide film under the gate electrode on the drain side.
The insulating layer is
After depositing a silicon nitride film on the substrate excluding at least a portion where the insulating layer is formed, formed by thermal oxidation of the substrate,
The gate oxide film is
After removing the silicon nitride film by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate,
The integrated circuit is formed by removing the sacrificial oxide film by etching and then thermally oxidizing the substrate. In a method of manufacturing an integrated circuit in which a field effect transistor and a logic circuit for driving the field effect transistor are integrally formed on a substrate,
At least the field effect transistor is
An insulating layer that relaxes the electric field between the drain and the gate electrode is formed on a part of the gate oxide film under the gate electrode on the drain side.
The method of manufacturing the integrated circuit includes:
After depositing a silicon nitride film on the substrate excluding at least a portion where the insulating layer is to be formed, the insulating layer is formed by thermal oxidation of the substrate,
After removing the silicon nitride film by etching, a sacrificial oxide film is formed by thermal oxidation of the substrate,
The method of manufacturing an integrated circuit, wherein the sacrificial oxide film is removed by etching, and then the gate oxide film is formed by thermal oxidation of the substrate.

Images