JP2005168231A - Charging circuit for electric double-layer capacitor with parallel monitors - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charging circuit for an electric double-layer capacitor which is capable of realizing a circuit configuration of monitors in parallel with a minimum number of components, and easily separating each of the parallel monitors electronically in the course of transition to relaxation charging by constant voltage power supply, and which is connected with single cells connected in series. <P>SOLUTION: The parallel monitors consisting of one field effect transistor (FET) and two voltage dividing resistors are disposed in parallel to each of the single cells. MOSFET gates at all the parallel monitors are grounded by a comparator detecting that all the capacitor single cells are fully charged and MOSFET operated by the output of the comparator to electronically separate each of the parallel monitors from a charging circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electric double layer capacitor (capacitor) charging circuit in which single cells are connected in series.

  In recent years, an electric double layer capacitor (EDLC) has been applied to a solar power generation device as a power source for driving an electric vehicle and a memory backup power source. An electric double layer capacitor has advantages such as a large capacity (farad order), high energy density, high speed charge / discharge, and excellent cycle life.

  However, the rated voltage of the electric double layer capacitor element (single cell) does not have to be as low as 2.3 V to 2.5 V, which is a withstand voltage in which the electric double layer functions as a capacitor insulator and does not cause electrolysis. I do not get. Thus, for use in the field of power electronics, a plurality of single cells are connected in series. However, each capacitor cell has a difference in capacity and leakage resistance, and there is a residual voltage of each capacitor. It is difficult to uniformly charge a plurality of single cells connected in series to a withstand voltage (full charge). is there.

Simply charging a single cell connected in series results in uneven charging voltage due to leakage current peculiar to an electric double layer capacitor, many CR arrangements, and differences in capacitance. Thus, the charging voltage is restricted to the cell that has been fully charged first because of the withstand voltage of each single cell. For this reason, compared with the stored energy when all the single cells are fully charged, the power loss is significant. To solve this problem, the charging voltage is detected and monitored for each electric double layer capacitor (single cell) so that the charging voltage does not exceed the withstand voltage of the single cell, and the withstand voltage (withstand voltage guarantee) A parallel monitor circuit that stops the charging operation of the electric double layer capacitor (single cell) by bypassing the charging current when the voltage reaches (voltage) is known (for example, see Patent Document 1).
Japanese Patent Laid-Open No. 2003-244859

  However, the parallel monitor in the above prior art performs complex control while detecting the total current using a shunt regulator (comparator), an npn transistor, and the like. A charge change point is set at a voltage value lower than the set charge voltage of the capacitor, and when the capacitor module voltage exceeds the charge change point, a charge control system is adopted that shifts from constant current charge to constant voltage charge. Consists of a shunt regulator and a transistor, and the power consumed by a 100 A parallel monitor is 250 W.

  On the other hand, the parallel monitor requires only the number of electric double layer capacitors (single cells) connected in series, and it is desirable that the circuit configuration of the parallel monitor is simple. In many cases, a configuration in which a shunt regulator, a comparator, and a Zener diode are used and the bypass current flows through a transistor or a resistor is employed, and the number of electronic components is large. In addition, when all the electric double layer capacitors (single cells) connected in series are fully charged, it is unavoidable to perform relaxation charging at a constant voltage due to the nature of the electric double layer capacitor. It is difficult to set the charging voltage, and the amount of electricity stored in the electric double layer capacitor is reduced.

  The present invention realizes the circuit configuration of the parallel monitor with the minimum number of parts, and when the apparent charge of the single cell is reached, the charging current is bypassed to the parallel circuit to stop the charging operation of the single cell in series. When all the connected single cells are fully charged, the parallel monitor of each single cell can be switched to relaxed charging with a constant voltage power supply without using a parallel monitor that consumes a large amount of power in the case of constant voltage charging. An object of the present invention is to provide a charging circuit for an electric double layer capacitor having a parallel monitor that can be disconnected from the charging circuit.

  In order to solve the above-mentioned problems, an invention according to claim 1 is a charging circuit for an electric double layer capacitor in which single cells are connected in series, and a field effect transistor (FET) in parallel with each single cell. Or a hysteresis comparator for arranging a parallel monitor comprising one insulated gate bipolar transistor (IGBT) and two voltage dividing resistors and detecting full charge of all the electric double layer capacitor single cells connected in series; A field effect transistor (FET) capable of controlling the gate voltage of each parallel monitor FET to be turned on and turned off via diodes D1, -----, Dn, and a constant current, when an output signal from the hysteresis comparator is input Power supply controller for switching to either the power source or the constant voltage source, all connected in series When the electric double layer capacitor single cell is fully charged, it is detected and the parallel monitors are electronically disconnected from the charging circuit, and the charging power supply controller is switched from the constant current source to the constant voltage source for relaxation charging. It is a charging circuit for an electric double layer capacitor having a parallel monitor configured to shift.

  The invention according to claim 2 has the parallel monitor according to claim 1, wherein a light emitting diode (LED) is connected in series to the source side voltage dividing resistor so that the full charge of each single cell can be visually recognized. It is a charging circuit for an electric double layer capacitor.

  According to a third aspect of the present invention, a field effect transistor (FET) constituting a parallel monitor is connected to a resistor in series with a source in order to reduce a variation in bias due to a temperature change. Alternatively, an electric double layer capacitor charging circuit having the parallel monitor according to claim 2.

  According to a fourth aspect of the present invention, a resistor is inserted between a gate and a diode in a circuit that grounds the gate voltage of a field effect transistor (FET) in each parallel monitor via a diode, thereby reducing the current flowing through the voltage dividing resistor. A charging circuit for an electric double layer capacitor having a parallel monitor according to any one of claims 1 to 3, wherein the charging circuit is configured as described above.

  According to a fifth aspect of the present invention, a light emitting diode (LED) is connected in series with the ground resistance of the hysteresis comparator output so that it can be visually recognized that each parallel monitor is disconnected from the charging circuit. A charging circuit for an electric double layer capacitor having the parallel monitor according to claim 4.

  According to the present invention, since the parallel monitor has a circuit configuration having the minimum number of parts, the electric double layer capacitor charging circuit including single cells connected in series also has a very simple circuit configuration. The advantage increases as the number of single cells connected in series increases. In addition, when all the single cells of the electric double layer capacitor consisting of single cells connected in series are fully charged, a hysteresis comparator detects that the parallel monitor is easily electronically charged when shifting to relaxed charging. Since the circuit can be separated from the circuit, the electric double layer capacitor can be provided with the maximum power storage capacity without power loss.

  Moreover, in the electric double layer capacitor charging circuit of the present invention, there is a period in which the charging current flows to both the parallel monitor side and the capacitor (single cell) side, and all of the charging current flows to the parallel monitor side from a certain point in time. Compared with the monitor, when the operation period of the parallel monitor is the same, the power consumption can be reduced.

  The present invention can be applied to charging a redox flow battery, which is a large-capacity capacitor, and can be applied to various power electronics power supplies. Further, since the parallel monitor has a simple configuration and low power consumption, it can be modularized and integrated.

  Since the electric double layer capacitor cell has a complicated RC arrangement, if all of the single cells of the electric double layer capacitor connected in series are fully charged and then immediately stop charging, the cell terminal is self-discharged. Since the voltage drops, the battery is not fully charged and the maximum power storage capacity cannot be obtained. Therefore, if full charge is performed for a predetermined time with a constant voltage power supply, a true full charge can be obtained, and all capacitors (single cells) can exhibit the maximum power storage capacity. Here, when the parallel monitor operates during the relaxation charging period, most of the charging current flows to the parallel monitor side, resulting in a great power loss. Thus, the parallel monitor is not required during the relaxation charging period. Therefore, in the present invention, the relaxation monitor is configured so that the parallel monitor can be electronically disconnected from the charging circuit and relaxed charging can be performed.

  In the present invention, the parallel monitor is a low-voltage field-effect transistor MOSFET (metal-oxide semiconductor field effect transistor) or an insulated gate bipolar transistor (IGBT) and two resistors. This is a very simple configuration. In addition, when all the single cells connected in series are apparently fully charged, it is detected and it is very easy to disconnect each parallel monitor from the charging circuit and use a constant voltage power supply under the condition of minimum power loss. Transition to relaxed charging.

  FIG. 1A shows an embodiment of a parallel monitor in an electric double layer capacitor charging circuit having the parallel monitor of the present invention. In FIG. 1 (a), I is a charging current, C is a single cell of an electric double layer capacitor, and in parallel with this capacitor single cell C, it is composed of one MOSFET and two resistors aR and R in parallel. A monitor is connected. D is a drain, G is a gate, and S is a source, which constitutes a MOSFET having a body diode.

  To explain the operation of this circuit, the capacitor single cell starts to be charged by the current from the constant current power source, but the gate and source terminals of the MOSFET are in parallel with the single cell of the capacitor, and the voltage between the gate and source of the MOSFET is the single capacitor. This is the partial pressure of the cell. Thus, since the terminal voltage of the capacitor single cell is also low at the beginning of charging, the gate-source voltage is below the threshold value, no current flows through the MOSFET, the charging current flows exclusively to the capacitor single cell side, and the electric double layer capacitor The terminal voltage of a single cell increases linearly.

  When the terminal voltage of the capacitor single cell approaches the withstand voltage of the single cell, the voltage between the gate and source of the MOSFET exceeds the threshold value, and the current begins to flow through the MOSFET, and then the voltage between the gate and source further increases. All current flows through the MOSFET and is bypassed without flowing to the capacitor single cell side. Thus, the charging operation of the capacitor single cell is stopped, and the increase of the terminal voltage is stopped.

  By the way, in order to stop the charging current when the terminal voltage of the capacitor single cell has just reached the withstand voltage of the single cell and bypass it to the MOSFET side, the voltage between the gate and the source of the MOSFET versus the drain in advance. By examining the current characteristics, a of the voltage dividing resistors R and aR is determined. In order to set the current flowing through the resistors R and aR to a value that can be sufficiently ignored as compared with the charging current, the resistor is set to a value in the order of kΩ.

  The MOSFET of the parallel monitor in the electric double layer capacitor charging circuit having the parallel monitor of the present invention has a body diode as shown in FIG. This body diode also has an advantage of preventing reverse charging of the capacitor single cell.

  Next, in the present invention, a comparator is used for full charge detection of all single cells connected in series. When all the single cells are apparently fully charged, the output of the comparator (Comp) shown in FIG. 4 is changed from the low level to the high level, and the MOSFET (Q1) is turned on from off by the output signal from the comparator. By this operation, the gate voltage of the MOSFET which is the parallel monitor of each single cell is grounded via the diodes D1 to D4, so that all the MOSFETs (parallel monitor) are turned off and each parallel monitor is electronically disconnected from the charging circuit. . At this time, a part of the charging current flows through the resistors aR and R of each parallel monitor, but the resistance values of the resistors aR and R are in the order of kΩ, and the power consumption due to these resistors hardly poses a problem.

  In the present invention, the comparator (Comp) is a hysteresis comparator to prevent the MOSFET (Q1) from being turned on again from being turned off due to a decrease in the capacitor voltage when switching from constant current charging to constant voltage charging (relaxation charging). Yes.

  FIG. 1A shows a basic circuit of a parallel monitor in a charging circuit for an electric double layer capacitor having the parallel monitor of the present invention. The parallel monitor consists of a minimum number of parts including one MOSFET and two resistors. The drain D of the MOSFET is connected to the positive electrode of the capacitor single cell, and the source S is connected to the negative electrode of the single cell. The voltage dividing resistors R and aR are connected between the drain D and gate G of the MOSFET and between the gate G and source S. Each is inserted.

  At the initial stage of charging the capacitor single cell, the charging voltage of the capacitor single cell is also low, and the voltage between the gate G and the source S of the MOSFET is below the threshold value, so that the charging current flows exclusively to the capacitor single cell side and charging of the capacitor single cell is performed. Is done. Thus, when the charging voltage of the capacitor single cell approaches the withstand voltage of the single cell, the voltage between the gate G and the source S of the MOSFET exceeds the threshold value, and the charging current flows through both the MOSFET and the capacitor single cell. Thereafter, the voltage between the gate G and the source S further increases, and all the charging current flows to the MOSFET side and is bypassed, and the charging operation of the capacitor single cell is stopped.

In order to stop the charging current when the charging voltage of the capacitor single cell is just the withstand voltage of the single cell and to bypass to the MOSFET side, the drain current I _D (charging) The current S) is a parameter, and the voltage V _DS between the source S and the drain D versus the voltage V _GS between the gate G and the source S is measured by the circuit shown in FIG. FIG. 3 shows an example of the measurement result. From the measurement result shown in FIG. 3, the voltage dividing resistance ratio a is determined. First, if the withstand voltage of the capacitor single cell is 2.5V, for example, draw a straight line passing through V _DS = 2.5V and parallel to the horizontal axis. If the charging current is 2A, the intersection with the 2A curve Assuming P, the horizontal coordinate value V _{GS at} point P is the full charge voltage (withstand voltage). A is determined by substituting V _DS = 2.5 V and V _GS = 2.0 V into the formula V _DS = (1 + a) V _GS . R may be a resistance value in the order of kΩ.

Normally, electric double layer capacitors are connected in series with single cells of the same type and the same capacity. Therefore, if the same manufacturer and type are used for the MOSFETs of all parallel monitors, the above-mentioned voltage V _GS characteristics between the gate G and the source S are used. This measurement may be performed once, and the variation in full charge voltage (withstand voltage) is within an error range. When an electric double layer capacitor is used as a secondary battery, the power consumption of the parallel monitor is the maximum in the first charge, and the power consumption of the parallel monitor in the second and subsequent charging is so large that the operation time of the parallel monitor is shortened. Must not. This is because each single cell is reset at full charge in the first charge.

FIG. 4 shows a charging circuit for an electric double layer capacitor in which four single cells of the electric double layer capacitor are connected in series. A parallel monitor is connected to each single cell in parallel with the single cell, and is disconnected from the charging circuit during relaxation charging of each single cell by the operation of the parallel monitor disconnection circuit. When all the single cells have an apparent full charge voltage V _full , a hysteresis comparator (Comp) detects it and switches its output from off to on. As a result, the MOSFET (Q1) is turned on from off, and the gate voltage of each parallel monitor is grounded through the diodes D1 to D4.

Here, since the negative electrode (source voltage) of each single cell is all a positive voltage, the voltage V _GS between the gate G and the source S of the MOSFET in the parallel monitor is less than the threshold value, and each parallel monitor is disconnected from the charging circuit. It becomes a state. Detection (visual recognition) of this state can be performed by the light emitting diode LED1.

  When the switch SW1 is switched from the constant current source to the constant voltage source by the charging power supply controller, relaxation charging is started for a predetermined time. In this relaxed charging period, the parallel monitor is charged while being disconnected from the charging circuit, so that each single cell is fully charged and the amount of charge stored in the capacitor is maximized.

  The comparator (Comp), when the charging power source is switched, the terminal voltage of the single cell drops due to self-discharge, the MOSFET (Q1) is turned off and the parallel monitor operates again, and the charge charge of each single cell is monitored in parallel. Hysteresis comparator is used so that it does not flow to the side.

  FIG. 5 shows a circuit in which the power loss is further reduced in the charging circuit shown in FIG. When n single cells of an electric double layer capacitor are connected in series and k is a resistance voltage dividing coefficient,

The hysteresis width is V _full ⁺ −V _full ⁻ . In the circuit shown in FIG. 4, a current flows through the resistance aR of each parallel monitor although the current is small even during the relaxation charging period. These currents are in the order of aR current of the parallel monitor 4> aR current of the parallel monitor 3> aR current of the parallel monitor 2> aR current of the parallel monitor 1. The charging circuit improved so that these currents are further reduced is the circuit shown in FIG. Resistors r4 to r1 are connected in series to the diodes D1 to D4, respectively, to reduce the current flowing through the voltage dividing resistor. The resistance values are set in the order of r4>r3>r2> r1.

FIG. 1B shows a circuit in which the light emitting diode LED is connected in series with the voltage dividing resistor R in the parallel monitor shown in FIG. 1A so that the full charge voltage of each single cell can be visually recognized. In this embodiment, instead of the formula _{V DS = (1 + a)} V GS in Example 1 to apply the expression _{V DS = (1 + a)} V GS -aV F. Here, V _F is the forward voltage of the light emitting diode LED, the resistor R is to select a resistance value as light emitting diodes LED lights, the power consumption compared to the embodiment shown in FIG. 1 (a) slightly increases . The rest of the configuration of the electric double layer capacitor as the charging circuit is the same as in the first or second embodiment.

In FIG. 1 (c), in order to suppress the fluctuation of the full charge voltage caused by the temperature change of the MOSFET in the parallel monitor, a small resistance R _S is inserted in series with the source S of the MOSFET to improve the stability. The circuit is shown. In this embodiment, the V _DE vs. V _GE characteristic is measured in advance with the circuit shown in FIG. 2 using the MOSFET drain current I _D (which becomes the charging current) as a parameter. The equation V _DE = (1 + a) V _GE is used to determine the voltage _dividing resistance ratio a in this embodiment. The rest of the configuration of the electric double layer capacitor as the charging circuit is the same as in the first or second embodiment.

  The present invention can be applied not only to charging a redox flow battery that is a large-capacity capacitor but also to various power electronics power sources.

FIG. 2 is a circuit diagram showing a parallel monitor according to an embodiment of the present invention, wherein (a) a circuit diagram showing a basic circuit of the parallel monitor, (b) a light emitting diode LED is biased to make a full charge of a single cell visible. A circuit diagram showing a circuit inserted in series with the resistor R. (c) A circuit showing a circuit in which a small resistor is inserted in series with the source S of the MOSFET in order to suppress fluctuations in bias due to temperature changes of the MOSFETs constituting the parallel circuit. Figure 4 is a circuit diagram showing a circuit for measuring drain current I _D -gate-source voltage V _GS characteristics of a parallel monitor according to the present invention. FIG. 2 is a graph showing an example of the result of measuring the V _DS -V _GS characteristic using the _ID as a parameter in the circuit shown in FIG. The circuit diagram which shows the circuit for charge of the electric double layer capacitor which connected the four single cells in series based on one Example of this invention The circuit diagram which shows the circuit for charge of the electric double layer capacitor which connected the four unit cells based on the other Example of this invention in series

Explanation of symbols

I charging current C capacitor single cell D drain G gate S source aR voltage dividing resistor R voltage dividing resistor LED light emitting diode _RS resistance E source Comp comparator D1 to D4 diode SW1 switch Q1 MOSFET for gate voltage control of parallel monitor
r1-r4 resistance

Claims (5)

  A charging circuit for an electric double layer capacitor in which single cells are connected in series, each of which includes one field effect transistor (FET) or insulated gate bipolar transistor (IGBT) and two voltage dividing resistors. A parallel monitor is provided, and a hysteresis comparator that detects the full charge of all the electric double layer capacitors connected in series and an output signal from the hysteresis comparator are input, and the gate voltage of each parallel monitor FET is It consists of a field effect transistor (FET) that can be turned on and off via diodes D1, ----, Dn, and a charging power supply controller that switches to either a constant current source or a constant voltage source. When all the electric double layer capacitors that have been fully charged are detected, An electric double layer capacitor charging circuit having a parallel monitor configured to electronically disconnect the column monitor from the charging circuit and switch the charging power supply controller from a constant current source to a constant voltage source to shift to relaxed charging.   The electric double layer capacitor charging circuit having a parallel monitor according to claim 1, wherein a light emitting diode (LED) is connected in series with a source side voltage dividing resistor so that a full charge of each single cell can be visually recognized.   The parallel monitor according to claim 1 or 2, wherein a field effect transistor (FET) constituting the parallel monitor is connected to a resistor in series with a source so as to reduce a variation in bias due to a temperature change. An electric double layer capacitor charging circuit.   2. A structure in which a resistor is inserted between a gate and a diode in a circuit in which a gate voltage of a field effect transistor (FET) in each parallel monitor is grounded via a diode, so that a current flowing through the voltage dividing resistor is reduced. An electric double layer capacitor charging circuit comprising the parallel monitor according to claim 3. The light emitting diode (LED) is connected in series to a ground resistance of a hysteresis comparator output so that it can be visually recognized that each parallel monitor is disconnected from the charging circuit. An electric double layer capacitor charging circuit having a parallel monitor.

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