JP2005166249A - 磁気メモリセル書込み電流の調節 - Google Patents
磁気メモリセル書込み電流の調節 Download PDFInfo
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- JP2005166249A JP2005166249A JP2004349800A JP2004349800A JP2005166249A JP 2005166249 A JP2005166249 A JP 2005166249A JP 2004349800 A JP2004349800 A JP 2004349800A JP 2004349800 A JP2004349800 A JP 2004349800A JP 2005166249 A JP2005166249 A JP 2005166249A
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- 238000000034 method Methods 0.000 claims abstract description 36
- 230000003247 decreasing effect Effects 0.000 claims abstract description 5
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- 230000005415 magnetization Effects 0.000 description 7
- 230000004044 response Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 3
- 238000013500 data storage Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000005389 magnetism Effects 0.000 description 1
- 230000036316 preload Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
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Abstract
磁気メモリセル書込み電流を最適な大きさに調節する方法、およびそのような調節器を備えた磁気メモリセルアレイを提供すること。
【解決手段】
本発明は、磁気メモリセル書込み電流を調節する装置および方法を含む。本方法は、磁気メモリセル書込み電流に書込み電流オフセットを加算し、変更された磁気メモリセル書込み電流で磁気メモリセルに対する書込みを行なったときに書き込みエラー状態が発生するか否かを判定することを含む。書込みエラーが発生する場合、本方法は、書込みエラー状態が解消されるところまでその磁気メモリセル書込み電流をインクリメントまたはデクリメントする。
【選択図】図6
Description
本特許出願は2003年9月8日にFred Pernerによって出願された「An Apparatus and Method for Generating a Write Current for a Magnetic Memory Cell」と題する米国特許出願第10/658,442号に関連する。
図10は、2つの異なるMRAMセル温度において、MRAMメモリセルの状態を変化させるのに必要な外部磁界の強度を示すグラフを示す。第1の曲線1010は、第1の温度において、磁気トンネル接合の磁気的向きを変化すなわち反転させるために必要な磁界強度を示す。第2の曲線1020は、第2の温度において、磁気トンネル接合の磁気的向きを変化すなわち反転させるために必要な磁界強度を示す。
520 メモリセルアレイ
530 閾値検出器
610 アップ/ダウンカウンタ
Claims (10)
- メモリセルに書込みを行う装置であって、
メモリセルアレイ(520)に接続される書込み電流を生成するための書込み電流発生器(510)と、
前記書込み電流が最大書込み電流閾値より大きいか、または最小書込み電流閾値よりも小さい場合に、制御インジケータを前記書込み電流発生器(510)へフィードバックする閾値検出器(530)と、
からなる装置。 - 前記閾値検出器(530)は、書込み電流オフセットを前記書込み電流に加算し、書込みエラーが発生するか否かを判定することにより、前記書込み電流が最大書込み電流閾値よりも大きいか、最小書込み電流閾値よりも小さいかを判定する、請求項1に記載の装置。
- 前記書込み電流オフセットは前記書込み電流を増加させて、前記書込み電流閾値の大きさを減少させるべきか否かを判定する、請求項2に記載の装置。
- 前記書込み電流オフセットは前記書込み電流を減少させて、前記書込み電流閾値の大きさを増加させるべきか否かを判定する、請求項2に記載の装置。
- 磁気メモリセル書込み電流を調節する方法であって、
書込み電流オフセットを磁気メモリセル書込み電流に加算することにより該磁気メモリセル書込み電流を変更するステップと、
前記変更された磁気メモリセル書込み電流で磁気メモリセルに対して書込みを行う結果として、書込みエラー条件が発生するか否かを判定するステップと
書込みエラー状態が存在する場合、該書込みエラー状態が解消されるところまで、前記磁気メモリセル書込み電流をインクリメントまたはデクリメントするステップと、
からなる方法。 - 前記書込み電流オフセットは前記磁気メモリセル書込み電流を減少させて、前記磁気メモリセル書込み電流の大きさを増加させるべきか否かを判定する、請求項5に記載の方法。
- 前記書込み電流オフセットは前記磁気メモリセル書込み電流を増加させて、前記磁気メモリセル書込み電流の大きさを減少させるべきか否かを判定する、請求項5に記載の方法。
- 前記磁気メモリセル書込み電流は容易軸電流および困難軸電流を含み、該困難軸電流がデフォルト値に設定され、該容易軸線電流がインクリメントされる、請求項5に記載の方法。
- 前記磁気メモリセル書込み電流の大きさは、アップ/ダウンカウンタ(610)をインクリメントすることにより増加させられる、請求項6に記載の方法。
- 前記磁気メモリセル書込み電流の大きさは、アップ/ダウンカウンタ(610)をデクリメントすることにより減少させられる、請求項7に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/725,746 US6850430B1 (en) | 2003-12-02 | 2003-12-02 | Regulating a magnetic memory cell write current |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005166249A true JP2005166249A (ja) | 2005-06-23 |
JP4235606B2 JP4235606B2 (ja) | 2009-03-11 |
Family
ID=34080857
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004349800A Active JP4235606B2 (ja) | 2003-12-02 | 2004-12-02 | 磁気メモリセル書込み電流の調節 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6850430B1 (ja) |
EP (1) | EP1538631A1 (ja) |
JP (1) | JP4235606B2 (ja) |
CN (1) | CN1627434B (ja) |
TW (1) | TWI256055B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5302482B1 (ja) * | 2011-12-01 | 2013-10-02 | パナソニック株式会社 | 不揮発性半導体記憶装置およびその書き込み方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3866701B2 (ja) * | 2003-08-25 | 2007-01-10 | 株式会社東芝 | 磁気ランダムアクセスメモリ及びそのテスト方法 |
JP2007157206A (ja) * | 2005-12-01 | 2007-06-21 | Renesas Technology Corp | 半導体集積回路装置 |
TWI412035B (zh) * | 2008-04-17 | 2013-10-11 | Sony Corp | Recording method of magnetic memory element |
US8937841B2 (en) * | 2012-05-16 | 2015-01-20 | SK Hynix Inc. | Driver for semiconductor memory and method thereof |
US9583170B2 (en) * | 2015-02-12 | 2017-02-28 | Qualcomm Incorporated | Adjusting resistive memory write driver strength based on a mimic resistive memory write operation |
US10755779B2 (en) | 2017-09-11 | 2020-08-25 | Silicon Storage Technology, Inc. | Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof |
US10761749B2 (en) * | 2018-10-31 | 2020-09-01 | Micron Technology, Inc. | Vectorized processing level calibration in a memory component |
KR102661099B1 (ko) * | 2018-11-08 | 2024-04-29 | 삼성전자주식회사 | 전송 소자를 포함하는 불휘발성 메모리 장치 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6404671B1 (en) * | 2001-08-21 | 2002-06-11 | International Business Machines Corporation | Data-dependent field compensation for writing magnetic random access memories |
JP2003151260A (ja) * | 2001-11-13 | 2003-05-23 | Mitsubishi Electric Corp | 薄膜磁性体記憶装置 |
US6608790B2 (en) * | 2001-12-03 | 2003-08-19 | Hewlett-Packard Development Company, L.P. | Write current compensation for temperature variations in memory arrays |
US6606262B2 (en) * | 2002-01-10 | 2003-08-12 | Hewlett-Packard Development Company, L.P. | Magnetoresistive random access memory (MRAM) with on-chip automatic determination of optimized write current method and apparatus |
US6791865B2 (en) * | 2002-09-03 | 2004-09-14 | Hewlett-Packard Development Company, L.P. | Memory device capable of calibration and calibration methods therefor |
JP3908685B2 (ja) * | 2003-04-04 | 2007-04-25 | 株式会社東芝 | 磁気ランダムアクセスメモリおよびその書き込み方法 |
-
2003
- 2003-12-02 US US10/725,746 patent/US6850430B1/en not_active Expired - Lifetime
-
2004
- 2004-06-18 TW TW093117656A patent/TWI256055B/zh active
- 2004-12-01 EP EP04257485A patent/EP1538631A1/en not_active Withdrawn
- 2004-12-01 CN CN2004101001296A patent/CN1627434B/zh active Active
- 2004-12-02 JP JP2004349800A patent/JP4235606B2/ja active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5302482B1 (ja) * | 2011-12-01 | 2013-10-02 | パナソニック株式会社 | 不揮発性半導体記憶装置およびその書き込み方法 |
US9019747B2 (en) | 2011-12-01 | 2015-04-28 | Panasonic Intellectual Property Management Co., Ltd. | Nonvolatile semiconductor memory device and write method for the same |
Also Published As
Publication number | Publication date |
---|---|
CN1627434A (zh) | 2005-06-15 |
EP1538631A1 (en) | 2005-06-08 |
TWI256055B (en) | 2006-06-01 |
CN1627434B (zh) | 2010-07-14 |
JP4235606B2 (ja) | 2009-03-11 |
US6850430B1 (en) | 2005-02-01 |
TW200519960A (en) | 2005-06-16 |
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