JP2005150283A - Bga package - Google Patents

Bga package Download PDF

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Publication number
JP2005150283A
JP2005150283A JP2003383617A JP2003383617A JP2005150283A JP 2005150283 A JP2005150283 A JP 2005150283A JP 2003383617 A JP2003383617 A JP 2003383617A JP 2003383617 A JP2003383617 A JP 2003383617A JP 2005150283 A JP2005150283 A JP 2005150283A
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Japan
Prior art keywords
bga package
pads
pad
bypass capacitor
printed wiring
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Pending
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JP2003383617A
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Japanese (ja)
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JP2005150283A5 (en
Inventor
Kyoko Kobayashi
恭子 小林
Hirokazu Fukui
宏和 福井
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP2003383617A priority Critical patent/JP2005150283A/en
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Publication of JP2005150283A5 publication Critical patent/JP2005150283A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a BGA package, in which electrical characteristics can be improved and which can be miniaturized in the BGA package where semiconductor IC is stored inside and a plurality of pads for connection, with the other device being arranged on a base. <P>SOLUTION: A bypass capacitor 57 serving as a circuit component is connected to at least one pad 53' from among a plurality of pads 53 in the BGA package 51. The bypass capacitor 57 is connected to a pad 63' of a printed wiring board 61. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、内部に半導体ＩＣを収容し、底面に他の装置との接続のための複数のパッドが設けられたＢＧＡパッケージに関する。   The present invention relates to a BGA package in which a semiconductor IC is accommodated and a plurality of pads are provided on the bottom surface for connection to other devices.

プリント配線基板にデバイスを実装するために、表面実装デバイスが用いられる。表面実装デバイスとして、図６に示すようなＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージの半導体デバイスがある。図において、ＢＧＡパッケージ１の下面には、パッド３が格子状に設けられ、更に、端子３には、はんだボール５が付着されている。   A surface mount device is used to mount the device on a printed wiring board. As a surface mount device, there is a BGA (Ball Grid Array) package semiconductor device as shown in FIG. In the figure, pads 3 are provided in a lattice pattern on the lower surface of the BGA package 1, and solder balls 5 are attached to the terminals 3.

一方、プリント配線基板（ＰＣＢ）７には、ＢＧＡパッケージ１のパッド３と対応するパッド９が設けられている。そして、はんだボール５がプリント配線基板７のパッド９に接するようにＢＧＡパッケージ１を配置し、外部から熱を加えてはんだボール５を融解し、ＢＧＡパッケージ１をプリント配線基板７に実装する。装置全体が小型化しつつある現状においては、ＢＧＡパッケージが広く使用されつつある。   On the other hand, the printed wiring board (PCB) 7 is provided with pads 9 corresponding to the pads 3 of the BGA package 1. Then, the BGA package 1 is arranged so that the solder balls 5 are in contact with the pads 9 of the printed wiring board 7, heat is applied from the outside to melt the solder balls 5, and the BGA package 1 is mounted on the printed wiring board 7. In the present situation where the entire apparatus is becoming smaller, BGA packages are being widely used.

一方、デジタル回路や高周波回路等のような高速な動作クロックを用いて作動する半導体デバイスがプリント配線基板に実装された場合には、電源ラインに電流変動ノイズが発生し、半導体デバイスに悪影響が及ぶことがある。そのため、ノイズ除去のために、半導体デバイスの電力供給端子の近傍にバイパスコンデンサ（パスコン）を設けることがある。   On the other hand, when a semiconductor device that operates using a high-speed operation clock such as a digital circuit or a high-frequency circuit is mounted on a printed wiring board, current fluctuation noise occurs in the power supply line, which adversely affects the semiconductor device. Sometimes. Therefore, a bypass capacitor (pass capacitor) may be provided in the vicinity of the power supply terminal of the semiconductor device in order to eliminate noise.

図７にその一例を示す。図はＢＧＡパッケージ１１が実装されたプリント配線基板１３の裏面を示している。破線で示す１５はＢＧＡパッケージ１１のパッドである。又、実線で示す１７は、プリント配線基板１３の表面と裏面とを配線するビアホール（Ｖｉａ Ｈｏｌｅ）である。このビアホール１７を用いてプリント配線基板１３の裏面に、バイパスコンデンサ１９が接続されている。   An example is shown in FIG. The figure shows the back surface of the printed wiring board 13 on which the BGA package 11 is mounted. Reference numeral 15 indicated by a broken line denotes a pad of the BGA package 11. Reference numeral 17 shown by a solid line is a via hole for wiring the front surface and the back surface of the printed wiring board 13. A bypass capacitor 19 is connected to the back surface of the printed wiring board 13 using the via hole 17.

しかし、信号ラインとの関係でビアホール１７によりプリント配線基板の裏面まで配線できる電源ラインには制限があり、ＢＧＡパッケージ１１の周縁にもバイパスコンデンサ１９′を設けている。   However, there is a limit to the power supply line that can be wired to the back surface of the printed wiring board through the via hole 17 in relation to the signal line, and a bypass capacitor 19 ′ is also provided at the periphery of the BGA package 11.

バイパスコンデンサは、電源ラインに可能な限り近く設けることが必要で、ＢＧＡパッケージ１１の周縁に設けたバイパスコンデンサ１９′は、ノイズ除去効果があまり期待できない。又、プリント配線基板１３も大きくなる。   The bypass capacitor must be provided as close as possible to the power supply line, and the bypass capacitor 19 ′ provided at the periphery of the BGA package 11 cannot be expected to have a noise removal effect. Moreover, the printed wiring board 13 is also enlarged.

そこで、ＢＧＡパッケージの場合、以下のような方法で、バイパスコンデンサを設けることが提案されている。
（１）ＢＧＡパッケージ内にバイパスコンデンサを設ける。 Therefore, in the case of the BGA package, it has been proposed to provide a bypass capacitor by the following method.
(1) A bypass capacitor is provided in the BGA package.

図８に示すように、半導体ＩＣ（チップ）２１はサブ基板２３上に設けられ、サブ基板２３には、半導体ＩＣ２１を覆い、半導体ＩＣ２１の上面に当接する蓋状の放熱板２５が設けられている。サブ基板２３の下面には、他の装置との接続のための複数のパッド２７が設けられ、更に、各パッド２７には、はんだボール２９が付着されている。そして、バイパスコンデンサ３１がサブ基板２３上に設けられている。
（２）ＢＧＡパッケージの上面にバイパスコンデンサを搭載する（例えば、特許文献１参照。）。
特開２００２−１８４８９４号公報（第４頁、図３参照） As shown in FIG. 8, the semiconductor IC (chip) 21 is provided on the sub-substrate 23, and the sub-substrate 23 is provided with a lid-like heat radiation plate 25 that covers the semiconductor IC 21 and contacts the upper surface of the semiconductor IC 21. Yes. A plurality of pads 27 for connection to other devices are provided on the lower surface of the sub-board 23, and solder balls 29 are attached to the pads 27. A bypass capacitor 31 is provided on the sub-board 23.
(2) A bypass capacitor is mounted on the top surface of the BGA package (see, for example, Patent Document 1).
JP 2002-184894 A (see page 4, FIG. 3)

しかし、上述した（１）（２）のような方法では、以下のような問題点がある。
（１）半導体ＩＣ１の面積が大きくなると、サブ基板２３にバイパスコンデンサ３１を設けるスペースがなくなる。バイパスコンデンサ３１をサブ基板２３にどうしても設けようとすると、ＢＧＡパッケージが大形化し、プリント配線基板も大形化する。
（２）ＢＧＡパッケージの上面に放熱フィンや放熱ファンを載せる場合は、バイパスコンデンサは搭載できない。 However, the methods (1) and (2) described above have the following problems.
(1) When the area of the semiconductor IC 1 is increased, there is no space for providing the bypass capacitor 31 on the sub-board 23. If the bypass capacitor 31 is inevitably provided on the sub-board 23, the BGA package is enlarged and the printed wiring board is also enlarged.
(2) When a heat radiating fin or a heat radiating fan is placed on the upper surface of the BGA package, a bypass capacitor cannot be mounted.

又、バイパスコンデンサの代わりに、電気的特性の向上のために抵抗やコイル等の回路部品を用いる場合であっても、上述の（１）、（２）に示す方法が可能であるが、同様な問題点が生じる。   Even when circuit components such as resistors and coils are used to improve electrical characteristics instead of bypass capacitors, the methods shown in the above (1) and (2) are possible. Problems arise.

本発明は、上記問題点に鑑みてなされたもので、その課題は、電気的特性の向上、小型化が図れるＢＧＡパッケージを提供することにある。   The present invention has been made in view of the above problems, and an object thereof is to provide a BGA package capable of improving electrical characteristics and reducing the size.

上記課題を解決する請求項１に係る発明は、内部に半導体ＩＣを収容し、底面に他の装置との接続のための複数のパッドが設けられたＢＧＡパッケージにおいて、前記複数のパッドのうちの少なくとも１つに、回路部品が接続されたことを特徴とするＢＧＡパッケージである。   The invention according to claim 1, which solves the above problem, is a BGA package in which a semiconductor IC is housed and a plurality of pads are provided on the bottom surface for connection to other devices. A BGA package is characterized in that at least one circuit component is connected.

他の装置としては、プリント配線基板等があるが限定するものではない。   Other devices include, but are not limited to, a printed wiring board.

請求項２に係る発明は、前記回路部品の一方の端子は、前記ＢＧＡパッケージのパッドに接続され、他方の端子は前記他の装置に接続されることを特徴とする請求項１記載のＢＧＡパッケージである。   The invention according to claim 2 is the BGA package according to claim 1, wherein one terminal of the circuit component is connected to a pad of the BGA package, and the other terminal is connected to the other device. It is.

請求項３に係る発明は、前記回路部品は、前記ＢＧＡパッケージの複数のパッドのうちの隣接するパッド間に接続されることを特徴とする請求項１記載のＢＧＡパッケージである。   The invention according to claim 3 is the BGA package according to claim 1, wherein the circuit component is connected between adjacent pads of the plurality of pads of the BGA package.

請求項４に係る発明は、前記回路部品は複数あることを特徴とする請求項１乃至３のいずれかに記載のＢＧＡパッケージである。   The invention according to claim 4 is the BGA package according to any one of claims 1 to 3, wherein there are a plurality of the circuit components.

請求項５に係る発明は、前記回路部品は、前記回路部品は、バイパスコンデンサ、抵抗、コイルのうちの少なくとも１つであることを特徴とする請求項１乃至４のいずれかに記載のＢＧＡパッケージである。   The invention according to claim 5 is the BGA package according to any one of claims 1 to 4, wherein the circuit component is at least one of a bypass capacitor, a resistor, and a coil. It is.

請求項１に係る発明によれば、前記複数のパッドのうちの少なくとも１つに、回路部品が接続されることにより、ＢＧＡパッケージの電気的特性の向上を図れ、ＢＧＡパッケージ、及びＢＧＡパッケージが実装される装置の小型化が図れる。   According to the first aspect of the present invention, a circuit component is connected to at least one of the plurality of pads to improve the electrical characteristics of the BGA package, and the BGA package and the BGA package are mounted. Downsizing of the device can be achieved.

請求項２に係る発明によれば、前記回路部品の一方の端子は、前記ＢＧＡパッケージのパッドに接続され、他方の端子は前記他の装置に接続されることにより、ＢＧＡパッケージの電気的特性の向上を図れ、ＢＧＡパッケージ、及びＢＧＡパッケージが実装される装置の小型化が図れる。   According to the invention of claim 2, one terminal of the circuit component is connected to the pad of the BGA package, and the other terminal is connected to the other device. Improvement can be achieved, and the BGA package and the device on which the BGA package is mounted can be reduced in size.

請求項３に係る発明によれば、前記回路部品は、前記ＢＧＡパッケージの複数のパッドのうちの隣接するパッド間に接続されることにより、ＢＧＡパッケージの電気的特性の向上を図れ、ＢＧＡパッケージ、及びＢＧＡパッケージが実装される装置の小型化が図れる。   According to the invention of claim 3, the circuit component is connected between adjacent pads of the plurality of pads of the BGA package, so that the electrical characteristics of the BGA package can be improved. In addition, the apparatus on which the BGA package is mounted can be reduced in size.

請求項４に係る発明によれば、前記回路部品は複数あることにより、ＢＧＡパッケージの実装時に、はんだボールのつぶれによる実装不良を防止することができる。   According to the fourth aspect of the present invention, since there are a plurality of the circuit components, it is possible to prevent mounting failure due to collapse of the solder balls when mounting the BGA package.

請求項５に係る発明によれば、前記回路部品は、前記回路部品は、バイパスコンデンサ、抵抗、コイルのうちの少なくとも１つであることにより、ＢＧＡパッケージの電気的特性の向上を図れ、ＢＧＡパッケージ、及びＢＧＡパッケージが実装される装置の小型化が図れる。   According to the invention of claim 5, the circuit component is at least one of a bypass capacitor, a resistor, and a coil, so that the electrical characteristics of the BGA package can be improved. And a device on which the BGA package is mounted can be reduced in size.

以下、図面を用いて本発明を実施するための最良の形態を説明する。
（第１の形態例請求項１,２,４,５に対応）
第１の形態例の構成図である図１、図１のＡ部分の拡大図である図２を用いて説明する。図において、ＢＧＡパッケージ５１の下面には、複数のパッド５３が格子状に設けられている。複数のパッド５３のうちの少なくとも１つ、本形態例では、両サイドのパッド５３′以外のパッド５３には、はんだボール５５が付着されている。両サイドのパッド５３′（本実形態例では、電源ライン（Ｖｃｃ）である）には、回路部品、本形態例では、バイパスコンデンサ５７がはんだ５９を用いて実装されている。 Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.
(Corresponding to the first embodiment claim 1, 2, 4, 5)
Description will be made with reference to FIG. 1 which is a configuration diagram of the first embodiment and FIG. 2 which is an enlarged view of a portion A in FIG. In the figure, a plurality of pads 53 are provided in a lattice pattern on the lower surface of the BGA package 51. Solder balls 55 are attached to at least one of the plurality of pads 53, in this embodiment, the pads 53 other than the pads 53 'on both sides. Circuit parts, bypass capacitors 57 in this embodiment example, are mounted using solder 59 on the pads 53 ′ on both sides (in this embodiment example, the power supply line (Vcc)).

一方、プリント配線基板（ＰＣＢ）６１には、ＢＧＡパッケージ５１のパッド５３、パッド５３′と対応するパッド６３、パッド６３′が設けられている。本実形態例では、パッド６３′は接地ライン（ＧＮＤ）である。又、バイパスコンデンサ５７のパッド６３′と対向する部分には、はんだ６５が付着している。   On the other hand, a printed wiring board (PCB) 61 is provided with a pad 53 and a pad 63 ′ corresponding to the pad 53 and pad 53 ′ of the BGA package 51. In the present embodiment, the pad 63 'is a ground line (GND). Solder 65 is attached to the portion of the bypass capacitor 57 that faces the pad 63 ′.

そして、はんだボール５５がプリント配線基板６１のパッド６３に接するように、又、バイパスコンデンサ５７のはんだ６５がプリント配線基板６１のパッド６３′に接するようにＢＧＡパッケージ５１を配置し、外部から熱を加えてはんだボール５５、はんだ６５を融解することにより、ＢＧＡパッケージ５１はプリント配線基板６１に実装されている。   Then, the BGA package 51 is arranged so that the solder balls 55 are in contact with the pads 63 of the printed wiring board 61 and the solder 65 of the bypass capacitor 57 is in contact with the pads 63 'of the printed wiring board 61, and heat is externally applied. In addition, the BGA package 51 is mounted on the printed wiring board 61 by melting the solder balls 55 and the solder 65.

このような構成によれば、以下のような効果を得ることができる。
（１）ＢＧＡパッケージ５１の複数のパッドのうちの電源ラインであるパッド５３′に、バイパスコンデンサ（回路部品）５７が接続されることにより、ノイズの効果的な低減（電気的特性の向上）及びＢＧＡパッケージ５１、プリント配線基板６１の小型化が図れる。
（２）バイパスコンデンサ５７を複数設けたことにより、ＢＧＡパッケージ５１が熱により撓む場合、例えば、図１において、二点鎖線で示すように変形しても、はんだボール５５より圧縮や引張に対して変形しにくいバイパスコンデンサ５７を複数実装したことにより、はんだボール５５が圧縮されてショートしたり、引っ張られて切断され、電気的導通がなくなったりすることが防止できる。 According to such a configuration, the following effects can be obtained.
(1) By connecting a bypass capacitor (circuit component) 57 to a pad 53 ′ that is a power supply line among a plurality of pads of the BGA package 51, noise can be effectively reduced (electrical characteristics improved) and The BGA package 51 and the printed wiring board 61 can be downsized.
(2) When the BGA package 51 is bent due to heat by providing a plurality of bypass capacitors 57, for example, even if the BGA package 51 is deformed as shown by a two-dot chain line in FIG. By mounting a plurality of bypass capacitors 57 that are difficult to deform, it is possible to prevent the solder balls 55 from being compressed and short-circuited or from being pulled and cut to lose electrical conduction.

尚、本発明は、上記形態例に限定するものではない。上記形態例では、回路部品としてバイパスコンデンサ５７を用いた例で説明を行ったが、他に抵抗やコイル等の回路部品であってもよい。又、バイパスコンデンサ５７を複数設けたが、１つであってもよい。   The present invention is not limited to the above embodiment. In the above embodiment, the example in which the bypass capacitor 57 is used as the circuit component has been described. However, other circuit components such as a resistor and a coil may be used. Further, although a plurality of bypass capacitors 57 are provided, one may be used.

（第２の形態例請求項１,３,５に対応）
第２の形態例の構成図である図３、図３のＢ部分の拡大図である図４を用いて説明する。図において、ＢＧＡパッケージ１０１の下面には、複数のパッド１０３が格子状に設けられている。複数のパッド１０３のうちの隣接するパッド１０３′、パッド１０３″以外のパッド１０３には、はんだボール１０５が付着されている。尚、本形態例では、パッド１０３′は電源ライン（Ｖｃｃ）、パッド１０３″は接地ライン（ＧＮＤ）に接続されている。 (Corresponding to claims 1, 3, and 5 of the second embodiment)
This will be described with reference to FIG. 3 which is a configuration diagram of the second embodiment and FIG. 4 which is an enlarged view of a portion B in FIG. In the figure, a plurality of pads 103 are provided in a lattice shape on the lower surface of the BGA package 101. Solder balls 105 are attached to pads 103 ′ other than the adjacent pad 103 ′ and pad 103 ″ of the plurality of pads 103. In this embodiment, the pad 103 ′ is a power line (Vcc), a pad. 103 ″ is connected to a ground line (GND).

パッド１０３′、パッド１０３″間には、回路部品、本形態例では、バイパスコンデンサ１０７がはんだ１０９、はんだ１１１を用いて実装されている。   Between the pad 103 ′ and the pad 103 ″, circuit components, in this embodiment, a bypass capacitor 107 is mounted using solder 109 and solder 111.

一方、プリント配線基板（ＰＣＢ）１１３には、ＢＧＡパッケージ１０１のパッド１０３と対応するパッド１１５が設けられている。   On the other hand, the printed wiring board (PCB) 113 is provided with pads 115 corresponding to the pads 103 of the BGA package 101.

そして、はんだボール１０５がプリント配線基板１１３のパッド１１５に接するようにＢＧＡパッケージ１０１を配置し、外部から熱を加えてはんだボール１０５を融解することにより、ＢＧＡパッケージ１０１はプリント配線基板１１３に実装されている。   The BGA package 101 is mounted on the printed wiring board 113 by disposing the BGA package 101 so that the solder balls 105 are in contact with the pads 115 of the printed wiring board 113 and melting the solder balls 105 by applying heat from the outside. ing.

このような構成によれば、以下のような効果を得ることができる。
（１）ＢＧＡパッケージ１０１の複数のパッドのうちの隣り合うパッド（Ｖｃｃ）１０３′、パッド（ＧＮＤ）１０３″に、バイパスコンデンサ（回路部品）１０７が接続されることにより、ノイズの効果的な低減（電気的特性の向上）及びＢＧＡパッケージ１０１、プリント配線基板１１３の小型化が図れる。 According to such a configuration, the following effects can be obtained.
(1) By connecting a bypass capacitor (circuit component) 107 to adjacent pads (Vcc) 103 ′ and pads (GND) 103 ″ of a plurality of pads of the BGA package 101, noise can be effectively reduced. (Improvement of electrical characteristics) and downsizing of the BGA package 101 and the printed wiring board 113 can be achieved.

尚、本発明は、上記形態例に限定するものではない。上記実施の形態例では、バイパスコンデンサ１０７はＢＧＡパッケージ１０１のパッド（Ｖｃｃ）１０３′、パッド（ＧＮＤ）１０３″に実装したが、更に、図５に示すように、プリント配線基板１１３に、ＢＧＡパッケージ１０１のパッド（Ｖｃｃ）１０３′に対応し、プリント配線基板１１３の電源ラインに接続されるパッド１０５′と、ＢＧＡパッケージ１０１のパッド（ＧＮＤ）１０３″に対応し、プリント配線基板１１３の接地ラインに接続されるパッド１０５″とを設け、パッド１０５′とははんだ１１９を用いて、パッド１０５″とははんだ１２１を用いてバイパスコンデンサと接続するようにしてもよい。   The present invention is not limited to the above embodiment. In the above embodiment, the bypass capacitor 107 is mounted on the pad (Vcc) 103 ′ and the pad (GND) 103 ″ of the BGA package 101. Further, as shown in FIG. 101 corresponding to the pad (Vcc) 103 ′ of the pad 101 ′ connected to the power supply line of the printed wiring board 113 and the pad (GND) 103 ″ of the BGA package 101 corresponding to the ground line of the printed wiring board 113. A pad 105 ″ to be connected may be provided, and the pad 105 ′ may be connected to the bypass capacitor using the solder 119, and the pad 105 ″ may be connected to the bypass capacitor using the solder 121.

又、上記形態例では、回路部品としてバイパスコンデンサ１０７を用いた例で説明を行ったが、他に抵抗やコイル等の回路部品であってもよい。又、バイパスコンデンサ１０７を複数設けてもよい。   In the above-described embodiment, the example in which the bypass capacitor 107 is used as the circuit component has been described. However, other circuit components such as a resistor and a coil may be used. A plurality of bypass capacitors 107 may be provided.

第１の形態例の構成図である。It is a block diagram of a 1st form example. 図１のＡ部分の拡大図である。It is an enlarged view of the A part of FIG. 第２の形態例の構成図である。It is a block diagram of a 2nd form example. 図３のＢ部分の拡大図である。FIG. 4 is an enlarged view of a portion B in FIG. 3. 他の形態例を説明する図である。It is a figure explaining the other example of a form. ＢＧＡパッケージのプリント配線基板への実装を説明する図である。It is a figure explaining the mounting to the printed wiring board of a BGA package. 従来のバイパスコンデンサの実装を説明する図である。It is a figure explaining mounting of the conventional bypass capacitor. 従来のバイパスコンデンサの実装を説明する図である。It is a figure explaining mounting of the conventional bypass capacitor.

符号の説明Explanation of symbols

５１ ＢＧＡパッケージ
５３,５３′,６３,６３′ パッド
５５ はんだボール
５７ バイパスコンデンサ
６１ プリント配線基板 51 BGA Package 53, 53 ', 63, 63' Pad 55 Solder Ball 57 Bypass Capacitor 61 Printed Wiring Board

Claims (5)

内部に半導体ＩＣを収容し、底面に他の装置との接続のための複数のパッドが設けられたＢＧＡパッケージにおいて、
前記複数のパッドのうちの少なくとも１つに、回路部品が接続されたことを特徴とするＢＧＡパッケージ。 In a BGA package in which a semiconductor IC is accommodated inside and a plurality of pads are provided on the bottom surface for connection to other devices.
A BGA package, wherein a circuit component is connected to at least one of the plurality of pads. 前記回路部品の一方の端子は、前記ＢＧＡパッケージのパッドに接続され、他方の端子は前記他の装置に接続されることを特徴とする請求項１記載のＢＧＡパッケージ。   2. The BGA package according to claim 1, wherein one terminal of the circuit component is connected to a pad of the BGA package, and the other terminal is connected to the other device. 前記回路部品は、前記ＢＧＡパッケージの複数のパッドのうちの隣接するパッド間に接続されることを特徴とする請求項１記載のＢＧＡパッケージ。   2. The BGA package according to claim 1, wherein the circuit component is connected between adjacent pads of the plurality of pads of the BGA package. 前記回路部品は複数あることを特徴とする請求項１乃至３のいずれかに記載のＢＧＡパッケージ。   4. The BGA package according to claim 1, wherein there are a plurality of the circuit components. 前記回路部品は、バイパスコンデンサ、抵抗、コイルのうちの少なくとも１つであることを特徴とする請求項１乃至４のいずれかに記載のＢＧＡパッケージ。   The BGA package according to any one of claims 1 to 4, wherein the circuit component is at least one of a bypass capacitor, a resistor, and a coil.
JP2003383617A 2003-11-13 2003-11-13 Bga package Pending JP2005150283A (en)

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JP2007173669A (en) * 2005-12-26 2007-07-05 Murata Mfg Co Ltd Multilayered circuit board and integrated circuit package
JP2007250928A (en) * 2006-03-17 2007-09-27 Mitsubishi Electric Corp Multilayer printed wiring board
US9847299B2 (en) 2014-09-30 2017-12-19 Murata Manufacturing Co., Ltd. Semiconductor package and mounting structure thereof
JP2020520121A (en) * 2017-05-15 2020-07-02 エイブイエックス コーポレイション Multilayer capacitor and circuit board including multilayer capacitor
WO2020250947A1 (en) * 2019-06-14 2020-12-17 キヤノン株式会社 Semiconductor module manufacturing method, electronic device manufacturing method, semiconductor module, and electronic device
WO2023022047A1 (en) * 2021-08-20 2023-02-23 株式会社村田製作所 High-frequency module
JP7566054B2 (en) 2020-07-01 2024-10-11 インターナショナル・ビジネス・マシーンズ・コーポレーション Solder Column Grid Array Capacitors

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173669A (en) * 2005-12-26 2007-07-05 Murata Mfg Co Ltd Multilayered circuit board and integrated circuit package
JP2007250928A (en) * 2006-03-17 2007-09-27 Mitsubishi Electric Corp Multilayer printed wiring board
US9847299B2 (en) 2014-09-30 2017-12-19 Murata Manufacturing Co., Ltd. Semiconductor package and mounting structure thereof
JP2020520121A (en) * 2017-05-15 2020-07-02 エイブイエックス コーポレイション Multilayer capacitor and circuit board including multilayer capacitor
JP2020520122A (en) * 2017-05-15 2020-07-02 エイブイエックス コーポレイション Multilayer capacitor and circuit board including multilayer capacitor
US11636978B2 (en) 2017-05-15 2023-04-25 KYOCERA AVX Components Corporation Multilayer capacitor and circuit board containing the same
US12112891B2 (en) 2017-05-15 2024-10-08 KYOCERA AVX Components Corporation Multilayer capacitor and circuit board containing the same
WO2020250947A1 (en) * 2019-06-14 2020-12-17 キヤノン株式会社 Semiconductor module manufacturing method, electronic device manufacturing method, semiconductor module, and electronic device
US20220102330A1 (en) * 2019-06-14 2022-03-31 Canon Kabushiki Kaisha Semiconductor module manufacturing method, electronic equipment manufacturing method, semiconductor module, and electronic equipment
JP7566054B2 (en) 2020-07-01 2024-10-11 インターナショナル・ビジネス・マシーンズ・コーポレーション Solder Column Grid Array Capacitors
WO2023022047A1 (en) * 2021-08-20 2023-02-23 株式会社村田製作所 High-frequency module

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