JP2005150131A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005150131A
JP2005150131A JP2003380731A JP2003380731A JP2005150131A JP 2005150131 A JP2005150131 A JP 2005150131A JP 2003380731 A JP2003380731 A JP 2003380731A JP 2003380731 A JP2003380731 A JP 2003380731A JP 2005150131 A JP2005150131 A JP 2005150131A
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film
hole
electrodeposition
substrate
insulating film
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Masaki Mizuno
正樹 水野
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Canon Inc
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Canon Inc
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<P>PROBLEM TO BE SOLVED: To form an insulating film having good insulation in the interior of a through hole by an electrodeposition technology as a method of forming the insulating film since the formation of the insulating film inside a conductive film is necessary but is difficult from the problem of a heat resistant temperature of a MOS, when a thermal oxidation film is formed in prior art if an electric connection is performed on the front and rear surfaces of a silicon semiconductor substrate through the interior of very fine through holes provided in the substrate, a CVD or a PVD method has a limit in an aspect ratio and it is difficult to uniformly adhere in the interior. <P>SOLUTION: In a semiconductor device, before the through hole is provided in the silicon semiconductor substrate, the surface functional film of the position is removed where the through hole is provided in advance. When the electrodeposition is performed thereafter, its edge is raised largely and an electrodeposition film is deposited from the difference of the current densities of the edge and the interior, and the electrodeposition film having the good insulation can be formed without exposing the ground of the edge part even if curing is performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、シリコン半導体基板に設けた貫通孔内部に、電着塗装により絶縁膜を形成した半導体装置に関する。   The present invention relates to a semiconductor device in which an insulating film is formed by electrodeposition coating in a through hole provided in a silicon semiconductor substrate.

半導体装置の絶縁膜形成方法としては、現在一般的に熱酸化膜、CVD、PVDなどが用いられている。このような装置の具体的な例としては、特開2001−250912の発明が挙げられる。半導体チップに貫通孔を設け、その貫通孔を通して半導体チップの表裏面を電気的に接続する導電膜を形成することにおいて、貫通孔内の電気的絶縁を確実に図るために、貫通孔と導電膜の間に絶縁膜を設けている。絶縁膜は高温雰囲気中で熱処理して酸化膜を形成したシリコン酸化膜や、CVD法で形成したシリコン窒化膜、ポリイミドなどの有機絶縁膜で形成されている。   Currently, a thermal oxide film, CVD, PVD, or the like is generally used as a method for forming an insulating film of a semiconductor device. A specific example of such an apparatus is the invention of JP-A-2001-250912. In order to ensure electrical insulation in the through-hole in providing a through-hole in the semiconductor chip and forming a conductive film that electrically connects the front and back surfaces of the semiconductor chip through the through-hole, the through-hole and the conductive film An insulating film is provided between the two. The insulating film is formed of a silicon oxide film formed by heat treatment in a high temperature atmosphere, a silicon nitride film formed by a CVD method, an organic insulating film such as polyimide.

また、絶縁膜形成方法として電着技術を用いている例として、特開2002−319011の発明が挙げられる。前記同様に半導体チップの貫通孔内の絶縁膜を電着技術で形成している。
特開2001−250912 特開2002−319011
Further, as an example of using an electrodeposition technique as a method for forming an insulating film, there is an invention disclosed in JP-A-2002-319011. Similarly to the above, the insulating film in the through hole of the semiconductor chip is formed by the electrodeposition technique.
JP 2001-250912 A JP 2002-319011 A

近年、半導体装置は微細かつ複雑になってきており、非常に細かいパターンに絶縁膜を形成することが要求されている。特に、半導体基板に形成した貫通孔を利用してその表裏面の導通をとる半導体装置においては、導電パターンの高密度化に伴い50〜150μmといった非常に微細な貫通孔が要求され、その貫通孔の内側表面には必ず絶縁膜が必要となる。そのため、この微細な貫通孔の内表面に絶縁膜を均一な膜厚で形成する事が要求されている。   In recent years, semiconductor devices have become fine and complicated, and it is required to form an insulating film in a very fine pattern. In particular, in a semiconductor device that uses a through-hole formed in a semiconductor substrate to conduct on the front and back surfaces, a very fine through-hole of 50 to 150 μm is required as the conductive pattern becomes denser. An insulating film is always required on the inner surface of the film. Therefore, it is required to form an insulating film with a uniform film thickness on the inner surface of the fine through hole.

そこで前述した特開2001‐250912に記載されている絶縁膜形成方法を適用する事が提案されている。しかしながらMOS回路が搭載された半導体装置は耐熱温度350℃という制約を受けるため、1000℃近くで熱処理を行うシリコン酸化膜を形成することは不可能である。また、貫通孔の内径が微細になる傾向にあることから、CVD及びPVD法ではアスペクト比の問題から限界があり、貫通孔の内表面に均一な膜厚を形成することは不可能となってしまう。   Therefore, it has been proposed to apply the insulating film forming method described in JP-A-2001-250912 described above. However, since a semiconductor device on which a MOS circuit is mounted is restricted by a heat-resistant temperature of 350 ° C., it is impossible to form a silicon oxide film that is subjected to heat treatment near 1000 ° C. In addition, since the inner diameter of the through hole tends to be fine, the CVD and PVD methods have limitations due to the aspect ratio problem, and it becomes impossible to form a uniform film thickness on the inner surface of the through hole. End up.

そこで本発明は、シリコン半導体基板に設けられた貫通孔の内表面に絶縁膜を形成した半導体装置、貫通孔を形成する位置の表面機能膜をあらかじめ除去する工程と、該表面機能膜を除去した部分に貫通孔を形成する工程と、該貫通孔の内表面に電着を行い絶縁膜を形成する工程と、該絶縁膜の内側表面及びシリコン半導体基板の表裏面にパターン状の導電膜を形成することを特徴とした半導体装置を提案する。   Accordingly, the present invention provides a semiconductor device in which an insulating film is formed on the inner surface of a through hole provided in a silicon semiconductor substrate, a step of removing a surface functional film at a position where the through hole is to be formed, and the surface functional film is removed. Forming a through hole in a portion, forming an insulating film by electrodeposition on the inner surface of the through hole, and forming a patterned conductive film on the inner surface of the insulating film and on the front and back surfaces of the silicon semiconductor substrate A semiconductor device characterized by the above is proposed.

電着塗装は電気めっきと異なり、樹脂膜の硬化時にエッジ部分の樹脂膜がフローを起こして膜が薄くなってしまう。そのため表面機能膜を除去し、硬化前にエッジ部の樹脂膜を盛り上げておくことが必須となってくる。また電着塗装は通常エッジ部や平坦部にかかわらず、膜厚を均一につける手段として知られているが、貫通孔でこの手法を用いると、エッジ部と貫通孔内部の電流分布の大きな差を利用することで、よりエッジ部の盛り上がりの効果を引き出すことができる。   Unlike electroplating, electrodeposition coating causes the resin film at the edge to flow when the resin film is cured, resulting in a thin film. Therefore, it is essential to remove the surface functional film and swell the resin film at the edge portion before curing. Electrodeposition coating is generally known as a means of uniformly forming the film thickness regardless of the edge or flat part. However, when this method is used for through holes, there is a large difference in current distribution between the edge part and the through hole. By using, the effect of the swell of the edge portion can be further extracted.

以上説明したように本発明によれば、シリコン半導体基板に設けられた非常に微細な貫通孔の内側表面であっても、電着技術を用いることで絶縁性良好な絶縁膜を形成する事ができる。また、貫通孔の開口部においては、硬化時の熱流動によって下地が露出し未塗装状態になる事がなく、硬化後も確実に電着膜を形成する事ができる。よって電着膜の内側表面に導電膜を形成し、基板の表裏面で電気的接続を行っても、電気的絶縁を確実に図ることができる。   As described above, according to the present invention, an insulating film with good insulation can be formed by using an electrodeposition technique even on the inner surface of a very fine through hole provided in a silicon semiconductor substrate. it can. In addition, in the opening of the through hole, the base is not exposed due to heat flow at the time of curing, and an unpainted state does not occur, and an electrodeposited film can be reliably formed even after curing. Therefore, even if a conductive film is formed on the inner surface of the electrodeposition film and electrical connection is made on the front and back surfaces of the substrate, electrical insulation can be reliably achieved.

(第1の実施の形態)
図1は本発明の第1の実施の形態である、基板10に形成された貫通孔12の様子を示した図である。図1(イ)は上面図、図1(ロ)は断面図である。
(First embodiment)
FIG. 1 is a view showing a state of a through hole 12 formed in a substrate 10 according to the first embodiment of the present invention. 1A is a top view and FIG. 1B is a cross-sectional view.

図中10はシリコン半導体基板であり、11は基板10の表裏面にあらかじめ形成されているシリコン酸化膜もしくはシリコン窒化膜などの表面機能膜である。12は基板10を貫通する貫通孔である。13は貫通孔12の内側表面に形成された絶縁性の電着膜である。14は電着膜のさらに内側表面及び貫通孔12の開口部周辺に形成された導電膜である。導電膜14はあらかじめ基板10の表面に形成されている電極(不図示)と接続されている。電着膜13は信頼性の高い絶縁膜であり、導電膜14と基板10とは完全に絶縁されリークしないように形成されている。   In the figure, 10 is a silicon semiconductor substrate, and 11 is a surface functional film such as a silicon oxide film or silicon nitride film formed in advance on the front and back surfaces of the substrate 10. Reference numeral 12 denotes a through hole penetrating the substrate 10. Reference numeral 13 denotes an insulating electrodeposition film formed on the inner surface of the through hole 12. Reference numeral 14 denotes a conductive film formed on the inner surface of the electrodeposition film and around the opening of the through hole 12. The conductive film 14 is connected to an electrode (not shown) formed in advance on the surface of the substrate 10. The electrodeposition film 13 is a highly reliable insulating film, and is formed so that the conductive film 14 and the substrate 10 are completely insulated and do not leak.

図2は本発明の実施の形態におけるシリコン半導体基板に設けた貫通孔内部に電着塗装により絶縁膜を形成する、基板の製造工程を示す断面図である。まず図2(a)において、シリコン半導体基板20を準備する。次に図2(b)において、基板20の貫通孔を形成する部分の表面機能膜を□50×50〜150×150μm除去する。除去手法としては、レーザ加工、エッチング法などを使用することができる。   FIG. 2 is a sectional view showing a substrate manufacturing process in which an insulating film is formed by electrodeposition coating in a through hole provided in the silicon semiconductor substrate in the embodiment of the present invention. First, in FIG. 2A, a silicon semiconductor substrate 20 is prepared. Next, in FIG. 2B, the surface functional film in the portion where the through hole of the substrate 20 is formed is removed by □ 50 × 50 to 150 × 150 μm. As the removal method, laser processing, etching, or the like can be used.

次に図2(c)において、基板20にφ50〜150μmの貫通孔22を形成する。その製法は、レーザ加工、ドリル加工、エッチング法等であり、基板20の材質、貫通孔の形状、アスペクト比、生産性等を考慮して適宜選択する事ができる。   Next, in FIG. 2C, a through hole 22 having a diameter of 50 to 150 μm is formed in the substrate 20. The manufacturing method includes laser processing, drilling, etching, and the like, and can be appropriately selected in consideration of the material of the substrate 20, the shape of the through hole, the aspect ratio, productivity, and the like.

次に図2(d)において、基板20に電着膜23を形成する。電着塗料としては、ポリイミド、マレイミド等を使用する事ができる。   Next, in FIG. 2D, an electrodeposition film 23 is formed on the substrate 20. As the electrodeposition paint, polyimide, maleimide, or the like can be used.

ここで図3に電着を行う装置の概略図を示す。図中36は基板20に電着膜を形成するための電着塗料である。基板20は電着塗料36中で、2つの電極37に挟まれるようにセットされる。電極37に正電極、基板20に負電極を与えることで電着塗装が行われる。また電圧と電極の大きさは、電着膜が対向するエッジ部と接触しない範囲で調整する。このように電着を行うと信頼性の高い絶縁膜を形成することができる。   Here, a schematic view of an apparatus for performing electrodeposition is shown in FIG. In the figure, reference numeral 36 denotes an electrodeposition paint for forming an electrodeposition film on the substrate 20. The substrate 20 is set in the electrodeposition paint 36 so as to be sandwiched between two electrodes 37. Electrodeposition is performed by applying a positive electrode to the electrode 37 and a negative electrode to the substrate 20. Further, the voltage and the size of the electrode are adjusted in a range where the electrodeposition film does not contact the opposing edge portion. By performing electrodeposition in this way, a highly reliable insulating film can be formed.

次に図2(e)において、電着膜23の内側表面および、基板20の表裏面に導電層24を形成する。導電層の材料は、銅、ニッケル、パラジウム、金、銀を使用する事ができる。またその製法は、ドライめっき、ウェットめっき、ジェットプリンティング法を使用する事ができ、これらは、貫通孔22の形状やアスペクト比に応じて適宜選択される。   Next, in FIG. 2E, a conductive layer 24 is formed on the inner surface of the electrodeposition film 23 and the front and back surfaces of the substrate 20. As the material for the conductive layer, copper, nickel, palladium, gold, or silver can be used. Moreover, the manufacturing method can use dry plating, wet plating, and a jet printing method, and these are suitably selected according to the shape and aspect ratio of the through-hole 22.

次に図2(f)において、貫通孔22の内側表面の導電層24に囲まれた孔を、埋め込み用の材料25により埋め込む。この埋め込み材料は、例えば、銅、銀のような導電性金属材料や、ポリイミド、シリコン、アミド、エポキシ等の絶縁性樹脂材料を使用する事ができる。埋め込み方法は、ディッピング、ディスペンス、印刷、電着などを使用する事ができる。なお、埋め込み用の材料25は、必ずしも必要ではなく、貫通孔22の内側が埋め込まれていないままであっても良い。   Next, in FIG. 2 (f), the hole surrounded by the conductive layer 24 on the inner surface of the through hole 22 is buried with a filling material 25. As this embedding material, for example, a conductive metal material such as copper or silver, or an insulating resin material such as polyimide, silicon, amide, or epoxy can be used. As the embedding method, dipping, dispensing, printing, electrodeposition and the like can be used. Note that the embedding material 25 is not always necessary, and the inside of the through hole 22 may not be embedded.

次に図2(g)において、基板20の表裏面の導電層24のパターニングを行う。これにより、あらかじめ基板20に設けられていた電極(不図示)と選択的に電気的な接続を行う。なお、この工程は図2(f)に示す埋め込み工程の前に行っても良い。   Next, in FIG. 2G, the conductive layer 24 on the front and back surfaces of the substrate 20 is patterned. Thereby, an electrical connection is selectively made with an electrode (not shown) provided on the substrate 20 in advance. Note that this step may be performed before the embedding step shown in FIG.

以上の工程により、基板20の表裏面を結合させる電着膜23、導電層24、埋め込み用の材料25からなる貫通孔22の構造を備えた高密度実装可能な半導体装置を容易に実現することができる。   Through the above steps, a semiconductor device capable of high-density mounting having the structure of the electrodeposition film 23 for bonding the front and back surfaces of the substrate 20, the conductive layer 24, and the through hole 22 made of the embedding material 25 is easily realized. Can do.

次に本実施の形態における具体的な実施例を順に説明する。まず図2(a)に対応する工程として、シリコンからなる厚さは625μmの基板20を準備する。基板20の表面にはあらかじめ電極、半導体素子、配線が設けられており、電極部以外は絶縁膜であるシリコン酸化膜とシリコン窒化膜の表面機能膜によって覆われている。   Next, specific examples in the present embodiment will be described in order. First, as a process corresponding to FIG. 2A, a substrate 20 made of silicon and having a thickness of 625 μm is prepared. Electrodes, semiconductor elements, and wirings are provided in advance on the surface of the substrate 20, and the portions other than the electrode portions are covered with a silicon oxide film that is an insulating film and a surface functional film of a silicon nitride film.

次に、図2(b)(c)に対応する工程として、レーザを用いて表面機能膜21の除去と貫通孔22を形成する。レーザはNd:YAGレーザ第2高調波(波長532nm)を使用し、Q−スイッチパルス発振、パルス幅30nsec、発振周波数3kHzで□80×80μmの表面機能膜を除去し、その後加工孔径80μmの孔を加工した。その際、加工面でのフルエンス65J/cm、ショット数:20shot(表面機能膜)100shot(貫通孔)とした。レーザビームは、レーザ発信器より出射後、光学レンズの組み合わせによって、φ500μmのビーム径に拡大された後、φ400μm径のマスクを通過することによってビーム周辺部を除去し、円状のビーム形状を得る。次に、ビーム径が基板上で1/5(φ80μm)になるような縮小倍率の光学系によって集光する事により65J/cmのフルエンスまでレーザビーム強度は増大する。上記機能により、レーザビームを基板に照射すると直ちに加工が開始され、レーザビームにより発振パルス20shotで表面機能膜を除去し、発振パルス100shotで基板20に貫通孔を形成することができた。 Next, as a process corresponding to FIGS. 2B and 2C, the surface functional film 21 is removed and the through hole 22 is formed using a laser. The laser uses Nd: YAG laser second harmonic (wavelength 532 nm), Q-switch pulse oscillation, pulse width 30 nsec, oscillation frequency 3 kHz, □ 80 × 80 μm surface functional film is removed, and then a hole with a processed hole diameter of 80 μm Was processed. At that time, the fluence was 65 J / cm 2 on the processed surface, and the number of shots was 20 shots (surface functional film) and 100 shots (through holes). After the laser beam is emitted from the laser transmitter, it is expanded to a beam diameter of φ500 μm by a combination of optical lenses, and then passes through a mask having a diameter of φ400 μm to remove the peripheral portion of the beam to obtain a circular beam shape. . Next, the laser beam intensity is increased to a fluence of 65 J / cm 2 by focusing with an optical system with a reduction ratio such that the beam diameter is 1/5 (φ80 μm) on the substrate. With the above function, processing was started immediately after the substrate was irradiated with the laser beam, the surface functional film was removed by the laser beam with the oscillation pulse 20shot, and a through hole was formed in the substrate 20 with the oscillation pulse 100shot.

次に、図2(d)に対応する工程として、電着法により電着膜23を貫通孔22の内側表面および貫通孔22の開口部付近に形成する。   Next, as a step corresponding to FIG. 2D, an electrodeposition film 23 is formed on the inner surface of the through hole 22 and in the vicinity of the opening of the through hole 22 by electrodeposition.

電着塗料としては、カチオン型ポリイミド電着塗料(エレコート、シミズ社製)を使用し、図3に示すように基板を2つの電極で挟み込んで電極に正電極、基板に負電極を与えることで通電を行った。電界条件を150V、120sec、25℃として電着膜を析出させ、その後、250℃で60min硬化させた。   As the electrodeposition paint, a cation type polyimide electrodeposition paint (Elecoat, manufactured by Shimizu) is used, and the substrate is sandwiched between two electrodes as shown in FIG. Energized. An electrodeposition film was deposited under an electric field condition of 150 V, 120 sec, 25 ° C., and then cured at 250 ° C. for 60 minutes.

このように電着を行うことで、貫通孔ゆえにエッジ部が盛り上がりカバー性が良く、また貫通孔内部の平滑性も良好な電着膜を形成することができた。   By performing electrodeposition in this way, an electrodeposited film having a raised edge portion due to the through-hole and good coverability and excellent smoothness inside the through-hole could be formed.

次に、図2(e)に対応する工程として、絶縁層23の内側表面および基板の表裏面に導電層24を無電解めっきにより形成する。めっき条件は、水酸化カリウム75℃、5分、前処理液(メルプレートITOコンディショナー480、メルプレートコンディショナー1101、エンプレートアクチベーター440、メルテックス社製)、Niめっき液(メルプレートNI−867、メルテックス社製)で0.5μmの皮膜を形成した後、30分アニーリングした。   Next, as a step corresponding to FIG. 2E, the conductive layer 24 is formed by electroless plating on the inner surface of the insulating layer 23 and the front and back surfaces of the substrate. Plating conditions are potassium hydroxide 75 ° C., 5 minutes, pretreatment liquid (Melplate ITO conditioner 480, Melplate conditioner 1101, Enplate activator 440, manufactured by Meltex), Ni plating liquid (Melplate NI-867, A 0.5 μm film was formed by Meltex Co.) and then annealed for 30 minutes.

次に、図2(f)に対応する工程として、貫通孔22の内周面の導電層24に囲まれた孔は、印刷工法により埋め込み用の材料25によって埋め込まれる。印刷方法は、メタルマスクを用いて、スキージのアタック角度25°、スキージスピード30mm/sec、クリアランス1.5mm、印圧0.25Mpaでポリイミドインク(FS−510T40S、宇部興産社製)を埋め込む。印刷後、110℃、5分の乾燥を3回繰り返し、250℃、60分硬化した。   Next, as a step corresponding to FIG. 2F, the hole surrounded by the conductive layer 24 on the inner peripheral surface of the through hole 22 is filled with the embedding material 25 by a printing method. The printing method uses a metal mask to embed polyimide ink (FS-510T40S, manufactured by Ube Industries) with a squeegee attack angle of 25 °, a squeegee speed of 30 mm / sec, a clearance of 1.5 mm, and a printing pressure of 0.25 Mpa. After printing, drying at 110 ° C. for 5 minutes was repeated 3 times and cured at 250 ° C. for 60 minutes.

次に、図2(g)に対応する工程として、基板20の表裏面の導電層24のパターニングを行う。パターニング方法は、まず、スピンコーターによりポジ型感光性レジスト(OFPR800、東京応化社製)を2μm均一に塗布した後、110℃で90min乾燥させた。次にパターニングに対応したマスクを用いて、アライナーで露光した後、現像液(NMD−W、東京応化社製)で現像した。次に、リン酸10%、硝酸40%、酢酸40%のエッチング液に15min浸漬することでエッチングした。最後に、レジスト剥離液(剥離液104、東京応化社製)に2min浸漬することにより、残ったレジストを剥離し、所定のパターニングが完成する。これにより、基板に設けられた電極と導電層24は選択的に電気的な接続を行った。   Next, as a process corresponding to FIG. 2G, the conductive layer 24 on the front and back surfaces of the substrate 20 is patterned. In the patterning method, first, a positive photosensitive resist (OFPR800, manufactured by Tokyo Ohka Kogyo Co., Ltd.) was uniformly applied by 2 μm using a spin coater, and then dried at 110 ° C. for 90 minutes. Next, using the mask corresponding to patterning, after exposing with an aligner, it developed with the developing solution (NMD-W, Tokyo Ohka Co., Ltd.). Next, etching was performed by immersing in an etching solution of 10% phosphoric acid, 40% nitric acid, and 40% acetic acid for 15 minutes. Finally, by immersing in a resist stripping solution (stripping solution 104, manufactured by Tokyo Ohka Kogyo Co., Ltd.) for 2 minutes, the remaining resist is stripped, and predetermined patterning is completed. As a result, the electrode provided on the substrate and the conductive layer 24 were selectively electrically connected.

第1の実施の形態を示す概念図である。It is a conceptual diagram which shows 1st Embodiment. 第1の実施の形態の製造工程の例を示す断面図である。It is sectional drawing which shows the example of the manufacturing process of 1st Embodiment. 第1の実施の形態における電着装置を示す概略図である。It is the schematic which shows the electrodeposition apparatus in 1st Embodiment.

符号の説明Explanation of symbols

10、20、30 基板
11、21 表面機能膜
12、22 貫通孔
13、23 電着膜
14、24 導電層
15、25 穴埋め材料
36 電着塗料
37 電極
10, 20, 30 Substrate 11, 21 Surface functional film 12, 22 Through hole 13, 23 Electrodeposition film 14, 24 Conductive layer 15, 25 Filling material 36 Electrodeposition paint 37 Electrode

Claims (4)

貫通孔のエッジ部の表面機能膜が除去されており、そのエッジ部を含む貫通孔の内表面に電着膜が形成する事を特徴とするシリコン半導体基板。   A silicon semiconductor substrate, wherein a surface functional film at an edge portion of a through hole is removed, and an electrodeposition film is formed on an inner surface of the through hole including the edge portion. 前記電着膜は前記貫通孔に形成された絶縁膜である事を特徴とする請求項1に記載のシリコン半導体基板。   The silicon semiconductor substrate according to claim 1, wherein the electrodeposition film is an insulating film formed in the through hole. 前記貫通孔に形成された電着膜の内側表面には導電膜が形成する事を特徴とする請求項1に記載のシリコン半導体基板。   The silicon semiconductor substrate according to claim 1, wherein a conductive film is formed on an inner surface of the electrodeposition film formed in the through hole. 前記貫通孔の内径は、50μm〜150μmである事を特徴とする請求項1に記載のシリコン半導体基板。
The silicon semiconductor substrate according to claim 1, wherein an inner diameter of the through hole is 50 μm to 150 μm.
JP2003380731A 2003-11-11 2003-11-11 Semiconductor device Withdrawn JP2005150131A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010659A (en) * 2006-06-29 2008-01-17 Disco Abrasive Syst Ltd Method of processing via hole

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010659A (en) * 2006-06-29 2008-01-17 Disco Abrasive Syst Ltd Method of processing via hole

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