JP2005148286A - Display apparatus and driving method therefor - Google Patents

Display apparatus and driving method therefor Download PDF

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JP2005148286A
JP2005148286A JP2003383714A JP2003383714A JP2005148286A JP 2005148286 A JP2005148286 A JP 2005148286A JP 2003383714 A JP2003383714 A JP 2003383714A JP 2003383714 A JP2003383714 A JP 2003383714A JP 2005148286 A JP2005148286 A JP 2005148286A
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JP4701603B2 (en
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Kazuo Nakamura
和夫 中村
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Sony Corp
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problem; on a cellular phone mounted with a CCD sensor or a CMOS sensor and provided with a camera function and a cellular phone with a built-in fingerprint sensor for personal identification, these sensors are not integral with an image display part, therefore, the equipment has to be increased in packaging density. <P>SOLUTION: An active matrix type organic EL display apparatus 10 in which pixels 11 including light emitting circuits 22 and light receiving circuits 23 are arranged in a matrix form comprises an A-D converter circuit 238 in each pixel 11, and is configured so that image information can be fetched without arranging the CCD sensor and the CMOS sensor, further without a touch panel, by converting the light receiving signals into digital light receiving signals through the A-D converter circuit to output, and also the fetched image information can be externally outputted in digital data. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、表示装置およびその駆動方法に関し、特に表示エレメントとして自発光型の素子(以下、「自発光素子」と呼ぶ)を含む画素が行列状に配置されてなるアクティブマトリクス型表示装置およびその駆動方法に関する。   The present invention relates to a display device and a driving method thereof, and in particular, an active matrix display device in which pixels including self-luminous elements (hereinafter referred to as “self-luminous elements”) as display elements are arranged in a matrix, and the same The present invention relates to a driving method.

自発光素子として、例えば、有機薄膜に電界をかけると当該有機薄膜が発光する現象を利用した有機EL(electroluminescence) 素子がある。この有機EL素子を画素の表示エレメントとして用いてなる有機EL表示装置は、当該有機EL素子が10V以下の低い駆動電圧で数100nitの輝度を得ることができるため低消費電力であり、また自発光型の素子であるため液晶表示装置では必須な照明装置を必要とせず、軽量化および薄型化が容易であり、さらには有機EL素子の応答速度が数μs程度と非常に高速であるため、液晶表示装置に代表されるホールド型表示装置に比べて動画表示時に残像の問題が発生しなく、表示性能に優れている等の特長を持っている。   As a self-luminous element, there is, for example, an organic EL (electroluminescence) element that utilizes a phenomenon in which an organic thin film emits light when an electric field is applied. An organic EL display device using this organic EL element as a display element of a pixel has low power consumption because the organic EL element can obtain a luminance of several hundred nits with a driving voltage as low as 10 V or less, and is self-luminous. The liquid crystal display device does not require an illuminating device that is essential for the liquid crystal display device, can be easily reduced in weight and thickness, and the response speed of the organic EL element is as high as about several μs. Compared to a hold-type display device typified by a display device, there is a problem that an afterimage problem does not occur when displaying a moving image, and the display performance is excellent.

このように、低消費電力で、軽量化および薄型化が容易であり、動画表示時の表示性能に優れている等の特長を持つ有機EL表示装置は、近年、特に低消費電力化、軽量化および薄型化が要求される携帯電話や携帯情報端末(PDA;Personal Digital Assistants)に代表される携帯端末装置の表示装置として用いて好適なフラットパネルディスプレイとして有望視されている。この有機EL表示装置の中でも、とりわけ、画素の駆動素子として、多結晶シリコンを活性層とする薄膜トランジスタ(TFT;Thin Film Transistor)を用いたアクティブマトリクス型有機EL表示装置の開発が盛んである。   As described above, organic EL display devices having features such as low power consumption, easy weight reduction and thinning, and excellent display performance during moving image display have recently been particularly reduced in power consumption and weight. In addition, it is promising as a flat panel display suitable for use as a display device of a mobile terminal device represented by a mobile phone or a personal digital assistant (PDA) that is required to be thin. Among these organic EL display devices, in particular, active matrix organic EL display devices using a thin film transistor (TFT) having polycrystalline silicon as an active layer are actively developed as pixel drive elements.

一方、モバイル機器では、一般に、抵抗薄膜を用いた接触型タッチパネルが座標検出装置として用いられ、情報入力の手段として広く使用されている(例えば、非特許文献1参照)。   On the other hand, in a mobile device, a contact-type touch panel using a resistive thin film is generally used as a coordinate detection device, and is widely used as an information input means (for example, see Non-Patent Document 1).

雑誌「メカトロニクス」技術調査会、1993,VOL18,No12,p.36−37Magazine "Mechatronics" Technical Research Committee, 1993, VOL18, No12, p. 36-37

しかしながら、接触型タッチパネルでは、接触点における電位変化を検出する方式であるため、2点以上の接触点を検出することは不可能である。また、表示面上にタッチパネルを配置する構成を採らざるを得ないため、必然的に機器の厚さの増大および表示部の発光輝度の低下を招くという課題がある。   However, since the contact-type touch panel is a method for detecting a potential change at a contact point, it is impossible to detect two or more contact points. In addition, since a configuration in which a touch panel is disposed on the display surface is unavoidable, there is a problem that the thickness of the device is inevitably increased and the light emission luminance of the display unit is decreased.

また、近年、CCDセンサあるいはCMOSセンサを搭載し、カメラ機能を備えた携帯電話が広く普及しており、さらに個人認証用に指紋センサを内蔵する携帯電話も登場してきている。しかしながら、これらセンサは画像表示部とは一体となっていないため、機器の実装密度の増加を招くという課題がある。   In recent years, mobile phones equipped with a CCD sensor or CMOS sensor and equipped with a camera function have been widely used, and mobile phones with a built-in fingerprint sensor for personal authentication have also appeared. However, since these sensors are not integrated with the image display unit, there is a problem that the mounting density of the device is increased.

本発明は、上記課題に鑑みてなされたものであって、その目的とするところは、機器の厚さを厚くしたり、表示部の発光輝度を低下させたりすることなく、画像情報の取り込みが可能な表示装置およびその駆動方法を提供することにある。   The present invention has been made in view of the above problems, and the object of the present invention is to capture image information without increasing the thickness of the device or reducing the light emission luminance of the display unit. An object of the present invention is to provide a display device and a driving method thereof.

上記目的を達成するために、本発明では、発光回路と受光回路を含む画素が行列状に配置されてなる画素アレイ部を有する表示装置において、前記受光回路の受光素子で受光して得られる信号をデジタル信号に変換して画素単位で出力するようにする。   In order to achieve the above object, in the present invention, in a display device having a pixel array unit in which pixels including a light emitting circuit and a light receiving circuit are arranged in a matrix, a signal obtained by receiving light with a light receiving element of the light receiving circuit. Is converted into a digital signal and output in units of pixels.

画素アレイ部の各画素は、発光回路と受光回路を含むことで、本来の発光機能(表示機能)を持つことに加えて受光機能をも持つ。そして、受光素子で受光して得られる信号をデジタル信号に変換して出力することで、表示装置外部にCCDセンサやCMOSセンサを設けなくても画素単位で画像情報を取り込んでデジタルデータで出力したり、タッチパネルを設けなくても画素単位で座標情報を取り込んでデジタルデータで出力したりすることができる。   Each pixel of the pixel array section includes a light emitting circuit and a light receiving circuit, and thus has a light receiving function in addition to an original light emitting function (display function). Then, by converting the signal obtained by receiving light with the light receiving element into a digital signal and outputting it, the image information is taken in pixel units and output as digital data without providing a CCD sensor or CMOS sensor outside the display device. Or, coordinate information can be taken in pixel units and output as digital data without providing a touch panel.

本発明によれば、CCDセンサやCMOSセンサを設けたり、タッチパネルを設けたりしなくても、画像情報を取り込むことができるとともに、取り込んだ画像情報をデジタルデータで出力することができるため、機器の厚さを厚くしたり、表示部の発光輝度を低下させたりすることなく、低コストにてシステムを構成できる。   According to the present invention, image information can be captured without providing a CCD sensor or a CMOS sensor or a touch panel, and the captured image information can be output as digital data. A system can be configured at low cost without increasing the thickness or reducing the light emission luminance of the display unit.

以下、本発明の実施の形態について図面を参照して詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図1は、本発明の一実施形態に係る表示装置、例えば表示エレメントとして自発光素子である有機EL素子を含む画素が行列状に配置されてなるアクティブマトリクス型有機EL表示装置を示す概略構成図である。   FIG. 1 is a schematic configuration diagram illustrating a display device according to an embodiment of the present invention, for example, an active matrix organic EL display device in which pixels including organic EL elements that are self-luminous elements as display elements are arranged in a matrix. It is.

図1から明らかなように、本実施形態に係るアクティブマトリクス型有機EL表示装置10は、発光回路および受光回路(共に図示せず)を含む多数の画素11が基板12上に行列状に配置されてなる画素アレイ部(表示エリア部)13を有するとともに、その周辺駆動回路として、画素アレイ部13の各画素11に対して映像信号を供給する例えば4つに分割された水平駆動回路14−1〜14−4およびその制御回路基板15と、画素アレイ部13の各画素11を行単位で選択する例えば3つに分割された垂直駆動回路16−1〜16−3およびその制御回路基板17と、各画素11の受光回路から出力される受光信号を処理する受光信号処理基板18とを少なくとも有する構成となっている。   As is apparent from FIG. 1, the active matrix organic EL display device 10 according to the present embodiment has a large number of pixels 11 including light emitting circuits and light receiving circuits (both not shown) arranged on a substrate 12 in a matrix. The pixel array section (display area section) 13 and the peripheral drive circuit for supplying a video signal to each pixel 11 of the pixel array section 13 are divided into, for example, four horizontal drive circuits 14-1. 14-4 and its control circuit board 15, the vertical drive circuits 16-1 to 16-3 divided into three, for example, that select each pixel 11 of the pixel array section 13 in units of rows, and its control circuit board 17 The light receiving signal processing substrate 18 for processing the light receiving signal output from the light receiving circuit of each pixel 11 is provided.

上記構成のアクティブマトリクス型有機EL表示装置10において、画素11は、図2に示すように、発光素子として有機EL素子21(図4参照)を有する発光回路22と受光回路23を内蔵し、これら回路22,23の上方に有機EL発光層24が位置する構成となっている。水平駆動回路14−1〜14−4はIC化されている。水平駆動回路14−1〜14−4の分割数は4つに限られるものではなく、1つを含んで任意の分割数に設定可能である。垂直駆動回路16−1〜16−3もIC化されており、その分割数についても、1つを含んで任意の分割数に設定可能である。受光信号処理基板18は、画素アレイ部13が搭載された基板12に対して例えば4つのフレキシブルケーブル19−1〜19−4を介して電気的に接続されている。   In the active matrix organic EL display device 10 having the above configuration, the pixel 11 includes a light emitting circuit 22 and a light receiving circuit 23 each having an organic EL element 21 (see FIG. 4) as a light emitting element, as shown in FIG. The organic EL light emitting layer 24 is positioned above the circuits 22 and 23. The horizontal drive circuits 14-1 to 14-4 are integrated into an IC. The number of divisions of the horizontal drive circuits 14-1 to 14-4 is not limited to four, and can be set to any number of divisions including one. The vertical drive circuits 16-1 to 16-3 are also integrated into an IC, and the number of divisions can be set to any number including one. The received light signal processing substrate 18 is electrically connected to the substrate 12 on which the pixel array unit 13 is mounted via, for example, four flexible cables 19-1 to 19-4.

画素アレイ部13には、m行n列の画素11の配列に対して行ごとに制御線群25−1〜25−mが配線されるとともに、列ごとに映像信号線26−1〜26−nおよび受光信号線27−1〜27−nが配線されている。制御線群25−1〜25−mの各々は、後述するように、例えば5本の第1〜第5の制御線25A〜25Dからなり、各一端が垂直駆動回路16−1〜16−3に行単位で接続されている。   In the pixel array section 13, control line groups 25-1 to 25-m are wired for each row with respect to the arrangement of the pixels 11 of m rows and n columns, and video signal lines 26-1 to 26- are provided for each column. n and light receiving signal lines 27-1 to 27-n are wired. As will be described later, each of the control line groups 25-1 to 25-m includes, for example, five first to fifth control lines 25A to 25D, and one end of each of the control line groups 25-1 to 25-3 is vertical drive circuits 16-1 to 16-3. Are connected in line units.

垂直駆動回路16−1〜16−3は、主にシフトレジスタによって構成され、画素11の発光回路22を駆動するときに、第1の制御線25A−1〜25A−mを所定の走査サイクルにて順に走査しつつ駆動することにより、発光駆動すべき画素11を行単位で順次選択する。このとき、選択行の各画素11には、水平駆動回路14−1〜14−4から映像信号線26−1〜26−nを通して映像信号が供給される。垂直駆動回路16−1〜16−3はさらに、画素11の受光回路23を駆動するときに、第4,第5の制御線25D−1〜25D−m,25E−1〜25E−mを所定の走査サイクルにて順に走査しつつ駆動することにより、発光駆動すべき画素11を行単位で順次選択する。このとき、選択行の各画素11からは受光回路23の受光信号が出力される。   The vertical drive circuits 16-1 to 16-3 are mainly constituted by shift registers, and when driving the light emitting circuit 22 of the pixel 11, the first control lines 25A-1 to 25A-m are set to a predetermined scanning cycle. In this manner, the pixels 11 to be driven for light emission are sequentially selected in units of rows. At this time, a video signal is supplied to each pixel 11 of the selected row from the horizontal drive circuits 14-1 to 14-4 through the video signal lines 26-1 to 26-n. Further, when the vertical drive circuits 16-1 to 16-3 drive the light receiving circuit 23 of the pixel 11, the fourth and fifth control lines 25D-1 to 25D-m and 25E-1 to 25E-m are predetermined. In this scanning cycle, the pixels 11 to be driven to emit light are sequentially selected in units of rows. At this time, the light receiving signal of the light receiving circuit 23 is output from each pixel 11 of the selected row.

(実施例1)
図4は、実施例1に係る画素11の回路構成を示す回路図である。本実施例に係る画素回路30では、発光回路22の発光素子である有機EL素子21が、逆バイアス状態では受光素子として機能することに着目し、当該有機EL素子21を受光回路23の受光素子として兼用するようにしている。
(Example 1)
FIG. 4 is a circuit diagram illustrating a circuit configuration of the pixel 11 according to the first embodiment. In the pixel circuit 30 according to the present embodiment, attention is paid to the fact that the organic EL element 21 that is the light emitting element of the light emitting circuit 22 functions as a light receiving element in the reverse bias state, and the organic EL element 21 is used as the light receiving element of the light receiving circuit 23. I am trying to use it as both.

発光回路22は、有機EL素子21に加えて、駆動素子として薄膜トランジスタ221〜224、さらに保持容量225を有する構成となっている。因みに、薄膜トランジスタ(以下、「TFT」と記す)は、多結晶シリコンを活性層としており、駆動能力の高さから画素ごとの素子サイズを小さく形成できるため、有機EL表示装置の高精細化に有利である。   In addition to the organic EL element 21, the light emitting circuit 22 includes thin film transistors 221 to 224 and a storage capacitor 225 as drive elements. Incidentally, a thin film transistor (hereinafter referred to as “TFT”) has polycrystalline silicon as an active layer, and can be formed with a small element size for each pixel due to its high driving capability, which is advantageous for high definition of an organic EL display device. It is.

有機EL素子21はカソードが例えばグランドに接続されている。TFT221は、映像信号サンプリング用トランジスタであり、例えばNチャネル型トランジスタからなり、ゲートが第1の制御線25A(図3の5本の制御線群25−1〜25−mの各1本に相当)に、ソースが映像信号線26(図1のデータ線26−1〜26−nに相当)にそれぞれ接続されている。   The organic EL element 21 has a cathode connected to, for example, the ground. The TFT 221 is a video signal sampling transistor, which is composed of, for example, an N-channel transistor, and has a gate corresponding to the first control line 25A (one of each of the five control line groups 25-1 to 25-m in FIG. 3). ) Are connected to video signal lines 26 (corresponding to the data lines 26-1 to 26-n in FIG. 1), respectively.

TFT222は、有機EL素子21の駆動用トランジスタであり、例えばPチャネル型トランジスタからなり、ゲートがTFT221のドレインに、ソースが例えば正電源VDDにそれぞれ接続されている。TFT223は、有機EL素子21の発光期間制御用トランジスタであり、例えばNチャネル型トランジスタからなり、ゲートが第2の制御線25B(図3の5本の制御線群25−1〜25−mの各1本に相当)に、ドレインがTFT222のドレインに、ソースが有機EL素子21のアノードにそれぞれ接続されている。保持容量224は、TFT222のゲート−ソース間に接続されている。   The TFT 222 is a driving transistor for the organic EL element 21 and is composed of, for example, a P-channel transistor, and has a gate connected to the drain of the TFT 221 and a source connected to the positive power supply VDD, for example. The TFT 223 is a transistor for controlling the light emission period of the organic EL element 21 and is made of, for example, an N-channel transistor, and has a gate of the second control line 25B (the five control line groups 25-1 to 25-m in FIG. 3). The drain is connected to the drain of the TFT 222, and the source is connected to the anode of the organic EL element 21. The storage capacitor 224 is connected between the gate and source of the TFT 222.

受光回路23は、例えばNチャネル型の5つのTFT231〜235、保持容量236および反転増幅器237を有し、受光期間では有機EL素子21を逆バイアス状態にすることによって当該有機EL素子21を受光素子として用いる構成となっている。なお、反転増幅器237に代えて、増幅度=1のインバータを用いることも可能である。   The light receiving circuit 23 includes, for example, five N-channel TFTs 231 to 235, a holding capacitor 236, and an inverting amplifier 237, and the organic EL element 21 is placed in a reverse bias state during the light receiving period, thereby making the organic EL element 21 a light receiving element. It is the composition used as. Instead of the inverting amplifier 237, an inverter with an amplification factor of 1 can be used.

TFT231は、発光リセット用トランジスタであり、例えばNチャネル型トランジスタからなり、ゲートが第3の制御線25C(図3の5本の制御線群25−1〜25−mの各1本に相当)に、ドレインが有機EL素子21のアノードに、ソースがバイアス電源Vbにそれぞれ接続されている。ここで、バイアス電源Vbは、受光時に有機EL素子21が逆バイアス状態になるように、即ちアノード電圧がカソード電圧よりも低くなるように設定されている。本例の場合には、カソード電位がグランドレベル(0[V])であるために、バイアス電源Vbは負電源となる。TFT232は、受光信号電流制御用トランジスタであり、ゲートが第4の制御線25D(図3の制御線群25−1〜25−mの各1本に相当)に、ソースが有機EL素子21のアノードにそれぞれ接続されている。   The TFT 231 is a light emission reset transistor, which is made of, for example, an N-channel transistor, and has a gate corresponding to the third control line 25C (corresponding to one of each of the five control line groups 25-1 to 25-m in FIG. 3). The drain is connected to the anode of the organic EL element 21 and the source is connected to the bias power source Vb. Here, the bias power supply Vb is set so that the organic EL element 21 is in a reverse bias state when receiving light, that is, the anode voltage is lower than the cathode voltage. In the case of this example, since the cathode potential is the ground level (0 [V]), the bias power source Vb is a negative power source. The TFT 232 is a light receiving signal current control transistor, the gate is the fourth control line 25D (corresponding to each one of the control line groups 25-1 to 25-m in FIG. 3), and the source is the organic EL element 21. Each is connected to the anode.

TFT233は、基準電圧制御用トランジスタであり、ゲートが第5の制御線25E(図3の制御線群25−1〜25−mの各1本に相当)に、ドレインがTFT232のソースにそれぞれ接続され、ソースに基準電圧Vrefが与えられる。保持容量236は、一端がTFT232のソースとTFT233のドレインの共通接続点(ノードN11)に接続されている。反転増幅器237は、入力端が保持容量236の他端(ノードN12)に接続されている。TFT234は、ゲートが第4の制御線25Dに、ドレインが反転増幅器237の入力端に、ソースが反転増幅器237の出力端(ノードN13)にそれぞれ接続されている。TFT235は、ゲートが第5の制御線25Eに、ドレインが反転増幅器237の出力端に、ソースが受光信号線27(図3の受光信号線27−1〜27−nに相当)にそれぞれ接続されている。   The TFT 233 is a reference voltage control transistor, and has a gate connected to the fifth control line 25E (corresponding to one of the control line groups 25-1 to 25-m in FIG. 3) and a drain connected to the source of the TFT 232, respectively. The reference voltage Vref is applied to the source. One end of the storage capacitor 236 is connected to a common connection point (node N11) of the source of the TFT 232 and the drain of the TFT 233. The input terminal of the inverting amplifier 237 is connected to the other end (node N12) of the storage capacitor 236. The TFT 234 has a gate connected to the fourth control line 25D, a drain connected to the input terminal of the inverting amplifier 237, and a source connected to the output terminal (node N13) of the inverting amplifier 237. The TFT 235 has a gate connected to the fifth control line 25E, a drain connected to the output terminal of the inverting amplifier 237, and a source connected to the light receiving signal line 27 (corresponding to the light receiving signal lines 27-1 to 27-n in FIG. 3). ing.

この受光回路23の回路構成において、TFT232〜234、保持容量236および反転増幅器237は、比較回路構成のA/D(アナログ−デジタル)変換回路238を構成している。すなわち、受光回路23は、画素ごとにA/D変換回路238を内蔵し、有機EL素子21を受光素子として用いたときに、当該有機EL素子21で受光して得られるアナログ受光信号をデジタル受光信号に変換して受光信号線27に出力する構成となっている。   In the circuit configuration of the light receiving circuit 23, the TFTs 232 to 234, the holding capacitor 236, and the inverting amplifier 237 constitute an A / D (analog-digital) conversion circuit 238 having a comparison circuit configuration. That is, the light receiving circuit 23 incorporates an A / D conversion circuit 238 for each pixel, and when the organic EL element 21 is used as a light receiving element, an analog light reception signal obtained by receiving light from the organic EL element 21 is digitally received. The signal is converted into a signal and output to the light receiving signal line 27.

続いて、上記構成の実施例1に係る画素回路30を有するアクティブマトリクス型有機EL表示装置10の動作について説明する。図5は、画素回路30の1フレーム期間の動作を示すタイミングチャートである。1フレーム期間は、発光回路22による発光動作が行われる発光期間と、受光回路23による受光動作が行われる受光期間に分けられる。ただし、発光期間と受光期間の順番を逆にすることも可能である。   Next, the operation of the active matrix organic EL display device 10 having the pixel circuit 30 according to the first embodiment having the above configuration will be described. FIG. 5 is a timing chart showing the operation of the pixel circuit 30 in one frame period. One frame period is divided into a light emitting period in which a light emitting operation by the light emitting circuit 22 is performed and a light receiving period in which a light receiving operation by the light receiving circuit 23 is performed. However, the order of the light emission period and the light reception period can be reversed.

先ず、受光期間での受光回路22の動作について説明する。図4に示す画素回路30において、TFT221は、1水平サンプリング期間ごとに、垂直駆動回路16−1〜16−3(図1、図3参照)から第1の制御線25Aを通して書き込み走査信号WSがゲートに与えられることで、映像信号線26を通して供給される映像信号Sigをサンプリングする。このサンプリングされた映像信号Sigは、TFT222のゲートに与えられるとともに、保持容量224によって保持される。   First, the operation of the light receiving circuit 22 during the light receiving period will be described. In the pixel circuit 30 shown in FIG. 4, the TFT 221 receives the write scanning signal WS from the vertical drive circuits 16-1 to 16-3 (see FIGS. 1 and 3) through the first control line 25A every horizontal sampling period. The video signal Sig supplied through the video signal line 26 is sampled by being given to the gate. The sampled video signal Sig is supplied to the gate of the TFT 222 and held by the holding capacitor 224.

その後、垂直駆動回路16−1〜16−3から第2の制御線25Bを通して発光制御信号LONが略VDDレベル(以下、「“H”レベル」と記す)になり、TFT223がオン状態になると、TFT222は、映像信号Sigの信号レベルに応じた駆動電流をTFT223を介して有機EL素子21に供給し、当該有機EL素子21を映像信号Sigの信号レベルに対応した輝度で発光させる。この発光駆動が行単位で順次行われることによって画像表示が行われる。最終行(m行)の各画素11の発光駆動が終了すると、受光期間に移行する。   After that, when the light emission control signal LON becomes approximately VDD level (hereinafter referred to as “H” level) through the second control line 25B from the vertical drive circuits 16-1 to 16-3, and the TFT 223 is turned on, The TFT 222 supplies a drive current corresponding to the signal level of the video signal Sig to the organic EL element 21 via the TFT 223, and causes the organic EL element 21 to emit light with a luminance corresponding to the signal level of the video signal Sig. Image display is performed by sequentially performing the light emission driving in units of rows. When the light emission driving of each pixel 11 in the final row (m row) is completed, the light receiving period starts.

次に、受光期間での受光回路23の動作について説明する。受光期間に入ると最初に、垂直駆動回路16−1〜16−3から第3の制御線25Cを通して全画素に対して“H”レベルのリセット信号RESET#1〜#mが与えられる。リセット信号RESET#1〜#mが“H”レベル状態にある期間がリセット期間である。このリセット期間では、全画素のTFT231がオン状態となり、有機EL素子21のアノードにバイアス電圧Vbを印加する。ここで、バイアス電圧Vbが負電圧であるため、有機EL素子21は逆バイアス状態となり、当該有機EL素子21の端子間容量には、カソード電位をVc(本例では、グランドレベル)とすると、Vb−Vc<0なる電位が充電される。   Next, the operation of the light receiving circuit 23 during the light receiving period will be described. In the light receiving period, first, reset signals RESET # 1 to #m of “H” level are given to all the pixels from the vertical drive circuits 16-1 to 16-3 through the third control line 25C. A period in which the reset signals RESET # 1 to #m are in the “H” level state is a reset period. In this reset period, the TFTs 231 of all the pixels are turned on, and the bias voltage Vb is applied to the anode of the organic EL element 21. Here, since the bias voltage Vb is a negative voltage, the organic EL element 21 is in a reverse bias state. When the cathode potential is Vc (in this example, the ground level), the capacitance between the terminals of the organic EL element 21 is: A potential Vb−Vc <0 is charged.

リセット期間が終了すると撮像期間に入る。この撮像期間では、有機EL素子21に入射する光量によってリーク電流が変化することで、有機EL素子21の端子間電圧が変化する。リーク電流は、ほぼ入射光エネルギーに対して線形に増加する。したがって、撮像期間終了時の各画素の有機EL素子21のアノード電圧は、光強度に応じた電位となる。すなわち、高エネルギー光が入射された画素では、アノード電圧はカソード電位Vcに近づき、逆に、低エネルギー光が入射された画素では、リセット時のアノード電圧に近い電位となる。   When the reset period ends, the imaging period starts. During this imaging period, the leakage current changes depending on the amount of light incident on the organic EL element 21, whereby the terminal voltage of the organic EL element 21 changes. The leakage current increases almost linearly with the incident light energy. Therefore, the anode voltage of the organic EL element 21 of each pixel at the end of the imaging period becomes a potential corresponding to the light intensity. That is, the anode voltage approaches the cathode potential Vc in the pixel to which high energy light is incident, and conversely, the pixel to which the low energy light is incident has a potential close to the anode voltage at reset.

撮像期間が終了するとデータ読み出し期間に入る。このデータ読み出し期間の受光回路23の動作について、図6のタイミングチャートを用いて詳細に説明する。なお、図6において、図4と対応させると、AはノードN11の電位を、BはノードN12の電位を、CはノードN13の電位をそれぞれ示している。   When the imaging period ends, the data reading period starts. The operation of the light receiving circuit 23 during this data reading period will be described in detail with reference to the timing chart of FIG. In FIG. 6, in correspondence with FIG. 4, A indicates the potential of the node N <b> 11, B indicates the potential of the node N <b> 12, and C indicates the potential of the node N <b> 13.

データ読み出し期間において、垂直駆動回路16−1〜16−3から第4の制御線25Dを通して与えられる読み出し信号READが略グランドレベル(以下、「“L”レベル」と記す)のときは、TFT232,235がオフ状態にある。このとき、読み出し信号READの反転信号である非読み出し信号xREADが“H”レベルの状態にあるため、TFT233,234はオン状態にある。TFT233がオン状態にあることで、当該TFT233を通して基準電圧VrefがノードN11に与えられ、当該ノードN11の電位Aが基準電圧Vrefになる。   In the data read period, when the read signal READ supplied from the vertical drive circuits 16-1 to 16-3 through the fourth control line 25D is substantially at the ground level (hereinafter referred to as “L” level), the TFT 232 235 is in the off state. At this time, since the non-read signal xREAD, which is an inverted signal of the read signal READ, is in the “H” level, the TFTs 233 and 234 are in the on state. Since the TFT 233 is in the on state, the reference voltage Vref is supplied to the node N11 through the TFT 233, and the potential A of the node N11 becomes the reference voltage Vref.

そして、反転増幅器237の入出力端間がTFT234によって短絡されているため、ノードN12の電位BとノードN13の電位Cが等しくなり、この電位は反転増幅器237の動作点電圧Vinvとなる。このとき、保持容量236の端子間電圧Vc2がVc2=Vinv−Vrefとなり、保持容量236はこの電位差を保持する。   Since the input / output terminal of the inverting amplifier 237 is short-circuited by the TFT 234, the potential B of the node N12 is equal to the potential C of the node N13, and this potential becomes the operating point voltage Vinv of the inverting amplifier 237. At this time, the voltage Vc2 between the terminals of the storage capacitor 236 becomes Vc2 = Vinv−Vref, and the storage capacitor 236 holds this potential difference.

次に、読み出し信号READが“H”レベルに、非読み出し信号xREADが“L”レベルになると、TFT232,235がオン状態に、TFT233,234がオフ状態になる。すると、ノードN11の電位Aは入力電位Vinに等しくなる。このとき、ノードN12の電位Bは、保持容量236によってその端子間電圧が保持されているため、Vinv+(Vin−Vref)なる電位となる。この例では、ノードN12の電位Bが反転増幅器237の動作点電圧Vinvよりも大きくなるため、ノードN13の電位C、即ち反転増幅器237の出力電位は“L”レベルとなり、TFT235を介して出力電圧Voutとして受光信号線27に出力される。   Next, when the read signal READ becomes “H” level and the non-read signal xREAD becomes “L” level, the TFTs 232 and 235 are turned on and the TFTs 233 and 234 are turned off. Then, the potential A of the node N11 becomes equal to the input potential Vin. At this time, the potential B of the node N12 is Vinv + (Vin−Vref) because the voltage between the terminals is held by the storage capacitor 236. In this example, since the potential B of the node N12 becomes higher than the operating point voltage Vinv of the inverting amplifier 237, the potential C of the node N13, that is, the output potential of the inverting amplifier 237 becomes “L” level, and the output voltage is output via the TFT 235. It is output to the light receiving signal line 27 as Vout.

このように、TFT232〜234、保持容量236および反転増幅器237からなる比較回路構成のA/D変換回路238では、入力電位Vinと基準電圧Vrefの大小関係により、反転増幅器237の出力電位は“L”レベルか“H”レベルのどちらかに落ち着くので、基準電圧Vrefに対する入力電位Vinの比較動作が可能となる。本実施例に係る受光回路23では、このA/D変換回路238により、受光時の有機EL素子21の端子電位を1ビットのデジタルデータに変換し、画素11の受光信号として受光信号線27を経由して外部へ出力する。   As described above, in the A / D conversion circuit 238 having the comparison circuit configuration including the TFTs 232 to 234, the storage capacitor 236, and the inverting amplifier 237, the output potential of the inverting amplifier 237 is “L” due to the magnitude relationship between the input potential Vin and the reference voltage Vref. Since it settles at either the “level” or the “H” level, the comparison operation of the input potential Vin with respect to the reference voltage Vref becomes possible. In the light receiving circuit 23 according to the present embodiment, the A / D conversion circuit 238 converts the terminal potential of the organic EL element 21 during light reception into 1-bit digital data, and the light receiving signal line 27 is used as the light receiving signal of the pixel 11. Output to the outside via.

(実施例2)
図7は、実施例2に係る画素11の回路構成を示す回路図であり、図中、図4と同等部分には同一符号を付して示している。
(Example 2)
FIG. 7 is a circuit diagram illustrating a circuit configuration of the pixel 11 according to the second embodiment. In the drawing, the same parts as those in FIG. 4 are denoted by the same reference numerals.

先述した実施例1に係る画素回路30では、発光回路22の発光素子である有機EL素子21が、逆バイアス状態では受光素子として機能することに着目し、当該有機EL素子21を受光回路23の受光素子として兼用した構成を採っているのに対して、本実施例に係る画素回路40では、受光回路23′が専用の受光素子を持つ構成を採っている。したがって、受光回路23′の構成以外は、実施例1に係る画素回路30と同じであるので、重複する部分についてはその説明を省略するものとする。   In the pixel circuit 30 according to the first embodiment described above, paying attention to the fact that the organic EL element 21 which is the light emitting element of the light emitting circuit 22 functions as a light receiving element in the reverse bias state, the organic EL element 21 is used as the light receiving circuit 23. The pixel circuit 40 according to the present embodiment adopts a configuration in which the light receiving circuit 23 'has a dedicated light receiving element, whereas the configuration also used as the light receiving element is adopted. Accordingly, since the configuration other than the configuration of the light receiving circuit 23 ′ is the same as that of the pixel circuit 30 according to the first embodiment, the description of the overlapping portions will be omitted.

本実施例に係る画素回路40では、受光回路23′の専用の受光素子として、フォトダイオード239を設け、発光回路22と受光回路23′を分離した構成を採っている。フォトダイオード239については、非晶質シリコンあるいは多結晶シリコンTFTのドレインとゲートを接続した所謂ダイオード接続構成のフォトダイオードや、PIN(positive intrinsic negative)ダイオードなどを用いることができる。   In the pixel circuit 40 according to the present embodiment, a photodiode 239 is provided as a dedicated light receiving element for the light receiving circuit 23 ', and the light emitting circuit 22 and the light receiving circuit 23' are separated. As the photodiode 239, a so-called diode-connected photodiode in which the drain and gate of an amorphous silicon or polycrystalline silicon TFT are connected, a PIN (positive intrinsic negative) diode, or the like can be used.

上記構成の実施例2に係る画素回路40の回路動作については、図5および図6の各タイミングチャートに基づく実施例1に係る画素回路30の回路動作と同様である。なお、受光回路23に専用の受光素子を設けた構成を採ることにより、回路素子が1つ増えるものの、実施例1に係る画素回路30の場合のように、発光動作と受光動作とを順番に行う必要がなく、両動作を非同期に行うことができる利点がある。   The circuit operation of the pixel circuit 40 according to the second embodiment having the above-described configuration is the same as the circuit operation of the pixel circuit 30 according to the first embodiment based on the timing charts of FIGS. 5 and 6. Note that, by adopting a configuration in which the light receiving circuit 23 is provided with a dedicated light receiving element, the circuit element is increased by one, but the light emitting operation and the light receiving operation are sequentially performed as in the pixel circuit 30 according to the first embodiment. There is an advantage that both operations can be performed asynchronously.

なお、上記実施例1,2に係る受光回路23,23′では、基準電圧Vrefの電圧値を固定とし、当該基準電圧Vrefと入力電圧Vinとを比較することによって1ビットのデジタルデータに変換する場合を例に挙げて説明したが、受光動作を複数回行って各受光動作に対応した異なるタイミングで受光信号をTFT232によって取り込む一方、当該取り込みのタイミングごとに基準電圧Vrefの電圧値を変化させ、比較動作を行うことによって多ビットのデジタルデータに変換するように構成することも可能である。この構成を採ることにより、画素11の情報として受光量に応じたデータ、即ち階調データを得ることができる。   In the light receiving circuits 23 and 23 'according to the first and second embodiments, the voltage value of the reference voltage Vref is fixed, and the reference voltage Vref and the input voltage Vin are compared to convert to 1-bit digital data. Although the case has been described as an example, the light reception operation is performed a plurality of times, and the light reception signal is captured by the TFT 232 at different timings corresponding to each light reception operation, while the voltage value of the reference voltage Vref is changed at each capture timing, It is also possible to configure to convert into multi-bit digital data by performing a comparison operation. By adopting this configuration, data corresponding to the amount of received light, that is, gradation data can be obtained as information of the pixels 11.

上述したように、発光回路22と受光回路23(23′)を含む画素11が行列状に配置されてなる有機EL表示装置10において、画素11ごとにA/D変換回路238を内蔵し、当該A/D変換回路238によって受光信号をデジタル受光信号に変換して出力するようにしたことにより、CCDセンサやCMOSセンサ、さらにはタッチパネルを設けなくても、画像情報を取り込むことができるとともに、取り込んだ画像情報をデジタルデータで外部に出力することができるため、機器の厚さを厚くしたり、表示部の発光輝度を低下させたりすることなく、低コストにてシステムを構成できる。   As described above, in the organic EL display device 10 in which the pixels 11 including the light emitting circuit 22 and the light receiving circuit 23 (23 ′) are arranged in a matrix, the A / D conversion circuit 238 is built in each pixel 11, and By converting the light reception signal into a digital light reception signal by the A / D conversion circuit 238 and outputting it, image information can be captured and captured without a CCD sensor, CMOS sensor, or touch panel. Since the image information can be output to the outside as digital data, the system can be configured at low cost without increasing the thickness of the device or reducing the light emission luminance of the display unit.

特に、発光素子である有機EL素子21を逆バイアス状態にすることによって当該有機EL素子を受光素子として用いるようにしたことにより、画素回路20を構成する素子数を削減できるため、画素回路20の構成を簡略化でき、画素11の微細化を図る上で有利である。   In particular, since the organic EL element 21 which is a light emitting element is used as a light receiving element by putting the organic EL element 21 in a reverse bias state, the number of elements constituting the pixel circuit 20 can be reduced. The configuration can be simplified, which is advantageous for miniaturization of the pixel 11.

また、受光回路23(23′)に内蔵するA/D変換回路238が、入力電圧Vinを基準電圧Vrefと比較する比較回路構成の簡単な構成となっていることにより、当該A/D変換回路238を画素ごとに配置することができるため、受光信号処理基板18側にA/D変換回路を設ける必要がなく、外部システムの簡略化を図ることができる。   Further, since the A / D conversion circuit 238 incorporated in the light receiving circuit 23 (23 ′) has a simple configuration of a comparison circuit configuration for comparing the input voltage Vin with the reference voltage Vref, the A / D conversion circuit Since 238 can be arranged for each pixel, it is not necessary to provide an A / D conversion circuit on the light receiving signal processing substrate 18 side, and the external system can be simplified.

なお、上記実施形態では、受光回路23,23′のA/D変換回路238として、入力電圧Vinを基準電圧Vrefと比較する比較回路構成のものを用いた場合を例に挙げて説明したが、これに限られるものではなく、画素アレイ部13の画素ごとに配置可能な回路構成のものであれば、どのような回路方式のものであっても良い。   In the above embodiment, the A / D conversion circuit 238 of the light receiving circuits 23 and 23 ′ is described as an example using a comparison circuit configuration that compares the input voltage Vin with the reference voltage Vref. The circuit configuration is not limited to this, and any circuit system may be used as long as the circuit configuration can be arranged for each pixel of the pixel array unit 13.

本発明に係る表示装置は、画素アレイ部を画面表示部としてのみならず、座標検出装置として用いたり、撮像装置として用いることができるため、モバイル機器に画面表示部兼座標検出装置として搭載したり、カメラ機能を備えた携帯電話等の形態端末装置に画面表示部兼撮像デバイスとして搭載したりすることができる。   Since the display device according to the present invention can be used not only as a screen display unit but also as a coordinate detection device or an imaging device, it can be mounted on a mobile device as a screen display unit and coordinate detection device. In addition, it can be mounted as a screen display unit and an imaging device in a terminal device such as a mobile phone having a camera function.

本発明の一実施形態に係るアクティブマトリクス型有機EL表示装置の構成の概略を示すブロック図である。1 is a block diagram illustrating an outline of a configuration of an active matrix organic EL display device according to an embodiment of the present invention. 画素の構成の概略を示す平面図である。It is a top view which shows the outline of a structure of a pixel. 画素アレイ部の構成を示すブロック図である。It is a block diagram which shows the structure of a pixel array part. 実施例1に係る画素回路の回路構成を示す回路図である。3 is a circuit diagram illustrating a circuit configuration of a pixel circuit according to Embodiment 1. FIG. 実施例1に係る画素回路の1フレーム期間の動作を示すタイミングチャートである。3 is a timing chart illustrating an operation in one frame period of the pixel circuit according to the first embodiment. データ読み出し期間の受光回路の動作説明に供するタイミングチャートである。6 is a timing chart for explaining the operation of the light receiving circuit during a data reading period. 実施例2に係る画素回路の回路構成を示す回路図である。6 is a circuit diagram illustrating a circuit configuration of a pixel circuit according to Embodiment 2. FIG.

符号の説明Explanation of symbols

10…アクティブマトリクス型有機EL表示装置、11…画素、13…画素アレイ部、14−1〜14−4…水平駆動回路、16−1〜16−3…垂直駆動回路、21…有機EL素子、22…発光回路、23,23′…受光回路、30,40…画素回路、238…A/D変換回路   DESCRIPTION OF SYMBOLS 10 ... Active matrix type organic EL display device, 11 ... Pixel, 13 ... Pixel array part, 14-1 to 14-4 ... Horizontal drive circuit, 16-1 to 16-3 ... Vertical drive circuit, 21 ... Organic EL element, 22 ... Light emitting circuit, 23, 23 '... Light receiving circuit, 30, 40 ... Pixel circuit, 238 ... A / D conversion circuit

Claims (12)

発光回路と受光回路を含む画素が行列状に配置されてなる画素アレイ部を有する表示装置であって、
前記受光回路は、受光素子で受光して得られる受光信号をデジタル信号に変換して画素単位で出力するアナログ−デジタル変換回路を有する
ことを特徴とする表示装置。
A display device having a pixel array unit in which pixels including a light emitting circuit and a light receiving circuit are arranged in a matrix,
The light receiving circuit includes an analog-digital conversion circuit that converts a light reception signal obtained by receiving light with a light receiving element into a digital signal and outputs the digital signal in units of pixels.
前記発光回路は、発光素子として有機EL素子を有し、
前記受光回路は、受光期間中に前記有機EL素子を逆バイアス状態にすることによって当該有機EL素子を前記受光素子として用いる
ことを特徴とする請求項1記載の表示装置。
The light emitting circuit has an organic EL element as a light emitting element,
The display device according to claim 1, wherein the light receiving circuit uses the organic EL element as the light receiving element by putting the organic EL element in a reverse bias state during a light receiving period.
前記受光回路は、非晶質あるいは多結晶シリコンで形成されたダイオードを前記受光素子として用いる
ことを特徴とする請求項1記載の表示装置。
The display device according to claim 1, wherein the light receiving circuit uses a diode formed of amorphous or polycrystalline silicon as the light receiving element.
前記アナログ−デジタル変換手段は、
前記受光回路の受光素子に流れる電流に応じた電圧を取り込む第1のスイッチ手段と、
前記第1のスイッチの出力端に一端が接続された保持容量と、
前記保持容量の他端に入力端が接続された反転増幅器と、
前記反転増幅器の入出力端間を選択的に短絡する第2のスイッチ手段と、
前記保持容量の一端に基準電圧を与える第3のスイッチ手段とを有する
ことを特徴とする請求項1記載の表示装置。
The analog-digital conversion means includes:
First switch means for taking in a voltage corresponding to the current flowing in the light receiving element of the light receiving circuit;
A holding capacitor having one end connected to the output end of the first switch;
An inverting amplifier having an input terminal connected to the other end of the storage capacitor;
Second switch means for selectively short-circuiting the input / output terminals of the inverting amplifier;
The display device according to claim 1, further comprising a third switch unit that applies a reference voltage to one end of the storage capacitor.
前記アナログ−デジタル変換手段は、前記第3のスイッチ手段によって固定の前記基準電圧を前記保持容量の一端に与える
ことを特徴とする請求項4記載の表示装置。
The display device according to claim 4, wherein the analog-to-digital conversion unit applies the fixed reference voltage to one end of the storage capacitor by the third switch unit.
前記アナログ−デジタル変換手段は、前記受光素子に流れる電流に応じた電圧を前記第1のスイッチ手段によって異なるタイミングで取り込むとともに、当該取り込みタイミングごとに電圧値が異なる前記基準電圧を前記第3のスイッチ手段によって前記保持容量の一端に与える
ことを特徴とする請求項4記載の表示装置。
The analog-to-digital conversion means takes in the voltage corresponding to the current flowing through the light receiving element at different timings by the first switch means, and the third switch takes in the reference voltage having a different voltage value at each fetching timing. The display device according to claim 4, wherein the display device is provided to one end of the storage capacitor by means.
発光回路と受光回路を含む画素が行列状に配置されてなる画素アレイ部を有する表示装置の駆動方法であって、
前記受光回路の受光素子で受光して得られる受光信号をデジタル信号に変換して画素単位で出力する
ことを特徴とする表示装置の駆動方法。
A driving method of a display device having a pixel array unit in which pixels including a light emitting circuit and a light receiving circuit are arranged in a matrix,
A method for driving a display device, comprising: converting a light reception signal obtained by receiving light with a light receiving element of the light receiving circuit into a digital signal and outputting the digital signal in units of pixels.
前記発光回路は、発光素子として有機EL素子を有し、
前記受光回路は、受光期間中に前記有機EL素子を逆バイアス状態にすることによって当該有機EL素子を前記受光素子として用いる
ことを特徴とする請求項7記載の表示装置の駆動方法。
The light emitting circuit has an organic EL element as a light emitting element,
The display device driving method according to claim 7, wherein the light receiving circuit uses the organic EL element as the light receiving element by setting the organic EL element in a reverse bias state during a light receiving period.
前記受光回路は、非晶質あるいは多結晶シリコンで形成されたダイオードを前記受光素子として用いる
ことを特徴とする請求項7記載の表示装置の駆動方法。
The display device driving method according to claim 7, wherein the light receiving circuit uses a diode formed of amorphous or polycrystalline silicon as the light receiving element.
前記受光回路の受光素子に流れる電流に応じた電圧を基準電圧と比較することによって前記受光信号をデジタル信号に変換する
ことを特徴とする請求項7記載の表示装置の駆動方法。
The method for driving a display device according to claim 7, wherein the light reception signal is converted into a digital signal by comparing a voltage corresponding to a current flowing through the light receiving element of the light receiving circuit with a reference voltage.
前記受光回路の受光素子に流れる電流に応じた電圧を、電圧値が固定の前記基準電圧と比較する
ことを特徴とする請求項10記載の表示装置の駆動方法。
The voltage according to the electric current which flows into the light receiving element of the said light receiving circuit is compared with the said reference voltage with a fixed voltage value. The drive method of the display apparatus of Claim 10 characterized by the above-mentioned.
前記受光素子に流れる電流に応じた電圧を異なるタイミングで取り込み、当該取り込みタイミングごとに電圧値が異なる前記基準電圧と比較する
ことを特徴とする請求項10記載の表示装置の駆動方法。
The method for driving a display device according to claim 10, wherein a voltage corresponding to a current flowing through the light receiving element is captured at different timings and compared with the reference voltage having a different voltage value at each capture timing.
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