JP2005136483A - Synthesizer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synthesizer circuit realizing high speed lockup and eliminating the need for extra components to take measures to cope with load variations or the like. <P>SOLUTION: The synthesizer circuit is provided with: a first oscillation circuit (1); a second oscillation circuit (20) oscillated synchronously with the first oscillation circuit (1) and at a frequency different from that of an output of the first oscillation circuit (1); a switch (4) for switching outputs of the first oscillation circuit (1) and the second oscillation circuit (20), and a third oscillation circuit (30) for receiving the output of the switch (4) and providing an oscillation output being the output of the synthesizer circuit (100) synchronously with the output of the switch (4). <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a synthesizer circuit used in a mobile radio device or the like.

A synthesizer unit of a mobile radio in the TDMA (Time Division Multiple Access) method or the like conventionally has a frequency division ratio of an N counter (frequency divider) included in a PLL (Phase Locked Loop) oscillator when switching the oscillation frequency. Since rewriting takes time and high-speed lockup cannot be performed, it is often configured using two PLL oscillators (see FIG. 2 or FIG. 1 of Patent Document 1). The synthesizer unit configured in this manner locks another PLL oscillator to the next frequency while using one PLL oscillator (the PLL oscillator is locked to a certain frequency at this time) At the start of the next slot (burst switching), the oscillation output of the VCO (voltage controlled oscillator) included therein is switched by a switch.
JP-A-4-21220

  In the above configuration, a problem of load variation applied to the voltage controlled oscillator at the time of switching, an isolation problem between the two PLL oscillators, and the like occur. For this reason, as shown in FIG. 2, AMP (amplifier), ATT (attenuator), etc. must be added as a countermeasure for these problems. This increases the number of parts and has a disadvantage in terms of cost. It also has many disadvantages in terms of characteristics.

  The present invention has been made in view of the above points, and provides a synthesizer circuit that can realize high-speed lockup and does not require extra parts for measures such as load fluctuations.

  In order to solve the above-described problem, the invention according to claim 1 includes a first oscillation circuit and a second oscillation that oscillates at a frequency different from the output of the first oscillation circuit in synchronization with the first oscillation circuit. Circuit, a switch for switching the output of the first oscillation circuit and the second oscillation circuit, and a third oscillation circuit for receiving the output of the switch and generating an oscillation output that is synchronized with the output and is the output of the synthesizer circuit It is characterized by comprising.

  According to a second aspect of the present invention, in the synthesizer circuit according to the first aspect, the first oscillation circuit includes a crystal oscillator, and the second oscillation circuit includes the first voltage-controlled oscillator and the crystal. The oscillator comprises an oscillation frequency as a reference frequency, and comprises a phase comparator and a frequency divider for synchronizing the output of the first voltage controlled oscillator with the output of the crystal oscillator based on the reference frequency. The oscillation circuit receives, as a reference frequency, an oscillation frequency of the second voltage controlled oscillator and the crystal oscillator or the first voltage controlled oscillator output from the switch, and based on the reference frequency, the oscillation circuit of the second voltage controlled oscillator It is characterized by comprising a phase comparator and a frequency divider for synchronizing the output with the output of the crystal oscillator or the first voltage controlled oscillator output from the switch.

  According to a third aspect of the present invention, in the synthesizer circuit according to the first or second aspect, the second oscillation circuit and the third oscillation circuit are PLL oscillators.

  According to the present invention, since the oscillation output of the third oscillation circuit becomes the output of the synthesizer circuit, the problem of load fluctuation at the time of switching the oscillation output as in the conventional synthesizer circuit using two PLL oscillators and There is no isolation problem between the two PLL oscillators. This eliminates the need for extra parts to deal with these problems as in the conventional circuit, enables cost reduction by reducing the number of parts, and at the same time reduces the component mounting area and further reduces current consumption. be able to.

  Further, when switching the oscillation frequency of the synthesizer circuit (that is, the oscillation frequency of the third oscillation circuit), the first oscillation circuit and the first oscillation circuit are switched by a switch, compared to a configuration in which the oscillation frequency is changed using a set of PLL oscillation circuits. By switching the output of the second oscillation circuit, it is possible to rewrite the division ratio of the frequency divider included in the third oscillation circuit, which takes time to rewrite, with smaller changes, resulting in high-speed lockup. Is possible.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a synthesizer circuit according to an embodiment of the present invention.

  The synthesizer circuit 100 according to the present embodiment includes two reference oscillators (VC-TCXO1 and VC-TCXO2) composed of two voltage-controlled temperature-compensated crystal oscillators that oscillate at different frequencies (F1, F2 MHz; F1 ≠ F2), and 1 Two voltage controlled oscillators (VCO3), a switch (SW) 4 for switching the oscillation outputs of VC-TCXO1 and VC-TCXO2, and a synchronization control unit 21 for synchronizing the oscillation output of VC-TCXO2 with the oscillation output of VC-TCXO1 And a VCO 3 for obtaining a stable oscillation output based on the oscillation output of VC-TCXO 1 or VC-TCXO 2 output from the switch 4 and a synchronization control unit 31.

The VC-TCXO 1 also supplies a clock signal (CLK) to the digital block 5. Further, the control signal (Vcon1) given from the digital block 5 is digital / analog converted by the D / A converter (DAC) 6 and supplied to the VC-TCXO1, and the oscillation frequency of the VC-TCXO1 is variable.
When the oscillation frequency of the VC-TCXO1 portion is fixed, a crystal oscillator with a fixed oscillation frequency can be used instead of the VC-TCXO1.

  The synchronization controller 21 includes an R1 counter (R1 divider) that divides the output (Ref1) of the reference oscillator VC-TCXO1 by R1, and an N1 counter (N1 divider) that divides the oscillation output of the VC-TCXO2 by N1. The first reference frequency output, which is the output obtained by dividing Ref1 by the R1 divider, and the first comparison frequency output, which is the output obtained by dividing the oscillation output of VC-TCXO2 by the N1 divider, are compared. The first phase error (DC component), which is the comparison result, is configured from a first phase comparator that supplies a control signal (Vcon2) to VC-TCXO2 (none of which is shown).

The synchronization control unit 31 includes an R2 counter (R2 divider) that divides the output of the switch 4 (Ref2) by R2, an N2 counter (N2 divider) that divides the oscillation output of the VCO 3 by N2, and Ref2 as R2. The second reference frequency output, which is the output divided by the frequency divider, and the second comparison frequency output, which is the output obtained by dividing the oscillation output of the VCO 3 by the N2 frequency divider, are compared, and the second phase is the comparison result. The second phase comparator supplies an error as a control signal (Vcon3) to the VCO 3 (none is shown).
The second oscillation circuit 20 composed of the synchronization control unit 21 and VC-TCXO2 and the third oscillation circuit 30 composed of the synchronization control unit 31 and VCO3 each constitute a PLL oscillator.

  In the synthesizer circuit 100 configured as described above, the first reference frequency obtained by dividing the reference signal (Ref1) by R1 and the oscillation circuit (in the second oscillation circuit 20) in synchronization with the oscillation output (Ref1) of the VC-TCXO1. The comparison frequency obtained by dividing the output of VC-TCXO2, VCO3) in the third oscillation circuit 30 by N1 or N2 is compared by a phase comparator, and as a result, a reference frequency × N frequency is output.

  Here, for example, consider a case where the output of the VCO (3) is locked using a set of voltage-controlled temperature-compensated crystal oscillator VC-TCXO (1, 2) and a synchronization control unit (31), and oscillation of VC-TCXO1 Assume that the frequency is 19.2 MHz and the oscillation frequency of the VCO 3 is greatly changed from 1645.2 MHz to 1671 MHz and locked. At this time, if the division ratio of the R2 counter of the synchronization control unit 31 is 1, the second reference frequency is 19.2M / 1 = 19.2 MHz.

  In this example, in order to lock the frequency of the third oscillation circuit 30, the division ratio of the N2 counter of the synchronization control unit 31 is from 85.6875 (= 1645.2 / 19.2) to 87.003125 (= 1671 / 19.2). However, in the case of rewriting that changes the frequency division ratio of the N2 counter in this way, it takes some time to lock. Therefore, in this embodiment, when the oscillation frequency is greatly changed in this way, the control of switching the reference oscillator to another VC-TCXO2 is performed instead of greatly changing the frequency division ratio of the N2 counter. Here, when the oscillation frequency of VC-TCXO2 is 19.35 MHz, the above-described frequency lock is as follows.

  In the oscillation state of the previous VC-TCXO1, the third oscillation circuit 30 is locked at the frequency division ratio of the N2 counter of 85.6875. Here, when the output of the switch 4 is switched to the oscillation output of the VC-TCXO2, the frequency dividing ratio of the N2 counter remains unchanged (85.6875) and the frequency is locked to 19.35 × 85.6875 = 1658.053125 MHz. However, if the N2 counter frequency division ratio is rewritten to 86.356589214868 (this change is smaller than the previous example) simultaneously with this switch change, it locks to 1671 MHz. Since switching of the switch 4 and rewriting of the division ratio of the N2 counter in this case can be performed at high speed, high-speed lockup can be realized as a result.

As described above, in the present embodiment, the oscillation frequency of the synthesizer circuit 100 can be controlled by controlling the frequency division ratio of the N counter of the switch 4 and the synchronization control unit 31.
In this embodiment, since the oscillation output is supplied to the outside as the oscillation output of the synthesizer circuit 100 from the third oscillation circuit 30 which is one PLL oscillator, two PLL oscillators are used as in the prior art. In this case, it is possible to solve the problem of load fluctuation applied to the voltage controlled oscillator and the problem of isolation.

Further, in the present embodiment, since it is configured as described above, it is possible to avoid a case where spurious is generated inside the second oscillation circuit 20 or the third oscillation circuit 30 constituting the PLL oscillator. For example, when spurious occurs due to VC-TCXO1, it can be replaced with VC-TCXO2 to stop spurious generation or change the spurious generation position.
In order to avoid or reduce spurious generated in the PLL oscillator, in the above configuration, the selection of the oscillation frequency of the first oscillation circuit 1 and the second oscillation circuit 20 and the frequency division ratio of each frequency divider are performed. It is desirable to make appropriate selections.

  In the conventional mobile radio apparatus in the TDMA system or the like, the digital block 5 synchronizes the oscillation output of the VC-TCXO1 with the reference clock inside the base station based on the reference clock given from the base station. The configuration of the VC-TCXO1, the digital block 5, and the D / A converter 6 shown in FIG. 1 is a configuration for this purpose. Of course, VC-TCXO2 also needs to be synchronized with the reference clock of the base station, similarly to VC-TCXO1. Therefore, in the digital block 5, it is sufficient to make a circuit that can synchronize the oscillation output of the VC-TCXO2 with the reference clock in the same way as the VC-TCXO1, but this is very costly. . Therefore, in this embodiment, the synchronization control unit 21 is used to synchronize with the reference clock.

  The first reference frequency which is the reference frequency of the synchronization control unit 21 is generated based on the reference signal (Ref1) given from the VC-TCXO1, and the VC-TCXO2 is controlled by the synchronization control unit 21 (described above). In this way, the VC-TCXO2 and the synchronization control unit 21 constitute a PLL oscillator), and VC-TCXO1 and VC-TCXO2 can be synchronized. As a result, the oscillation output of VC-TCXO2 is also synchronized with the reference clock.

  As mentioned above, although embodiment of this invention has been explained in full detail with reference to drawings, the concrete composition is not restricted to this embodiment, and the composition of the range which does not deviate from the gist of this invention is included. Needless to say.

It is a block diagram which shows the structure of the synthesizer circuit which is one embodiment of this invention. It is a block diagram which shows the structure of the conventional synthesizer circuit.

Explanation of symbols

1 ... VC-TCXO (first oscillation circuit, crystal oscillator)
2 ... VC-TCXO (first voltage controlled oscillator)
3 ... VCO (second voltage controlled oscillator)
4 ... Switch (SW)
5 ... Digital Block (Digital Block)
6. D / A converter (DAC)
DESCRIPTION OF SYMBOLS 20 ... 2nd oscillation circuit 21 ... Synchronization control part 30 ... 3rd oscillation circuit 31 ... Synchronization control part 100 ... Synthesizer circuit

Claims (3)

A first oscillation circuit;
A second oscillation circuit that oscillates at a different frequency from the output of the first oscillation circuit in synchronization with the first oscillation circuit;
A switch for switching an output of the first oscillation circuit and the second oscillation circuit;
A synthesizer circuit comprising: a third oscillation circuit that receives an output of the switch and generates an oscillation output that is synchronized with the output and is an output of the synthesizer circuit. The first oscillation circuit comprises a crystal oscillator,
The second oscillation circuit receives the first voltage controlled oscillator and the oscillation frequency of the crystal oscillator as a reference frequency, and synchronizes the output of the first voltage controlled oscillator with the output of the crystal oscillator based on the reference frequency. A phase comparator and a frequency divider
The third oscillation circuit receives, as a reference frequency, an oscillation frequency of the second voltage controlled oscillator and the crystal oscillator or the first voltage controlled oscillator output from the switch, and based on the reference frequency, The phase comparator and the frequency divider for synchronizing the output of the voltage controlled oscillator with the output of the crystal oscillator or the first voltage controlled oscillator output from the switch. Synthesizer circuit. The synthesizer circuit according to claim 1, wherein the second oscillation circuit and the third oscillation circuit are PLL oscillators.

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