JP2005124948A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine in which the processing load of a microprocessor is reduced. <P>SOLUTION: First a CPU set an interrupting mode, stack pointer and a register of an internal device after setting an interrupting inhibiting mode when the pachinko game machine is turned on. Next, the CPU determines the presence or absence of backup and carries out parity check, executes game condition restoring processing when there is the backup and check result is normal, and executes initialization processing when there is no backup or the check result is not normal. Then, the CPU executes random number circuit setting program and sets a random number maximal value a random number resetting system and the frequency of an internal clock signal or others in a random number circuit. Thereafter, performs setting for timer interrupting to progresses to loop processing. Thus, the processing load of the microprocessor is reduced, because there becomes no need to perform resetting processing of random numbers in a limited interrupting processing time by performing the random number circuit setting processing before progressing to the loop processing after energizing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a gaming machine such as a pachinko machine, and more specifically, based on the fact that a variable display start condition is satisfied after a variable display execution condition is satisfied, a plurality of types of identification information that can be individually identified The present invention relates to a gaming machine that includes a variable display device that variably displays and controls a specific gaming state that is advantageous for a player when the display result of the variable display becomes a predetermined specific display result.

  In gaming machines such as pachinko machines, variable display is performed by updating and displaying predetermined identification information (hereinafter referred to as display symbols) on a display device such as a liquid crystal display (hereinafter referred to as LCD). There are provided a number of games that are enhanced by a so-called variable display game that determines whether or not to give a predetermined game value based on a display result that is a combination result.

  Some variable display games are played by using the above-described display device as an image display device (hereinafter referred to as a special game). The special figure game is based on the detection of the game ball passing through the start winning opening (the start condition of the variable display is established), and the display design is updated and the display design update display is completely stopped. A game in which the case where the stop symbol form is a predetermined specific display form is “big hit”. Whether or not it is a “big hit” in the special game is determined by whether or not the random number value read from the random counter or the like matches a predetermined big hit judgment value. Alternatively, a special electric accessory called an attacker is opened, and a state in which winning of a game ball is extremely easy for a player is continuously provided for a certain period of time.

Conventionally, a random number for determining whether or not to make a “big hit” (hereinafter referred to as a big hit determination random number) has been generated by a random number circuit externally attached to a game control microprocessor (for example, a patent) The counter unit 62) described in Document 1. In addition, a technique in which a microprocessor generates a random number using an application program has been proposed (for example, Patent Document 2).
JP 2000-300183 A. JP 2002-282457 A.

  However, in the configuration of Patent Document 1, a circuit for generating random numbers must be arranged separately from the microprocessor, which increases the amount of hardware and occupies board space. Further, since the random number circuit of Patent Document 1 only counts the output of the pulse generator, there is a possibility that the randomness such as the periodicity of the generated random number may be lowered.

  In the technique described in Patent Document 2, a microprocessor generates a random number by software processing. Therefore, no hardware is required other than the microprocessor. However, since the program generates random numbers, the processing load on the microprocessor is large. In particular, because a random number update process is performed during the execution of a timer interrupt process for game control, it is necessary to develop a program similar to that for game control, and a random number for a limited interrupt processing time. There has been a problem that processing for generation has to be started and ended, increasing the processing load on the microprocessor.

  In addition, since the count value of the counter is periodically counted up, a random number value that matches the jackpot determination value is generated when the count-up cycle or the cycle in which the counter count value makes one round is detected by any means. Timing is recognized. Then, it is possible to frequently generate “hit” by playing a game aimed at the timing at which a random number value that matches the jackpot determination value is generated. In some cases, an illegal board is attached to a gaming machine in order to aim at a timing at which a random number value that matches the jackpot value is generated. Such a fraudulent board introduces a signal output to the outside from the circuit part that performs game control, detects the start timing of the circuit part that performs game control based on the signal, and the random value that matches the jackpot determination value is The timing of occurrence is detected. Then, the illegal board can send a predetermined signal to the circuit portion that controls the game at that timing, and illegally generate a “big hit”. As a result, there is a disadvantage in the game store where the gaming machine is installed.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a gaming machine capable of reducing the processing load of a microprocessor.

  Another object of the present invention is to provide a gaming machine capable of generating a random number with high randomness. Furthermore, an object of the present invention is to provide a gaming machine that prevents fraud. Another object of the present invention is to provide a gaming machine that can secure a board space.

  In order to achieve the above object, a gaming machine according to claim 1 of the present application provides a variable display start condition (for example, a variable display device) after a variable display execution condition (for example, winning a normal variable winning ball device 6) is established. 4 is provided with a variable display device (for example, a variable display device 4) that variably displays a plurality of types of identification information that can be identified based on the fact that the previous variable display in 4 and the end of the big hit gaming state have been established. A power supply means for controlling the game machine to a specific game state (for example, a big hit game state) advantageous to the player when the display result is a predetermined specific display result, and supplying power to the game machine (For example, the power supply board 10) and a random number circuit (for example, random number circuit 103) that generates a random number (for example, random R), and operates using the power supplied from the power supply means, A microprocessor for controlling the progress of the technique (for example, a game control microprocessor 100 mounted on the main board 11), and a variable for controlling the variable display of the identification information in the variable display device based on a control signal from the microprocessor. Display control means (for example, display control board 12), and the random number circuit has a clock signal (for example, an internal clock signal shown in FIG. 4) having a predetermined period (for example, “period of system clock signal × 128 × 16”). ) And a numerical value update register (for example, count value update register) that stores numerical value update data (for example, count value update data “01h”) for requesting the update of numerical data. 135) and the first and second random number update methods that are methods for updating random numbers A random number update method selection register (for example, random number update method selection register 137) that stores random number update method selection data (for example, random number update method selection data “01b”, “10b”) that specifies the selected random number update method; When random number update method selection data (for example, random number update method selection data “01b”) for designating the first random number update method is stored in the random number update method selection register, the numerical value update data is written into the numerical value update register. In response to this, the numerical data is updated, and random number update method selection data (for example, random number update method selection data “10b”) for specifying the second random number update method is stored in the random number update method selection register. A numerical value updating means for updating the numerical data in response to the clock signal output from the clock signal output means. (For example, the counter 121), random number storage means (for example, a random value register 131) for storing numerical data updated by the numerical value updating means as random number values, and numerical data updated by the numerical value updating means as random number values Numerical value acquisition register (for example, count value acquisition register 136) for storing numerical value acquisition data (for example, count value acquisition data “01h”) instructing storage in the random value storage means, and selection of the random number update method When the random number update method selection data designating the first random number update method is stored in the register, the numerical data updated by the numerical value update unit is received in response to the clock signal output from the clock signal output unit. Random number update method that stores in the random value storage means and designates a second random number update method in the random number update method selection register When the selection data is stored, the random number storage means stores the numerical data updated by the numerical value update means in response to the numerical value acquisition data being written to the numerical value acquisition register. Numerical value fetching means (for example, a second selector 129), and after the start of power supply by the power supply means, the microprocessor at least as the setting for causing the random number circuit to update the random number value Random number circuit setting for writing the random number update method selection data designating the random number update method selected from among the first and second random number update methods to the random number update method selection register (for example, the process of step S22) Means (for example, the part where the CPU 106 executes the random number circuit setting process in step S10) and the random number circuit setting means to the random number circuit. Timer interrupt process execution permission means (for example, the part where the CPU 106 executes the process in step S14) that permits execution of the timer interrupt process that occurs periodically (for example, every 2 milliseconds), When the first random number update method is selected while the timer interrupt process is being executed (for example, when the game control interrupt process is being executed by the CPU 106), the numerical value update data is written into the numerical value update register to The random number value stored in the numerical value storage means is updated (for example, the CPU 106 executes the process of step S196), and the random number value stored in the random number value storage means is read according to the fulfillment of the execution condition ( For example, the CPU 106 executes the process of step S162), and whether or not the read random number value matches predetermined determination value data (for example, “3”). To determine whether the display result in the variable display triggered by the establishment of the execution condition is a specific display result, and when the second random number update method is selected, the numerical value capture Data is written in the numerical value acquisition register, and the random value storage means stores the random value (for example, the CPU 106 executes the process of step S142), and stores in the random value storage means when the execution condition is satisfied. The read random number value is read (for example, the CPU 106 executes the process of step S143), and it is determined whether the read random number value matches the predetermined determination value data, thereby satisfying the execution condition. Display result determining means (for example, the CPU 106 determines whether or not the display result in the variable display as an opportunity is a specific display result) And a portion for executing the jackpot determination process of step S131).

  In the gaming machine according to claim 2, the microprocessor, after the start of power supply by the power supply means, a predetermined recovery condition (for example, there is a backup and the backup data check result is normal) ) Is established (for example, the CPU 106 determines Yes in steps S6 and S7), a process for restoring the control state at the time of the previous power supply stop (for example, the internal state of the main board 11 and the sub state). Recovery processing execution means (for example, a portion where the CPU 106 executes the game state recovery processing in step S8) for executing the processing for returning the control state of each control board to the state when the power is turned off, and the power supply means After the start of power supply, the predetermined recovery condition is not satisfied (for example, the CPU 106 determines No in step S6 or S7). Based on the initialization processing execution means (for example, the CPU 106 clears the RAM 105, initializes the predetermined work area, etc.) (for example, the CPU 106 performs the processing in step S9). The random number circuit setting means outputs the random number value to the random number circuit after executing the recovery process by the recovery process executing means or after executing the initialization process by the initialization process executing means. Settings for updating are performed (for example, the CPU 106 executes the random number circuit setting process in step S10).

  In the gaming machine according to claim 3, the random number circuit includes random number maximum value setting data (for example, random number maximum value setting data “00FFh”) that specifies a maximum value (for example, “255”) of a random number generated by the random number circuit. , Etc.) for storing random number maximum value setting registers (for example, random number maximum value setting register 132) and the update range by the numerical value updating means according to the random number maximum value setting data specified in the random number maximum value setting register (for example, Update range restriction means (eg, comparator 122) for restricting the range from “1” to “255”, etc., and the random number circuit setting means stores the random number maximum value setting data in the random number maximum value setting register. It includes random number maximum value setting means for writing (for example, a portion where the CPU 106 executes the process of step S21).

  5. The gaming machine according to claim 4, wherein the microprocessor includes system reset means (for example, a reset controller 102) for system resetting the microprocessor until the microprocessor resets the system by the system reset means. The random number maximum value setting means controls the random number maximum value setting register in which the random number maximum value setting data is written to be unwritable.

  In the gaming machine according to claim 5, the microprocessor has a predetermined maximum value of the random number specified by the random number maximum value setting data written by the random number maximum value setting means in the random number maximum value setting register. When the value is smaller than a lower limit value (for example, “4”, etc.) (for example, when the maximum random number value specified by the random number maximum value setting data is “0” to “3”), a predetermined value (for example, greater than the predetermined lower limit value) Random number maximum value setting data (for example, random value maximum value setting data “0FFFh” or the like) specifying “4095” or the like is stored in the random number maximum value setting register.

  7. The gaming machine according to claim 6, wherein the numerical value updating means circularly updates the numerical data from a predetermined initial value to a predetermined final value, and the random number circuit is updated by the numerical value updating means. When the numerical data is updated to the predetermined final value, notification signal output means (for example, a portion where the counter 121 outputs the notification signal) that outputs a notification signal (for example, the notification signal shown in FIG. 4) notifying that effect is provided. And the microprocessor includes an initial value changing means (for example, a portion where the CPU 106 executes the initial value changing process of S104) for changing the predetermined initial value in response to the notification signal output from the numerical value updating means. .

  In the gaming machine according to claim 7, the initial value changing means is configured such that the changed initial value is larger than the maximum value (for example, “255”, etc.) of the random number (for example, the changed initial value is “256”). And the like (for example, a portion for changing the initial value changed by the CPU 106 again).

  In the gaming machine according to claim 8, the microprocessor selects a function for changing the predetermined initial value from the first, second, and third initial value changing methods (for example, the CPU 106 uses the initial value). And a storage means (for example, RAM 105) for storing predetermined data, and the initial value change means is selected when the first initial value change method is selected (a part for executing the value change program 153). For example, when it is determined Yes in step S172, the predetermined initial value is changed to a value set based on an identification number (for example, an ID number) unique to the microprocessor, and the second initial value changing method Is selected (when it is determined No in step S172 and then determined Yes in step S173), the predetermined initial value When the value is changed to a value stored in a predetermined address (for example, a specified RAM address) of the storage means and the third initial value update method is selected (No is determined in step S172), and further the step When it is determined No in S173 and then determined Yes in Step S174), the predetermined initial value is stored in a predetermined address (for example, addresses 7EFFh to 7FFFh) of the storage means. Change based on value.

  10. The random number circuit according to claim 9, wherein the random number circuit stores numerical permutation change data (for example, count value permutation change data “01h”) for requesting change of a permutation that is an update order of numerical data. When the numerical permutation change data is stored in the permutation change register 133) and the numerical permutation change register, the numerical permutation is changed to a permutation having an update order different from the permutation when the numerical permutation change data is not stored. Changing means (for example, count value permutation changing circuit 123), and the microprocessor is a numerical permutation change data writing means (for example, the CPU 106 counts the count value in step S105) for writing the numerical permutation change data into the numerical permutation change register. Part for executing the permutation change process).

  According to another aspect of the present invention, the microprocessor initializes the numerical permutation change register in response to the permutation being changed by the numerical permutation changing means.

  11. The numerical value permutation changing means according to claim 11, wherein when the numerical permutation data is rewritten in the numerical permutation register after the numerical permutation change register is initialized, the changed numerical data permutation is displayed. Further change.

  13. The random number update method selection data according to claim 12, wherein the microprocessor includes system reset means (for example, a reset controller 102) for system resetting the microprocessor until the microprocessor is system reset by the system reset means. The random number update method selection register in which is written is controlled to be unwritable.

  14. The microprocessor according to claim 13, wherein the microprocessor includes a system clock signal output means (for example, a clock circuit 101) for outputting a system clock signal, and the display result determining means is a system clock output by the system clock signal output means. The numerical value update data is written into the numerical value update register after a time longer than the signal cycle.

  In the gaming machine according to claim 14, the random number circuit includes a cycle setting register (for example, cycle setting register 134) that stores cycle setting data (for example, cycle setting data “0Fh”) that specifies the update cycle; Clock signal generation means (for example, clock signal output circuit 124) that generates and outputs a clock signal having a period specified by the period setting data stored in the period setting register, and the random number circuit setting means includes: It includes cycle setting means for writing the cycle setting data for designating a preset update cycle into the cycle setting register (for example, a portion where the CPU executes the process of step S23).

  16. The microprocessor according to claim 15, further comprising system reset means (for example, a reset controller 102) for system resetting the microprocessor, wherein the cycle setting data is written until the microprocessor is system reset by the system reset means. The cycle setting register is controlled to be unwritable.

  17. The microprocessor according to claim 16, wherein the period of the clock signal specified by the period setting data written to the period setting register by the period setting unit is a predetermined lower limit value (for example, “period of system clock signal × 128 (for example, when the period of the clock signal specified by the period setting data is “0” to “the period of the system clock signal × 128 × 7”), the predetermined lower limit value is specified. Period setting data (for example, period setting data “0Fh”) is stored in the period setting register.

  18. The gaming machine according to claim 17, wherein the random number circuit stores a random number circuit activation register (for example, random number circuit activation data) that stores random number circuit activation data (for example, random number circuit activation data “80h”) that requests activation of the random number circuit. And a random number circuit activation signal output means (for example, random number circuit activation) for outputting a random number circuit activation signal for activating the random number circuit in response to the writing of the random number circuit activation data in the random number circuit activation register. The random number circuit setting means writes the random number circuit activation data into the random number circuit activation register and activates the random number circuit (for example, the CPU 106 performs the process of step S24). To execute).

  In the gaming machine according to claim 18, the microprocessor includes a system reset unit (for example, a reset controller 102) for system resetting the microprocessor, and the random number circuit activation setting unit is configured to perform the micro reset by the system reset unit. When the processor is reset, the random number circuit activation data is rewritten in the random number circuit activation register to activate the random number circuit (for example, the CPU 106 executes the process of step S24).

  The inventions according to claims 1 to 18 of the present application have the following effects.

  According to the configuration of claim 1, after the start of the supply of power, the random number circuit is set to update the numerical data, and thereafter, periodically interrupted timer interrupt processing is permitted. Therefore, it is not necessary to start / end the process for generating random numbers within a limited interrupt processing time, and an increase in the processing load on the microprocessor can be prevented. In addition, since the random number value can be stored in the random value storage unit by the selected random number update method, by selecting a different random number update method for each gaming machine, it is read from the random value storage unit and the variable display It is possible to improve the randomness of random numbers used to determine whether or not the display result in is used as the specific display result. Furthermore, since the random number value is updated by a random number circuit, the capacity of the program stored in the microprocessor can be reduced as compared with that updated by software. In addition, it is possible to specify the timing at which the random number updating unit updates the random number, and the timing at which the random number fetching unit fetches the numerical data as a random value into the random value storing unit and updates the random number. It is possible to prevent a random value that has not been read out from being read out. Further, since the random number circuit is built in the microprocessor, a board space can be secured. Further, by incorporating the random number circuit in the microprocessor, it is possible to make forgery such as installation of an illegal base.

  According to the configuration of claim 2, after the execution of the recovery process by the recovery process execution unit or the execution of the initialization process by the initialization process execution unit, the random number circuit is set to update the random number value. After that, the execution of the timer interrupt processing that occurs periodically is permitted, so there is no need to start and end the processing for generating random numbers during the limited interrupt processing time, and the processing load of the microprocessor is reduced. An increase can be prevented. Further, it is possible to reduce the capacity of the program stored in the microprocessor by using the random number generated by the random number circuit to determine whether or not the display result in the variable display is the specific display result.

  According to the configuration of claim 3, since the random number value stored in the random value updating means can be updated with the maximum value of the random number set in advance as an upper limit, the different value for each gaming machine By setting the maximum value of the random number, it is possible to improve the randomness of the random number that is read from the random value storage means and used to determine whether or not the display result in the variable display is the specific display result. .

  According to the configuration of claim 4, since the maximum value of the random number set in the random number circuit cannot be changed until the system is reset by the system reset unit, a malicious player can By changing the value, it is possible to freely set the timing at which the random value read from the random value storage means matches the predetermined determination value, thereby preventing illegal acts such as frequent occurrence of the specific gaming state.

  According to the configuration described in claim 5, it is possible to prevent a value equal to or smaller than the predetermined lower limit value from being set in the random number circuit as the maximum value of the random number.

  According to the configuration of the sixth aspect, the predetermined initial value of the numerical data updated by the numerical value updating unit is changed, and the numerical data is updated from the predetermined initial value to the predetermined final value. Fraudulent acts such as outputting a predetermined signal aiming at a timing at which a random value read from the random number storage means matches the predetermined determination value and causing the specific gaming state to occur frequently Can be prevented.

  According to the configuration of claim 7, when the initial value changed by the initial value changing unit is larger than the maximum value of the random number set in the random number circuit, the changed initial value can be further changed. Therefore, it is possible to prevent the numerical data output to the random value storage means from becoming larger than the maximum random number.

  According to the configuration of claim 8, the predetermined initial value can be changed by an initial value changing method selected from the first, second, and third initial value changing methods. By selecting the first, second or third initial value changing method every time, it is read out from the random value storage means to determine whether or not the display result in the variable display is the specific display result The randomness of the random numbers used can be improved.

  According to the configuration of claim 9, by changing the permutation, which is the update order of the numerical data input to the random value storage means, it is read from the random value storage means and the display result in the variable display It is possible to improve the randomness of random numbers used to determine whether or not to be a specific display result.

  The numerical data output to the random value storage means for initializing the numerical permutation change register in response to the permutation being changed by the numerical permutation changing means. Can be prevented from being continuously changed.

  According to the configuration of claim 11, after the numerical permutation change register is initialized, the permutation of the changed numerical data is further changed to be read out from the random value storage means and the variable The randomness of the random number used for determining whether or not the display result in the display is the specific display result can be further enhanced.

  According to the configuration of claim 12, since the random number update method set in the random number circuit cannot be changed until the system is reset by the system reset unit, a malicious player can change the random number update method. By changing it, it is possible to freely set the timing at which the random number value read from the random number value storage means matches a predetermined determination value, thereby preventing illegal acts such as frequent occurrence of the specific gaming state.

  According to the configuration of claim 13, the display result determining means sets the numerical value update data to the numerical value update register after a time longer than the period of the system clock signal output by the system clock signal output means. In order to write, it is possible to secure a time for reading the updated random value from the random value storage means.

  According to the configuration of claim 14, the numerical value data output from the numerical value updating unit is updated every predetermined period, the updated numerical data is taken into the random value storage unit, and the random value Since the random value stored in the storage means can be updated, by setting a different period for each gaming machine, the random number value is read from the random value storage means, and the display result in the variable display is specified display result It is possible to increase the randomness of the random number used to determine whether or not.

  According to the configuration of claim 15, since the update cycle set in the random number circuit cannot be changed until the system is reset by the system reset unit, a malicious player changes the update cycle. Thus, it is possible to freely set the timing at which the random number value read from the random value storage means matches a predetermined determination value, thereby preventing illegal acts such as frequent occurrence of the specific gaming state.

  According to the structure of Claim 16, it can prevent that the value below the said predetermined | prescribed lower limit is set to the said random number circuit as said update period.

  According to the configuration of claim 17, since the random number circuit can be activated after setting the random number circuit to update the random number value, the setting is performed after the power supply is started. It is possible to prevent such a problem that the random number circuit generates a random number before it is performed.

  According to the configuration described in claim 18, even when the system is reset by the system reset means, the random number circuit can be activated again.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the reach display state means a symbol that is derived and displayed as a display result (referred to as a reach symbol) and is not yet derived and displayed when the symbol is a part of the jackpot symbol (referred to as a reach variable symbol). Is a state in which variable display is being performed, or a state in which all or some of the symbols are variably displayed synchronously while constituting all or part of the jackpot symbol. Specifically, an effective line that becomes a big hit is determined in a plurality of predetermined display areas by stopping predetermined symbols, and predetermined symbols are displayed in some display areas on the effective lines. A state in which variable display is being performed in the display area on the active line that has not been stopped when the is stopped (for example, the left, right, and right display areas are jackpot symbols in the left, middle, and right display areas) (For example, “7”) is stopped and displayed, and the display area inside is still in variable display), or all or part of the display area on the active line Is a variable display that is synchronously displayed while constituting all or part of the jackpot symbol (for example, variable display is performed in all of the left, middle, and right display areas, and any state is displayed. Variable display is performed with the pattern being arranged. And is that state).

  The gaming machine in the present embodiment is a gaming machine that performs a special game with an image display device such as an LCD, and is a card reader (CR: Card Reader) type 1 pachinko gaming machine that lends a ball with a prepaid card. A gaming machine such as a slot machine equipped with an LCD.

  Further, the gaming machine may be a ball and ball game machine such as a pachinko gaming machine, and if it has an image display device, for example, a pachinko gaming machine classified into the second type or the third type, It may be an electric machine or a ball game machine with a probability setting function called pachikon. Furthermore, it is applicable not only to a CR-type pachinko gaming machine that lends a ball with a prepaid card, but also to a pachinko gaming machine that lends a ball with cash. That is, any form of game machine may be used as long as it has an image display device such as an LCD and can variably display symbols as identification information.

  FIG. 1 is a front view of a pachinko gaming machine according to the present embodiment and shows an arrangement layout of main members. A pachinko gaming machine (gaming machine) 1 is roughly divided into a gaming board (gauge board) 2 constituting a gaming board surface and a gaming machine frame (base frame) 3 for supporting and fixing the gaming board 2. . The game board 2 is formed with a substantially circular game area surrounded by guide rails. A variable display device 4 that displays special symbols as variable identification information that can be variably displayed is provided at a substantially central position of the game area. Under the variable display device 4, an ordinary variable winning ball device (start winning port) 6 is arranged. A special variable winning ball apparatus (large winning opening) 7 is disposed below the normal variable winning ball apparatus 6. In addition, a normal symbol display 40 is provided above the variable display device 4.

  The variable display device 4 includes an LCD (Liquid Crystal Display) module that variably displays symbols as identification information by a plurality of variable display units. For example, a game ball wins a normal variable winning ball device 6. In the special figure game where is the execution condition, the variable display of three display symbols (special symbols) composed of numbers, letters, symbols, etc. is started, and after a certain period of time, they are displayed in the order of left, right, and middle Confirm the design. The variable display device 4 may be provided with four start memory display areas for displaying the number of effective winning balls that have entered the normal variable winning ball device 6, that is, the start memory number.

  In this embodiment, a special symbol with an even symbol number is a normal jackpot symbol, and a special symbol with an odd symbol number is an odd jackpot symbol. In other words, in the special game with the variable display device 4, after starting the variable display of special symbols, when the same special symbols are derived and displayed as display results in the left, middle and right display areas, the pachinko game The machine 1 is in a big hit gaming state. In addition, in the special game with the variable display device 4, after starting the variable display of the special symbol, when the same probability variation big winning symbol is derived and displayed as the display result in the left, middle and right display areas, the pachinko The gaming machine 1 enters a special gaming state (probability improvement state) following the end of the jackpot gaming state, and thereafter, the probability that the display result in the special figure game becomes a jackpot combination is increased until a predetermined condition is satisfied. In the probability improvement state, the opening time of the normally variable winning ball apparatus 6 is longer than that in the normal gaming state, and the number of times of opening is increased compared to that in the normal gaming state. This is an advantageous state. The normal gaming state is a gaming state other than the big hit gaming state or the probability improvement state.

  The normal symbol display 40 is configured with a light emitting diode (LED) or the like, and is lit, flashing, colored, etc. in a normal diagram game where the starting condition is that a game ball passes through a pass gate provided in the game area. Is controlled. When a display with a predetermined hit pattern is performed in this normal figure game, the display result in the normal figure game is “win”, and the movable wing piece of the electric tulip constituting the normal variable winning ball apparatus 6 is passed for a predetermined time. Tilt control.

  The normally variable winning ball apparatus 6 is a tulip-type accessory (ordinary electric motor) having a pair of movable wing pieces that are controlled to move between a vertical (normally open) position and a tilt (enlarged open) position by a solenoid 21 (FIG. 3). (Community). The special symbol variable display based on the winning of the game ball on the normal variable winning ball apparatus 6 is stored in a special figure holding memory 170 (FIG. 24) described later up to a predetermined number of times (in this embodiment, four times).

  The special variable winning ball apparatus 7 includes an opening / closing plate that opens and closes a winning area by a solenoid 22 (FIG. 3). This opening / closing plate is normally closed, and when a special game is played by the variable display device 4 based on the winning of the game ball to the normal variable winning ball device 6, the solenoid is turned on when the big hit gaming state is achieved. 22 is set so that the winning area is opened (opening cycle) until a predetermined period (for example, 29 seconds) or a predetermined number (for example, 10) of winning balls are generated. Receiving game balls falling in the game area. The opening cycle can be repeated up to 16 times, for example. A game ball won in the special variable winning ball apparatus 7 is detected by a predetermined detection unit. In response to the detection of a winning ball, a predetermined number of winning balls are paid out by a main board 11 and a payout control board 15 (FIG. 2) which will be described later.

  In addition to the above-described configuration, the surface of the game board 2 is provided with a windmill with a built-in lamp, an out port, and the like. Further, the pachinko gaming machine 1 is provided with a game effect lamp 9 that lights or flashes and speakers 8L and 8R that generate sound effects.

  FIG. 2 is a rear view of the pachinko gaming machine 1 and shows an arrangement layout of main boards. The pachinko gaming machine 1 in this embodiment mainly includes a power supply board 10 that functions as power supply means, a main board 11, a display control board 12, a voice control board 13, a lamp control board 14, and a payout control board 15. And an information terminal board 16 are disposed at appropriate positions. In addition, the display control board 12, the audio | voice control board 13, and the lamp | ramp control board 14 may be arrange | positioned in the state accommodated in one box, for example in the back surface of the pachinko gaming machine 1, as an independent board | substrate, for example. Furthermore, the display control board 12, the sound control board 13, and the lamp control board 14 may be configured as a single board.

  The power supply board 10 supplies predetermined power to each circuit in the pachinko gaming machine 1.

  The main board 11 is a main-side control board on which various circuits for controlling the progress of the game in the pachinko gaming machine 1 are mounted. The main board 11 mainly has a function of inputting a signal from a switch or the like disposed at a predetermined position, a sub-side including a display control board 12, a sound control board 13, a lamp control board 14, a payout control board 15, and the like. Each control board has a function of outputting and transmitting control data, which is an example of command information, and a function of outputting various information to a hall management computer.

  The control command transmitted from the main board 11 to the display control board 12 is a display control command. FIG. 3 is a block diagram illustrating a circuit configuration of the main board 11 and signal lines of display control commands transmitted from the main board 11 to the display control board 12. As shown in FIG. 3, in this embodiment, a display control command is sent from the main board 11 to the display control board 12 through eight signal lines of display control signals CD0 to CD7. A signal line for a display control INT signal for transmitting and receiving a strobe signal is also wired between the main board 11 and the display control board 12.

  As shown in FIG. 3, the main board 11 is provided with an ordinary variable winning ball device 6 that is a start winning port, a special variable winning ball device 7 that is a large winning port, and a prize of game balls to other winning ports. Wiring from each winning opening switch 70 for detection is also connected. Further, the main board 11 is connected to wirings to solenoids 21 and 22 for performing movable control of the movable blade piece in the normal variable winning ball apparatus 6 and opening / closing control in the special variable winning ball apparatus 7. .

  The main board 11 includes a game control microprocessor 100, a switch circuit 109, a solenoid circuit 110, and the like. The game control microprocessor 100 is, for example, a one-chip microprocessor, and includes a clock circuit 101, a reset controller 102 that functions as a system reset means, a random number circuit 103, a ROM (Read Only Memory) 104 that stores a game control program, and the like. A RAM (Random Access Memory) 105 used as a work memory, a CPU (Central Processing Unit) 106 that performs a control operation, a CTC (Counter Timer Circuit) 107 that sends an interrupt request signal to the CPU, and an I / O (Input / Input) Output) port 108 is built-in.

  The clock circuit 101 outputs a system clock signal to the CPU 106, and outputs a reference clock signal generated by 27 (= 128) weeks of the system clock signal to the random number circuit 103. When a low level signal is input for a certain period, the reset controller 102 outputs a predetermined initialization signal to the CPU 106, the random number circuit 103, and the like, thereby resetting the game control microprocessor 100 as a system.

  FIG. 4 is a block diagram illustrating a configuration example of the random number circuit 103. As shown in FIG. 4, the random number circuit 103 functions as a counter 121 functioning as a numerical value updating means, a count value permutation changing circuit 123, a comparator 122 functioning as an update range regulating means, and a clock signal generating means. Including a clock signal output circuit 124, a first trigger signal output circuit 125, a second trigger signal output circuit 126, a random number update method selection signal output circuit 127, a first selector 128, and a second selector 129. And a random number circuit activation signal output circuit 130, and a random value register (RND) 131 that functions as a random value storage means. The random number circuit 103 generates a random R that is a random number for determining a big hit that generates a big hit and determines whether or not the pachinko gaming machine 1 is put into a big hit gaming state.

  In response to the count value update signal instructing to update the count value, the counter 121 updates the output count value cyclically from the initial value to the final value according to a certain rule. Then, when the counter 121 updates the count value to the final value, it outputs a notification signal to that effect to the CPU 106, and the CPU 106 responding to this notification signal changes the initial value. In this embodiment, every time the count value update signal is input, the counter 121 increments the count value from “1” to “4095” one by one, and when it counts up to “4095”, that fact Is sent to the CPU 106. Then, the CPU 106 responding to this notification signal changes the initial value, and the counter 121 counts up again from this changed initial value to “4095”.

  The count value permutation change circuit 123 includes a count value permutation change register (RCS) 133 that stores count value permutation change data “01h” for requesting a change in the permutation, which is the count value update order, and an update rule selection register (RRC). 141 and an update rule memory 142. When the numerical value permutation change data “01h” is stored in the count value permutation change register, the count value permutation change circuit 123 changes the permutation to be different from the permutation when the count value permutation change data “01h” is not stored. To do.

  FIG. 5 is a block diagram illustrating a configuration example of the update rule selection register 141. As shown in FIG. 5, the update rule selection register 141 is an 8-bit register, and its initial value is set to “0 (= 00h)”. The update rule selection register 141 is configured so that bits 0 to 3 can be written and read, and bits 4 to 7 cannot be written and read. Therefore, even if a value is written in bit 4 to bit 7 of the update rule selection register 141, the value is invalid, and all the values read from bit 4 to bit 7 are “0 (= 0000b)”.

  In response to the count value permutation change data “01h” being written in the count value permutation change register 133, the value (register value) of the update rule selection register 141 is changed from “0 (= 00h)” to “15 (= 0Fh) ”is updated cyclically. That is, each time the count value permutation data “01h” is written to the count value permutation change register 133, the register value is incremented from “0” by “1”, and when it becomes “15”, it returns to “0” again.

  FIG. 6 is a block diagram illustrating a configuration example of the update rule memory 142. As illustrated in FIG. 6, the update rule memory 142 stores the count value update rule and the value of the update rule selection register 141 in association with each other. In the update rule memory 142, the same update rule A as the update rule of the counter 121 is stored in correspondence with the register value “0”, and the update rules B to P different from the update rule of the counter 121 have the register value “1”. To "15".

  When the count value permutation change data “01h” is written in the count value permutation change register 133, the count value permutation change circuit 123 shown in FIG. 4 receives the final count value “4095” from the counter 121. Based on the updated register value, the update rule of the count value to be output is switched by selecting and setting the update rule from the update rule memory 142. In response to the input from the counter 121, the count value permutation changing circuit 123 updates and outputs the count value according to the switched update rule.

  In this way, the count value permutation changing circuit 123 switches the update rule in response to the count value permutation change data “01h” being written in the count value permutation change register 133, thereby outputting the permutation of the count values to be output. To change.

  FIG. 7 is an explanatory diagram of the operation of changing the count value permutation in the count value permutation changing circuit 123. As shown in FIG. 7, when the count value permutation change data “01h” is written to the count value permutation change register 133 at a predetermined timing by the CPU 106, the register value is incremented by 1, for example, from “0” to “1”. Updated. Thereafter, the count value permutation changing circuit 123 updates the count value according to the “update rule A” corresponding to the register value “0” before the update until the final value “4095” of the count value is input from the counter 121. Output. At this time, the permutation of count values output from the count value permutation changing circuit 123 is “1 → 2 →... → 4095”.

  When the final value “4095” of the count value is input from the counter 121, the count value permutation changing circuit 123 stores “update rule B” corresponding to the updated register value “1” from the update rule memory 142. Select and set. In response to the input from the counter 121, the count value permutation changing circuit 123 updates and outputs the count value according to the “update rule B” set and set. Thereby, the permutation of the count values output from the count value permutation changing circuit 123 is changed from “1 → 2 →... → 4095” to “4095 → 4094 →.

  Thereafter, the count value permutation change register 133 is initialized as will be described later, and the permutation of count values output from the count value permutation change circuit 123 remains “4095 → 4094 →... → 1”.

  When the count value permutation change data “01h” is written again to the count value permutation change register 133 by the CPU 106, the register value is updated from “1” to “2”. When the final count value “4095” is input from the counter 121, the count value permutation changing circuit 123 selects the “update rule C” corresponding to the register value “2” from the update rule memory 142. Set. In response to the input from the counter 121, the count value permutation changing circuit 123 updates and outputs the count values according to the “update rule C” selected and set, thereby further changing the permutation of the count values, "1 → 3 → ... → 4095 → 2 ... → 4094".

  As described above, after the count value permutation change register 133 is initialized, the count value permutation data “01h” is written again into the count value permutation change register 133, so that the permutation of the changed count value can be further changed. .

  FIG. 8 is a diagram illustrating a configuration example of the count value permutation change register 133. As shown in FIG. 8, the count value permutation change register 133 is a readable 8-bit register, and its initial value is set to “0 (= 00h)”. The count value permutation change register 133 is configured so that only bit 0 is writable and writable. Therefore, even if a value is written to bit 1 to bit 7, the value is invalid, and bit 1 to bit 7 All the values read from “0” are “0 (= 0000000b)”.

  In response to the count value permutation change circuit 123 starting the count value update operation in accordance with the switched update rule, the CPU 106 counts the count value permutation change register 133 in which the count value permutation change data “01h” is written. Is initialized and the stored value is returned to the initial value “0 (= 00h)”.

  The comparator 122 includes a random number maximum value setting register (RMX) 132 that stores random number maximum value setting data that specifies the maximum value of random R (random number maximum value). The comparator 122 regulates the update range of the count value by the counter 121 according to the random number maximum value setting data stored in the random number maximum value setting register 132. In this embodiment, the random number maximum value (for example, “255”) designated by the count value input from the counter 121 and the random number maximum value setting data (for example, “00FFh”) stored in the random number maximum value setting register 132. When the input count value is less than or equal to the random number maximum value, the input count value is output to the random value register 131. When the input count value is greater than the random number maximum value, the count value update signal is Output to the counter 121.

  FIG. 9 is an explanatory diagram of a count value update operation in the counter 121 and the comparator 122. FIG. 9 illustrates an example in which the update rule A is selected in the count value permutation changing circuit 123 and the maximum random number is set to “255”.

  When the input count value is “1” to “255”, the comparator 122 outputs the input count value to the random value register 131 as it is. When the input count value becomes a value “256” larger than the random number maximum value “255”, the comparator 122 outputs a count value update signal to the counter 121 to update the count value to “257”. By repeating such an operation, the comparator 122 continuously counts up the input count value from “256” to “4095” by the counter 121. When the counter 121 counts up to “4095”, it outputs a notification signal to that effect to the CPU 106.

  When the initial value changed by the CPU 106 in response to the notification signal is larger than the random number maximum value “255” (for example, “256”), the counter 121 outputs the count value of the changed initial value to the comparator 122. The comparator 122 outputs a count value update signal to the counter 121 to update the count value. By repeating such an operation, the comparator 122 causes the counter 121 to continuously count up the input count value to “4095” and cause the counter 121 to output a notification signal. Then, the initial value is further changed by the CPU 106 responding to the notification signal. In this way, the initial value is changed until it becomes a value equal to or less than the maximum random number. When the initial value changed by the CPU 106 in response to the notification signal is equal to or less than the random number maximum value “255” (for example, “15”), the counter 121 compares the count value of the changed initial value with a comparator. The comparator 122 outputs the input count value to the random value register 131 as it is.

  By the operation of the counter 121 and the comparator 122 described above, the random number circuit 103 outputs only the count value less than or equal to the random number maximum value stored in the random number maximum value setting register 132 to the random number value register 132, so that the random number circuit 103 It is possible to generate a random R with the maximum random number “255” stored in the value setting register 131 as an upper limit. Further, by changing the initial value until the initial value becomes equal to or smaller than the random number maximum value, a value equal to or smaller than the random number maximum value “255” is input to the random value register 131 as the changed initial value.

  FIG. 10 is a block diagram illustrating a configuration example of the random number maximum value setting register 132. As shown in FIG. 10, the random number maximum value setting register 132 is a 16-bit register, and its initial value is set to “4095 (= 0FFFh)”. The random number maximum value setting register 132 is configured such that bits 0 to 11 are writable and readable, and bits 12 to 15 are not writable and readable. Therefore, even if a value is written in bit 12 to bit 15 of the random number maximum value setting register 132, the value is invalid, and all the values read from bit 12 to bit 15 are “0 (= 0000b)”.

  When random number maximum value setting data “0000h” to “0003h” for designating a value smaller than the lower limit “4” is written in the random number maximum value setting register 132, the CPU 106 stores the random number maximum value setting register 132 in the random number maximum value setting register 132. The random number maximum value setting data “0FFFh” designating the initial value “4095” is stored. That is, the maximum random number value that can be set in the random number maximum value setting register 132 is from “4” to “4095”. The CPU 106 controls the random number maximum value setting register 132 in which the random number maximum value setting data is written to be unwritable until the game controller microprocessor 100 is system reset by the reset controller 102.

  The clock signal output circuit 124 shown in FIG. 4 stores cycle setting data that specifies the cycle of the clock signal that specifies the cycle of the clock signal output to the first and second selectors 128 and 129 (count value update cycle). A period setting register (RPS) 134 is provided. The clock signal output circuit 124 divides the reference clock signal input from the clock circuit 101 outside the random number circuit 103 based on the period setting data stored in the period setting register 134 and uses it within the random number circuit 103. A clock signal (internal clock signal) is generated, and the generated internal clock signal is output to the random value register 131.

  For example, when the cycle setting data written in the cycle setting register 134 is “0Fh (= 16)”, the clock signal output circuit 124 sets the internal clock signal by dividing the reference clock signal input from the clock circuit 101 by 16 minutes. Is generated. The cycle of the generated internal clock signal is “system clock signal cycle × 128 × 16”.

  FIG. 11 is a block diagram illustrating a configuration example of the period setting register 134. As shown in FIG. 11, the cycle setting register 134 is a writable and readable 8-bit register, and its initial value is set to “256 (= FFh)”.

  When the cycle setting data “00h to 06h” designating a value smaller than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 134, the CPU 106 stores the lower limit value in the cycle setting register 134. Cycle setting data “07h” for designating “cycle of system clock signal × 128 × 7” is stored. That is, the period that can be set in the period setting register 134 is from “system clock signal period × 128 × 7” to “system clock signal period × 128 × 256”. The CPU 106 controls the period setting register 134 in which the period setting data is written to be unwritable until the game controller microprocessor 100 is system-reset by the reset controller 102.

  The first trigger signal output circuit 125 shown in FIG. 4 includes a count value update register (RGN) 135 that stores count value update data “01h” for requesting update of the count value. The first trigger signal output circuit 125 outputs the first trigger signal to the first selector 128 in response to the count value update data “01h” being written in the count value update register 135.

  FIG. 12 is a block diagram illustrating a configuration example of the count value update register 135. As shown in FIG. 12, the count value update register 135 is an unreadable 8-bit register, and is configured so that only bit 0 is writable. Even if a value is written to bits 1 to 7, the value is invalid. is there.

  The second trigger signal output circuit 126 shown in FIG. 4 includes a count value capture register (RLT) 136 that stores count value capture data “01h” for requesting capture of a count value. The second trigger signal output circuit 126 outputs the second trigger signal to the second selector 129 in response to the count value fetch data “01h” being written in the count value fetch register 136.

  FIG. 13 is a block diagram illustrating a configuration example of the count value fetch register 136. As shown in FIG. 13, the count value fetch register 136 is an 8-bit register that cannot be read. Only the bit 0 is writable, and even if a value is written to the bits 1 to 7, the value is invalid. It is.

  The random number update method selection signal output circuit 127 shown in FIG. 4 is a random number update method selection data that designates a random number update method selected from the first and second random number update methods that are methods for updating the value of the random R. Is stored in a random number update method selection register (RTS) 137. The random number update method selection signal output circuit 127 responds to the writing of the random number update method selection data in the random number update method selection register 137 and corresponds to the random number update method specified by the written random number update method selection data. The random number update method selection signal to be output to the first and second selectors 128 and 129.

  FIG. 14A is a block diagram illustrating a configuration example of the random number update method selection register 137. As shown in FIG. 14A, the random number update method selection register 137 is an 8-bit register, and its initial value is set to “00h”. The random number update method selection register 137 is configured such that bits 0 to 1 are writable and readable, and bits 2 to 7 are not writable and readable. Therefore, even if a value is written in bits 2 to 7 of the random number update method selection register 137, the value is invalid, and all values read from bits 2 to 7 are “0 (= 000000b)”.

  FIG. 14B is an explanatory diagram of an example of random number update method selection data written to the random number update method selection register 137. As shown in FIG. 14B, the random number update method selection data is composed of 2-bit data, “01b” is data specifying the first random number update method, and “10b” is the second This data specifies the random number update method. When the random number update method selection data “00b” or “11b” is written in the random number update method selection register 137, the random number circuit 103 cannot be activated.

  The first selector 128 shown in FIG. 4 receives a random number update method selection signal (first random number update method selection signal) corresponding to the first random number update method from the random number update method selection signal output circuit 127. In response to the first trigger signal output from the first trigger signal output circuit 125, the count value update signal is output to the counter 121. On the other hand, when the first selector 128 receives a random number update method selection signal (second random number update method selection signal) corresponding to the second random number update method from the random number update method selection signal output circuit 127, the clock signal In response to the internal clock signal output from the output circuit 124, the count value update signal is output to the counter 121.

  When the first random number update method selection signal output circuit 127 receives the first random number update method selection signal output circuit 127, the second selector 129 outputs the count value in response to the internal clock signal output from the clock signal output circuit 124. A count value acquisition signal instructing acquisition is output to the random value register 131. On the other hand, the second selector 129 counts in response to the internal clock signal output from the clock signal output circuit 124 when the second random number update method selection signal output circuit 127 receives the second random number update method selection signal. The value fetch signal is output to the random value register 131.

  The random value register 131 stores a random R value extracted in a winning process in step S122 described later. In response to the count value fetch signal output from the second selector 129, the random value register 131 stores the count value output from the counter 121 via the comparator 122 as a random R value. Update the value of random R.

  FIG. 15 is a block diagram illustrating a configuration example of the random value register 131. As shown in FIG. 15, the random value register 131 is a non-writable 16-bit register, and its initial value is set to “0001h”. The random value register 131 is configured such that bits 0 to 11 can be read and bits 12 to 15 cannot be read. Therefore, all the values read from bit 12 to bit 15 of the random value register 131 are “0 (= 0000b)”.

  The random number circuit activation signal output circuit 130 shown in FIG. 4 includes a random number circuit activation register (RST) 140 that stores random number circuit activation data “80h” for requesting activation of the random number circuit 103. The random number circuit start signal output circuit 130 outputs a predetermined random number circuit start signal in response to the random number circuit start data “80h” being written in the random number circuit start register 140, and the counter 121 and the clock signal output circuit 124. And the random number circuit 103 is activated by starting the update operation of the count value by the counter 121 and the output operation of the internal clock signal by the clock signal output circuit 124.

  FIG. 16 is a block diagram illustrating a configuration example of the random number circuit activation register 140. As shown in FIG. 16, the random number circuit activation register 140 is an 8-bit register, and its initial value is set to “00h”. The random number circuit activation register 140 is configured so that only bit 7 can be read and read, and even if a value is written in bits 0 to 6, the value is invalid, and all the values read from bit 0 to bit 6 are “ 0 (= 0000b) ".

  FIG. 17 is a diagram showing an example of an address map in the gaming control microprocessor 100 shown in FIG. As shown in FIG. 17, the area from address 0000h to 1FFFh is allocated to the ROM 104, the area from address 7E00h to 7FFFh is allocated to the RAM 105, and the area from address FD00h to address FE00h is the random number maximum value setting register 132. Assigned to the internal register.

  A program (user program) 150 created in advance by the user is stored in the user program area in the area from 0000h to 1F7Fh in the ROM 104, and the CPU 106 is used by the user in the user program management area in the area from 1F80h to 1FFFh. Data necessary for executing the program 150 (user program execution data) is stored. Further, the area from 7E00h to 7EFFh in the RAM 105 is not used, and the 7EFFh to 7FFFh addresses are used as work areas.

  FIG. 18 is a diagram showing an example of an address map in the user program execution data area shown in FIG. As shown in FIG. 18, in the area of address 1F97h, an initial value changing method selected by the user from the first, second, and third initial value changing methods that are methods for changing the initial value is specified. Value change method setting data is stored. In the area of address 1F98h, RAM address data for specifying an address in RAM 105 (designated RAM address) designated in advance by the user from among addresses 7EFFh to 7FFFh assigned to RAM 105 is stored as a lower value. . In the area of address 1F99h, the RAM address data at the address next to the designated RAM address is stored as a higher value.

  FIG. 19 is an explanatory diagram of an example of initial value change method setting data selected by the user. As shown in FIG. 19, the initial value change data is composed of 8-bit data, “00h” is data specifying that the initial value is not changed, and “01h” is the first initial value change data. This data specifies the method. “02h” is data specifying the second initial value changing method, and “03h” is data specifying the third initial value changing method.

  FIG. 20 is a diagram illustrating a configuration example of the user program 150. In this embodiment, as shown in FIG. 20, the user program 150 includes a random number circuit setting program 151 composed of a plurality of types of program modules, a display result determination program 152, an initial value change program 153, a count value, And a permutation change register 154.

  The random number circuit setting program 151 is a program for executing a random number circuit setting process for setting the random number circuit 103 to update the random R value. The CPU 106 executes the random number circuit setting program 151 by executing the random number circuit setting program 151. , Function as random number circuit setting means.

  FIG. 21 is a diagram illustrating a configuration example of the random number circuit setting program 151. As shown in FIG. 21, the random number circuit setting program 151 includes a random number maximum value setting module 151a, a random number update method selection module 151b, a cycle setting module 151c, and a random number circuit activation module 151d as the above-described plural types of program modules. And.

  The random number maximum value setting module 151 a is a program module for setting a random R maximum value preset by the user in the random number circuit 103. The CPU 106 executes the random number maximum value setting module 151a and writes the random number maximum value setting data designating the maximum value of the random R preset by the user, thereby obtaining the preset maximum value of the random R. The random number circuit 103 is set. For example, when the maximum value of the random R preset by the user is “255”, the CPU 106 writes the random number maximum value setting data “00FFh” in the random number maximum value setting register 132 and the random R maximum value “255”. Is set in the random number circuit 103.

  The random number update method selection module 151 b is a program module for setting a random number update method selected by the user from the first and second random number update methods in the random number circuit 103. The CPU 106 executes the random number update method selection module 151b and writes the random number update method selection data “01b” or “10b” for designating the random number update method selected by the user into the random number update method selection register 137. The selected random number update method is set in the random number circuit 103. Accordingly, the game control microprocessor 100 can exhibit a function of selecting a random number update method set in the random number circuit 103 from the first and second random number update methods. In this embodiment, the CPU 106 writes the random number update method selection data “10b” in the random number update method selection register 137 and sets the second random number update method in the random number circuit 103.

  The cycle setting module 151 c is a program module for setting the cycle of the internal clock signal preset by the user in the random number circuit 103. The CPU 106 executes the cycle setting module 151c and writes cycle setting data for specifying the cycle of the internal clock signal preset by the user in the cycle setting register 134, whereby the cycle of the preset internal clock signal is set. Is set in the random number circuit 103. For example, when the period of the internal clock signal preset by the user is “system clock signal period × 128 × 16”, the CPU 106 writes the period setting data “0Fh” in the period setting register 134 to The cycle “cycle of system clock signal × 128 × 16” is set in the random number circuit 103.

  The random number circuit activation module 151 d is a program module for activating the random number circuit 103. The CPU 106 activates the random number circuit 103 by executing the random number circuit activation module 151 d and writing the random number circuit activation data “80h” in the random number circuit activation register 140.

  The random value update program 155 is a program for updating the value of the random R stored in the random value register 131 when the first random number update method is selected. The CPU 106 functions as a random value updating unit by executing the random value updating program 155. The CPU 106 executes the random value update program 155 and writes the count value update data “01h” to the count value update register 135 to update the random R value stored in the random value register 131.

  The display result determination program 152 is a program for determining whether or not the display result in the special figure game is a big hit, and the CPU 106 functions as a display result determination means by executing the display result determination program 152. To do.

  In response to the fact that the game ball wins the normal variable winning ball device 6 and the condition (execution condition) for executing the variable display (special game) of the special symbol is established, the display result determination program 152 Is executed to read out the updated random R value from the random value register 131 and determine whether or not the display result of the special figure game by the variable display device 4 is a big hit.

  FIG. 22 is an explanatory diagram of a random R value update operation and a read operation by the CPU 106 when the first random number update method is selected. As shown in FIG. 22, when the first random number update method is selected, the CPU 106 writes the count value update data “01h” into the count value update register 135, thereby storing the random number stored in the random value register 131. The value of R (for example, “2”) is updated. Then, in response to the fact that the game ball has won the normal variable winning ball device 6 and the condition (execution condition) for executing the variable symbol display (special game) is established, the random number value register 131 is set. The value of random R (for example, “2”) is read out. When the value of the random R stored in the random value register 131 is further updated, an interval equal to or longer than the period of the system clock signal output by the clock circuit 101 from the time when the value of the previous random R is updated, The count value update data “01h” must be written to the count value update register 135. This is to secure time for reading the updated random R value from the random value register 131.

  FIG. 23 is an explanatory diagram of a random R value update operation and a read operation performed by the CPU 106 when the second random number update method is selected. As shown in FIG. 23, when the second random number update method is selected, the CPU 106 writes the count value take-in command “01h” into the count value take-in register 136, thereby outputting the count output from the counter 121. A value (for example, “2”) is taken into the random value register 131 and the value of the random R stored in the random value register 131 is updated. Then, the updated random R value (for example, “2”) is read from the random value register 131.

  If the CPU 106 does not write the count value capture command “01h” in the count value capture register 136, the random number value stored in the random value register 131 is updated even if the count value output from the counter 121 is updated. Will not be updated. For example, the CPU 106 writes the count value capture command “01h” into the count value capture register 136, captures the count value “3” output from the counter 121 into the random value register 131, and stores it in the random value register 131. When the random R value “3” is updated, the CPU 106 does not write the count value capture command “01h” in the count value capture register 136 after that, the count value output from the counter 121 is “3”. Even if it is updated from “4” or “5”, the random value stored in the random value register 131 is not updated, and the random value read from the random value register 131 remains “3”.

  The initial value changing program 153 shown in FIG. 20 is a program for changing the initial value of the count value updated by the counter 121, and the CPU 106 executes the initial value changing program 153 to thereby change the initial value changing means. Function as. The CPU 106 executes the initial value change program 153, and uses the initial value change method selected by the user from the first, second, and third initial value change methods to initialize the count value updated by the counter 121. Change the value. Thereby, the microprocessor 100 for game control can exhibit the function which selects the system which changes an initial value from the 1st, 2nd and 3rd initial value change system.

  More specifically, when initial value change method setting data “01h” for specifying the first initial value change method is stored in the area of address 1F97h in the user program execution data area shown in FIG. The initial value is changed to a value set on the basis of an ID (Identification) number unique to the game control microprocessor 100.

  When initial value change method setting data “02h” for designating the second initial value change method is stored in the area of the user program execution data area at address 1F97h, the CPU 106 addresses address 1F97h in the user program execution data area. The designated RAM address is specified from the address data stored in the area, the value stored in the area of the specified designated RAM address is read, and the initial value is changed to the read value.

  When initial value change method setting data “03h” for designating the third initial value change method is stored in the area of address 1F97h in the user program execution data area, the CPU 106 stores the values stored in the respective addresses of the RAM 105. And the read value is added. Then, the CPU 106 changes the initial value to this added value.

  The count value permutation change program 154 writes the count value permutation change data “01h” in the count value permutation change register 133 and executes a count value permutation change process for changing the permutation of the count values stored in the random value register 131. The CPU 106 functions as numerical data permutation changing means by executing the count value permutation changing program 154. The CPU 106 executes the count value permutation update program 154 and writes the count value permutation change data “01h” in the count value permutation change register 133, so that it is output from the count value permutation change circuit 123 and stored in the random value register 131. Change the permutation of input count values.

  Further, as shown in FIG. 24, the gaming control microprocessor 100 shown in FIG. 3 includes a special figure holding memory 170, a jackpot determination table memory 171 and a flag memory 172.

  In the special figure holding memory 170, the condition (execution condition) for executing the variable display (special game) of the special symbol when the game ball wins the normal variable winning ball apparatus 6 is established, but the previous variable display is displayed. This is a memory for storing a pending state in which a condition (start condition) for actually starting variable display is not satisfied due to reasons such as being executed. The special figure holding memory 170 includes four entries, and each entry has a holding number and a random R value read from the random number register 131 in accordance with the winning order in the order of winning in the normal variable winning ball apparatus 6. Are stored in association with each other. Each time the special symbol determination command is sent from the main board 11 to the display control board 12 and the variable symbol special display is ended once or the big hit gaming state is ended, the variable display based on the highest level information is performed. The start condition is satisfied, and variable display based on the highest level information is executed. At this time, the second and lower registration information is moved up by one place. Further, when a game ball newly wins the normal variable winning ball apparatus 6 during variable display of a special symbol or the like, the random R value read from the random value register 131 based on the winning is the highest empty. Registered in the entry.

  The jackpot determination table memory 171 shown in FIG. 24 stores a plurality of jackpot determination tables set for the CPU 106 to determine whether or not the display result in the special figure game is a jackpot. Specifically, the jackpot determination table memory 171 stores a normal jackpot determination table 171a shown in FIG. 25A and a probability change jackpot determination table 171b shown in FIG. 25B.

  The normal big hit determination table 171a shown in FIG. 25 (A) and the probability variation big hit determination table 171b shown in FIG. 25 (B) indicate whether or not the display result of the special figure game by the variable display device 4 is a big hit. It is a table for judging. In each jackpot determination table 171a, 171b, the value of random R and setting data indicating the display result of the special figure game are stored in association with each other. In the probability change big hit determination table 171b, more random R values are associated with the display result of “big hit” than in the normal time big hit determination table 171a. That is, by determining the display result of the special figure game using the probability change jackpot determination table 171b, it is possible to achieve a probability improvement state in which the probability of becoming a jackpot gaming state is higher than that in the normal gaming state.

  In the flag memory 172 shown in FIG. 24, various flags used for controlling the progress of the game in the pachinko gaming machine 1 are set. For example, the flag memory 172 is provided with a special symbol process flag, a normal symbol process flag, a big hit state flag, an input state flag, a timer interrupt flag, an initial value change flag, and the like.

  The special symbol process flag indicates which processing should be selected and executed in the special symbol process (described later) (FIG. 30). The normal symbol process flag indicates which process should be selected and executed in a predetermined normal symbol process in order to control the display state of the normal symbol display 40 in a predetermined order. The big hit state flag is set to the on state when the display result of the special figure game by the variable display device 4 is a big hit, and is cleared to the off state when the big hit gaming state is finished.

  The input state flag is a flag composed of a plurality of bits that are set or cleared in accordance with the state of various signals input to the I / O port 108, the state of the detection signal input from each winning prize switch 70, and the like. The timer interrupt flag is set to the on state every time a predetermined time elapses and a timer interrupt is generated. The initial value change flag is set to an on state in response to the notification signal output from the random number circuit 103, and is cleared to an off state when the initial value is changed.

  The switch circuit 109 shown in FIG. 3 takes in the detection signal from each winning opening switch 70 and transmits it to the game control microprocessor 100. The solenoid circuit 110 drives the solenoids 21 and 22 in accordance with a command from the game control microprocessor 100. The solenoid 21 is connected to the movable wing piece of the normally variable winning ball apparatus 6 through a link mechanism. The solenoid 22 is connected to the opening / closing plate of the special variable winning ball apparatus 7 through a link mechanism.

  The display control board 12 is for performing effect control according to the control command received from the main board 11. Specifically, the display control board 12 performs display control of the variable display device 4 and lighting control of the game effect lamp 9 and the normal symbol display 40.

  The audio control board 13 and the lamp control board 14 are sub-side control boards that execute audio output control and lamp output control independently of the main board 11 based on control commands transmitted from the main board 11. is there. The payout control board 15 performs payout control for game balls, prize balls, and the like. The information terminal board 16 is for outputting various game-related information to the outside.

  FIG. 26 is a flowchart of the game control main process executed by the CPU 106 in the game control microprocessor 100. When the power to the pachinko gaming machine 1 is turned on, the game control main process is started. First, the CPU 106 sets the interrupt prohibition (step S1), and then sets the interrupt mode to mode 2 (step S1). S2).

  Thereafter, the CPU 106 sets a stack pointer designation address in the stack pointer (step S3). Then, a register setting such as CTC 107 which is a built-in device of the main board 11 of the game control microprocessor 100 is performed (step S4). For example, an interrupt vector is set for the CTC 107.

  Subsequent to step S4, the CPU 106 checks, for example, a backup flag area provided in the RAM 105 (step S5), and all or part of the RAM 105 is backed up by a predetermined data protection process when the power is last turned off. It is determined whether or not (step S6). In the pachinko gaming machine 1, when an unexpected power failure occurs, a data protection process for protecting all or a part of the data stored in the RAM 105 is performed. If such data protection processing has been performed, it is determined that there is a backup.

  When it is determined in step S6 that there is a backup (step S6; Yes), the CPU 106 performs a parity check as a backup data check, and determines whether the check result is normal (step S7). If the check result is normal (step S7; Yes), the internal state of the main board 11 and the control boards on the sub side (display control board 12, voice control board 13, lamp control board 14, and payout control board 15). A game state restoration process for returning the control state to the state at the time of power-off is executed (step S8). Then, it progresses to step S10.

  When it is determined in step S6 that there is no backup (step S6; No), or when the check result is not normal in step S7 (step S7; No), the CPU 106 clears the RAM 105 or performs a predetermined work area. Initialization processing such as initial setting is performed (step S9).

  Subsequently, the CPU 106 executes the random number circuit setting program 151 to perform random number circuit setting processing (step S10). In this random number circuit setting process, a setting for causing the random number circuit 103 to update the value of the random R is performed.

  FIG. 27 is a flowchart showing the random number circuit setting process in step S10. In this random number circuit setting process, the CPU 106 first executes a random number maximum value setting module 151a included in the random number circuit setting program 151, and sets random number maximum value setting data for specifying a random number maximum value preset by the user as a random number. By writing in the maximum value setting register 132, the preset maximum value of the random R is set in the random number circuit 103 (step S21).

  Next, the CPU 106 executes the random number update method selection module 151b included in the random number circuit setting program 151 and writes the random number update method selection data “10b” to the random number update method selection register 137, thereby performing the second random number update. The method is set in the random number circuit 103 (step S22).

  Subsequently, the CPU 106 executes the period setting module 151c included in the random number circuit setting program 151, and writes period setting data specifying the period of the internal clock signal preset by the user in the period setting register 134. The preset period of the internal clock signal is set in the random number circuit 103 (step S23).

  Thereafter, the CPU 106 executes the random number circuit activation module 151d included in the random number circuit setting program 151 and writes the random number circuit activation data “80h” to the random number circuit activation register 140, thereby activating the random number circuit 103 (step S24).

  Following the random number circuit setting process in step S10, the CPU 106 performs setting for timer interruption by the CTC 107 (step S11). Specifically, the timer mode is set by giving interrupt permission to one of a plurality of channels included in the CTC 107 (specifically, the third channel from the 0th channel to the third channel) of the CTC 107. And specify the initial count value for the channel. Thereby, thereafter, an interrupt request signal is sent from the CTC 107 to the CPU 106 every predetermined time (for example, 2 milliseconds), and the CPU 106 can periodically execute a timer interrupt process.

  Thereafter, the CPU 106 proceeds to a loop process for monitoring whether or not a timer interrupt has occurred due to an interrupt request signal from the CTC 107. In this loop process, after setting the interrupt prohibition (step S12), the display random number update process (step S13) is executed, and when the display random number update process is completed, the interrupt permission is set (step S14).

  When the CPU 106 that has executed the game control main process shown in FIG. 26 receives the interrupt request signal from the CTC 107 and receives the interrupt request, the CPU 106 starts executing the game control interrupt process shown in FIG.

  When the game control interrupt process is started, the CPU 106 executes a predetermined power-off process, thereby making it possible to execute a predetermined data protection process or the like when the power supplied from the power supply board 10 is reduced (step) S101). Subsequently, by executing a predetermined switch process, the state of the detection signal input from each winning port switch 70 is determined (step S102).

  Next, the CPU 106 executes a display random number update process (step S103). Subsequently, the CPU 106 executes the initial value change program 153 to perform an initial value change process (step S104).

  FIG. 29 is a flowchart showing the initial value changing process in step S104. In this initial value change process, the CPU 106 first checks an initial value change flag provided in the flag memory 172 to determine whether or not a notification signal is output from the random number circuit 103 (step S171). When the initial value flag is in the off state (step S171; No), it is determined that the count value of the counter 121 has not been counted up to the final value, and the initial value changing process is terminated. On the other hand, if the initial value flag is on (step S171; Yes), the initial value change method setting data stored in the area 1F97h in the user program execution data area is read and the initial value change selected by the user is read. A method is specified (steps S172, S173, and S174).

  When initial value change method setting data “01h” for designating the first initial value change method is stored (step S172; Yes), the CPU 106 sets the initial value as an ID (Identification) unique to the game control microprocessor 100. The value is changed to a value set based on the number (step S175).

  When initial value change method setting data “02h” for designating the second initial value change method is stored (step S172; No, step S173; Yes), the CPU 106 stores the area 1F97h in the user program execution data area. The specified RAM address is specified from the RAM address data stored in the memory, and the value stored in the area of the specified specified RAM address is read (step S176). Then, the CPU 106 changes the initial value to the read value (step S177).

  When the initial value change method setting data “03h” for designating the third initial value change method is stored (step S172; No, step S173; No, step S174; Yes), the CPU 106 at each address of the RAM 105. The stored value is read (step S178), and the read value is added (step S179). Then, the CPU 106 changes the initial value to this added value (step S180).

  If it is determined No in step S172, step S173, and step S174, the initial value change method setting data stored in the area 1F97h in the user program execution data area is determined as “00h”, and the initial value is set. Without changing, the process proceeds to step S181.

  Thereafter, the CPU 106 clears the initial value change flag to turn it off (step S181), and ends the initial value change process.

  Subsequently, the CPU 106 executes the count value permutation change program 154 to perform a count value permutation change process (step S105). In this count value permutation update process, the CPU 106 changes the permutation of the count values input to the random value register 131 by writing the count value permutation change data “01h” into the count value permutation change register 133.

  Subsequently, the CPU 106 executes special symbol process processing (step S106). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 106 executes normal symbol process processing (step S107). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the normal symbol display 40 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state. Further, the special symbol command control process (step S108) and the normal symbol command control process (step S109) are sequentially executed. Thus, the CPU 106 sends a display control command from the main board 11 to the display control board 12 to instruct display control of the variable display device 4 and lighting control of the normal symbol display 40.

  Subsequently, the CPU 106 executes predetermined information output processing to output various output data to each output port included in the I / O port 108 (step S110). In this information output process, a command for outputting jackpot information, starting information, probability variable information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16.

  Further, the CPU 106 executes predetermined prize ball processing to set the number of prize balls based on the detection signal input from each winning opening switch 70 and outputs a payout control command to the payout control board 15. It is possible (step S111). Further, the CPU 106 performs a predetermined solenoid output process to open and close the movable wing piece in the normal variable winning ball device 6 and the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied ( Step S112).

  FIG. 30 is a flowchart showing the special symbol process executed in step S106. When the special symbol process is started, the CPU 106 first executes the display result determination program 152 to determine whether or not the game ball has won the normal variable winning ball apparatus 6 and is included in each winning opening switch 70. A determination is made by checking a detection signal input from the detection switch, an input state flag provided in the flag memory 172, and the like (step S121). When the game ball is won and the detection signal from the start ball detection switch is turned on (step S121; Yes), the winning process is executed (step S122), and when the game ball is not won (step S121; No), the winning process is skipped.

  FIG. 31 is a flowchart showing the winning process in step S122. In this winning process, the CPU 106 first determines whether or not the starting winning memory number stored in the special figure reservation memory 170 is the maximum value “4” (step S141). Here, when the value of random R corresponding to the start winning memory number “4” is stored in the special figure holding memory 170, it is determined that the start winning memory number is “4”.

  When the start winning memory number is “4” (step S141; Yes), the start detection by the current winning is invalidated and the winning process is ended as it is. On the other hand, when the start winning memorized number is less than “4” (step S141; No), the count value fetch data “01h” is written in the count value fetch register 136 and stored in the random value register 131. The value of R is updated (step S142).

  Subsequently, the CPU 106 reads the updated random R value from the random value register 131 (step S143), and stores the read random R value in a predetermined buffer area provided in the RAM 105, for example ( In step S144), “1” is added to the start winning memorized number (step S145). Then, the CPU 106 sets the random R value stored in the predetermined buffer area at the head of the empty entry in the special figure reservation memory 170 (step S146).

  Thereafter, the CPU 106 selects one of the nine processes of steps S130 to S138 shown in FIG. 30 based on the value of the special symbol process flag stored in the flag memory 172. Below, each process of step S130-S138 is demonstrated.

  The special symbol normal process of step S130 is a process executed when the value of the special symbol process flag is the initial value “0”. In this process, the CPU 106 determines whether or not the number of reserved memories stored in the special figure reservation memory 170 is “0”. Here, in the special figure hold memory 170, when various data such as the value of the random R1 corresponding to the hold number “1” is not stored, it is determined that the hold storage number is “0”. If the reserved storage number is “0”, the special symbol normal process is terminated by displaying a demonstration screen on the variable display device 4 via the display control board 12. On the other hand, if it is determined that the number of reserved memories is not “0”, the value of the special symbol process flag is updated to “1” which is a value corresponding to the big hit determination process.

  The jackpot determination process in step S131 is a process executed when the value of the special symbol process flag is “1”. In this process, as shown in FIG. 32, the CPU 106 first reads the random R value stored in correspondence with the hold number “1” from the special figure hold memory 170 (step S151). At this time, 1 is subtracted from the reserved storage number, and the value of the random R stored in the second to fourth entries (holding numbers “2” to “4”) of the special figure holding memory 170 is increased by one entry. Shift (step S152).

  Subsequently, the CPU 106 determines whether or not the probability improvement state (probability change is in progress) (step S153). If the probability change is not in progress (step S153; No), the CPU 106 determines that the game is in the normal game state and the special game. As a table for determining whether or not the display result is a big hit, a normal big hit determination table 171a as shown in FIG. 25A is set (step S154). On the other hand, if the probability change is in progress (step S153; Yes), a probability change big hit determination table 171b as shown in FIG. 25B is set (step S155).

  Based on the random R value read in step S151, the CPU 106 determines whether or not to display the special game display result as a big hit using the big hit determination table 171a or 171b set in step S154 or S155 ( Step S156). If it is decided to win the game (step S156; Yes), the big game status flag provided in the flag memory 172 is set to the on state (step S157), and if it is decided to be lost. (Step S156; No), the big hit state flag is cleared and turned off (Step S158). Thereafter, the value of the special symbol process flag is updated to “2” which is a value corresponding to the fixed symbol determination process (step S159).

  The confirmed symbol determination process in step S132 shown in FIG. 30 is a process executed when the value of the special symbol process flag is “2”. In this processing, the CPU 106 determines whether or not the big hit state flag provided in the flag memory 172 is on, and determines whether or not to reach based on the result of extracting a predetermined reach determination random number or the like. Is determined. According to these determination results, a final fixed symbol in the special figure game by the variable display device 4 is set. Thereafter, the value of the special symbol process flag is updated to “3” which is a value corresponding to the variable display pattern setting process.

  The variable display pattern setting process of step S133 is a process executed when the value of the special symbol process flag is “3”. In this process, the CPU 106 first determines whether or not the big hit state flag provided in the flag memory 172 is turned on, and whether or not it is determined to reach in the determined symbol determination process in step S132 above. Is determined, and a predetermined variable display pattern table is set according to these determination results. Then, based on the result of extracting the predetermined variable display pattern determination random number, etc., the variable display pattern to be used in this special figure game is determined from the set variable display pattern table. After determining the variable display pattern in this way, the CPU 106 updates the value of the special symbol process flag to “4”, which is a value corresponding to the variable display command process.

  The variable display command process in step S134 is a process executed when the value of the special symbol process flag is “4”. In this process, the CPU 106 controls the variable display device 4 so that all the special symbols start variable display. Specifically, control data corresponding to the fixed symbol of the special symbol determined in the fixed symbol determination process in step S132 described above, or control data corresponding to the variable display pattern determined in the variable display pattern setting process in step S133 Is set in a predetermined command transmission table so that the variable display start command and the left / middle / right symbol designation command can be sent to the display control board 12. Then, the total variable display time corresponding to the variable display pattern is set in a predetermined variable display time timer, a variable display start command is transmitted, and countdown is started. Thereafter, when the predetermined variable display time timer times out, the value of the special symbol process flag is updated to “5” which is a value corresponding to the variable display stop process.

  The variable display stop process in step S135 is a process executed when the value of the special symbol process flag is “5”. In this process, the CPU 106 performs settings for sending a special symbol confirmation command from the main board 11 to the display control board 12. Specifically, the special symbol confirmation command is set to be sent to the display control board 12 by setting control data corresponding to the special symbol confirmation command in a predetermined command transmission table. Further, when the pachinko gaming machine 1 is in the probability improved state, it is determined whether or not to return from the probability improved state to the normal gaming state. Transition to the gaming state. When the display result of variable display is a big hit, the value of the special symbol process flag is updated to “6” which is a value corresponding to the pre-opening process for the big prize opening. Update the value to “0”.

  The pre-opening process for the special winning opening in step S136 is a process executed when the value of the special symbol process flag is “6”. In this process, the CPU 106 performs setting for starting control for opening the special variable winning ball apparatus 7 as a big winning opening. Then, the control for opening the special variable winning ball apparatus 7 is started, and the value of the special symbol process flag is updated to “7” which is a value corresponding to the large winning opening opening process.

  The special winning opening opening process in step S137 is a process executed when the value of the special symbol process flag is “7”. In this processing, the CPU 106 detects the winning of the game ball to the opened special variable winning ball device 7, sets the display control command for the winning ball payout command, the measurement of the opening time, and the round number of the opening cycle. I do. For example, the number of opening of the special variable winning ball apparatus 7 is counted for one big hit, and if the number of opening reaches 16 times, the condition for ending the specific gaming state (big hit gaming state) is finished. As a result, the value of the special symbol process flag is updated to “8” which is a value corresponding to the big hit end process. On the other hand, if the number of opening times has not reached 16, the special variable winning ball apparatus 7 is once closed and then opened again after a predetermined time has elapsed.

  The jackpot end process in step S138 is a process executed when the value of the special symbol process flag is “8”. In this process, the CPU 106 ends the jackpot gaming state by making settings for sending a predetermined jackpot end command to the display control board 12. Further, the CPU 106 clears the big hit state flag provided in the flag memory 172 and sets it to the off state. Then, the value of the special symbol process flag is updated to “0”.

  As described above, according to this embodiment, after the power is turned on to the pachinko gaming machine 1 and the game control main process is started, the CPU 106 permits the execution of the timer interrupt process to execute the loop process. Before the transition, since the random number circuit setting program 151 is executed to perform the random number circuit setting process, it is necessary to start / end the random number generation process within a limited interrupt processing time (for example, 2 milliseconds). Thus, an increase in processing load on the game control microprocessor 100 can be prevented.

  Preferably, the random number circuit setting process permits the execution of the timer interrupt process after the execution of the game state restoration process or the initialization process such as clearing the RAM 105 or initial setting for a predetermined work area. Therefore, it is desirable to execute this before moving to the loop processing.

  Further, since the CPU 106 determines whether or not the display result in the special game is a big hit using the random R generated by the random number circuit 103, the capacity of the program stored in the ROM 104 or the like can be reduced.

  Furthermore, since the value of the random R is updated by the random number circuit 103, the capacity of the program stored in the ROM 104 or the like can be reduced as compared with that updated by software.

  Moreover, since the value of the random R stored in the random value register 131 can be updated according to the setting made by executing the random number circuit setting program 151, by performing different settings for each pachinko gaming machine 1 The randomness of the random R read from the random value register 131 and used to determine whether or not the display result in the special game is a big hit can be improved.

  More specifically, the CPU 106 executes the random number maximum value setting module 151a, the random number update method selection module 151b, and the period setting module 151c included in the random number circuit setting program 151, and the user appropriately sets for each pachinko gaming machine 1. The maximum value of random R, the random number update method, and the cycle of the internal clock signal are set in the random number circuit 103, and then the random number circuit activation module 151d is executed to activate the random number circuit 103. In this way, by updating the random R value stored in the random value register 131 in accordance with the maximum value of the random R, the random number update method, and the period of the internal clock signal set in the random number circuit 103, the random value register It is possible to improve the randomness of the random R that is read from 131 and used to determine whether or not the display result in the special figure game is a big hit.

  Furthermore, by executing the count value permutation change program 154 to change the permutation that is the update order of the count values, the randomness of the count values input to the random value register 131 is increased. It is possible to improve the randomness of the random R that is issued and used to determine whether or not the display result in the special figure game is a big hit.

  Further, in response to the count value permutation change circuit 123 starting the count value update operation in accordance with the switched update rule, the CPU 106 counts the count value permutation change register 133 in which the count value permutation change data “01h” is written. Can be prevented from being continuously changed in the permutation of the count values output from the count value permutation changing circuit 123 and input to the random value register 131.

  Furthermore, after the count value permutation change register 133 is initialized, the CPU 106 can further change the permutation of the changed count value by rewriting the count value permutation data “01h” in the count value permutation register 133. .

  Further, by changing the initial value of the count value updated by the counter 121, it is possible to make it difficult to detect the cycle in which the count value is counted up from the initial value to the final value. Thereby, it is possible to prevent a fraudulent act such as outputting a predetermined signal aiming at a timing when the value of the random R read from the random value register 131 in step S143 coincides with the jackpot determination value and causing frequent jackpots. .

  Further, the CPU 106 writes the random number maximum value setting register 132 in which the random number maximum value setting data is written, the cycle setting register 134 in which the cycle setting data is written, and the random number update method selection data until the system is reset by the reset controller 102. The random number update method selection register 137 is controlled to be unwritable so that the random number maximum value, the period of the internal clock signal, and the random number update method set in the random number circuit 103 cannot be changed. As a result, the malicious player can freely set the timing at which the random R value read from the random value register 131 matches the jackpot determination value by changing the random number maximum value, the period of the internal clock signal, and the random number update method. , Fraudulent acts such as frequent hits can be prevented.

  In addition, in order to change the initial value of the count value by the initial value changing method appropriately selected for each pachinko gaming machine 1 by the user, whether or not the display result in the special game is read out from the random value register 131 The randomness of the random R used for determining can be improved.

  Further, when random number maximum value setting data “0000h” to “0003h” for designating a value lower than the lower limit value “4” is written in the random number maximum value setting register 132, the CPU 106 stores the random number maximum value setting register 132 in this random number maximum value setting register 132. Since “0FFFh” is stored, a value of “4” or less can be prevented from being set in the random number circuit 103 as the maximum random number.

  When the initial value changed by the CPU 106 is larger than the random number maximum value, the comparator 122 sequentially outputs a count value update signal and continuously outputs the count value to the counter 121 from the changed initial value to the final value. The updated initial value can be further changed by the CPU 106 by outputting the notification signal. Thereby, it is possible to prevent the count value output to the random value register 131 from becoming larger than the maximum random number.

  Further, when a cycle setting command “00h” to “06h” for designating a value equal to or lower than the lower limit value “system clock signal cycle × 128 × 7” is written in the cycle setting register 134, the CPU 106 determines the maximum random number value. Since “07h” is stored in the setting register 132, a value smaller than “system clock signal cycle × 128 × 7” can be prevented from being set in the random number circuit 103 as the cycle of the internal clock signal.

  In addition, the CPU 106 sets the maximum random number value, the random number update method, and the cycle of the internal clock signal in the random number circuit 103, and then starts the random number circuit 103. It is possible to prevent a problem that a random number is generated from the random number circuit 103 before setting the cycle of the internal clock signal.

  When the system is reset by the reset controller 102, the random number circuit activation data “80h” is written in the random number circuit activation register 140 so that the random number circuit 103 can be activated again.

  Furthermore, since the random number circuit 103 is built in the game control microprocessor 100, a space for the main board 11 can be secured, and counterfeiting such as installation of an illegal base can be made difficult.

  Also, the timing for updating the random R value stored in the random value register 131, that is, the timing when the CPU 106 writes the count value update data “01h” into the count value update register 135, or the count value fetch register 136 counts. By designating in advance the timing for writing the value fetch data “01h”, it is possible to prevent the random R value that has not been updated from being read from the random value register 131.

  However, in this case, the count value update data “01h” is written in the count value update register 135 at an interval equal to or longer than the period of the system clock signal output by the clock circuit 101 from when the previous random R value was updated. There is a need. This is to ensure time for the CPU 106 to read the updated random R value from the random value register 131.

  In addition, this invention is not restricted to said embodiment, A various deformation | transformation and application are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

  In the above embodiment, the second random number update method has been selected by the user. However, the present invention is not limited to this, and the first random number update method may be selected. FIG. 33 is a flowchart of the random number circuit setting process at this time, FIG. 34 is a flowchart of the game control interrupt process, and FIG. 35 is a flowchart of the winning process.

  In the random number circuit setting process shown in FIG. 33, the CPU 106 first executes the random number maximum value setting module 151a included in the random number circuit setting program 151 to set a random number maximum value setting that specifies a random number maximum value preset by the user. By writing data to the random number maximum value setting register 132, the preset maximum value of the random R is set in the random number circuit 103 (step S31). Next, the CPU 106 executes the random number update method selection module 151 b included in the random number circuit setting program 151, and writes the random number update method selection data “01b” in the random number update method selection register 137, thereby performing the first random number update. The method is set in the random number circuit 103 (step S32). Thereafter, the CPU 106 executes the random number circuit activation module 151d included in the random number circuit setting program 151 and writes the random number circuit activation data “80h” to the random number circuit activation register 140, thereby activating the random number circuit 103 (step S33).

  In the game control interrupt process shown in FIG. 34, the CPU 106 can execute a predetermined data protection process or the like when the power supplied from the power supply board 10 is reduced by first executing a predetermined power-off process. (Step S191). Subsequently, the state of the detection signal input from each winning port switch 70 is determined by executing a predetermined switch process (step S192). Next, the CPU 106 executes display random number update processing (step S193). Subsequently, the CPU 106 executes the initial value changing program 153 to perform the initial value changing process shown in FIG. 29 (step S194). Further, the CPU 106 executes the count value permutation change program 154 to perform a count value permutation change process (step S195).

  Then, the CPU 106 executes the random value update program 155 to perform a random value update process (step S196). In this random number value update process, the CPU 106 writes the count value update data “01h” into the count value update register 135 to update the random R value stored in the random value register 131.

  Subsequently, special symbol process processing is executed (step S197). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, the CPU 106 executes normal symbol process processing (step S198). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the normal symbol display 40 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state. Further, the special symbol command control process (step S199) and the normal symbol command control process (step S200) are sequentially executed. Thus, the CPU 106 sends a display control command from the main board 11 to the display control board 12 to instruct display control of the variable display device 4 and lighting control of the normal symbol display 40. Subsequently, the CPU 106 executes predetermined information output processing to output various output data to each output port included in the I / O port 108 (step S201). In this information output process, a command for outputting jackpot information, starting information, probability variable information, etc. to the hall management computer is also sent from the main board 11 to the information terminal board 16. Further, the CPU 106 executes predetermined prize ball processing to set the number of prize balls based on the detection signal input from each winning opening switch 70 and outputs a payout control command to the payout control board 15. It is possible (step S202). Further, the CPU 106 performs a predetermined solenoid output process to open and close the movable wing piece in the normal variable winning ball device 6 and the open / close plate in the special variable winning ball device 7 when a predetermined condition is satisfied ( Step S203).

  In the winning process shown in FIG. 35, the CPU 106 first determines whether or not the start winning memorized number stored in the special figure reservation memory 170 is the maximum value “4” (step S161). Here, when the value of random R corresponding to the start winning memory number “4” is stored in the special figure holding memory 170, it is determined that the start winning memory number is “4”.

  When the start winning memorized number is “4” (step S161; Yes), the start detection by the current winning is invalidated and the winning process is ended as it is. On the other hand, when the start winning memory number is less than “4” (step S161; No), the random R value is read from the random value register 131 (step S162), and the read random R value is provided in the RAM 105, for example. After storing in the predetermined buffer area (step S163), “1” is added to the start winning memory number (step S164). Then, the CPU 106 sets the random R value stored in the predetermined buffer area at the head of the empty entry in the special figure reservation memory 170 (step S165).

  In the above-described embodiment, the counter 121 updates the count value from “1” to “4095” by one. However, the present invention is not limited to this, and the rule for updating the count value of the counter 121 is arbitrary. Further, the randomness of the count value input to the random value register 131 may be improved by switching the connection of each bit output terminal of the counter 121.

  Furthermore, in the above embodiment, the update range restriction means compares the count value input from the counter 121 with the random number maximum value specified by the random number maximum value setting data stored in the random number maximum value setting register 132. When the input count value is less than or equal to the random number maximum value, the input count value is output to the random value register 131. When the input count value is greater than the random number maximum value, the count value update signal is sent to the counter 121. The comparator 122 is an output.

  However, the present invention is not limited to this, and the update range restricting means performs a predetermined calculation according to the random number maximum value setting data stored in the random number maximum value setting register 132, and sets the update range of the count value. Anything to regulate is optional.

  For example, as shown in FIG. 36, the update range restriction means has a count value input from the counter 121 of “0” to “99” and is designated by the random number maximum value setting data stored in the random number maximum value setting register 132. In the case of the maximum random number “9”, the count value “0” when the input count value is “0” to “9”, the count value “1” when the input count value is “10” to “19”,. The count value update range may be restricted to “9” by outputting the count value “9” when the input count value is “90” to “99”.

  Further, in the above embodiment, the random number read from the random value register 131 is used as a big hit determination random number for determining whether or not the pachinko gaming machine 1 is put into a big hit gaming state by generating a big hit. . However, the present invention is not limited to this, and the read random number can be used for any purpose, and reach determination random numbers for determining whether or not to reach a loss, special symbols, and decorative symbols can be changed. Display random number for determining the variable display pattern used for display, display random number for determining the fixed symbol for the special symbol at the time of big hit, display for determining the fixed symbol for the special symbol at the time of loss Random numbers, random numbers for determining whether to change to a high probability state (special game state) in which the probability of generating a big hit is improved, or a display result in the normal figure game by the normal symbol display 40 is hit. It may be used for a random number for determining per normal drawing for determining whether or not to do so. However, it is not necessary to update all the random numbers listed here using the random number circuit 103, and some random numbers may be updated without using the random number circuit 103. For example, a part of these random numbers may be updated by executing a predetermined program during the game control interrupt process, or a random number update method using a refresh register may be used in combination. Good. Furthermore, the random number value read from the random number value register 131, the random number value updated by executing a predetermined program during the game control interrupt process, and / or the random number value updated using the refresh register, A value obtained by calculation such as addition, subtraction, integration, multiplication, and division may be used as a random number for determining jackpot, reach, variable pattern, and the like.

  Furthermore, in the above-described embodiment, the gaming machine incorporating the random number circuit 103 is variable after the first type pachinko gaming machine, that is, the variable display execution condition (for example, winning to the normal variable winning ball apparatus 6) is established. A variable display device (for example, variable) that variably displays a plurality of types of identification information that can be identified based on the establishment of a display start condition (for example, the previous variable display and end of jackpot gaming state in the variable display device 4). The display device 4) is a gaming machine that controls to a specific gaming state (for example, a big hit gaming state) that is advantageous to the player when the display result of variable display becomes a predetermined specific display result.

  However, the present invention is not limited to this. For example, a gaming machine having a built-in random number circuit 103 uses start detection means (for example, a start ball detector) that detects a game medium in a start area provided in the game area. A variable winning device having a variable winning device (for example, a variable winning ball device) that performs a starting operation (for example, a releasing operation) that changes from a second state unfavorable to the player to a first state advantageous to the player by detection. The variable winning device is set to the first state in a specific manner more advantageous to the player than the starting operation by detection of specific detection means (for example, a specific ball detector) that detects the game medium in a specific area provided in It may be a second type pachinko gaming machine that generates a specific gaming state to be controlled (for example, a big hit gaming state).

  In this case, the random number read from the random value register 131 is used for determination of the upper limit number of rounds in a specific gaming state (for example, a big hit gaming state) or for determination related to a change in the internal structure of a variable winning device (for example, a variable winning ball device). It can be used as a random number.

  In addition, the gaming machine incorporating the random number circuit 103 is provided on the condition that a game ball is detected by special detection means (for example, a specific ball detection switch or a special region switch) provided in a special area (for example, a special device operation area). During the period in which the right is generated and the right is generated, start detection means (for example, an operation ball detection switch or a start port switch) provided in a start area (for example, an operation winning opening or a starting opening in a starting winning device) Based on the detection of the game ball, control is performed to change the special variable prize-winning device (for example, a big prize opening) from a state unfavorable for the player (for example, a closed state) to a state advantageous for the player (for example, an open state). It may be a third type pachinko gaming machine that can be performed.

  This type 3 pachinko gaming machine has a variable display device that displays a display result related to opening and closing of a winning device that generates a right generation state by winning a prize (so-called normal symbol type type 3 pachinko gaming machine) In this case, the random number read from the random value register 131 can be used as a random number for prior determination of a normal symbol.

  Furthermore, when a specific display result is displayed on the variable display device, the type 3 pachinko gaming machine generates a right generation state for the game medium that caused the variable display device to derive the specific display result. In the case of a gaming machine (a so-called judgment symbol type type 3 gaming machine) that guides the game ball to the specific detection device to be used, the random number read from the random value register 131 is used as a random number for prior judgment of the judgment symbol Can do.

  Further, in the above embodiment, the CPU 106 in the game control main process, after the game state restoration process in step S8 or the initialization process in S9, before setting for timer interruption by the CTC 107 in step S11, Although the random number circuit setting process has been executed, the present invention is not limited to this, and is arbitrary as long as the power is turned on and before the transition to the loop process. For example, interrupt prohibition is performed in step S1. Or may be performed immediately after setting the interrupt mode to mode 2 in step S2. Further, immediately after setting the stack pointer designation address to the stack pointer in step S3, immediately after setting the register such as CTC 107 in step S4, or immediately after setting for timer interruption in step S11. Good.

  Furthermore, in the above-described embodiment, the CPU 106 executes the random number value update process after the count value permutation change process at step S105 and before the special symbol process process at step S106 in the game control interrupt process. The present invention is not limited to this, and is arbitrary as long as the game control interrupt process is in progress. For example, the random number value update process may be executed before the display random number update process in step S103. The random value update process may be performed after the display random number update process in step S103 and before the initial value change process in step S104. Further, after the initial value change process in step S104, step S105 is performed. It may be performed before the count value permutation change processing by.

  In the above embodiment, the CPU 106 writes the count value capture data “01h” to the count value capture register 136 at the time of winning, and updates the random R value stored in the random value register 131. It was. However, the present invention is not limited to this, and the value of random R stored in the random value register 131 by writing the count value capture data “01h” into the count value capture register 136 for each timer interrupt. May be updated.

  Furthermore, in the above embodiment, when initial value change method setting data “03h” for designating the third initial value change method is stored in the area of address 1F97h in the user program execution data area, the CPU 106 The initial value of the count value updated by 121 is changed to the addition value of the value stored in each address of the RAM 105. However, the present invention is not limited to this, and when the initial value change method setting data “03h” is stored, the value to be changed is based on the value stored at a predetermined address in the RAM 105. If it is a thing, it is arbitrary. For example, the CPU 106 may change the initial value of the count value updated by the counter 121 to an integrated value or a multiplied value of a value stored in each address of the RAM 105.

  Also, the device configuration shown in FIGS. 1 and 2, the block configuration shown in FIGS. 3, 4 and 24, the register configuration shown in FIGS. 5, 8, and 10 to 16, and the program shown in FIGS. The configuration, the table configuration shown in FIGS. 6 and 25, and the flowchart configuration shown in FIGS. 26 to 35 can be arbitrarily changed and modified without departing from the spirit of the invention.

  Furthermore, the present invention can be applied to a game machine that simulates the operation of the pachinko gaming machine 1. The program and data for realizing the present invention are not limited to a form distributed and provided on a computer device or the like by a detachable recording medium, but preinstalled in a storage device such as a computer device or the like in advance. You may take the form distributed by keeping it. Further, the program and data for realizing the present invention are distributed by downloading from other devices on a network connected via a communication line or the like by providing a communication processing unit. It doesn't matter.

  The game execution mode is not only executed by attaching a removable recording medium, but can also be executed by temporarily storing the downloaded program and data via a communication line or the like in an internal memory or the like. It is also possible to execute directly using hardware resources on the other device side on a network connected via a communication line or the like. Furthermore, the game can be executed by exchanging data with other computer devices or the like via a network.

  In addition, the present invention is not limited to a payout type gaming machine that pays out a predetermined number of prize balls in response to detection of winning balls, and encloses game balls and gives points in response to detection of winning balls. It can also be applied to an enclosed game machine.

It is a front view of the pachinko gaming machine in the embodiment of the present invention. It is a rear view of the pachinko gaming machine in the embodiment of the present invention. It is a block diagram which shows the circuit structure etc. in a main board | substrate. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example of an update rule selection register. It is a figure which shows the structural example of an update rule memory. It is explanatory drawing of the change operation | movement of the permutation of count value by a count value permutation change circuit. It is a figure which shows the structural example of a count value permutation change register. It is explanatory drawing of the update operation of the count value by a counter and a comparator. It is a figure which shows the structural example of a random number maximum value setting register. It is a figure which shows the structural example of a period setting register. It is a figure which shows the structural example of a count value update register. It is a figure which shows the structural example of a count value taking-in register. (A) is a figure which shows the structural example of a random number update system selection register, (B) is explanatory drawing of random number update system selection data. It is a figure which shows the structural example of a random value register. It is a figure which shows the structural example of a random number circuit starting register. It is a figure which shows an example of the address map in the microprocessor for game control. It is a figure which shows an example of the address map in ROM. It is explanatory drawing of initial value change system selection data. It is a figure which shows the structural example of a user program. It is a figure which shows the structural example of a random number circuit setting program. It is explanatory drawing of the update operation | movement of the random value by CPU when the 1st random number update system is selected. It is explanatory drawing of the update operation | movement of the random value by CPU when the 2nd random number update system is selected. It is a block diagram which shows the structural example of the microprocessor for game control. It is a figure which shows the structural example of a big hit determination table. It is a flowchart which shows a game control main process. It is a flowchart which shows a random circuit setting process. It is a flowchart which shows a game control interruption process. It is a flowchart of the initial value change process in FIG. It is a flowchart which shows a special symbol process process. FIG. 31 is a flowchart showing details of a winning process in FIG. 30. FIG. It is a flowchart which shows the detail of the big hit determination process in FIG. It is a flowchart which shows the modification of the random number circuit setting process in FIG. It is a flowchart which shows the modification of the game control interruption process in FIG. FIG. 31 is a flowchart showing a modified example of the winning process in FIG. 30. FIG. It is explanatory drawing of the modification of the update operation | movement of the count value shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Pachinko machine 2 ... Game board 3 ... Gaming machine frame 4 ... Variable display device 6 ... Normal variable winning ball device 7 ... Special variable winning ball device 8L, 8R ... Speaker 9 ... Game effect lamp 10 ... Power supply board 11 ... Main board 12 ... Display control board 13 ... Audio control board 14 ... Lamp control board 15 ... Dispensing control board 16 ... Information terminal boards 21, 22 ... Solenoid 40 ... Normal symbol display 70 ... Each prize opening switch 100 ... Micro for game control Processor 101 ... Clock circuit 102 ... Reset controller 103 ... Random number circuit 104 ... ROM
105 ... RAM
106 ... CPU
107… CTC
DESCRIPTION OF SYMBOLS 108 ... I / O port 109 ... Switch circuit 110 ... Solenoid circuit 121 ... Counter 122 ... Comparator 123 ... Count value permutation change circuit 124 ... Clock signal output circuit 125 ... First trigger signal output circuit 126 ... Second trigger signal Output circuit 127 ... Random number update method selection signal output circuit 128 ... First selector 129 ... Second selector 130 ... Random circuit start signal output circuit 131 ... Random value register 132 ... Random number maximum value setting register 133 ... Count value permutation change register 134 ... Period setting register 135 ... Count value update register 136 ... Count value fetch register 137 ... Random number update method selection register 140 ... Random circuit start register 141 ... Update rule selection register 142 ... Update rule memory 150 ... Program 151... Random number circuit setting program 151 a... Random number maximum value setting module 151 b... Random number update method selection module 151 c... Program 170 ... Special figure holding memory 171 ... Big hit judgment table memory 171a ... Normal big hit judgment table 171b ... Precise change big hit judgment table 172 ... Flag memory

Claims (18)

A variable display device that variably displays a plurality of types of identification information that can be identified based on the fact that the variable display start condition is satisfied after the variable display execution condition is satisfied, and the display result of the variable display is predetermined. A gaming machine that controls to a specific gaming state advantageous to the player when the specified display result is obtained,
Power supply means for supplying power to the gaming machine;
A microprocessor that includes a random number circuit for generating a random number, operates using the power supplied from the power supply means, and controls the progress of the game;
Variable display control means for controlling variable display of identification information in the variable display device based on a control signal from the microprocessor;
With
The random number circuit includes:
Clock signal output means for outputting a clock signal of a predetermined period;
Numeric update register for storing numeric update data for requesting numeric data update;
A random number update method selection register for storing random number update method selection data for designating a random number update method selected from the first and second random number update methods which are methods for updating random numbers;
When the random number update method selection data for designating the first random number update method is stored in the random number update method selection register, the numerical value data is received in response to the numerical value update data being written in the numerical value update register. And when the random number update method selection data for designating the second random number update method is stored in the random number update method selection register, the numerical value in response to the clock signal output from the clock signal output means Numerical value updating means for updating data;
Random value storage means for storing numerical data updated by the numerical value update means as a random value;
A numerical value acquisition register for storing numerical value acquisition data instructing to store the numerical data updated by the numerical value update means as a random value in the random value storage means;
When the random number update method selection data for specifying the first random number update method is stored in the random number update method selection register, it is updated by the numerical value update unit in response to the clock signal output from the clock signal output unit. Stored in the random number value storage means, and when the random number update method selection data for specifying the second random number update method is stored in the random number update method selection register, the numerical value acquisition register stores the numerical value In response to the fetched data being written, the random number value fetching means for storing the numeric data updated by the numeric value updating means in the random number value storing means;
Including
The microprocessor is
Specifying a random number update method selected from at least the first and second random number update methods as a setting for causing the random number circuit to update the random number value after starting the supply of power by the power supply means Random number circuit setting means for writing random number update method selection data to the random number update method selection register;
Timer interrupt process execution permitting means for permitting execution of a timer interrupt process that occurs periodically after the setting is made to the random number circuit by the random number circuit setting means;
When the first random number update method is selected during execution of the timer interrupt process, the numerical value update data is written to the numerical value update register to update the random number value stored in the random value storage means. In response to establishment of the execution condition, the random number value stored in the random value storage means is read out, and it is determined whether the read random number value matches predetermined determination value data. It is determined whether or not the display result in the variable display triggered by the establishment of the condition is a specific display result, and when the second random number update method is selected, the numerical value acquisition data is acquired. A random number value is stored in the random number value storage unit by writing to a register, and when the execution condition is satisfied, the random number value stored in the random value storage unit is read out, and the read random number value is a predetermined determination value. By determining whether they meet the over data, and display result determining means for determining whether a specific display results display result in the variable display triggered by the establishment of the execution conditions,
including,
A gaming machine characterized by that. The microprocessor is
A recovery process executing means for executing a process for recovering the control state at the time of the previous power supply stop based on the establishment of a predetermined recovery condition after the start of power supply by the power supply means;
An initialization process executing means for executing an initialization process for initializing a control state based on the failure of the predetermined recovery condition after the power supply means starts supplying power;
Including
The random number circuit setting unit performs setting for updating the random number value in the random number circuit after the execution of the recovery process by the recovery process execution unit or after the initialization process by the initialization process execution unit.
The gaming machine according to claim 1. The random number circuit includes:
A random number maximum value setting register for storing random number maximum value setting data for specifying a maximum value of a random number generated by the random number circuit;
Update range restriction means for restricting the update range by the numerical value update means according to the random number maximum value setting data specified in the random number maximum value setting register;
Including
The random number circuit setting means includes random number maximum value setting means for writing random number maximum value setting data in the random number maximum value setting register.
The gaming machine according to claim 1 or 2, characterized in that. The microprocessor is
System reset means for system resetting the microprocessor;
The random number maximum value setting register in which the random number maximum value setting data is written is controlled to be unwritable until the microprocessor is system reset by the system reset means.
The gaming machine according to claim 3. When the maximum value of the random number specified by the random number maximum value setting data written in the random number maximum value setting register by the random number maximum value setting unit is smaller than a predetermined lower limit value, the microprocessor The random number maximum value setting data for designating the predetermined value is stored in the random number maximum value setting register.
The gaming machine according to claim 3 or 4, characterized in that. The numerical value updating means circularly updates the numerical data from a predetermined initial value to a predetermined maximum value,
The random number circuit includes notification signal output means for outputting a notification signal for notifying that when the numerical data is updated to the predetermined final value by the numerical value updating means,
The microprocessor includes an initial value changing unit that changes the predetermined initial value in response to a notification signal output from the numerical value updating unit.
The gaming machine according to any one of claims 1 to 5, characterized in that: The initial value changing means includes means for changing the changed initial value again when the changed initial value is larger than the maximum value of the random number.
The gaming machine according to claim 6. The microprocessor has a function of selecting a method for changing the predetermined initial value from the first, second and third initial value changing methods, and includes a storage means for storing predetermined data,
When the first initial value changing method is selected, the initial value changing means changes the predetermined initial value to a value set based on an identification number unique to the microprocessor, and When the initial value changing method is selected, the predetermined initial value is changed to a value stored at a predetermined address of the storage means, and when the third initial value updating method is selected, Changing the predetermined initial value based on a value stored in a predetermined address of the storage means;
The gaming machine according to claim 6 or 7, characterized in that The random number circuit includes:
A numerical permutation change register for storing numerical permutation change data for requesting a change in the permutation, which is a numerical data update order;
When the numerical permutation change data is stored in the numerical permutation change register, the numerical permutation changing means for changing to a permutation of an update order different from the permutation when the numerical permutation change data is not stored;
Including
The microprocessor includes numerical permutation change data writing means for writing the numerical permutation change data to the numerical permutation change register.
The gaming machine according to any one of claims 1 to 8, wherein the gaming machine is characterized by that. The microprocessor initializes the numerical permutation change register in response to the permutation being changed by the numerical permutation changing means;
The gaming machine according to claim 9. The numerical permutation changing means further changes the permutation of the changed numerical data when the numerical permutation data is rewritten in the numerical permutation register after the numerical permutation change register is initialized.
The gaming machine according to claim 10. The microprocessor is
System reset means for system resetting the microprocessor;
Until the system is reset by the system reset means, the random number update method selection register in which the random number update method selection data is written is controlled to be unwritable.
The gaming machine according to any one of claims 1 to 11, wherein the gaming machine is characterized by that. The microprocessor includes system clock signal output means for outputting a system clock signal,
The display result determining means writes the numerical value update data into the numerical value update register with a time longer than the period of the system clock signal output by the system clock signal output means.
The gaming machine according to any one of claims 1 to 12, characterized in that: The random number circuit includes:
A cycle setting register for storing cycle setting data for designating the update cycle;
A clock signal generating means for generating and outputting a clock signal having a period specified by the period setting data stored in the period setting register;
Including
The random number circuit setting means includes a period setting means for writing the period setting data for designating a preset update period to the period setting register.
The gaming machine according to any one of claims 1 to 13, wherein the gaming machine is any one of the above. The microprocessor is
System reset means for system resetting the microprocessor;
Until the system is reset by the system reset means, the cycle setting register in which the cycle setting data is written is controlled to be unwritable.
The gaming machine according to claim 14, wherein When the update cycle specified by the cycle setting data written by the cycle setting means in the cycle setting register is smaller than a predetermined lower limit value, the microprocessor sets cycle setting data for specifying the predetermined lower limit value. Store in the cycle setting register,
The gaming machine according to claim 14 or 15, characterized in that The random number circuit includes:
A random number circuit activation register for storing random number circuit activation data for requesting activation of the random number circuit;
Random number circuit starting means for starting the random number circuit in response to the random number circuit starting data being written in the random number circuit starting register;
Including
The random number circuit setting means includes random number circuit activation setting means for writing the random number circuit activation data into the random number circuit activation register.
The gaming machine according to any one of claims 1 to 16, wherein the gaming machine is characterized by that. The microprocessor includes system reset means for system resetting the microprocessor,
The random number circuit activation setting means, when the system is reset by the system reset means, rewrites the random number circuit activation data in the random number circuit activation register to activate the random number circuit.
The gaming machine according to claim 17, wherein

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