JP2005123894A - High frequency multichip module board - Google Patents

High frequency multichip module board Download PDF

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JP2005123894A
JP2005123894A JP2003356692A JP2003356692A JP2005123894A JP 2005123894 A JP2005123894 A JP 2005123894A JP 2003356692 A JP2003356692 A JP 2003356692A JP 2003356692 A JP2003356692 A JP 2003356692A JP 2005123894 A JP2005123894 A JP 2005123894A
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signal
conductor layer
signal line
ground conductor
ground
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Toru Mugiuda
徹 麦生田
Takeshi Hashimoto
健 橋本
Shinsuke Ko
真祐 高
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Panasonic Electric Works Co Ltd
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Matsushita Electric Works Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To realize a high frequency multichip module board exhibiting excellent high frequency signal transmission characteristics in which chips can be mounted with high integration efficiency and mounting on a mother board is facilitated. <P>SOLUTION: The high frequency multichip module board 1 comprises a high frequency signal line 3 for connecting a chip formed on the upper surface of a dielectric substrate 2, a ground conductor layer 4, a signal terminal 31 for mounting on a mother board 5, and a ground terminal 41 formed on the lower surface of the dielectric substrate 2. The signal line 3 and the ground conductor layer 4 constitute a microstrip line. Furthermore, a ground post 7 connected with the ground conductor layer 4 and arranged substantially in parallel with a signal connection member 6 rationalizes the characteristic impedance at the part of signal connection member 6, and an adjusting plate 8 connected with the ground post 7 suppresses increase in characteristic impedance at a part where the line structure is changed from the signal line 3 to the signal connection member 6. The signal terminal 31 and the ground terminal 41 collected on the lower surface facilitate mounting of the board 1 onto the mother board 5. Since the ground conductor layer is not formed on the upper surface of the dielectric substrate 2, integration efficiency of chips is enhanced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、高周波用マルチチップモジュール基板に関する。   The present invention relates to a high-frequency multichip module substrate.

従来、マイクロ波やミリ波といった高周波信号を伝送する伝送線路構造を有する高周波用配線基板（高周波用マルチチップモジュール基板）に、光学素子やスイッチング素子などの複数のチップ状の高周波対応素子を実装して集積化する高周波用マルチチップモジュールが知られている。高周波用マルチチップモジュールの正常動作（信号品質確保）には、高周波用マルチチップモジュール基板における伝送線路の特性インピーダンスを適正化することが重要である。伝送線路の特性インピーダンスは回路要素の幾何学的構造に依存する。そこで、伝送線路として信号ラインと接地導体層とによるマイクロストリップライン構造の組み込みが図られている。マイクロストリップラインを構成できる部分においては、接地導体層に対する信号ラインの特性インピーダンスを、例えば５０Ωや７５Ωに設計することができる。   Conventionally, a plurality of chip-shaped high-frequency compatible elements such as optical elements and switching elements are mounted on a high-frequency wiring board (high-frequency multichip module board) having a transmission line structure for transmitting high-frequency signals such as microwaves and millimeter waves. A multi-chip module for high frequency that is integrated with each other is known. For normal operation of the high-frequency multichip module (to ensure signal quality), it is important to optimize the characteristic impedance of the transmission line in the high-frequency multichip module substrate. The characteristic impedance of the transmission line depends on the geometric structure of the circuit elements. Therefore, the incorporation of a microstrip line structure using a signal line and a ground conductor layer as a transmission line has been attempted. In the portion where the microstrip line can be formed, the characteristic impedance of the signal line with respect to the ground conductor layer can be designed to be, for example, 50Ω or 75Ω.

上述のマイクロストリップラインを構成できない部分においては他の構造によるインピーダンス適正化が図られている。例えば、多層基板における層間接続導体（層間ビア）による層間信号ライン接続部分において、接地電位とされる第１及び第２導体部材を接続導体の左右対称位置に配置してインピーダンス適正化を図るものが知られている（例えば、特許文献１参照）。   In a portion where the above-described microstrip line cannot be formed, impedance optimization by another structure is achieved. For example, in an interlayer signal line connection portion by an interlayer connection conductor (interlayer via) in a multilayer board, the first and second conductor members that are set to the ground potential are arranged at symmetrical positions of the connection conductor to optimize the impedance. It is known (see, for example, Patent Document 1).

また、上述の層間接続導体（層間ビア）が信号周波数の波長との関係から長すぎる場合の対応として、層間接続体を２分割して接地導体層を挿入するものが知られている（例えば、特許文献２参照）。
特開平７−２２１５１２号公報 特開２００２−１９８７０９号公報 In addition, as a countermeasure when the above-described interlayer connection conductor (interlayer via) is too long due to the relationship with the signal frequency wavelength, there is known a method in which the interlayer connection body is divided into two and a ground conductor layer is inserted (for example, Patent Document 2).
JP-A-7-221512 JP 2002-198709 A

しかしながら、上述した特許文献に示されるような高周波用マルチチップモジュール基板においては、特性インピーダンスの適正化について述べられているが、高周波用マルチチップモジュールという観点から言及されていない。すなわち、高周波用マルチチップモジュールを親基板に実装する場合の端子構造や、高周波用マルチチップモジュール基板に集積効率良く複数のチップを実装する回路構造の観点から、回路要素の幾何学的構造を考慮して特性インピーダンスの適正化を図る必要がある。   However, in the high-frequency multichip module substrate as shown in the above-mentioned patent document, optimization of characteristic impedance is described, but it is not mentioned from the viewpoint of a high-frequency multichip module. In other words, the geometric structure of the circuit elements is taken into consideration from the viewpoint of the terminal structure when the multichip module for high frequency is mounted on the parent substrate and the circuit structure for mounting a plurality of chips efficiently on the multichip module substrate for high frequency. Therefore, it is necessary to optimize the characteristic impedance.

本発明は、上記課題を解消するものであって、高周波信号伝送特性に優れ、チップを集積効率良く実装でき、また親基板への実装が容易な高周波用マルチチップモジュールを実現できる高周波用マルチチップモジュール基板を提供することを目的とする。   The present invention solves the above-described problems, and is a high-frequency multichip capable of realizing a high-frequency multichip module that is excellent in high-frequency signal transmission characteristics, can be mounted on a chip efficiently, and can be easily mounted on a parent substrate. An object is to provide a module substrate.

上記課題を達成するために、請求項１の発明は、誘電体材料からなる誘電体基板と、この誘電体基板の一方の面に設けられたチップ接続用の高周波用信号ラインと、前記信号ラインの設けられた面とは異なる誘電体基板の面に設けられた接地導体層と、親基板への実装用の信号端子及び接地端子とを有し、前記信号ラインと信号端子とは信号接続部材によって電気的に接続され、前記接地導体層と接地端子とは電気的に接続して接地電位とされ、前記信号ラインと接地導体層とは対をなして高周波信号伝送用のマイクロストリップラインを構成して成る高周波用マルチチップモジュール基板において、前記接地導体層に電気的に接続された接地柱を有し、前記接地柱は、前記信号接続部材と略平行に配置され、前記信号端子と接地端子とは、前記誘電体基板の略同一面に配置されていることを特徴とする高周波用マルチチップモジュール基板である。   In order to achieve the above object, a first aspect of the present invention provides a dielectric substrate made of a dielectric material, a high-frequency signal line for chip connection provided on one surface of the dielectric substrate, and the signal line. A grounding conductor layer provided on a surface of a dielectric substrate different from the surface provided with a signal terminal and a grounding terminal for mounting on a parent substrate, the signal line and the signal terminal being a signal connection member The ground conductor layer and the ground terminal are electrically connected to a ground potential, and the signal line and the ground conductor layer are paired to constitute a microstrip line for high-frequency signal transmission. A multi-chip module substrate for high frequency comprising: a grounding column electrically connected to the grounding conductor layer, wherein the grounding column is disposed substantially parallel to the signal connection member, and the signal terminal and the grounding terminal Is Serial is a high-frequency multi-chip module substrate, characterized in that it is arranged in substantially the same plane of the dielectric substrate.

請求項２の発明は、請求項１に記載の高周波用マルチチップモジュール基板において、前記接地柱に接続された調整板をさらに備え、前記調整板は前記信号ラインの配置された前記誘電体基板の面と略同一面に配置されていることを特徴とする。
ものである。 The invention of claim 2 is the high-frequency multichip module substrate according to claim 1, further comprising an adjustment plate connected to the grounding pillar, the adjustment plate of the dielectric substrate on which the signal lines are arranged. It is arrange | positioned on the surface substantially the same as the surface.
Is.

請求項３の発明は、請求項１又は請求項２に記載の高周波用マルチチップモジュール基板において、前記信号接続部材を接続している部分の信号ラインの線幅が、マイクロストリップラインを構成している部分の信号ラインの線幅よりも広いものである。   According to a third aspect of the present invention, in the high frequency multichip module substrate according to the first or second aspect, the line width of the signal line connecting the signal connection members constitutes a microstrip line. It is wider than the line width of the signal line in the part.

請求項４の発明は、請求項１乃至請求項３のいずれかに記載の高周波用マルチチップモジュール基板において、前記信号接続部材の断面の外周長が、前記接地導体層に近づくにつれて短くなるものである。   According to a fourth aspect of the present invention, in the multi-chip module substrate for high frequency according to any one of the first to third aspects, an outer peripheral length of a cross section of the signal connection member becomes shorter as approaching the ground conductor layer. is there.

請求項５の発明は、請求項１乃至請求項４のいずれかに記載の高周波用マルチチップモジュール基板において、前記接地柱が、信号接続部材の周囲に複数本配置されているものである。   According to a fifth aspect of the present invention, in the high frequency multichip module substrate according to any one of the first to fourth aspects, a plurality of the grounding pillars are arranged around the signal connection member.

請求項６の発明は、請求項１乃至請求項５のいずれかに記載の高周波用マルチチップモジュール基板において、前記誘電体基板は、２層以上の誘電体材料層からなり、前記接地導体層が、前記信号ラインを配置した面と前記接地端子及び信号端子を配置した面との間に配置され、前記信号接続部材は、前記接地導体層によって囲まれているものである。   According to a sixth aspect of the present invention, in the high-frequency multichip module substrate according to any one of the first to fifth aspects, the dielectric substrate comprises two or more dielectric material layers, and the ground conductor layer is The signal line is disposed between the surface on which the signal line is disposed and the surface on which the ground terminal and the signal terminal are disposed, and the signal connection member is surrounded by the ground conductor layer.

請求項７の発明は、請求項１乃至請求項５のいずれかに記載の高周波用マルチチップモジュール基板において、前記接地柱が、前記誘電体基板の外周面に配置されているものである。   According to a seventh aspect of the present invention, in the high-frequency multichip module substrate according to any one of the first to fifth aspects, the grounding pillar is disposed on an outer peripheral surface of the dielectric substrate.

請求項８の発明は、誘電体材料からなる誘電体ベースと、この誘電体ベースの表面に設けられたチップ接続用の高周波用信号ラインと、接地導体層と、親基板への実装用の信号端子及び接地端子とを有し、前記信号ラインと接地導体層が、誘電体ベースを挟んで対をなして対向配置されて成る高周波用マルチチップモジュール基板において、前記信号ラインは、互いに略垂直に位置する信号ライン端部と信号ライン中央部とを有し、前記接地導体層は、互いに略垂直に位置する接地導体層端部と接地導体層中央部とを有し、前記信号ライン中央部と接地導体層中央部の対、及び前記信号ライン端部と接地導体層端部の対は、それぞれマイクロストリップラインを形成し、前記信号端子は、前記信号ライン端部に接続され、前記接地端子は、前記接地導体層端部に接続され、前記信号端子と接地端子とは、前記誘電体ベース表面の略同一面に配置されていることを特徴とする高周波用マルチチップモジュール基板である。   According to an eighth aspect of the present invention, there is provided a dielectric base made of a dielectric material, a high frequency signal line for chip connection provided on the surface of the dielectric base, a ground conductor layer, and a signal for mounting on a parent substrate. A high-frequency multichip module substrate having a terminal and a ground terminal, wherein the signal line and the ground conductor layer are arranged to face each other across a dielectric base, and the signal lines are substantially perpendicular to each other. A signal line end portion and a signal line center portion, and the ground conductor layer has a ground conductor layer end portion and a ground conductor layer center portion positioned substantially perpendicular to each other, and the signal line center portion; The pair of the ground conductor layer center portion and the pair of the signal line end portion and the ground conductor layer end portion respectively form a microstrip line, the signal terminal is connected to the signal line end portion, and the ground terminal is ,Previous Is connected to the ground conductor layer end, the signal terminals and the ground terminal, a high-frequency multi-chip module substrate, characterized in that it is arranged in substantially the same plane of the dielectric base surface.

請求項９の発明は、請求項１乃至請求項８のいずれかに記載の高周波用マルチチップモジュール基板上に、入力信号に応じて光信号を発光する発光素子と、前記発光素子の光信号を受光して光起電力を発生する受光素子と、前記受光素子の光起電力がゲート・ソース間に印加されてドレイン・ソース間のインピーダンスが変化する出力用半導体素子と、前記発光素子を実装する発光素子用回路パターンと、前記受光素子を実装する受光素子用回路パターンとを備え、前記基板上に設けられた信号ラインが第１の信号ラインと第２の信号ラインとから成り、前記出力用半導体素子が前記信号ライン間に実装され、該出力用半導体素子のドレイン・ソース間のインピーダンス変化により前記信号ライン間の線路が開閉されることを特徴とする半導体リレーである。   According to a ninth aspect of the present invention, a light emitting element that emits an optical signal according to an input signal on the high frequency multichip module substrate according to any one of the first to eighth aspects, and an optical signal of the light emitting element. A light receiving element that receives a photoelectromotive force by receiving light, an output semiconductor element in which an impedance between the drain and the source changes when a photoelectromotive force of the light receiving element is applied between a gate and a source, and the light emitting element are mounted A circuit pattern for a light emitting element and a circuit pattern for a light receiving element for mounting the light receiving element, wherein a signal line provided on the substrate includes a first signal line and a second signal line, A semiconductor element is mounted between the signal lines, and the line between the signal lines is opened and closed by a change in impedance between the drain and source of the output semiconductor element. A relay.

請求項１の発明によれば、信号端子と接地端子が略同一面に集約して配置されているので、信号端子及び接地端子を用いて高周波用マルチチップモジュール基板を親基板に容易に実装することできる。また、高周波信号伝送用の信号ラインと信号端子を電気的に接続する信号接続部材に略平行に接地柱を配置して信号接続部材部分の特性インピーダンスが調整されているので、信号伝送線路の特性インピーダンスの不整合が軽減され、高周波信号の波形品質の劣化を軽減することができる。また、信号伝送ラインの特性インピーダンスが、接地柱、及び信号ラインの設けられた面とは異なる面に設けられた接地導体層によって適正化されるので、信号ラインの設けられた面には接地導体層がなく集積効率良くチップを実装することができる。   According to the first aspect of the present invention, since the signal terminals and the ground terminals are concentrated on the same surface, the high frequency multichip module substrate is easily mounted on the parent substrate using the signal terminals and the ground terminals. I can. In addition, the characteristic impedance of the signal connection member portion is adjusted by arranging a grounding pillar substantially parallel to the signal connection member that electrically connects the signal line and signal terminal for high-frequency signal transmission. Impedance mismatch is reduced, and deterioration of the waveform quality of the high-frequency signal can be reduced. In addition, since the characteristic impedance of the signal transmission line is optimized by the grounding pillar and the grounding conductor layer provided on a surface different from the surface provided with the signal line, the grounding conductor is provided on the surface provided with the signal line. There is no layer, and the chip can be mounted with high integration efficiency.

請求項２の発明によれば、信号ラインと略同一面に配置され接地柱に接続された調整板が、マイクロストリップライン構造の信号ラインから信号接続部材へと線路構造が変化するときの線路の特性インピーダンス増を抑制し、また高周波信号の伝達モードの変化による反射を低減するので、信号ラインを通過する高周波信号の波形劣化を低減できる。   According to the second aspect of the present invention, the adjustment plate arranged substantially on the same plane as the signal line and connected to the grounding pillar is used for the line when the line structure changes from the signal line of the microstrip line structure to the signal connection member. Since the increase in characteristic impedance is suppressed and the reflection due to the change in the transmission mode of the high frequency signal is reduced, the waveform deterioration of the high frequency signal passing through the signal line can be reduced.

請求項３の発明によれば、信号ラインの線幅拡大部分が上述の調整板と同様に、特性インピーダンス増加抑制に寄与するので、上記同様の効果が得られる。   According to the invention of claim 3, the line width enlarged portion of the signal line contributes to the suppression of the increase in characteristic impedance as in the above-described adjustment plate, and thus the same effect as described above can be obtained.

請求項４の発明によれば、信号接続部材とこれに略平行に配置した接地柱との間隔が、接地導体層に近づくほど広くなり、従って信号接続部材と接地柱との高周波的結合が弱まるので、信号接続部材が接地導体層に近付くほど信号接続部材と接地導体層との高周波的結合が強まる傾向を打ち消すことができ、信号接続部材の特性インピーダンスの変化を抑えて略一定にすることができ、特性インピーダンスが変化することによる信号波形品質の劣化を抑制できる。   According to the fourth aspect of the present invention, the distance between the signal connection member and the grounding pillar disposed substantially parallel thereto increases as it approaches the grounding conductor layer, and therefore the high-frequency coupling between the signal connection member and the grounding pillar is weakened. Therefore, the tendency that the high frequency coupling between the signal connection member and the ground conductor layer becomes stronger as the signal connection member approaches the ground conductor layer can be canceled, and the change in the characteristic impedance of the signal connection member can be suppressed to be substantially constant. It is possible to suppress deterioration of signal waveform quality due to change in characteristic impedance.

請求項５の発明によれば、信号接続部材と平行に配置した接地柱によって、上記の効果をより効果的に実現できる。すなわち、信号接続部材と接地柱の間の電界が分散され、より安定して高周波信号を通過させることができ、また、接地柱によるシールド効果が増して信号接続部材が外乱から受ける影響を小さくできる。   According to invention of Claim 5, said effect is more effectively realizable by the grounding pillar arrange | positioned in parallel with the signal connection member. In other words, the electric field between the signal connection member and the grounding column is dispersed, allowing high-frequency signals to pass more stably. Further, the shielding effect by the grounding column is increased, and the influence of the signal connection member on the disturbance can be reduced. .

請求項６の発明によれば、複数の接地柱を信号接続部材の周囲に配置する場合よりも全体を小さくした導体構造で高周波用マルチチップモジュール基板を構成して、上記同様の効果を奏することができる。   According to the invention of claim 6, the multi-chip module substrate for high frequency is configured with a conductor structure which is made smaller as a whole than the case where a plurality of grounding pillars are arranged around the signal connection member, and the same effect as described above can be obtained. Can do.

請求項７の発明によれば、ＭＩＤ（Ｍｏｌｄｅｄ Ｉｎｔｅｒｃｏｎｎｅｃｔｅｄ Ｄｅｖｉｃｅ）工法等により誘電体基板の外周面に面的な配線パターンとして接地柱を高密度に形成でき、内部に３次元的な導体構造を構成するよりも小型化した高周波用マルチチップモジュール基板を実現できる。   According to the invention of claim 7, the ground pillar can be formed with a high density as a planar wiring pattern on the outer peripheral surface of the dielectric substrate by a MID (Molded Interconnected Device) method or the like, and a three-dimensional conductor structure is formed inside Thus, it is possible to realize a high-frequency multichip module substrate that is smaller than the above.

請求項８の発明によれば、信号端子と接地端子の直近までマイクロストリップライン構造の高周波線路を構成して信号ラインに高周波信号を通過させたときの波形品質の劣化を抑えることができ、かつ、親基板に実装しやすい端子構造を有する高周波用マルチチップモジュール基板を実現できる。ＭＩＤ等の工法を用いて高周波用マルチチップモジュール基板を安価、かつ容易に形成することができる。   According to the invention of claim 8, it is possible to suppress deterioration in waveform quality when a high frequency signal having a microstrip line structure is formed up to the immediate vicinity of the signal terminal and the ground terminal and a high frequency signal is passed through the signal line, and Thus, a high-frequency multichip module substrate having a terminal structure that can be easily mounted on the parent substrate can be realized. A high-frequency multichip module substrate can be formed inexpensively and easily using a method such as MID.

請求項９の発明によれば、マイクロストリップラインを構成している信号ラインの部分だけでなく、信号端子付近まで特性インピーダンスの整合が可能であり、高周波信号の波形品質の劣化の少ない半導体リレーを実現できる。   According to the ninth aspect of the present invention, there is provided a semiconductor relay capable of matching the characteristic impedance not only to the signal line portion constituting the microstrip line but also to the vicinity of the signal terminal and causing little deterioration of the waveform quality of the high frequency signal. realizable.

以下、本発明の一実施形態に係る高周波用マルチチップモジュール基板について、図面を参照して説明する。図１（ａ）（ｂ）は親基板に実装した状態の高周波用マルチチップモジュール基板１を示し、図１（ｂ）（ｃ）は同モジュール基板下面の端子構造を示す。高周波用マルチチップモジュール基板１は、誘電体材料からなる誘電体基板２と、この誘電体基板２の一方の面（上面）に設けられたチップ接続用の高周波用信号ライン３と、信号ライン３の設けられた面とは異なる誘電体基板の面（下面）に設けられた接地導体層４と、親基板５への実装用の信号端子３１及び接地端子４１とを有し、信号ライン３と信号端子３１とは信号接続部材６によって電気的に接続され、接地導体層４と接地端子４１とは電気的に接続して接地電位とされ、信号ライン３と接地導体層４とは対をなして高周波信号伝送用のマイクロストリップラインを構成している。   Hereinafter, a high-frequency multichip module substrate according to an embodiment of the present invention will be described with reference to the drawings. FIGS. 1A and 1B show the high-frequency multichip module substrate 1 mounted on the parent substrate, and FIGS. 1B and 1C show the terminal structure on the lower surface of the module substrate. The high frequency multichip module substrate 1 includes a dielectric substrate 2 made of a dielectric material, a high frequency signal line 3 for chip connection provided on one surface (upper surface) of the dielectric substrate 2, and a signal line 3. A grounding conductor layer 4 provided on the surface (lower surface) of the dielectric substrate different from the surface on which the signal line 3 is provided, and a signal terminal 31 and a grounding terminal 41 for mounting on the parent substrate 5. The signal terminal 31 is electrically connected by the signal connection member 6, the ground conductor layer 4 and the ground terminal 41 are electrically connected to have a ground potential, and the signal line 3 and the ground conductor layer 4 form a pair. Thus, a microstrip line for high-frequency signal transmission is configured.

このように構成された高周波用マルチチップモジュール基板１は、さらに、接地導体層４に電気的に接続された接地柱７を有し、接地柱７は、信号接続部材６と略平行に配置され、接地柱７には調整板８が接続され、調整板８は信号ライン３の配置された誘電体基板２の面と略同一面に配置されており、また、信号端子３１と接地端子４１とは、誘電体基板２の略同一面（下面）に配置されている。   The high-frequency multichip module substrate 1 configured as described above further includes a grounding column 7 electrically connected to the grounding conductor layer 4, and the grounding column 7 is disposed substantially in parallel with the signal connection member 6. An adjustment plate 8 is connected to the grounding pillar 7, and the adjustment plate 8 is disposed on substantially the same plane as the surface of the dielectric substrate 2 on which the signal line 3 is disposed, and the signal terminal 31, the ground terminal 41, Are disposed on substantially the same surface (lower surface) of the dielectric substrate 2.

上述の高周波用マルチチップモジュール基板１において、信号接続部材６及び接地柱７は、スルーホール形状になっており、それぞれ誘電体基板２を貫通して設けられている。また、高周波用マルチチップモジュール基板１は、信号端子３１と接地端子４１を親基板５に設けられた配線パターン５１，５２にそれぞれ、はんだ５３等により接続されて、実装される。また、高周波用マルチチップモジュール基板１の上面には、抵抗、コイル、コンデンサ、半導体素子等のチップ素子が実装され（不図示）、高周波用マルチチップモジュールが形成される。   In the above-described high-frequency multichip module substrate 1, the signal connection member 6 and the grounding pillar 7 have a through-hole shape, and are respectively provided through the dielectric substrate 2. Further, the multi-chip module substrate 1 for high frequency is mounted by connecting the signal terminal 31 and the ground terminal 41 to the wiring patterns 51 and 52 provided on the parent substrate 5 with solder 53 or the like, respectively. Further, chip elements such as resistors, coils, capacitors, and semiconductor elements (not shown) are mounted on the upper surface of the high-frequency multichip module substrate 1 to form a high-frequency multichip module.

高周波用マルチチップモジュール基板１の各構成要素の機能及び作用について説明する。信号ライン３と接地導体層４はマイクロストリップラインを構成しているので、信号ライン３の接地導体層４に対する特性インピーダンスを任意の値、例えば５０Ωや７５Ωに設計することができる。また、信号接続部材６と接地柱７は、互いに略平行に配設されているので、信号接続部材６と接地柱７の間の距離、又は信号接続部材６や接地柱７の太さを変更することで、信号接続部材６の接地柱７に対する特性インピーダンスを所望の値に設計することができる。   The function and operation of each component of the high-frequency multichip module substrate 1 will be described. Since the signal line 3 and the ground conductor layer 4 constitute a microstrip line, the characteristic impedance of the signal line 3 with respect to the ground conductor layer 4 can be designed to an arbitrary value, for example, 50Ω or 75Ω. Further, since the signal connection member 6 and the grounding column 7 are disposed substantially parallel to each other, the distance between the signal connection member 6 and the grounding column 7 or the thickness of the signal connection member 6 or the grounding column 7 is changed. By doing so, the characteristic impedance of the signal connection member 6 with respect to the grounding pillar 7 can be designed to a desired value.

ところで、信号ライン３の信号接続部材６の付近と対向する部分には、信号端子３１と接地導体層４との絶縁を保つため、接地導体層４が配置されていないため、信号ライン３の信号接続部材６の付近にはマイクロストリップラインを形成することができない。従って、この信号ライン３の信号接続部材６の付近について何らかの処置を施さない限り、対向する接地された導体がないので、特性インピーダンスがマイクロストリップラインの特性インピーダンスより高くなる。そこで、高周波用マルチチップモジュール基板１では、信号ライン３と信号端子３１を電気的に接続する信号接続部材６に略平行に接地柱７を配置することによって、信号接続部材６部分の特性インピーダンスが調整されている。   By the way, since the ground conductor layer 4 is not disposed in the portion of the signal line 3 facing the vicinity of the signal connection member 6 in order to maintain the insulation between the signal terminal 31 and the ground conductor layer 4, the signal of the signal line 3 A microstrip line cannot be formed in the vicinity of the connecting member 6. Therefore, unless any treatment is performed in the vicinity of the signal connection member 6 of the signal line 3, there is no opposing grounded conductor, so that the characteristic impedance is higher than the characteristic impedance of the microstrip line. Therefore, in the multi-chip module substrate 1 for high frequency, the characteristic impedance of the signal connection member 6 portion is reduced by arranging the ground pillar 7 substantially parallel to the signal connection member 6 that electrically connects the signal line 3 and the signal terminal 31. It has been adjusted.

また、信号ライン３と略平行になるように調整板８を配置することで信号ライン３の信号接続部材６付近の特性インピーダンスを、調整板８を加えない状態よりも低くして、マイクロストリップライン部分の特性インピーダンスの値に近づけるように調整されている。また、この調整板８によって、高周波信号の伝達モードの変化による反射を低減することができ、線路構造の変化部分における高周波信号の反射による波形劣化を低減することができる。   Further, by arranging the adjusting plate 8 so as to be substantially parallel to the signal line 3, the characteristic impedance of the signal line 3 near the signal connecting member 6 is made lower than that in the state where the adjusting plate 8 is not added, so that the microstrip line It is adjusted to be close to the characteristic impedance value of the part. In addition, the adjustment plate 8 can reduce reflection due to a change in the transmission mode of the high-frequency signal, and can reduce waveform deterioration due to reflection of the high-frequency signal in the changed portion of the line structure.

上述の各作用を総合すると以下の効果が得られる。高周波用マルチチップモジュール基板１に流入出する高周波信号（例えば、略５００ＭＨｚ以上）は、例えば、親基板５の配線パターン５１から流入し、信号端子３１、信号接続部材６（設置柱７による特性インピーダンス調整）、信号接続部材６付近の信号ライン（調整板８による特性インピーダンス調整）、信号ライン（マイクロストリップ構造による特性インピーダンス調整）からなる一連の信号伝送線路を流れ、同様の構成の信号伝送線路を逆に辿って他の信号端子から流出する。このように、伝送線路の各部の特性インピーダンスが調整されて、インピーダンス不整合が軽減されているので、高周波信号の波形品質の劣化を軽減することができ、高周波信号伝送特性に優れ高周波用マルチチップモジュール基板１が実現される。   The following effects can be obtained by combining the above actions. A high-frequency signal (for example, approximately 500 MHz or more) flowing into and out of the high-frequency multichip module substrate 1 flows in from, for example, the wiring pattern 51 of the parent substrate 5, and the signal terminal 31 and the signal connection member 6 (characteristic impedance due to the installation column 7). Adjustment), a signal line in the vicinity of the signal connecting member 6 (characteristic impedance adjustment by the adjusting plate 8), and a signal line (characteristic impedance adjustment by the microstrip structure) flow through a series of signal transmission lines. Reversely, it flows out from other signal terminals. In this way, the characteristic impedance of each part of the transmission line is adjusted and impedance mismatch is reduced, so that deterioration of the waveform quality of the high-frequency signal can be reduced, and the high-frequency multi-chip has excellent high-frequency signal transmission characteristics. The module substrate 1 is realized.

また、上記の構成によると信号端子と接地端子を略同一面に集約して配置できる。その結果、高周波用マルチチップモジュール基板１を容易に親基板５に実装することができる。高周波用マルチチップモジュール基板１の親基板５への実装には、例えば、通常の表面実装型のはんだリフロー工程を用いることができる。   Further, according to the above configuration, the signal terminal and the ground terminal can be concentrated and arranged on substantially the same plane. As a result, the high-frequency multichip module substrate 1 can be easily mounted on the parent substrate 5. For mounting the high-frequency multichip module substrate 1 on the parent substrate 5, for example, a normal surface mounting type solder reflow process can be used.

さらに、上述の一連の信号伝送線路の特性インピーダンスを適正化する手段が、接地柱７、及び信号ライン３の設けられた面とは異なる面に設けられた接地導体層４等であるので、信号ラインの設けられた誘電体基板の上面を有効に用いることができ、集積効率良くチップを実装することができる。   Furthermore, since the means for optimizing the characteristic impedance of the series of signal transmission lines is the grounding pole 7 and the grounding conductor layer 4 provided on a surface different from the surface on which the signal line 3 is provided, the signal The upper surface of the dielectric substrate provided with the line can be used effectively, and the chip can be mounted with high integration efficiency.

次に、高周波用マルチチップモジュール基板の他の例を説明する。図２（ａ）（ｂ）は信号ラインの構成が前述のものと異なる高周波用マルチチップモジュール基板を示す。この高周波用マルチチップモジュール基板１の信号ライン３は、信号接続部材６を接続している部分において、マイクロストリップラインを構成している部分の線幅よりも広い線幅を有している。また、調整板８は、前出の図１に示した物より小型になっている。このように、信号ライン３の信号接続部材６付近の線幅を広くすることによって、調整板と同等の効果が得られ、信号ライン３の信号接続部材６付近の特性インピーダンスを低くしてマイクロストリップラインの特性インピーダンスとほぼ同程度にすることができる。つまり、各部分での特性インピーダンスの不整合を軽減することができる。   Next, another example of the high-frequency multichip module substrate will be described. FIGS. 2A and 2B show a high-frequency multichip module substrate having a signal line configuration different from that described above. The signal line 3 of the high-frequency multichip module substrate 1 has a line width wider than the line width of the portion constituting the microstrip line in the portion where the signal connection member 6 is connected. Further, the adjusting plate 8 is smaller than that shown in FIG. Thus, by increasing the line width of the signal line 3 in the vicinity of the signal connection member 6, an effect equivalent to that of the adjustment plate can be obtained. The characteristic impedance of the line can be made approximately the same. That is, the mismatch of characteristic impedance in each part can be reduced.

次に、高周波用マルチチップモジュール基板のさらに他の例を説明する。図３（ａ）（ｂ）は信号接続部材の構成が前述までのものと異なる高周波用マルチチップモジュール基板を示す。この高周波用マルチチップモジュール基板１の信号接続部材６は、信号接続部材の断面の外周長が、接地導体層４に近づくほど短い形状（図の例では逆円錐形状）になっている。また、設置導体層４に電気的に接続された２つの接地端子４１が信号端子３１を挟んで配置されると共に、各接地端子４１に接地柱７が電気的に接続されている。各接地柱７の上端には、調整板８が設けられている。   Next, still another example of the high-frequency multichip module substrate will be described. FIGS. 3A and 3B show a multi-chip module substrate for high frequency in which the configuration of the signal connection member is different from that described above. The signal connection member 6 of the multi-chip module substrate 1 for high frequency has a shape (an inverted conical shape in the example in the figure) that is shorter as the outer peripheral length of the cross section of the signal connection member is closer to the ground conductor layer 4. Further, two ground terminals 41 electrically connected to the installed conductor layer 4 are arranged with the signal terminal 31 interposed therebetween, and the ground pillar 7 is electrically connected to each ground terminal 41. An adjustment plate 8 is provided at the upper end of each grounding column 7.

上述のように、信号接続部材６と接地柱７を略平行に配置することで、信号接続部材６の特性インピーダンスを下げて、マイクロストリップ線路における特性インピーダンスに合わせるように設計できるようになるが、信号接続部材６が接地導体層４に近づくほど、信号接続部材６と接地導体層４との高周波的結合が強くなり、特性インピーダンスが下がり過ぎてしまう。そこで、接地導体層４に近いほど信号接続部材６を細く、信号接続部材６の断面の外周長を短くする（すなわち、信号接続部材６と接地柱７との距離を大きくする）ことによって、接地導体層４近傍における信号接続部材６の特性インピーダンス低下が抑制され、略一定の特性インピーダンス特性が実現される。このように、信号接続部材６の特性インピーダンスを略一定に保てるので、特性インピーダンスが変化することによる波形品質の劣化を軽減できる。   As described above, by arranging the signal connection member 6 and the grounding pillar 7 substantially in parallel, the characteristic impedance of the signal connection member 6 can be lowered and designed to match the characteristic impedance in the microstrip line. The closer the signal connection member 6 is to the ground conductor layer 4, the stronger the high frequency coupling between the signal connection member 6 and the ground conductor layer 4 and the lower the characteristic impedance. Therefore, the closer to the ground conductor layer 4, the thinner the signal connection member 6 and the shorter the outer peripheral length of the cross section of the signal connection member 6 (that is, the distance between the signal connection member 6 and the ground pillar 7 is increased). A decrease in characteristic impedance of the signal connection member 6 in the vicinity of the conductor layer 4 is suppressed, and a substantially constant characteristic impedance characteristic is realized. Thus, since the characteristic impedance of the signal connection member 6 can be kept substantially constant, the deterioration of the waveform quality due to the change of the characteristic impedance can be reduced.

また、信号接続部材６と接地柱７とが互いに１本ずつであって、いわゆるスロットラインに近い形状となる線路を、２つの接地柱７により信号接続部材６を挟んで配置することで信号接続部材６の部分をいわゆるコプレーナ型の伝送線路に近い形状にでき、より安定な状態で信号接続部材に高周波信号を通過させることができる。接地柱７を３本以上として信号接続部材６の周囲に配置した場合、その部分の高周波伝送線路形状が同軸線路の形状に近くなり、特性インピーダンス設定が容易となる。さらに、信号接続部材６の両側に接地柱７を配置することは、信号接続部材６が外乱の影響を受けにくくする効果がある。   Further, a signal connection member 6 and a grounding pillar 7 are arranged one by one, and a line having a shape close to a so-called slot line is disposed by sandwiching the signal connection member 6 between the two grounding pillars 7. The part of the member 6 can be shaped like a so-called coplanar transmission line, and a high-frequency signal can be passed through the signal connection member in a more stable state. When three or more grounding pillars 7 are arranged around the signal connection member 6, the shape of the high-frequency transmission line at that portion is close to the shape of the coaxial line, and the characteristic impedance setting is facilitated. Furthermore, disposing the grounding pillars 7 on both sides of the signal connection member 6 has an effect of making the signal connection member 6 less susceptible to disturbance.

次に、高周波用マルチチップモジュール基板のさらに他の例を説明する。図４（ａ）（ｂ）は接地導体層を信号ラインに近づけて接地導体層で信号接続部材を囲んだ構造の高周波用マルチチップモジュール基板を示す。この高周波用マルチチップモジュール基板１の誘電体基板２は、２層の誘電体材料層２１、２２から構成され、接地導体層４が、信号ライン３を配置した面と信号端子３１及び接地端子４１を配置した面との間にある誘電体材料２１、２２の接合面に配置され、信号接続部材６が、接地導体層４に設けられた開口４ａを貫通して設けられている。従って、信号接続部材６は接地導体層４によって囲まれた状態になっている。   Next, still another example of the high-frequency multichip module substrate will be described. 4A and 4B show a high-frequency multichip module substrate having a structure in which the ground conductor layer is brought close to the signal line and the signal connection member is surrounded by the ground conductor layer. The dielectric substrate 2 of the multi-chip module substrate 1 for high frequency is composed of two dielectric material layers 21 and 22, and the ground conductor layer 4 has a surface on which the signal line 3 is arranged, a signal terminal 31 and a ground terminal 41. The signal connection member 6 is provided through the opening 4 a provided in the ground conductor layer 4. Accordingly, the signal connection member 6 is surrounded by the ground conductor layer 4.

さらに、接地導体層４と接地端子４１は、誘電体材料層２２を貫通する接地接続部材４２によって接続され、接地導体層４の上部には接続部材４２に連続する位置に誘電体材料層２１を貫通する接地柱７が接続され、接地柱７の上端には調整板８が設けられている。接地接続部材４２と接地柱７は、信号接続部材６に略平行な略一直線上に配置されている。なお、接地導体層４の形状は、前出のいずれかの図に示した接地導体層に限られず、例えば、所定の特性インピーダンスが得られる場合には、図４（ｂ）に示すように、信号ラインの直下付近の狭い範囲に設ける形状であってもよい。   Further, the ground conductor layer 4 and the ground terminal 41 are connected by a ground connection member 42 penetrating the dielectric material layer 22, and the dielectric material layer 21 is placed on the ground conductor layer 4 at a position continuous with the connection member 42. A penetrating grounding pillar 7 is connected, and an adjustment plate 8 is provided at the upper end of the grounding pillar 7. The ground connection member 42 and the ground pillar 7 are arranged on a substantially straight line substantially parallel to the signal connection member 6. The shape of the ground conductor layer 4 is not limited to the ground conductor layer shown in any of the previous drawings. For example, when a predetermined characteristic impedance is obtained, as shown in FIG. The shape may be provided in a narrow range near the signal line.

上記構成によれば、信号接続部材６を接地導体（すなわち接地導体層）で取り囲むことができ、接地端子４１の数を増やすことがないので、複数の接地柱７を信号接続部材６の周囲に配置する（図３参照）場合よりも、全体を小さくした導体構造で高周波用マルチチップモジュール基板１を構成して同様の効果を得ることができる。また、信号端子３１及び接地端子４１を配置する面と接地導体層４の配置面とを分離することで、高周波用マルチチップモジュール基板の厚みによる設計上の制約を受けることなく接地導体層４を配置できるのでマイクロストリップラインの設計自由度が増す。つまり、より広範囲の形状及び種類の多層基板に対して、上述の特性インピーダンス適正化の構造を適用することができる。   According to the above configuration, the signal connection member 6 can be surrounded by the ground conductor (that is, the ground conductor layer), and the number of the ground terminals 41 is not increased. Therefore, the plurality of ground pillars 7 are arranged around the signal connection member 6. The same effect can be obtained by configuring the high-frequency multichip module substrate 1 with a conductor structure that is reduced in size as compared with the case of arranging (see FIG. 3). Further, by separating the surface on which the signal terminal 31 and the ground terminal 41 are disposed from the surface on which the ground conductor layer 4 is disposed, the ground conductor layer 4 can be formed without being restricted by the design due to the thickness of the multichip module substrate for high frequency. Since it can be arranged, the design freedom of the microstrip line is increased. That is, the characteristic impedance optimization structure described above can be applied to a wider range of shapes and types of multilayer substrates.

次に、高周波用マルチチップモジュール基板のさらに他の例を、図５（ａ）（ｂ）に示す。この高周波用マルチチップモジュール基板は、前出の図４に示したものと信号接続部材６の形状が異なったものである。すなわち、接地導体層４で囲まれている信号接続部材６の断面の外周長が一定ではなく、接地導体層４に近づくほど短くなっている。信号接続部材６は、接地導体層４の開口４ａ部分において細く、くびれた構造になっているので、この部分で信号接続部材６と接地導体層４（及び接地柱７）との距離が大きくなり、信号接続部材６が接地導体層４に近づくことによる特性インピーダンスの低下を抑制でき、より効果的に特性インピーダンスの適正化を図ることができる。   Next, still another example of the high-frequency multichip module substrate is shown in FIGS. This high-frequency multichip module substrate is different from that shown in FIG. 4 in the shape of the signal connection member 6. That is, the outer peripheral length of the cross section of the signal connection member 6 surrounded by the ground conductor layer 4 is not constant, and becomes shorter as it approaches the ground conductor layer 4. Since the signal connection member 6 has a narrow and narrow structure in the opening 4a portion of the ground conductor layer 4, the distance between the signal connection member 6 and the ground conductor layer 4 (and the ground column 7) increases in this portion. The reduction in characteristic impedance due to the signal connection member 6 approaching the ground conductor layer 4 can be suppressed, and the characteristic impedance can be optimized more effectively.

次に、高周波用マルチチップモジュール基板のさらに他の例を説明する。図６（ａ）（ｂ）は信号接続部材を誘電体基板の外周面に設けた構造の高周波用マルチチップモジュール基板を示す。この高周波用マルチチップモジュール基板１において、信号ライン３，調整板８，接地導体層４、信号端子３１、及び接地端子４１は前出の図１に示したものと同様に誘電体基板２の表面に設けられているが、信号接続部材６と接地柱７は、誘電体基板２の内部ではなく誘電体基板２の外周面に導体パターンとして形成されている。   Next, still another example of the high-frequency multichip module substrate will be described. 6A and 6B show a high-frequency multichip module substrate having a structure in which signal connection members are provided on the outer peripheral surface of a dielectric substrate. In this multi-chip module substrate 1 for high frequency, the signal line 3, the adjusting plate 8, the ground conductor layer 4, the signal terminal 31, and the ground terminal 41 are the same as those shown in FIG. The signal connection member 6 and the grounding pillar 7 are formed as conductor patterns not on the inside of the dielectric substrate 2 but on the outer peripheral surface of the dielectric substrate 2.

この構成において、接地柱７は、信号接続部材６と略平行に配置されており、接地柱７と信号接続部材６との間の距離を変更することで、信号接続部材６の（接地柱７に対する）特性インピーダンスを設定することができる。また、信号ライン３の信号接続部材６に接続されている付近と対向する誘電体基板２の反対側表面には接地導体層４がなく、代わりに信号端子３１と接地端子４１があり、従ってマイクロストリップラインが形成されていない。そこで、上述した同様の理由で（調整板８を加えない状態では信号ライン３の信号接続部材６付近の特性インピーダンスが高くなるのを抑制して、マイクロストリップライン部分の特性インピーダンスの大きさと合わせる）、信号ライン３と略平行になるように調整板８を配置して、特性インピーダンスを下げる調整が行われる。その結果、前述と同様に、（１）信号接続部材６と、（２）信号ライン３の信号接続部材６が接続される付近と、（３）信号ライン３のマイクロストリップラインを構成する部分との、それぞれの特性インピーダンスをほぼ同程度に揃えることができ、高周波信号がマルチチップモジュールを通過するときの波形品質の劣化を軽減することができる。   In this configuration, the ground pillar 7 is disposed substantially parallel to the signal connection member 6, and the distance between the ground pillar 7 and the signal connection member 6 is changed to change the (ground pillar 7 of the signal connection member 6. Characteristic impedance can be set. Further, there is no ground conductor layer 4 on the opposite surface of the dielectric substrate 2 facing the vicinity of the signal line 3 connected to the signal connection member 6, and instead there are a signal terminal 31 and a ground terminal 41, and therefore a micro The strip line is not formed. Therefore, for the same reason as described above (when the adjustment plate 8 is not added, the characteristic impedance of the signal line 3 in the vicinity of the signal connection member 6 is suppressed to match the magnitude of the characteristic impedance of the microstrip line portion). The adjustment plate 8 is arranged so as to be substantially parallel to the signal line 3, and adjustment for lowering the characteristic impedance is performed. As a result, in the same manner as described above, (1) the signal connection member 6, (2) the vicinity of the signal line 3 connected to the signal connection member 6, and (3) the portion constituting the microstrip line of the signal line 3 These characteristic impedances can be made substantially equal to each other, and deterioration of waveform quality when a high-frequency signal passes through the multichip module can be reduced.

また、図６に示した高周波用マルチチップモジュール基板１は、ＭＩＤ（ＭｏｌｄｅｄＩｎｔｅｒｃｏｎｎｅｃｔｅｄ Ｄｅｖｉｃｅ）等の工法を用いて、誘電体材料の外周に、信号接続部材６や接地柱７等の導体を面的な配線パターンとして高密度に形成できる。従って、誘電体基板内部に３次元的な導体構造を構成するよりも小型化した高周波用マルチチップモジュール基板を実現できる。   In addition, the high-frequency multichip module substrate 1 shown in FIG. 6 uses a method such as MID (Molded Interconnected Device) or the like to place conductors such as the signal connection member 6 and the grounding pillar 7 on the outer periphery of the dielectric material. It can be formed with high density as a wiring pattern. Therefore, it is possible to realize a high-frequency multichip module substrate that is smaller than a three-dimensional conductor structure in the dielectric substrate.

次に、高周波用マルチチップモジュール基板のさらに他の例を図７に示す。図７に示す高周波用マルチチップモジュール基板１は、前出の図６（ａ）〜（ｅ）に示した高周波用マルチチップモジュール基板１における接地導体層４を誘電体基板２の内部に設けたものである。２つの誘電体層２１，２２及び接地接続部材４２と接地柱７の配置、機能、及び作用は、前出の図４や図６に示した高周波用マルチチップモジュール基板１について説明したものと同様である。ただ、接地接続部材４２、接地柱７、及び信号接続部材６等の層間接続導体の構造が、スルーホールを略半分に割った状態で誘電体基板２の端面に設けられている端面スルーホールである点が前述のものと異なっている。   Next, still another example of the multichip module substrate for high frequency is shown in FIG. The high-frequency multichip module substrate 1 shown in FIG. 7 has a grounding conductor layer 4 in the high-frequency multichip module substrate 1 shown in FIGS. 6A to 6E provided inside the dielectric substrate 2. Is. The arrangement, function, and operation of the two dielectric layers 21 and 22 and the ground connection member 42 and the grounding pillar 7 are the same as those described for the high-frequency multichip module substrate 1 shown in FIGS. It is. However, the structure of the interlayer connection conductors such as the ground connection member 42, the ground pillar 7, and the signal connection member 6 is an end face through hole provided on the end face of the dielectric substrate 2 with the through hole substantially divided in half. There are some differences from the above.

この端面スルーホールを有する高周波用マルチチップモジュール基板１の製造には、通常のスルーホールを挟んで両側に一体形成された複数の高周波用マルチチップモジュール基板１を、スルーホール部分で切断して個片化する工法が用いられる。従って、このような高周波用マルチチップモジュール基板１は、通常の多層基板材料と同じ基板材料を用いて作ることが可能であり、材料による制限が少なく、マイクロストリップライン等の高周波線路の設計の自由度が大きいという利点がある。   In manufacturing the high-frequency multichip module substrate 1 having the end surface through-holes, a plurality of high-frequency multichip module substrates 1 integrally formed on both sides of the normal through-hole are cut at the through-hole portions. A method of separating pieces is used. Therefore, such a multi-chip module substrate 1 for high frequency can be manufactured using the same substrate material as a normal multilayer substrate material, and there are few restrictions by material, and freedom of design of high frequency lines, such as a microstrip line. There is an advantage that the degree is large.

次に、本発明の一実施形態に係るさらに他の高周波用マルチチップモジュール基板、及び半導体リレーについて、図８乃至図１０を参照して説明する。まずモジュール基板についてを説明し、その後、半導体リレーについて説明する。この高周波用マルチチップモジュール基板１１は、誘電体材料からなる誘電体ベース２０と、この誘電体ベース２０の表面に設けられたチップ接続用の高周波用信号ライン３Ａ，３Ｂと、接地導体層４と、親基板（不図示）への実装用の信号端子３１及び接地端子４１とを有し、信号ライン３Ａ，３Ｂと接地導体層４が、誘電体ベース２０を挟んで対をなして対向配置され、信号端子３１が、信号ライン端部（後述）３ｃに接続され、接地端子４１が、接地導体層端部（後述）４ｃに接続され、信号端子３１と接地端子４１とは、誘電体ベース２０表面の略同一面に配置されている。   Next, still another high-frequency multichip module substrate and semiconductor relay according to an embodiment of the present invention will be described with reference to FIGS. First, the module substrate will be described, and then the semiconductor relay will be described. The high-frequency multichip module substrate 11 includes a dielectric base 20 made of a dielectric material, high-frequency signal lines 3A and 3B for chip connection provided on the surface of the dielectric base 20, and a ground conductor layer 4. And a signal terminal 31 for mounting on a parent substrate (not shown) and a ground terminal 41, and the signal lines 3A and 3B and the ground conductor layer 4 are arranged to face each other with the dielectric base 20 in between. The signal terminal 31 is connected to a signal line end (described later) 3c, the ground terminal 41 is connected to a ground conductor layer end (described later) 4c, and the signal terminal 31 and the ground terminal 41 are connected to the dielectric base 20. They are arranged on substantially the same surface.

さらに、信号ライン３Ａ，３Ｂと接地導体層４の細部について述べる。信号ライン３Ａ，３Ｂと接地導体層４は誘電体ベース２０を挟んで対向しており、信号ライン３Ａ、３Ｂと接地導体層４は対をなしてマイクロストリップラインを構成している。信号ライン３Ａ，３Ｂは、それぞれ信号ライン中央部３ａと信号ライン屈曲部３ｂと信号ライン端部３ｃ４ｃとから構成されている。信号ライン屈曲部３ｂは、信号ライン中央部３ａと信号ライン端部３ｃとの間に位置している。また、接地導体層４は、接地導体層中央部４ａと接地導体層屈曲部４ｂと接地導体層端部４ｃとから構成されている。接地導体層屈曲部４ｂは、接地導体層中央部４ａと接地導体層端部４ｃとの間に位置している。   Further, details of the signal lines 3A and 3B and the ground conductor layer 4 will be described. The signal lines 3A and 3B and the ground conductor layer 4 are opposed to each other with the dielectric base 20 in between, and the signal lines 3A and 3B and the ground conductor layer 4 are paired to constitute a microstrip line. Each of the signal lines 3A and 3B includes a signal line center portion 3a, a signal line bent portion 3b, and a signal line end portion 3c4c. The signal line bent portion 3b is located between the signal line center portion 3a and the signal line end portion 3c. The ground conductor layer 4 includes a ground conductor layer central portion 4a, a ground conductor layer bent portion 4b, and a ground conductor layer end portion 4c. The ground conductor layer bent portion 4b is located between the ground conductor layer central portion 4a and the ground conductor layer end portion 4c.

そして、信号ライン屈曲部３ｂと接地導体層屈曲部４ｂは、略同心円状に屈曲している。信号ライン端部３ｃは、信号ライン中央部３ａと略垂直に位置している。接地導体層端部４ｃは、接地導体層中央部４ａと略垂直に位置している。信号ライン端部３ｃと接地導体層端部４ｃとの間の距離は、信号ライン中央部３ａと接地導体層中央部３ａとの間の距離と略同一である。信号ライン屈曲部３ｂと接地導体層屈曲部４ｂとの間の距離は、信号ライン中央部３ａと接地導体層中央部４ａとの間の距離と略同一である。   The signal line bent portion 3b and the ground conductor layer bent portion 4b are bent substantially concentrically. The signal line end 3c is positioned substantially perpendicular to the signal line center 3a. The ground conductor layer end 4c is positioned substantially perpendicular to the ground conductor layer center 4a. The distance between the signal line end 3c and the ground conductor layer end 4c is substantially the same as the distance between the signal line center 3a and the ground conductor layer center 3a. The distance between the signal line bent portion 3b and the ground conductor layer bent portion 4b is substantially the same as the distance between the signal line central portion 3a and the ground conductor layer central portion 4a.

従って、信号ライン３Ａ、３Ｂと接地導体層４（及び誘電体基板２０）とで構成されているマイクロストリップラインは、略同一断面構造となっており、その特性インピーダンスは全長にわたって略一定の値となっている。また、このような構成によると、信号ライン３Ａ，３Ｂと接地導体層４で構成する高周波伝送路の特性インピーダンスを所望の値、例えば７５Ωや５０Ωに設計することができる。高周波伝送路の全長にわたって（信号ライン中央部３ａ、信号ライン屈曲部３ｂ、信号ライン端部３ｃ）、略一様なマイクロストリップラインが形成されているので、高周波信号の波形品質が劣化し難い構造になっている。   Therefore, the microstrip line composed of the signal lines 3A and 3B and the ground conductor layer 4 (and the dielectric substrate 20) has substantially the same cross-sectional structure, and its characteristic impedance is a substantially constant value over the entire length. It has become. Further, according to such a configuration, the characteristic impedance of the high-frequency transmission line formed by the signal lines 3A and 3B and the ground conductor layer 4 can be designed to a desired value, for example, 75Ω or 50Ω. A substantially uniform microstrip line is formed over the entire length of the high-frequency transmission line (the signal line central portion 3a, the signal line bent portion 3b, and the signal line end portion 3c), so that the waveform quality of the high-frequency signal is unlikely to deteriorate. It has become.

このような、高周波用マルチチップモジュール基板１１は、ＭＩＤ等の工法を用いることにより製造可能である。すなわち、ＭＩＤ工法によると、平板基板を積層する通常の基板工法と異なり、信号ライン屈曲部３ｂや接地導体層屈曲部４ｂの構造を容易に形成することが可能である。そこで、前出の図１に示した高周波用マルチチップモジュール基板１における信号接続部材６及び接地柱７と調整板８に代わるものとして、信号ライン端部３ｃと接地導体層端部４ｃを設けることが可能であり、さらに、これらの信号ライン端部３ｃと接地導体層端部４ｃはマイクロストリップラインを構成するように形成することができる。このように、信号ライン端部３ｃに信号端子３１を直接接続でき、また、接地導体層端部４ｃに接地端子４１を信号接地部材や接地柱を用いることなく直接接続することができるので、親基板に接続するための端子部に至るまでマイクロストリップラインを延長して、高周波用マルチチップモジュール基板１１における高周波信号の波形品質の劣化を抑えることができる。さらに加えて、親基板に実装しやすい端子構造を保持した高周波用マルチチップモジュール基板１１を実現できる。   Such a high-frequency multichip module substrate 11 can be manufactured by using a method such as MID. That is, according to the MID method, the structure of the signal line bent portion 3b and the ground conductor layer bent portion 4b can be easily formed, unlike a normal substrate method in which flat substrates are laminated. Therefore, the signal line end portion 3c and the ground conductor layer end portion 4c are provided as an alternative to the signal connection member 6, the grounding pillar 7, and the adjusting plate 8 in the high-frequency multichip module substrate 1 shown in FIG. Furthermore, the signal line end 3c and the ground conductor layer end 4c can be formed to constitute a microstrip line. Thus, the signal terminal 31 can be directly connected to the signal line end 3c, and the ground terminal 41 can be directly connected to the ground conductor layer end 4c without using a signal grounding member or a grounding pillar. By extending the microstrip line to the terminal portion for connection to the substrate, it is possible to suppress the deterioration of the waveform quality of the high-frequency signal in the high-frequency multichip module substrate 11. In addition, it is possible to realize the high-frequency multichip module substrate 11 having a terminal structure that can be easily mounted on the parent substrate.

次に、上述の高周波用マルチチップモジュール基板１１を半導体リレーに適用した例を説明する。上記の高周波用マルチチップモジュール基板１１（図８）上には、入力信号に応じて光信号を発光する発光素子Ｐ１と、発光素子Ｐ１の光信号を受光して光起電力を発生する受光素子Ｐ２と、受光素子Ｐ２の光起電力がゲート・ソース間に印加されてドレイン・ソース間のインピーダンスが変化する出力用半導体素子（例えば、ＭＯＳＦＥＴ）Ｍ１，Ｍ２と、発光素子Ｐ１を実装する発光素子用回路パターン１３、１４と、受光素子Ｐ２を実装する受光素子用回路パターン１５，１６が備えられている。また、発光素子用回路パターン１３、１４には、それぞれ親基板に電気接続するための入力端子１７，１８が接続されている。図１０（ａ）に示すように、発光素子Ｐ１と受光素子Ｐ２は、ともに透明樹脂により封止され、その表面は、光を遮断する外部薄膜２４によって覆われている。さらに、図１０（ｂ）に示すように、外部封止部材２５が、透明樹脂を覆った外部薄膜２４と、出力用半導体素子Ｍ１、Ｍ２と、信号ライン３Ａ、３Ｂと、を一体に封止（パッケージング）して、高周波用半導体リレー１２が形成される。以下に、上述の各素子の実装形態、及び半導体リレー１２の動作について説明する。   Next, an example in which the above-described high-frequency multichip module substrate 11 is applied to a semiconductor relay will be described. On the high-frequency multichip module substrate 11 (FIG. 8), a light emitting element P1 that emits an optical signal according to an input signal, and a light receiving element that receives the optical signal of the light emitting element P1 and generates a photovoltaic force. P2 and output semiconductor elements (for example, MOSFETs) M1 and M2 in which the impedance between the drain and the source changes when the photoelectromotive force of the light receiving element P2 is applied between the gate and the source, and the light emitting element on which the light emitting element P1 is mounted Circuit patterns 13 and 14 and light receiving element circuit patterns 15 and 16 on which the light receiving element P2 is mounted. The light emitting element circuit patterns 13 and 14 are connected to input terminals 17 and 18 for electrical connection to the parent substrate, respectively. As shown in FIG. 10A, both the light emitting element P1 and the light receiving element P2 are sealed with a transparent resin, and the surfaces thereof are covered with an external thin film 24 that blocks light. Furthermore, as shown in FIG. 10B, the external sealing member 25 integrally seals the external thin film 24 covered with the transparent resin, the output semiconductor elements M1 and M2, and the signal lines 3A and 3B. (Packaging) is performed to form the high-frequency semiconductor relay 12. Below, the mounting form of each element described above and the operation of the semiconductor relay 12 will be described.

まず、上述の各素子の実装形態について説明する（図８参照）。発光素子Ｐ１は、発光ダイオードとして表裏に電極を有している。その裏面電極は、導電性ボンディング材によって発光素子用回路パターン１３に電気接続され、表面電極はワイヤＷ１によって発光素子用回路パターン１４に電気接続されている。   First, the mounting form of each element described above will be described (see FIG. 8). The light emitting element P1 has electrodes on both sides as a light emitting diode. The back electrode is electrically connected to the light emitting element circuit pattern 13 by a conductive bonding material, and the front electrode is electrically connected to the light emitting element circuit pattern 14 by a wire W1.

受光用素子Ｐ２は、裏面にソース用電極、表面にゲート用電極を有している。裏面のソース用電極は、導電性ボンディング材によって受光素子用回路パターン（ソース用パターン）１５に電気接続され、受光素子Ｐ２の表面のゲート用電極は、ワイヤＷ２によって受光素子用回路パターン（ゲート用パターン）１６に電気接続されている。   The light receiving element P2 has a source electrode on the back surface and a gate electrode on the front surface. The source electrode on the back surface is electrically connected to the light receiving element circuit pattern (source pattern) 15 by a conductive bonding material, and the gate electrode on the surface of the light receiving element P2 is connected to the light receiving element circuit pattern (for gate) by the wire W2. Pattern) 16 is electrically connected.

ＭＯＳＦＥＴからなる出力用半導体素子Ｍ１，Ｍ２は、裏面にドレイン電極、表面にゲート電極及びソース電極を有している。裏面の各ドレイン電極は、導電性ボンディング材によって信号ライン３Ａ，３Ｂに電気接続され、表面の各ゲート電極は、ゲートワイヤＷ５，Ｗ６によって受光素子用回路パターン１６に電気接続されている。また、出力用半導体素子Ｍ１表面のソース電極は、ソースワイヤＷ３によって受光素子用回路パターン１５に電気接続されるとともに、ソースワイヤＷ４によって出力用半導体素子Ｍ２の表面のソース電極に電気接続されている。   The output semiconductor elements M1 and M2 made of MOSFET have a drain electrode on the back surface and a gate electrode and a source electrode on the surface. The drain electrodes on the back surface are electrically connected to the signal lines 3A and 3B by a conductive bonding material, and the gate electrodes on the front surface are electrically connected to the light receiving element circuit pattern 16 by gate wires W5 and W6. Further, the source electrode on the surface of the output semiconductor element M1 is electrically connected to the light receiving element circuit pattern 15 by the source wire W3 and is electrically connected to the source electrode on the surface of the output semiconductor element M2 by the source wire W4. .

発光素子Ｐ１と受光素子Ｐ２は光信号を効率良く授受できるように対向して配置されている。これらは透明樹脂で封止され、その透明樹脂の表面は光を遮断する外部薄膜２４によって覆われている（図１０）。透明樹脂を覆った外部薄膜２４を含む誘電体基板２０上の出力用半導体素子Ｍ１，Ｍ２及び各回路パターンの一部は、耐湿性及び遮光性を有する封止樹脂２５で封止され、一体化したパッケージとして半導体リレー１２が形成される。   The light emitting element P1 and the light receiving element P2 are arranged to face each other so that an optical signal can be exchanged efficiently. These are sealed with a transparent resin, and the surface of the transparent resin is covered with an external thin film 24 that blocks light (FIG. 10). The output semiconductor elements M1 and M2 on the dielectric substrate 20 including the external thin film 24 covered with the transparent resin and a part of each circuit pattern are sealed and integrated with a sealing resin 25 having moisture resistance and light shielding properties. A semiconductor relay 12 is formed as the package.

次に、半導体リレー１２の電気回路的な構成を、図１１に示す回路図を参照して説明する。半導体リレー１２の電気回路において、発光素子Ｐ１の発光部Ｄ１は、例えば、発光ダイオードである。受光用素子Ｐ２は、複数のフォトダイオード（受光部）Ｄ２を直列接続したフォトダイオードアレイと充放電制御回路９とを一体化して構成されている。充放電制御回路９はフォトダイオードアレイが光起電力を発生しているときに、その起電力によって出力用半導体（ＭＯＳＦＥＴ）Ｍ１，Ｍ２の各ゲート・ソース電極間に効率よく電荷を充電できるよう制御する。また、充放電制御回路９は、フォトダイオードアレイが光起電力を発生していないときは、各ゲート・ソース電極間に充電された電荷の放電経路になる。   Next, the electrical circuit configuration of the semiconductor relay 12 will be described with reference to the circuit diagram shown in FIG. In the electric circuit of the semiconductor relay 12, the light emitting part D1 of the light emitting element P1 is, for example, a light emitting diode. The light receiving element P2 is configured by integrating a photodiode array in which a plurality of photodiodes (light receiving portions) D2 are connected in series with the charge / discharge control circuit 9. The charge / discharge control circuit 9 performs control so that charges can be efficiently charged between the gate and source electrodes of the output semiconductors (MOSFETs) M1 and M2 by the electromotive force when the photodiode array generates the photoelectromotive force. To do. The charge / discharge control circuit 9 serves as a discharge path for charges charged between the gate and source electrodes when the photodiode array does not generate photovoltaic power.

次に、上記構成された半導体リレー１２の動作を説明する。引き続いて、図１１の回路図を参照する。入力端子ａ（１７：図８における入力端子１７に対応、以下同様），ｂ（１８）間に入力信号が入力されると、発光素子Ｐ１の発光部Ｄ１が光信号を発光する。この発光信号は、受光素子Ｐ２の受光部Ｄ２によって受光される。受光部Ｄ２は、発光素子Ｐ１の発光した光信号を受光することにより、光起電力を発生する。光起電力は充放電制御回路９を介して、ゲート用端子ｃ、ソース用端子ｄへと出力される。出力用半導体素子Ｍ１，Ｍ２のゲートｆ，ｅとソースｓ、ｓ間に光起電力が印加されると、ゲート・ソース間が充電され、出力用半導体素子Ｍ１のドレインｉ・ソースｓ間、及び出力用半導体素子５のドレインｈ・ソースｓ間が導通する。従って、信号ラインｉ（３Ａ），ｈ（３Ｂ）間が導通する（リレー閉）。   Next, the operation of the semiconductor relay 12 configured as described above will be described. Subsequently, the circuit diagram of FIG. 11 will be referred to. When an input signal is input between the input terminal a (17: corresponding to the input terminal 17 in FIG. 8, the same applies hereinafter) and b (18), the light emitting portion D1 of the light emitting element P1 emits an optical signal. This light emission signal is received by the light receiving portion D2 of the light receiving element P2. The light receiving part D2 generates a photovoltaic power by receiving the optical signal emitted from the light emitting element P1. The photovoltaic power is output to the gate terminal c and the source terminal d via the charge / discharge control circuit 9. When a photovoltaic force is applied between the gates f and e of the output semiconductor elements M1 and M2 and the sources s and s, the gate and the source are charged, and between the drain i and the source s of the output semiconductor element M1, and The drain h and the source s of the output semiconductor element 5 are electrically connected. Therefore, the signal lines i (3A) and h (3B) are electrically connected (relay closed).

入力端子ａ（１７），ｂ（１８）間に信号の入力がなくなると、発光素子Ｐ１が光信号を発光しなくなり、受光素子Ｐ２が光起電力を発生しなくなる。出力用半導体素子Ｍ１，Ｍ２のゲート・ソース間に充電されていた電荷が、充放電制御回路９を介して放電され、出力用半導体素子Ｍ１，Ｍ２のドレイン・ソース間が遮断され、信号ラインｉ（３Ａ），ｈ（３Ｂ）間が遮断される（リレー開）。このような半導体リレー１２によれば、一方の信号端子から他方の信号端子までの全長にわたって特性インピーダンスの整合が可能であり、波形品質の劣化の少ない高周波信号の開閉を実現できる。   When there is no signal input between the input terminals a (17) and b (18), the light emitting element P1 does not emit an optical signal, and the light receiving element P2 does not generate photovoltaic power. The charge charged between the gate and source of the output semiconductor elements M1 and M2 is discharged through the charge / discharge control circuit 9, and the drain and source of the output semiconductor elements M1 and M2 are interrupted, and the signal line i (3A) and h (3B) are disconnected (relay open). According to such a semiconductor relay 12, it is possible to match the characteristic impedance over the entire length from one signal terminal to the other signal terminal, and it is possible to realize opening and closing of a high-frequency signal with little deterioration in waveform quality.

次に、本発明の一実施形態に係るさらに他の半導体リレーについて説明する。図１２（ａ）（ｂ）（ｃ）は接地柱７と調整板８を備えた構造の伝送線路を有する半導体リレー１３を示す（ただし、封止樹脂及び誘電体部分は不図示）。この半導体リレー１３に用いられている高周波用マルチチップモジュール基板は、前出の図４に示したように、２つの誘電体材料層２１，２２間に接地導体層４を備え、また、接地接続部材４２と接地柱７を略直線状に配置して備え、さらに接地柱７の先端には調整板８を備えており、マイクロストリップラインを構成している信号ライン３Ａ、３Ｂの部分だけでなく、信号端子３１付近まで特性インピーダンス整合が行われている。このモジュール基板に、上述の半導体リレー１２と同様に、各素子を実装、封止して半導体リレーが形成される。半導体リレー１３の回路構成及び回路動作は、上述の半導体リレー１２と同様であり、高周波信号の波形品質の劣化の少ない半導体リレーが実現される。   Next, still another semiconductor relay according to an embodiment of the present invention will be described. 12A, 12B, and 12C show a semiconductor relay 13 having a transmission line having a structure including a grounding pillar 7 and an adjusting plate 8 (however, a sealing resin and a dielectric portion are not shown). The multi-chip module substrate for high frequency used in the semiconductor relay 13 includes a ground conductor layer 4 between two dielectric material layers 21 and 22 as shown in FIG. The member 42 and the grounding pillar 7 are arranged in a substantially straight line, and further, an adjustment plate 8 is provided at the tip of the grounding pillar 7, and not only the signal lines 3A and 3B constituting the microstrip line. The characteristic impedance matching is performed up to the vicinity of the signal terminal 31. Similar to the semiconductor relay 12 described above, each element is mounted and sealed on the module substrate to form a semiconductor relay. The circuit configuration and circuit operation of the semiconductor relay 13 are the same as those of the semiconductor relay 12 described above, and a semiconductor relay in which the waveform quality of the high-frequency signal is less deteriorated is realized.

なお、上述した図１乃至図７において、基板全体を図示せずに端子部及び信号ラインに注目してこれらの主要部を含む部分のみを示して説明しているが、本発明はこのような主要部を有する高周波用マルチチップモジュール基板全体を含むものである。誘電体材料層や誘電体基板を貫通する信号接続部材、接地柱、接地接続部材等は、内面をめっきにより導体化したスルーホールであってもよく、また、貫通孔に導電性材料を充填して構成したものでものよい。また、接地接続部材と接地柱は必ずしも同一直線上に配置される必要はなく、また、同一断面形状である必要はない。また、本発明は、上記説明で示した構成の端子数や信号ライン数、実装できる素子数、モジュール基板形状等に限られることなく種々の変形が可能である。   In FIGS. 1 to 7 described above, the entire substrate is not shown, but only the portions including these main portions are shown by focusing on the terminal portions and signal lines. However, the present invention is not limited to this. The whole multi-chip module substrate for high frequency having a main part is included. The signal connection member, the grounding pillar, and the ground connection member that penetrate the dielectric material layer and the dielectric substrate may be through holes whose inner surfaces are made conductive by plating, and the through holes are filled with a conductive material. It may be configured. Further, the ground connection member and the ground pillar need not be arranged on the same straight line, and need not have the same cross-sectional shape. The present invention is not limited to the number of terminals, the number of signal lines, the number of elements that can be mounted, the shape of the module substrate, and the like, and can be variously modified.

（ａ）は本発明の一実施形態に係る高周波用マルチチップモジュール基板を親基板に実装した状態を示す斜視図、（ｂ）は同モジュール基板の導体部分のみを示した斜視図、（ｃ）は同モジュール基板の下面斜視図、（ｄ）同モジュール基板の導体部分のみを示した下面斜視図。(A) is a perspective view showing a state in which a high-frequency multichip module substrate according to an embodiment of the present invention is mounted on a parent substrate, (b) is a perspective view showing only a conductor portion of the module substrate, (c) FIG. 3 is a bottom perspective view of the module substrate, and (d) a bottom perspective view showing only a conductor portion of the module substrate. （ａ）は本発明の一実施形態に係る高周波用マルチチップモジュール基板の他の例を示す斜視図、（ｂ）は同モジュール基板の導体部分のみを示した斜視図。(A) is the perspective view which shows the other example of the multichip module board for high frequency which concerns on one Embodiment of this invention, (b) is the perspective view which showed only the conductor part of the module board. （ａ）は本発明の一実施形態に係る高周波用マルチチップモジュール基板のさらに他の例を示す斜視図、（ｂ）は同モジュール基板の導体部分のみを示した斜視図。(A) is a perspective view which shows the other example of the multichip module board for high frequency which concerns on one Embodiment of this invention, (b) is the perspective view which showed only the conductor part of the module board. （ａ）は本発明の一実施形態に係る高周波用マルチチップモジュール基板のさらに他の例を示す斜視図、（ｂ）は同モジュール基板の導体部分のみを示した斜視図。(A) is a perspective view which shows the other example of the multichip module board for high frequency which concerns on one Embodiment of this invention, (b) is the perspective view which showed only the conductor part of the module board. （ａ）は本発明の一実施形態に係る高周波用マルチチップモジュール基板のさらに他の例を示す斜視図、（ｂ）は同モジュール基板の導体部分のみを示した斜視図。(A) is a perspective view which shows the other example of the multichip module board for high frequency which concerns on one Embodiment of this invention, (b) is the perspective view which showed only the conductor part of the module board. （ａ）は本発明の一実施形態に係る高周波用マルチチップモジュール基板のさらに他の例を示す斜視図、（ｂ）は同モジュール基板の導体部分のみを示した斜視図。(A) is a perspective view which shows the other example of the multichip module board for high frequency which concerns on one Embodiment of this invention, (b) is the perspective view which showed only the conductor part of the module board. （ａ）は本発明の一実施形態に係る高周波用マルチチップモジュール基板のさらに他の例を示す斜視図、（ｂ）は同モジュール基板の導体部分のみを示した斜視図、（ｃ）〜（ｅ）は同モジュール基板の導体層の平面図。(A) is a perspective view showing still another example of the multi-chip module substrate for high frequency according to an embodiment of the present invention, (b) is a perspective view showing only the conductor portion of the module substrate, (c) ~ ( e) is a plan view of a conductor layer of the module substrate. （ａ）は半導体リレー用にチップを実装した本発明の一実施形態に係る高周波用マルチチップモジュール基板のさらに他の例を示す斜視図、（ｂ）は同モジュール基板から誘電体部分を除いた斜視図、（ｃ）は同モジュール基板の接地導体層の斜視図、（ｄ）は同モジュール基板の接地導体層を除いた導体及び実装状態素子の斜視図。(A) is a perspective view which shows the further another example of the multichip module board for high frequency based on one Embodiment of this invention which mounted the chip | tip for semiconductor relays, (b) removed the dielectric part from the module board | substrate. FIG. 4C is a perspective view of a ground conductor layer of the module substrate, and FIG. 4D is a perspective view of a conductor and a mounted state element excluding the ground conductor layer of the module substrate. （ａ）は同上モジュール基板の下面斜視図、（ｂ）は同上モジュール基板の断面図。(A) is a lower surface perspective view of a module board same as the above, (b) is sectional drawing of a module board same as the above. （ａ）は同上モジュール基板のチップ実装状態斜視図、（ｂ）は同上モジュール基板を用いて構成した半導体リレーの外観斜視図。(A) is a chip mounting state perspective view of the same module substrate, (b) is an external perspective view of a semiconductor relay configured using the module substrate. 図８に示した構成の半導体リレーの回路図。FIG. 9 is a circuit diagram of the semiconductor relay having the configuration shown in FIG. 8. （ａ）は半導体リレー用にチップを実装した本発明の一実施形態に係る高周波用マルチチップモジュール基板のさらに他の例を示す斜視図、（ｂ）（ｃ）は同モジュール基板から誘電体部分を除いた斜視図。(A) is a perspective view which shows the further another example of the multichip module board for high frequencies based on one Embodiment of this invention which mounted the chip | tip for semiconductor relays, (b) (c) is a dielectric part from the module board | substrate. FIG.

符号の説明Explanation of symbols

１，１１ 高周波用マルチチップモジュール基板
２ 誘電体基板
３，３Ａ，３Ｂ 信号ライン
４ 接地導体層
５ 親基板
６ 信号接続部材
７ 接地柱
８ 調整板
１２，１３ 半導体リレー
２０ 誘電体ベース
２１，２２ 誘電体材料層
３１ 信号端子
４１ 接地端子
３ａ 信号ライン中央部
３ｃ 信号ライン端部
４ａ 接地導体層中央部
４ｃ 接地導体層端部
Ｐ１ 発光素子
Ｐ２ 受光素子
Ｍ１，Ｍ２ 出力用半導体素子
１３，１４ 発光素子用回路パターン
１５，１６ 受光素子用回路パターン DESCRIPTION OF SYMBOLS 1,11 Multichip module substrate for high frequency 2 Dielectric substrate 3, 3A, 3B Signal line 4 Ground conductor layer 5 Parent substrate 6 Signal connection member 7 Grounding pillar 8 Adjustment plate 12, 13 Semiconductor relay 20 Dielectric base 21, 22 Dielectric Body material layer 31 Signal terminal 41 Ground terminal 3a Signal line center 3c Signal line end 4a Ground conductor layer center 4c Ground conductor layer end P1 Light emitting element P2 Light receiving element M1, M2 Output semiconductor element 13, 14 For light emitting element Circuit pattern 15, 16 Light receiving element circuit pattern

Claims (9)

誘電体材料からなる誘電体基板と、この誘電体基板の一方の面に設けられたチップ接続用の高周波用信号ラインと、前記信号ラインの設けられた面とは異なる誘電体基板の面に設けられた接地導体層と、親基板への実装用の信号端子及び接地端子とを有し、
前記信号ラインと信号端子とは信号接続部材によって電気的に接続され、
前記接地導体層と接地端子とは電気的に接続して接地電位とされ、
前記信号ラインと接地導体層とは対をなして高周波信号伝送用のマイクロストリップラインを構成して成る高周波用マルチチップモジュール基板において、
前記接地導体層に電気的に接続された接地柱を有し、
前記接地柱は、前記信号接続部材と略平行に配置され、
前記信号端子と接地端子とは、前記誘電体基板の略同一面に配置されていることを特徴とする高周波用マルチチップモジュール基板。 A dielectric substrate made of a dielectric material, a high-frequency signal line for chip connection provided on one surface of the dielectric substrate, and a surface of the dielectric substrate different from the surface on which the signal line is provided A grounding conductor layer, a signal terminal and a grounding terminal for mounting on the parent substrate,
The signal line and the signal terminal are electrically connected by a signal connection member,
The ground conductor layer and the ground terminal are electrically connected to a ground potential,
In the multi-chip module substrate for high frequency formed by forming a microstrip line for high-frequency signal transmission by pairing the signal line and the ground conductor layer,
A grounding column electrically connected to the grounding conductor layer;
The grounding pillar is disposed substantially parallel to the signal connection member,
The multi-chip module substrate for high frequency, wherein the signal terminal and the ground terminal are disposed on substantially the same surface of the dielectric substrate. 前記接地柱に接続された調整板をさらに備え、前記調整板は前記信号ラインの配置された前記誘電体基板の面と略同一面に配置されていることを特徴とする請求項１に記載の高周波用マルチチップモジュール基板。   The adjustment plate according to claim 1, further comprising an adjustment plate connected to the grounding pillar, wherein the adjustment plate is arranged substantially on the same plane as the surface of the dielectric substrate on which the signal lines are arranged. Multi-chip module substrate for high frequency. 前記信号接続部材を接続している部分の信号ラインの線幅が、マイクロストリップラインを構成している部分の信号ラインの線幅よりも広いことを特徴とする請求項１又は請求項２に記載の高周波用マルチチップモジュール基板。   3. The line width of a signal line in a portion connecting the signal connection members is wider than a line width of a signal line in a portion constituting a microstrip line. Multi-chip module substrate for high frequency. 前記信号接続部材の断面の外周長が、前記接地導体層に近づくにつれて短くなることを特徴とする請求項１乃至請求項３のいずれかに記載の高周波用マルチチップモジュール基板。   The multichip module substrate for high frequency according to any one of claims 1 to 3, wherein an outer peripheral length of a cross section of the signal connection member becomes shorter as approaching the ground conductor layer. 前記接地柱が、信号接続部材の周囲に複数本配置されていることを特徴とする請求項１乃至請求項４のいずれかに記載の高周波用マルチチップモジュール基板。   5. The multichip module substrate for high frequency according to claim 1, wherein a plurality of the ground pillars are arranged around the signal connection member. 6. 前記誘電体基板は、２層以上の誘電体材料層からなり、
前記接地導体層が、前記信号ラインを配置した面と前記接地端子及び信号端子を配置した面との間に配置され、
前記信号接続部材は、前記接地導体層によって囲まれていることを特徴とする請求項１乃至請求項５のいずれかに記載の高周波用マルチチップモジュール基板。 The dielectric substrate comprises two or more dielectric material layers,
The ground conductor layer is disposed between the surface on which the signal line is disposed and the surface on which the ground terminal and the signal terminal are disposed;
The high-frequency multichip module substrate according to claim 1, wherein the signal connection member is surrounded by the ground conductor layer. 前記接地柱が、前記誘電体基板の外周面に配置されていることを特徴とする請求項１乃至請求項５のいずれかに記載の高周波用マルチチップモジュール基板。   6. The multichip module substrate for high frequency according to claim 1, wherein the grounding pillar is disposed on an outer peripheral surface of the dielectric substrate. 誘電体材料からなる誘電体ベースと、この誘電体ベースの表面に設けられたチップ接続用の高周波用信号ラインと、接地導体層と、親基板への実装用の信号端子及び接地端子とを有し、
前記信号ラインと接地導体層が、誘電体ベースを挟んで対をなして対向配置されて成る高周波用マルチチップモジュール基板において、
前記信号ラインは、互いに略垂直に位置する信号ライン端部と信号ライン中央部とを有し、
前記接地導体層は、互いに略垂直に位置する接地導体層端部と接地導体層中央部とを有し、
前記信号ライン中央部と接地導体層中央部の対、及び前記信号ライン端部と接地導体層端部の対は、それぞれマイクロストリップラインを形成し、
前記信号端子は、前記信号ライン端部に接続され、
前記接地端子は、前記接地導体層端部に接続され、
前記信号端子と接地端子とは、前記誘電体ベース表面の略同一面に配置されていることを特徴とする高周波用マルチチップモジュール基板。 A dielectric base made of a dielectric material, a high-frequency signal line for chip connection provided on the surface of the dielectric base, a ground conductor layer, and a signal terminal and a ground terminal for mounting on the parent substrate are provided. And
In the high-frequency multichip module substrate in which the signal line and the ground conductor layer are arranged to face each other with a dielectric base interposed therebetween,
The signal line has a signal line end portion and a signal line center portion which are positioned substantially perpendicular to each other,
The ground conductor layer has a ground conductor layer end portion and a ground conductor layer center portion positioned substantially perpendicular to each other,
The signal line center and ground conductor layer center pair, and the signal line end and ground conductor layer end pair each form a microstrip line,
The signal terminal is connected to the signal line end,
The ground terminal is connected to the end of the ground conductor layer,
The multi-chip module substrate for high frequency, wherein the signal terminal and the ground terminal are disposed on substantially the same surface of the dielectric base surface. 請求項１乃至請求項８のいずれかに記載の高周波用マルチチップモジュール基板上に、
入力信号に応じて光信号を発光する発光素子と、
前記発光素子の光信号を受光して光起電力を発生する受光素子と、
前記受光素子の光起電力がゲート・ソース間に印加されてドレイン・ソース間のインピーダンスが変化する出力用半導体素子と、
前記発光素子を実装する発光素子用回路パターンと、
前記受光素子を実装する受光素子用回路パターンとを備え、
前記基板上に設けられた信号ラインが第１の信号ラインと第２の信号ラインとから成り、前記出力用半導体素子が前記信号ライン間に実装され、該出力用半導体素子のドレイン・ソース間のインピーダンス変化により前記信号ライン間の線路が開閉されることを特徴とする半導体リレー。
On the high-frequency multichip module substrate according to any one of claims 1 to 8,
A light emitting element that emits an optical signal in response to an input signal;
A light receiving element that receives a light signal of the light emitting element and generates a photovoltaic force;
An output semiconductor element in which the photoelectromotive force of the light receiving element is applied between the gate and the source to change the impedance between the drain and the source; and
A light emitting element circuit pattern for mounting the light emitting element;
A light receiving element circuit pattern for mounting the light receiving element,
The signal line provided on the substrate is composed of a first signal line and a second signal line, the output semiconductor element is mounted between the signal lines, and between the drain and source of the output semiconductor element A semiconductor relay, wherein a line between the signal lines is opened and closed by an impedance change.
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