JPH11195731A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the monolithic microwave IC(MMIC) of a small parasitic effect for hardly causing resonance and unrequited oscillation even if flip chip mounting is performed and to surely mount the MMIC and an millimeter-wave flip-chip IC(MFIC). SOLUTION: A GND plane 12, a dielectric film 13 and a first wiring pattern 14 are successively formed on the main surface of a substrate 11, composed of Si or the like and a microstrip line is constituted of the first wiring pattern 14, the dielectric film 13 and the GND plane 12. On the substrate 11, an MMIC chip 11 for which a high frequency transistor and a second wiring pattern 21 are formed on an element formation surface is fixed by using an MBB method, while making the element formation surface and the main surface of the substrate 11 face opposite to each other. In the MMIC chip 22, the microstrip line is constituted of the second wiring parttern 21 and the dielectric film 13 and the GND plane 12 provided on the substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for high frequencies from a quasi-millimeter wave band to a millimeter wave band, and more particularly to a semiconductor device for reducing a parasitic effect.

[0002]

2. Description of the Related Art In recent years, the technology in the field of information communication has been remarkably advanced, and the frequency band handled by communication devices has been expanded from a microwave band to a millimeter wave band to a higher frequency band. Along with this, the speed of transistor elements used in communication equipment has been remarkably increased. Recently, devices having a cutoff frequency exceeding 100 GHz have been realized in heterojunction transistor elements using compound semiconductors of III-V group or the like. I have. However, in a communication device that handles such a high-frequency band from the microwave band to the millimeter wave band, a method of mounting a semiconductor chip forming a circuit becomes a problem similarly to the element characteristics of a transistor. For example, a new parasitic capacitance or parasitic inductance (= parasitic reactance) often occurs in a circuit after a mounting process, and the influence of the parasitic reactance on a communication device is large in proportion to the frequency handled by the communication device. Therefore, it is necessary to suppress the parasitic reactance component as the frequency increases. Also, in communication equipment that handles the frequency band from the microwave band to the millimeter wave band, the dimensions of the elements that constitute the circuit or the connecting parts that connect the circuits are close to the wavelength of the signal. When performing this, it is necessary to sufficiently consider the dimensions of the connecting parts.

As a first conventional example, a technique for solving such a problem is an MMIC (== MMIC) in which a transistor element and a passive circuit are formed on a semiconductor substrate by using a semiconductor process.
Monolithic Microwave IC). In this MMIC, a transistor and a peripheral circuit are integrated on one semiconductor chip, and the integration reduces the number of connection components, thereby reducing a parasitic reactance component. In addition, since a semiconductor process excellent in fine processing is used, high-precision processing can be realized, and a reduction in manufacturing cost can be expected due to a mass production effect of the semiconductor process.

Further, as a second conventional example, a document "The Institute of Electronics, Information and Communication Engineers, Autumn 1994," which realizes a semiconductor integrated circuit from a quasi-millimeter-wave band to a millimeter-wave band, which has a further low cost, high performance, and a wide application range. Conference Papers 39
Section ”and the like, the MFIC (Millimeter-
wave Flip-chip IC). This M
FIC uses a micro-bump bonding method (hereinafter referred to as MB
Called method B. This is an IC module technology that suppresses parasitic effects by using a flip-chip mounting method called “flip-chip mounting method”, which ensures high design flexibility while utilizing the precision and mass productivity of semiconductor processes, and provides high-performance millimeter-wave band semiconductor ICs. Is realized at low cost.

A MFIC according to a second conventional example will be described below with reference to the drawings.

FIG. 10 shows a cross-sectional structure of a conventional MFIC. As shown in FIG. 10, a substrate 10 made of Si or the like is provided.
1, a GND plane 102 made of Au, a dielectric film 103 made of SiO _2, and a wiring pattern 104 made of a conductive film are sequentially formed.
4. A microstrip line is formed by the dielectric film 103 and the GND plane 102. On the wiring pattern 104 on the substrate 101, a semiconductor chip 105 made of a compound semiconductor or the like and having a high-frequency transistor is formed on the element forming surface by the wiring pattern 104.
And is fixed using a photocurable insulating resin 106. Electrode pads 107 are selectively formed on the element forming surface of the semiconductor chip 105, and bonding pads 104 a are selectively formed on the wiring pattern 104, and are electrically connected to each other via micro bumps 108.

Thus, the MFIC according to the second conventional example
Can reduce the thickness of the bump 108 to several μm.
The parasitic inductor component of the bump 108 can be neglected. Further, since the wiring pattern 104 can be manufactured using a semiconductor process, patterning with much higher precision can be realized as compared with an ordinary hybrid IC in which wiring is performed on an alumina substrate or the like by using a printing technique. Further, an MMI according to a first conventional example using a similar semiconductor process.
Compared with C, this MFIC can form a passive circuit not on a compound semiconductor substrate but on an inexpensive substrate 101 made of Si or the like, so that the cost can be significantly reduced.

[0008]

However, in the MMIC according to the first conventional example, it is extremely difficult at present to integrate all the circuits of the communication device into a one-chip semiconductor IC. It is necessary to divide all the circuits of the communication device into several MMICs, provide different functions to each of the divided MMICs, and configure a predetermined circuit by combining the MMICs.

Therefore, flip-chip mounting has been attempted as a mounting method of the MMIC. For flip-chip mounting of the MMIC, for example, a document “IEICE 19
1997 General Conference Lecture Papers Electronics 1 Volume
Page 68 (lecture number C-2-13) ". This problem will be described with reference to the drawings.

FIG. 11 shows a sectional structure of a semiconductor device in which a conventional MMIC is flip-chip mounted. As shown in FIG. 11, a first wiring pattern 112 is formed on a main surface of an insulating substrate 111, and a first GND plane 113 is formed on a surface opposite to the main surface. A first microstrip line is formed by the first ground plane 112 and the first GND plane 113, and the first wiring pattern 112 is grounded through a first via hole 114 appropriately provided in the insulating substrate 111.

On the main surface of the insulating substrate 111, an MMIC chip 115 whose element forming surface is opposed to the main surface has bumps 1 formed thereon.
16 are interposed. MMIC chip 11
No. 5, a high-frequency transistor (not shown) and a second wiring pattern 117 are formed on the element forming surface, and a second wiring pattern 117 and a second microstrip line are formed on the surface opposite to the element forming surface. Second GND plane 1
The second wiring pattern 117 is grounded through a second via hole 119 appropriately provided in the substrate.

As described above, the flip-chip mounting using the conventional MMIC 115 is performed by using the insulating substrate 111 and the MMI.
Each of the C chips 115 is a GND plane 113, 1
18, which are spatially separated from each other, so that the ground potential is not stabilized, and there is a risk that unexpected troubles such as resonance and unnecessary oscillation may occur. Also, as shown in FIG. 11, a pseudo closed space including a first GND plane 113, a first via hole 114, a first wiring 112, a bump 116, a second via hole 119, and a second GND plane 118. This closed space is easily excited by a signal propagating in the microstrip line and causes cavity resonance. As a result, when the resonance frequency of the cavity resonance approaches the used frequency depending on the materials and dimensions of the insulating substrate 111 and the MMIC chip 115, there is a problem that the circuit operation is unexpectedly greatly affected. .

On the other hand, in the MFIC shown in FIG.
At present, it is impossible to integrate all the circuits of the communication device on the substrate 101. Like the above-mentioned MMIC, it is integrated into one MFIC for each function, and these MFICs having different functions are connected to each other. A method of realizing the function of the entire circuit by connecting them is realistic. Therefore, like the MMIC, the MFIC chips or the MFIC chips
How to connect the IC chip to another substrate remains unresolved. Moreover, as shown in FIG.
Unlike the MIC chip, the MFIC chip has a problem that the semiconductor chip 105 is already provided on the substrate 101, so that it cannot be mounted only by extension of the MMIC technology.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is a first object of the present invention to provide an MMIC which is less likely to cause resonance or unnecessary oscillation even with flip-chip mounting and has a small parasitic effect. A second object of the present invention is to enable flip-chip mounting in a semiconductor device for a high-frequency circuit using an MMIC in combination,
Further, a third object is to realize a mounting method instead of flip chip mounting.

[0015]

A first semiconductor device according to the present invention is an MMIC which achieves the first object, wherein a ground pattern made of a conductor film, a dielectric film,
A high-frequency transistor, and a semiconductor chip having a second wiring pattern of a conductive film connected to the high-frequency transistor on an element formation surface; In the state where the element formation surface of the semiconductor chip faces the main surface of the substrate, the second
And the first wiring pattern are connected to each other, and the second wiring pattern, the dielectric film, and the ground pattern constitute a microstrip line of a semiconductor chip.

According to the first semiconductor device, only when the element forming surface of the semiconductor chip on the substrate is opposed to the main surface of the substrate, the second wiring pattern of the semiconductor chip and the dielectric material provided on the substrate are not provided. Since a microstrip line of a semiconductor chip composed of a film and a ground pattern is formed, it is not necessary to provide a ground pattern on the surface of the semiconductor chip opposite to the element forming surface. Therefore, the microstrip line is formed on the semiconductor chip without providing a ground pattern on the surface of the semiconductor chip opposite to the element formation surface, and the microstrip line does not form a pseudo closed space.

A second semiconductor device according to the present invention is an MMIC that achieves the first object, has a first wiring pattern made of a conductive film on a main surface, and has a first wiring pattern on a surface opposite to the main surface. A semiconductor substrate having a high-frequency transistor and a second wiring pattern made of a conductive film connected to the high-frequency transistor on the element formation surface, wherein the element formation surface of the semiconductor chip has an element formation surface; The second wiring pattern and the first wiring pattern are connected to each other while facing the main surface of the substrate, and the microstrip line of the semiconductor chip is formed by the second wiring pattern, the dielectric film, and the ground pattern. It is configured.

According to the second semiconductor device, only when the element forming surface of the semiconductor chip on the substrate faces the main surface of the substrate, the semiconductor consisting of the second wiring pattern of the semiconductor chip, the substrate, and the ground pattern is first obtained. Since the microstrip line of the chip is configured, it is not necessary to provide a ground pattern on the surface of the semiconductor chip opposite to the element forming surface. Therefore, since the microstrip line is formed on the semiconductor chip without providing the ground pattern on the surface opposite to the main surface of the semiconductor chip, the microstrip line does not form a pseudo closed space.

A third semiconductor device according to the present invention is an MMIC that achieves the first object, and has, on its main surface, a first ground pattern made of a conductor film, a dielectric film, and a conductor film. A substrate on which a first wiring pattern is sequentially formed; a second wiring pattern including a high-frequency transistor and a conductive film connected to the high-frequency transistor on an element forming surface; and a conductor on a surface opposite to the element forming surface. A semiconductor chip having a second ground pattern made of a film, wherein the second wiring pattern and the first wiring pattern are connected to each other with the element forming surface of the semiconductor chip facing the main surface of the substrate. In addition, the first ground pattern has an opening in a region of the first wiring pattern facing the element formation surface of the semiconductor chip.

According to the third semiconductor device, even if the semiconductor chip having the element formation surface facing the main surface of the substrate has the second ground pattern on the surface opposite to the element formation surface, the first semiconductor device has the first ground pattern on the substrate. Of the first ground pattern has an opening in a region facing the element forming surface of the semiconductor chip in the first ground pattern, so that the first ground pattern is similar to the second wiring pattern of the semiconductor chip. It does not constitute a closed space.

In the first or second semiconductor device, it is preferable that the dielectric film is made of BCB or polyimide.

A fourth semiconductor device according to the present invention is an MMIC that achieves the first object, has a first wiring pattern made of a conductive film on a main surface, and has a first wiring pattern on a surface opposite to the main surface. A substrate made of a dielectric having a first ground pattern, a high-frequency transistor on a device forming surface and a second wiring pattern made of a conductor film connected to the high-frequency transistor, and a second wiring pattern on a surface opposite to the device forming surface A semiconductor chip having a second ground pattern made of a conductive film, wherein the second wiring pattern and the first wiring pattern are connected to each other in a state where the element formation surface of the semiconductor chip faces the main surface of the substrate. And the first ground pattern is
The first wiring pattern has an opening in a region facing the element forming surface of the semiconductor chip.

According to the fourth semiconductor device, even if the semiconductor chip having the element formation surface facing the main surface of the substrate has the second ground pattern on the surface opposite to the element formation surface, the semiconductor chip has the second ground pattern. Since the first ground pattern provided on the opposite surface has an opening in a region of the first ground pattern facing the element forming surface of the semiconductor chip, the first ground pattern is formed on the semiconductor chip. There is no formation of a pseudo closed space with the second wiring pattern.

In the first to fourth semiconductor devices, the first wiring pattern and the second wiring pattern have a thickness of 5 μm.
It is preferable to be connected via the following bumps.

In the first to fourth semiconductor devices, the operating frequency of the high-frequency transistor is preferably 10 GHz or more.

In the first to fourth semiconductor devices, the semiconductor chip is preferably an MMIC having at least one high-frequency transistor and at least one passive element.

A fifth semiconductor device according to the present invention is an MFIC which achieves the second object, and has a space portion formed of a concave portion or a hole portion on a main surface and a first portion formed of a conductive film.
A first substrate having a wiring pattern of: and a main surface facing the main surface of the first substrate and straddling a space of the first substrate, and a ground pattern, a dielectric film, and A second substrate on which a second wiring pattern made of a conductive film is sequentially formed, and an element formation surface provided to face a main surface of the second substrate; A semiconductor chip having a third wiring pattern made of a connected conductive film, wherein the semiconductor chip is provided so as to be located in a space of the first substrate, and the first wiring pattern and the second wiring pattern are provided. The wiring pattern is connected to each other, and the second wiring pattern and the third wiring pattern are connected to each other.

According to the fifth semiconductor device, the second substrate whose main surface faces the element forming surface of the semiconductor chip has a space formed by a concave portion or a hole provided in the first substrate. Since the semiconductor chip provided so as to straddle and is provided on the main surface of the second substrate is located in the space of the first substrate, the second substrate is provided on the first substrate. On the other hand, when flip-chip mounting is performed, the semiconductor chip provided on the main surface of the second substrate does not hinder.

In the fifth semiconductor device, it is preferable that the first wiring pattern and the second wiring pattern are connected via bumps.

In the fifth semiconductor device, it is preferable that the first substrate and the second substrate are fixed to each other by a photocurable resin material.

In the fifth semiconductor device, it is preferable that the first substrate is made of a film containing polyimide as a main component.

In the fifth semiconductor device, it is preferable that the first substrate further has an external lead electrically connected to the first wiring pattern.

A sixth semiconductor device according to the present invention is an MFIC that achieves the third object, and is provided on a first substrate such that a main surface is located on a side opposite to the first substrate. ,
A second substrate having a high-frequency transistor or a high-frequency circuit formed on the main surface and a first wiring pattern electrically connected to the semiconductor chip; and a main surface on the first substrate. Are provided so as to be located on the side opposite to the first substrate, and a third substrate having a second wiring pattern on the main surface; and a main surface of the second substrate and a main surface of the third substrate. And a plate-like connection provided so as to straddle an end of the second substrate and an end of the third substrate adjacent to each other and electrically connect the first wiring pattern and the second wiring pattern. Means.

According to the sixth semiconductor device, each main surface is provided on the first substrate so as to be located on the side opposite to the first substrate, and has the semiconductor chip and the first wiring pattern on the main surface. Since the second substrate and the third substrate having the second wiring pattern on the main surface are electrically connected by the plate-like connecting means, the second substrate and the third substrate are flip-flop-connected. They can be combined without using an implementation. Further, since the connecting means has a plate shape, the mechanical strength is improved as compared with the bonding wire or the ribbon.

[0035] In the sixth semiconductor device, it is preferable that the connecting means is formed of a conductive lead.

In the sixth semiconductor device, it is preferable that the leads are connected to the first wiring pattern and the second wiring pattern via bumps.

In the sixth semiconductor device, it is preferable that the leads are fixed to the first wiring pattern and the second wiring pattern, respectively, by a photocurable resin material.

In the sixth semiconductor device, it is preferable that the connection means comprises a connection semiconductor chip and a third wiring pattern provided on the connection semiconductor chip.

In the sixth semiconductor device, it is preferable that the connecting semiconductor chip further has an element connected to the third wiring pattern.

In the sixth semiconductor device, it is preferable that the connecting semiconductor chip further includes a filter circuit connected to the third wiring pattern.

In the sixth semiconductor device, it is preferable that the connection means comprises a resin film and a third wiring pattern provided on the film.

In the sixth semiconductor device, the third wiring pattern is preferably a coplanar line.

In the sixth semiconductor device, it is preferable that the third substrate further has a high-frequency transistor or a high-frequency circuit on the main surface.

A seventh semiconductor device according to the present invention is an MMIC that achieves the third object, and is provided on a first substrate such that a main surface is located on a side opposite to the first substrate. ,
A second substrate having a high-frequency transistor or a high-frequency circuit and a first wiring pattern electrically connected to the high-frequency transistor or the high-frequency circuit on the main surface; and a first substrate having a main surface on the first substrate. And a third substrate having a second wiring pattern on the main surface, and a third substrate adjacent to the third substrate on the main surface of the second substrate and the third substrate. A plate-like connecting means provided so as to straddle an end of the second substrate and an end of the third substrate, and electrically connecting the first wiring pattern and the second wiring pattern; I have.

According to the seventh semiconductor device, the respective main surfaces are provided on the first substrate so as to be located on the side opposite to the first substrate, and the high-frequency transistor or the high-frequency circuit and the first wiring are provided on the main surfaces. Since the second substrate having the pattern and the third substrate having the second wiring pattern on the main surface are electrically connected by the plate-like connecting means, the second substrate and the third substrate are connected to each other. Can be combined without using a flip-flop implementation. Further, since the connecting means has a plate shape, the mechanical strength is improved as compared with the bonding wire or the ribbon.

An eighth semiconductor device according to the present invention is an MFIC that achieves the second or third object, wherein a first substrate having a first wiring pattern on a main surface and an element formation surface are provided. A semiconductor chip having a high-frequency transistor or a high-frequency circuit which is provided to face the main surface of the first substrate and is electrically connected to the first wiring pattern on the element formation surface;
A conductor member is provided on the main surface of the first substrate, one end of which is electrically connected to the first wiring pattern and the other end of which is provided inside the waveguide.

According to the eighth semiconductor device, the first surface has the first
A first substrate having a wiring pattern and a semiconductor chip electrically connected to the first wiring pattern has one end connected to the first wiring pattern and the other end positioned inside the waveguide. Because it is provided with a conductor member provided in
Since the semiconductor chip and the waveguide are easily and reliably connected, it is possible to operate in a higher frequency band.

A ninth semiconductor device according to the present invention is an MMIC that achieves the second or third object, and has a main surface connected to a high-frequency transistor or a high-frequency circuit and a high-frequency transistor or a high-frequency circuit. A first substrate having a first wiring pattern, provided on a main surface of the first substrate such that one end is electrically connected to the first wiring pattern and the other end is located inside the waveguide; Provided conductor member.

According to the ninth semiconductor device, the first substrate having the high-frequency transistor or high-frequency circuit formed on the main surface and the first wiring pattern connected to the high-frequency transistor or high-frequency circuit has one end connected to the first substrate. Since the semiconductor chip and the waveguide are easily and securely connected to each other because the conductor member is provided so as to be connected to the first wiring pattern and the other end is located inside the waveguide. It is possible to operate in a higher frequency band.

[0050] In the eighth or ninth semiconductor device, the conductor member is preferably plate-shaped or needle-shaped.

[0051]

(First Embodiment) A first embodiment of the present invention.
Is an MMIC that enables flip-chip mounting
About.

Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1A shows a sectional configuration of the semiconductor device according to the first embodiment. As shown in FIG. 1A, for example, on a main surface of a substrate 11 made of Si or glass or the like, a GND plane 12 formed by stacking titanium (Ti) and gold (Au) and benzocyclobutene (BCB) And a first wiring pattern 14 formed by laminating Ti and Au are sequentially formed, and the first wiring pattern 14, the dielectric film 13 and the GND plane 12 are formed.
Constitute a microstrip line. First
The wiring pattern 14 is connected to the GND plane 12 via a via hole (not shown) at a place requiring grounding.

On the substrate 11, a high-frequency transistor (not shown) having an operating frequency of 30 GHz on the element formation surface and a second wiring pattern 2 connected to the high-frequency transistor
MM made of gallium arsenide (GaAs) with 1 formed
The IC chip 22 has its element formation surface and the main surface of the substrate 11 opposed to each other, and is fixed by filling a gap between the IC chip 22 and the photocurable resin material 23.

A plurality of electrode pads 21a are provided at appropriate positions on the second wiring pattern 21 of the MMIC chip 22, and the second wiring pattern 21 and the first wiring pattern 14 of the substrate 11 A bump 24 is interposed between the pad 21a and the first wiring pattern 14, respectively.
They are electrically connected using the MBB method.

In the MMIC chip 22 according to this embodiment, the MMIC chip 22 is flip-chip mounted, so that the second wiring pattern 21, the dielectric film 13 provided on the substrate 11, and the GND plane 12 Since the microstrip line is configured, there is no need to provide a GND plane on the surface of the MMIC chip 22 opposite to the device forming surface.

That is, the second wiring pattern 21 of the MMIC chip 22 is
Material and film thickness, height of bump 24 and MMIC
A microstrip line having desired characteristics can be obtained in a state where the MMIC chip 22 is flip-chip mounted on the substrate 11 in consideration of the type of material and the distance of a member located between the chip 22 and the substrate 11. It is designed to be.

The inventors of the present application have proposed an MMI using the MBB method.
When a BCB film having a thickness of, for example, 26 μm is used for the dielectric film 13 when the C chip 22 is flip-chip mounted,
It has been found that if the line width of the MMIC chip 22 is about 70 μm, a line having a characteristic impedance of 50Ω can be obtained.

As described above, the semiconductor device according to the present embodiment normally functions as a high-frequency circuit only when the MMIC chip 22 is flip-chip mounted on the substrate 11.
The dielectric film 13 and the GND plane 12 on the substrate 11 side, which are considered to have a bad effect as a parasitic effect during mounting.
Is positively used as a part of the circuit on the MMIC chip 22 side. As a result, since the GND plane is not provided on the surface (rear surface) opposite to the main surface of the MMIC chip 22, the microstrip line does not form a pseudo closed space with via holes and bumps, so that cavity resonance does not occur. As a result, a high-frequency circuit whose operation is stable can be obtained.

When the MMIC chip 22 is formed, the thickness of the entire chip is adjusted, the rear surface is metallized to form a GND plane, and the via hole is used to electrically connect the GND plane to the wiring pattern on the element formation surface. Are not required, so that the manufacturing cost can be reduced as compared with a normal MMIC chip having a GND plane on the back surface.

As shown in a modification of FIG. 1B, a substrate 11A made of ceramic is used instead of the substrate 11.
May be used. Here, in FIG.
The same reference numerals are given to the same constituent members as those shown in FIG. In this case, FIG.
As shown in (b), the GND plane 12 is connected to the substrate 11A.
And a first wiring pattern 14 is formed on the main surface to form a microstrip line using the substrate 11A itself as a dielectric.

Even with such a configuration, the same effect as in the present embodiment can be obtained by designing the shape of the second wiring pattern 21 of the MMIC chip 22 in consideration of the thickness and the dielectric constant of the substrate 11A. Can play.

In this embodiment and each of the following embodiments, the bumps 24 are not necessarily required, and the wiring patterns 14, 21 and the electrode pads 21a are directly joined or contracted by simply contacting them. MM using resin material
The IC chip 22 and the substrate 11 may be fixed.

(Second Embodiment) A second embodiment of the present invention relates to a substrate structure which enables flip chip mounting of a normal MMIC.

Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 2A shows a sectional configuration of a semiconductor device according to the second embodiment. In FIG. 2A, the same components as those shown in FIG. 1A are denoted by the same reference numerals, and description thereof will be omitted. The first on the substrate 11
An opening 12a is provided in a region of the GND plane 12A facing the element forming surface of the semiconductor chip 22A, and the MMIC chip 22A has a second GND plane 25 on a surface opposite to the element forming surface. And normal MM
It has an IC configuration.

As described above, according to the present embodiment, the substrate 1
Since the opening 12a is provided in a region of the first GND plane 12A on the semiconductor chip 22A facing the element formation surface of the first GND plane 12A, a pseudo closed space in which the microstrip line is surrounded by the conductive film is formed. As a result, cavity resonance does not occur, and as a result, a high-frequency circuit with stable operation can be realized.

In general, in flip-chip mounting using a high-frequency circuit, a conductor surface having a relatively large area composed of a GND plane on the substrate side is provided near a microstrip line constituting a circuit of a semiconductor chip. Therefore, the electromagnetic wave radiated from the microstrip line of the semiconductor chip is reflected on this conductor surface,
It may affect the operation of the circuit of the semiconductor chip.
Therefore, the closer the conductor surface is to the microstrip line of the semiconductor chip, the greater the effect is.
Even if the height of the bumps is reduced by utilizing the features of the BB method to reduce the parasitic effect of the bumps, the effect of the reflection of electromagnetic waves from the conductor surface is rather increased, which may degrade the characteristics of the circuit. is there.

However, in the present embodiment, the MMIC chip 22 in the first GND plane 12A
Since the region facing the element formation surface of A has been removed,
It is not necessary to consider the influence of the reflection from the first GND plane 12A, and the optimum bump height can be selected.

As shown in a modification of FIG. 2B, a substrate 11A made of ceramic is used instead of the substrate 11.
May be used. Here, in FIG.
The same reference numerals are given to the same constituent members as those shown in FIG. In this case, FIG.
As shown in (b), the GND plane 12A is
The first wiring pattern 14 is formed on the surface opposite to the main surface of A, and the first wiring pattern 14 is formed on the main surface to form a microstrip line using the substrate 11A itself as a dielectric.

With such a configuration, the same effects as those of the second embodiment can be obtained. However, when another conductor is present in the vicinity of the lower side of the substrate 11A, it should be noted that the effect of providing the opening 12a in the first GND plane 12A cannot be sufficiently obtained.

(Third Embodiment) A third embodiment of the present invention relates to a substrate structure which enables flip-chip mounting of MFIC.

Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows a sectional configuration of a semiconductor device according to the third embodiment. As shown in FIG. 3, a first substrate 31 made of ceramic or the like and having a space 31a formed of a concave portion on the main surface has a first wiring pattern 32 formed by laminating Ti and Au on the main surface. A first GND plane 33 formed by laminating Ti and Au is formed on the surface opposite to the main surface, and a first GND plane 33 is formed from the first wiring pattern 32, the first substrate 31, and the first GND plane 33. Of the microstrip line 34 of FIG. The first wiring pattern 32 is grounded through a via hole (not shown) appropriately provided in the first substrate 31.

On the main surface of the first substrate 31, a second substrate 41 made of Si is flip-chip mounted so as to straddle the space 31a of the first substrate 31. Further, on the main surface of the second substrate 41, for example, GaAs on which a high-frequency transistor (not shown) having an operation frequency of 30 GHz or the like is formed.
The second substrate 41 and the MFIC chip 40 are configured by flip-chip mounting the semiconductor chip 42 made of s or the like so as to enter the space 31 a formed of the concave portion of the first substrate 31.

On the main surface of the second substrate 41, Ti and A
u, the second GND plane 43a, BC
A dielectric film 43b made of B and a second wiring pattern 43c formed by laminating Ti and Au are sequentially formed.
Of the second microstrip line 4 from the GND plane 43a, the dielectric film 43b and the second wiring pattern 43c.
3 are configured. The second wiring pattern 43c is electrically connected to the first wiring pattern 32 of the first substrate 31 and the semiconductor chip 42 via the bump 44. Here, the first substrate 31 and the second substrate 41
If the connection portion, that is, the vicinity of the bump 44 is fixed by using a photocurable resin material, the connection can be further strengthened.

As described above, according to the present embodiment, the first substrate 31 is provided on the main surface of the second substrate 41 in the MFIC chip 40 because the space 31a formed of the concave portion is provided in the first substrate 31. The semiconductor chip 42 is the first substrate 31
In this case, flip-chip mounting can be surely performed if it is inserted into the space 31a provided in the space.

In the present embodiment, the MFIC chip 40 having one semiconductor chip 42 is attached to the second substrate 4
1 is flip-chip mounted, but a plurality of semiconductor chips 4
The MFIC chip 40 having two may be used. In this case, on the main surface of the first substrate 31, a space 31 a may be provided over the entire surface facing the MFIC chip 40, and a plurality of spaces 31 a may be provided for each region facing each semiconductor chip 42. It may be provided.

In the present embodiment, the line provided on the first substrate 31 is the microstrip line 34, but may be another type of line such as a coplanar line.

The first substrate 31 may be provided with a space formed by a hole penetrating the recess instead of the space 31a formed by the recess.

(Fourth Embodiment) A fourth embodiment of the present invention relates to a substrate structure which enables flip chip mounting of MFIC.

Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

FIG. 4 shows a sectional configuration of a semiconductor device according to the fourth embodiment. 4, the same components as those shown in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 4, a difference from the semiconductor device according to the third embodiment is that a film base 31A having a space 31b made of polyimide or the like and having a hole is used as the first substrate. . Therefore, M
The semiconductor chip 42 provided on the main surface of the second substrate 41 of the FIC chip 40 is flip-chip mounted so as to enter the space 31b provided on the first substrate 31A.

In this embodiment, the MFIC chip 4
An inexpensive and easy-to-process film is used as the material of the substrate on which 0 is mounted. Generally, it is difficult to mechanically process a high-hardness substrate made of a ceramic or the like to form a recess, and the cost tends to be high. However, in the case of a film base 31A made of a polyimide or the like as in the present embodiment, If a punch or the like is used, the space 31b composed of a hole can be easily formed.
Therefore, the mounting of the MFIC chip 40 can be realized very easily.

The film base 31A may be provided with a space formed of a concave portion instead of the space 31b formed of a hole.

(Fifth Embodiment) A fifth embodiment of the present invention relates to MFIC packaging.

Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

FIGS. 5A and 5B show a semiconductor device according to the fifth embodiment, in which FIG.
(B) shows a plan configuration before mounting the MFIC chip on the II line in (a). As shown in FIG. 5A, the package housing 51 has a concave portion 52a on the main surface and a first wiring pattern 53 made of a conductive film, and a conductive film on the surface opposite to the main surface. A package base 52 made of ceramic as a first substrate on which a GND plane 54 made of is formed is fitted, and a microstrip line is constituted by the wiring pattern 53, the package base 52 and the GND plane 54.

The main surface of the package base 52 is provided with the second substrate 41 and the second substrate 41 shown in the third embodiment.
MFIC chip 40 comprising semiconductor chip 42 flip-chip mounted on
Flip chip mounting is performed so as to straddle 2a and insert the semiconductor chip 42 into the concave portion 52a. The wiring pattern 53 is connected to an internal lead 55 inside the housing 51, and the internal lead 55 is connected to an external lead 56 extending outside the housing. Here, the internal lead 55 and the external lead 56 may be formed integrally.

As shown in FIG. 5B, the wiring pattern 5 is located on the main surface of the package base 52, on the left and right ends of the periphery of the rectangular recess 52a in the drawing.
Four ground patterns 57 are formed on both sides of the base 3 at intervals, and each ground pattern 57 is connected to the GN via a via hole (not shown) penetrating the package base 52.
It is connected to the D plane 54.

In the package of the semiconductor device according to the present embodiment, a high-frequency signal is extracted from the external lead 56 on the side where the ground pattern 57 is formed as shown in FIG. Has a configuration suitable for taking out. Therefore, for example, if a GND plane like a coplanar line is also formed on the wiring pattern on the MFIC chip 40 side, grounding can be performed on the same surface as the wiring pattern, so that disturbance of impedance is reduced even in a higher frequency band. be able to.

As described above, according to the present embodiment, the MFI
Since the C chip 40 is packaged by flip-chip mounting with a small parasitic effect, it can be easily connected to another substrate while taking advantage of the excellent high-frequency characteristics of the MFIC.

(Sixth Embodiment) A sixth embodiment of the present invention relates to a mounting method replacing flip-chip mounting.
The present invention relates to a mounting structure for mounting an FIC or an MMIC on a motherboard.

Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.

FIG. 6A shows a sectional configuration of a semiconductor device according to the sixth embodiment. As shown in FIG. 6A, for example, a second substrate 71 made of Si and both sides of the second substrate 71 are formed on a first substrate 61 made of, for example, brass or the like and having conductivity. A third substrate 81 made of ceramic is fixed using, for example, a conductive paste or the like so that the main surface is located on the opposite side to the first substrate.

The second substrate 71 has Ti and Au on its main surface.
GND plane 72a, BCB
A first wiring pattern 72c formed by sequentially laminating a dielectric film 72b of Ti and Au and a first microstrip from the first GND plane 72a, the dielectric film 72b and the first wiring pattern 72c is formed. Track 72
Is configured. The first wiring pattern 72c is grounded through a via hole (not shown) appropriately provided in the second substrate 71.

On the second substrate 71, an MMIC chip 73 having a high-frequency transistor or a high-frequency circuit (not shown) having an operating frequency of 30 GHz on the element formation surface is flip-chip mounted by MBB using micro-bumps 74. And the MFIC chip 7 together with the second substrate 71
0.

The third substrate 81 has copper and copper on its main surface, respectively.
A second wiring pattern 82 made of titanium, gold, or the like is formed, and a second GND plane 83 made of copper, titanium, gold, or the like is formed on the surface opposite to the main surface. A second microstrip line is formed from the third substrate 81 and the second GND plane 83 to form a circuit substrate 80. Further, a passive element may be provided on the third substrate 81.

Here, the first wiring pattern 72c of the MFIC chip 70 based on the substrate surface of the first substrate 61 is used.
And the height position of the upper surface of the second wiring pattern 82 of the circuit board 80 are substantially the same, and the first wiring pattern 72c and the second wiring pattern 82 are plate-like connecting means. Are connected to each other by using a conductive lead 84 as a lead.

The lead 84 is made of, for example, a metal whose surface is plated with gold. The connection portions of the first wiring pattern 72c and the second wiring pattern 82 are connected by, for example, thermocompression bonding. Further, a microbump made of Au may be interposed using the MBB method, and a stronger connection can be obtained if the microbump is fixed using a photocurable resin material.

According to the present embodiment, the MFIC chip 70
The circuit board 80 and the circuit board 80 are fixed on the first board 61, and are electrically (high-frequency) connected to each other using the leads 84. Therefore, as compared with the case where a normal bonding wire or ribbon is used, the lead 84 itself is stronger and less deformed, so that it is possible to realize a connection structure in which impedance is not disturbed at a connection portion for electrically connecting the substrates.

Also, the width of the lead 84 can be designed in advance so that the MFIC chip 70 and the GND planes 72a and 83 of the circuit board 80 become microstrip lines having an appropriate impedance.
Optimized low-loss connection portions can be formed on the IC chip 70 and the circuit board 80, respectively. That is, the lead 84
Of the first wiring pattern 72c of the MFIC chip 70 on or near the MFIC chip 70, and not on the circuit board 80, but on the circuit board 80 or in the vicinity thereof. Of the first wiring pattern 72c and the second wiring pattern 82
Can be provided with impedance adjustment functions that match each other.

In the present embodiment, the first substrate 6 on the upper surface of the first wiring pattern 72c of the MFIC chip 70 and the upper surface of the second wiring pattern 82 of the circuit board 80
1 from the substrate surface, the total thickness of the second substrate 71 and the first macrostrip line 72 in the MFIC chip 70 and the circuit substrate 8
0, the total thickness of the third substrate 81, the second wiring pattern 82, and the second GND plane 83 is different from that of the MFIC chip 7 on the first substrate 61.
0 and the lower film thickness of the circuit board 80 are determined by the upper surface of the first wiring pattern 72c and the second wiring pattern 82.
It may be processed and adjusted so that the upper surface of the substrate is substantially at the same height.

The MFIC chip 70 and the circuit board 80
In order to clarify the positional relationship of the leads 84 and the MFIC chip 70 and the circuit board 80 adjacent to each other,
A gap is provided on each of the side surfaces of the semiconductor device, but an actual semiconductor device does not necessarily require this gap.

Further, as shown in a first modification of FIG. 6B, a configuration may be employed in which a plurality of MFIC chips 70 electrically connected to each other using leads 84 are provided on a first substrate 61. Good. This makes it possible to easily and reliably obtain a multistage high frequency circuit.

As shown in a second modification of FIG. 6C, an MMIC chip 75 may be provided on the first substrate 61 instead of the MFIC chip 70. The MMIC chip 75 has, for example, a high-frequency transistor unit 77 having a high-frequency transistor with an operating frequency of 30 GHz and a first wiring pattern 78 provided on an element formation surface of a second substrate 76 made of GaAs, and is opposite to the element formation surface. Is formed with a first GND plane 79.

As described above, the MMIC chip 75 can be provided directly on the first substrate 61, as shown in FIG.
As can be easily inferred from (b) and (c), one or more MFIC chips 70, MMI
The C chip 75 and the circuit board 80 may be appropriately combined so as to obtain desired characteristics.

(Seventh Embodiment) A seventh embodiment of the present invention relates to a mounting method replacing flip chip mounting.
The present invention relates to a mounting structure for mounting an FIC or an MMIC on a motherboard.

Hereinafter, a seventh embodiment of the present invention will be described with reference to the drawings.

FIG. 7 shows a sectional structure of a semiconductor device according to the seventh embodiment. In FIG. 7, the same components as those shown in FIG. 6A are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 7, a connection semiconductor chip 85 is used as a plate-like connection means for electrically connecting the MFIC chip 70 and the circuit board 80.

The semiconductor chip 85 for connection has a main surface of MFI.
The second substrate 71 of the C chip 70 and the third substrate of the circuit board 80
The main surface is placed on the second and third substrates 7 so as to
1, 81, and a third wiring pattern 86 is formed on the main surface. The third wiring pattern 86 is connected to the first wiring pattern 72c of the second substrate 71 and the second wiring pattern 82 of the third substrate 81 via bumps 87, respectively. Here, the connection semiconductor chip 85, the second substrate 71, and the third substrate 8
1 is fixed using a photocurable resin material, the electrical connection between the connection semiconductor chip 85 and the second and third substrates 71 and 81 is further ensured, and the long-term use of the device is improved. Reliability is improved.

In the present embodiment, a semiconductor chip 85 for connection is used instead of the lead 84 as an electrical connection means between the MFIC chip 70 and the circuit board 80. For this reason,
In the case of the lead 84, the lead 8
Although the shape of 4 is limited, in the case of the connection semiconductor chip 85, the MFIC chip 70 and the circuit board 80 are electrically connected using the third wiring pattern 86 provided on the connection semiconductor chip 85. Therefore, the shape of the third wiring pattern 86 can be designed independently of the mechanical strength.

Furthermore, it is possible to provide an impedance matching circuit including passive elements such as a capacitance element, a resistance element, and an inductor, and to provide a passive element to provide various functions to the connection means.

A filter circuit may be formed on the connection semiconductor chip 85 using the third wiring pattern 86, and connection means for transmitting only a desired frequency band may be provided.

Further, an MMIC chip including an appropriate active element may be used as the connection semiconductor chip 85. In this case, it is possible to provide various functions.

In this embodiment, as shown in the sixth embodiment, one or more MFIC chips 70, MMIC chips 75 and circuit boards 80 are each provided with desired characteristics on the first substrate 61. It is needless to say that they can be appropriately combined so as to obtain

(Eighth Embodiment) An eighth embodiment of the present invention relates to a mounting method replacing flip chip mounting.
The present invention relates to a mounting structure for easily mounting an FIC or an MMIC on a mother board.

Hereinafter, an eighth embodiment of the present invention will be described with reference to the drawings.

FIG. 8A shows a sectional configuration of a semiconductor device according to the eighth embodiment. In FIG. 8A, the same components as those shown in FIG. 6A are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 8A, a connection film 88 made of a resin such as polyimide is used as a plate-shaped connection means for electrically connecting the MFIC chip 70 and the circuit board 80.

The connection film 88 is made of the MFIC chip 7
0 second substrate 71 and third substrate 81 of circuit board 80
8 is provided on the surface facing the substrate side.
As shown in the plan view of (b), a signal line 89A and two ground lines 89 spaced from each other on both sides of the signal line 89A.
A coplanar line 89 is formed as a third wiring pattern composed of B.

The predetermined impedance of the coplanar line 89 can be obtained by appropriately selecting the line width of the signal line 89A and the distance between the side portions of the signal line 89A and the ground line 89B. The coplanar line 89 is connected to the signal line 8.
9A and the first wiring pattern 72c of the second substrate 71 and the second wiring pattern 82 of the third substrate 81 via bumps 90 provided at both ends of each ground line 89B. ing. Here, if the connection film 88 and the second substrate 71 and the third substrate 81 are fixed using a photo-curable resin material, the connection semiconductor chip 85 and the second and third substrates 71 and 81 are fixed. Connection with each other is further ensured.

As described above, according to the present embodiment, the MFI
As a means for electrically connecting the C chip 70 and the circuit board 80, a connection film 88 is used instead of the lead 84 or the connection semiconductor chip 85. Therefore, the degree of freedom of the wiring shape of the connection means and the addition of various functions can be realized more easily and at lower cost than in the case of using the connection semiconductor chip 85.

The wiring pattern on the connection film 88 is not limited to the coplanar line 89. For example, when impedance matching is performed without using the coplanar line 89, the line width of the wiring pattern on the connection film 88 is
The area on the MFIC chip 70 side may be the same as the first wiring pattern 72c, and the area on the circuit board 80 side may be the same as the second wiring pattern 82.

In this embodiment, as shown in the sixth embodiment, one or more MFIC chips 70, MMIC chips 75, and circuit boards 80 are each provided with desired characteristics on the first substrate 61. It is needless to say that they can be appropriately combined so as to obtain

(Ninth Embodiment) A ninth embodiment of the present invention relates to a packaging which can use MFIC or MMIC in a higher frequency band.

Hereinafter, a ninth embodiment of the present invention will be described with reference to the drawings.

FIG. 9 shows a sectional configuration of a semiconductor device according to the ninth embodiment. In FIG. 9, the same components as those shown in FIG. As shown in FIG. 9, a housing 91 made of a conductor is provided with a mounting stage 91a for mounting a semiconductor device and a waveguide 91b serving as a waveguide in a part thereof. Connecting leads 8 are provided on the mounting stage 91a.
The MFIC chip 70 and the circuit board 80 electrically connected using the 4A are fixed using a conductive paste or the like, and the first wiring pattern 72 of the MFIC chip 70 is fixed.
An antenna lead 94, one end of which is electrically connected to the first wiring pattern 72c and the other end of which is located at the waveguide 91b, is provided at the end of the circuit c opposite to the circuit board 80.

The waveguide portion 91b has a size to serve as a waveguide for an electromagnetic wave of a desired frequency, and the end of the antenna lead 94 is placed inside the waveguide portion 91b. A radio signal propagating through the waveguide 91 b can be transmitted to the MFIC chip 70.

As described above, according to the present embodiment, the position of the terminal end of the waveguide portion 91b and the position of the antenna lead 94 are optimized, as is known as a waveguide design technique, so that the desired position can be obtained. Signal transmission with low loss in the frequency band of

The housing 91 may be directly connected to a waveguide circuit (not shown), and a radio wave may be emitted into the space by using the opening of the waveguide 91b.

In the present embodiment, the antenna lead 94 is used for the antenna, but a needle-like member made of a conductor may be used.

The MFIC chip 70 and the circuit board 80
Although the connection leads 84A are used as the means for electrical connection with the semiconductor device, a connection semiconductor chip 85 shown in FIG. 7 or a connection film 88 shown in FIG. 8 may be used.

The mounting stage 91a of the housing 91
Above, one or more MFs as shown in the sixth embodiment
IC chip 70, MMIC chip 75 and circuit board 80
May be combined so as to obtain desired characteristics, respectively, or the flip-chip mounted MFIC chip 40 shown in the third or fourth embodiment may be used.

[0134]

According to the first or second semiconductor device of the present invention, the second wiring of the semiconductor chip is not provided until the semiconductor chip on the substrate has the element formation surface and the main surface of the substrate opposed to each other. Since a microstrip line composed of the pattern, the dielectric film provided on the substrate, and the ground pattern is configured, it is not necessary to provide a ground pattern on the surface of the semiconductor chip opposite to the element forming surface. As a result, since a microstrip line is formed without providing a ground pattern on the surface of the semiconductor chip opposite to the element formation surface, the microstrip line does not form a pseudo closed space. Oscillation does not occur, and stable and high-performance flip-chip mounting on a semiconductor chip can be realized.

According to the third or fourth semiconductor device of the present invention, it is assumed that the semiconductor chip having the element formation surface facing the main surface of the substrate has the second ground pattern on the surface opposite to the element formation surface. Also, the first ground pattern on the substrate is the first ground pattern.
The first ground pattern of the substrate constitutes a pseudo closed space with the second ground pattern of the semiconductor chip because the first ground pattern of the substrate has an opening in a region of the ground pattern facing the element forming surface of the semiconductor chip. Therefore, resonance and unnecessary oscillation do not occur, and stable and high-performance flip chip mounting on a semiconductor chip can be realized.

In the first or third semiconductor device, when the dielectric film is made of BCB or polyimide, a microstrip line having desired characteristics can be surely formed.

In the first to fourth semiconductor devices, the first wiring pattern and the second wiring pattern have a thickness of 5 μm.
When the connection is made via the following bumps, the thickness of the bumps is 5 μm or less even if the bumps are interposed, so that an increase in the parasitic inductance due to the thickness of the bumps can be ignored.

In the first to fourth semiconductor devices, when the operating frequency of the high-frequency transistor is 10 GHz or more,
A high-frequency semiconductor device from the quasi-millimeter wave band to the millimeter wave band can be reliably obtained.

In the first to fourth semiconductor devices, if the semiconductor chip is an MMIC having at least one high-frequency transistor and at least one passive element,
Generally, flip chip mounting of a multifunctional and high performance MMIC chip can be realized.

According to the fifth semiconductor device of the present invention, the second semiconductor device having the semiconductor chip mounted on the main surface by flip chip mounting is provided.
When the substrate is flip-chip mounted on the first substrate, the semiconductor chip protrudes above the second substrate because the semiconductor chip enters a space formed by a concave portion or a hole provided in the first substrate. Can be implemented reliably.

In the fifth semiconductor device, when the first wiring pattern and the second wiring pattern are connected via a bump, the electrical connection between the first wiring pattern and the second wiring pattern is made. Can be performed stably and reliably.

In the fifth semiconductor device, when the first substrate and the second substrate are fixed to each other with a photocurable resin material, the first substrate and the second substrate are more firmly fixed to each other. Therefore, the reliability of the device is improved.

In the fifth semiconductor device, when the first substrate is made of a film containing polyimide as a main component, the manufacturing cost can be reduced without sacrificing the characteristics of the device.

In the fifth semiconductor device, when the first substrate further has an external lead electrically connected to the first wiring pattern, it can be easily connected to another semiconductor device. .

According to the sixth or seventh semiconductor device of the present invention, the respective principal surfaces are provided on the first substrate so as to be located on the side opposite to the first substrate, and the plate-like connecting means is provided. Accordingly, the second substrate and the third substrate are electrically connected, so that different substrates can be combined without using flip-flop mounting. In addition, since the plate-like connection means having a mechanical strength larger than that of the bonding wire or the ribbon is used for the electrical connection between the second substrate and the third substrate, the impedance is not disturbed at the connection part. Also, the inductance can be reduced.

In the sixth or seventh semiconductor device, when the connection means is formed of conductive leads, electrical connection can be easily and reliably performed, and the inductance is smaller than that of the bonding wire.

In the sixth or seventh semiconductor device, if the leads are connected between the first wiring pattern and the second wiring pattern via bumps, respectively,
Wiring patterns on different substrates can be easily and stably connected.

In the sixth or seventh semiconductor device, when the connecting means comprises a connecting semiconductor chip and a third wiring pattern provided on the connecting semiconductor chip, the shape of the connecting means main body and the third wiring pattern are changed. And the shape of the third wiring pattern can be optimized without sacrificing the mechanical strength of the connection means main body.

In the sixth or seventh semiconductor device, if the connection semiconductor chip further includes an element connected to the third wiring pattern, for example, a capacitor element, a resistance element, Alternatively, since various functions can be provided by providing an impedance matching circuit including a passive element such as an inductor or providing a passive element, the degree of freedom in designing a high-frequency semiconductor device can be improved.

In the sixth or seventh semiconductor device, if the connection semiconductor chip further includes a filter circuit connected to the third wiring pattern, only a signal having a desired frequency can be transmitted. Therefore, the structure of a circuit formed over the second substrate or the third substrate can be simplified.

In the sixth or seventh semiconductor device, when the connecting means comprises a film made of resin and the third wiring pattern provided on the film, the shape of the connecting means main body and the shape of the third wiring pattern are reduced. Can be determined independently, the shape of the third wiring pattern can be optimized without sacrificing the mechanical strength of the connection means main body, and this optimization can be performed at a lower cost than when a semiconductor chip is used. .

In the sixth or seventh semiconductor device, the third
If the wiring pattern is a coplanar line, it can be connected to the second substrate side and the third substrate side without disturbing the characteristic impedance.

In the sixth or seventh semiconductor device, the third
When the substrate further has a high-frequency transistor or a high-frequency circuit on the main surface, a multi-stage high-frequency semiconductor device can be easily and reliably obtained.

According to the eighth or ninth semiconductor device of the present invention, one end is connected to the first wiring pattern on the first substrate on which a semiconductor chip provided with a high-frequency transistor or the like is flip-chip mounted. Since the end is provided with the conductor member located inside the waveguide, the semiconductor chip and the waveguide are easily and reliably connected, so that it is possible to operate in a higher frequency band.

[Brief description of the drawings]

FIG. 1A is a configuration sectional view showing a semiconductor device according to a first embodiment of the present invention. (B) is a sectional view showing a configuration of a semiconductor device according to a modification of the first embodiment of the present invention.

FIG. 2A is a configuration sectional view illustrating a semiconductor device according to a second embodiment of the present invention. (B) is a sectional view showing a configuration of a semiconductor device according to a modification of the second embodiment of the present invention.

FIG. 3 is a configuration sectional view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a configuration sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

FIGS. 5A and 5B are semiconductor devices according to a fifth embodiment, in which FIG. 5A is a cross-sectional view of the configuration, and FIG. 5B is an MFIC chip along line II in FIG. FIG. 4 is a plan view before mounting.

FIG. 6A is a configuration sectional view showing a semiconductor device according to a sixth embodiment of the present invention. (B) is a configuration sectional view showing a semiconductor device according to a first modification of the sixth embodiment of the present invention. (C) is a configuration sectional view showing a semiconductor device according to a second modification of the sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a configuration of a semiconductor device according to a seventh embodiment of the present invention.

8A and 8B show a semiconductor device according to an eighth embodiment, in which FIG. 8A is a cross-sectional view of a configuration, and FIG. 8B is a plan view of a connection means of FIG. .

FIG. 9 is a partial cross-sectional view of a semiconductor device according to a ninth embodiment of the present invention, showing a package on which an MFIC chip is mounted.

FIG. 10 is a configuration sectional view showing a conventional MFIC.

FIG. 11 is a sectional view showing a configuration of a semiconductor device in which a conventional MMIC is flip-chip mounted.

[Explanation of symbols]

 Reference Signs List 11 substrate 11A substrate (dielectric) 12 GND plane (ground pattern) 12A first GND plane 12a opening 13 dielectric film 14 first wiring pattern 21 second wiring pattern 21a electrode pad 22 MMIC chip (semiconductor chip) 22A MMIC chip (semiconductor chip) 23 Photocurable resin material 24 Bump 25 Second GND plane 31 First substrate 31A Film base (first substrate) 31a Space (recess) 31b Space (hole) 32 First 1 wiring pattern 33 first GND plane 34 first microstrip line 40 MFIC chip 41 second substrate 41 42 semiconductor chip 43 second microstrip line 43a second GND plane 43b dielectric film 43c second Wiring pattern 44 Bump 51 Housing 2 Package base (first substrate) 52a Recess 53 Wiring pattern 54 GND plane 55 Internal lead 56 External lead 57 Ground pattern 61 First substrate 70 MFIC chip 71 Second substrate 72 First microstrip line 72a First GND plane 72b Dielectric film 72c First wiring pattern 73 MMIC chip 74 Micro bump 75 MMIC chip 76 Second substrate 77 High-frequency transistor section 78 First wiring pattern 79 First GND plane 80 Circuit board 81 Third board 82 second wiring pattern 83 second GND plane 84 lead (connection means) 84A connection lead 85 connection semiconductor chip (connection means) 86 third wiring pattern 87 bump 88 connection film (connection means) 89 coplanar Road (third wiring pattern) 89A signal line 89B ground line 90 bumps 91 housing 91a mounted stage portion 91b waveguide (waveguide) 94 antenna lead (conductor member)

Claims (34)

[Claims] 1. A ground pattern made of a conductive film on a main surface,
A substrate on which a first wiring pattern composed of a dielectric film and a conductor film is sequentially formed; and a semiconductor having a high-frequency transistor and a second wiring pattern composed of a conductor film connected to the high-frequency transistor on an element formation surface. The second wiring pattern and the first wiring pattern are connected to each other in a state where an element formation surface of the semiconductor chip is opposed to a main surface of the substrate; A semiconductor device, wherein a microstrip line of the semiconductor chip is constituted by a wiring pattern, the dielectric film, and the ground pattern. 2. A substrate made of a dielectric having a first wiring pattern made of a conductive film on a main surface and having a ground pattern on a surface opposite to the main surface, a high-frequency transistor and a high-frequency transistor formed on an element formation surface. A semiconductor chip having a second wiring pattern made of a conductor film connected to the transistor, wherein the second wiring pattern and the second wiring pattern are provided in a state where an element formation surface of the semiconductor chip faces a main surface of the substrate. And a second wiring pattern, the dielectric film, and the ground pattern, wherein a microstrip line of the semiconductor chip is formed. 3. A substrate on which a first ground pattern made of a conductive film, a dielectric film, and a first wiring pattern made of a conductive film are sequentially formed on a main surface, a high-frequency transistor and a high-frequency transistor on a device forming surface. A semiconductor chip having a second wiring pattern made of a conductive film connected to the transistor and having a second ground pattern made of a conductive film on a surface opposite to the element forming surface; The second wiring pattern and the first wiring pattern are connected to each other with the formation surface facing the main surface of the substrate, and the first ground pattern is formed of the first wiring pattern. Wherein the semiconductor chip has an opening in a region facing the element forming surface of the semiconductor chip. 4. The semiconductor device according to claim 1, wherein said dielectric film is made of BCB or polyimide. 5. A substrate made of a dielectric material having a first wiring pattern made of a conductor film on a main surface and having a first ground pattern on a surface opposite to the main surface; A semiconductor chip having a second wiring pattern made of a conductive film connected to the high-frequency transistor, and having a second ground pattern made of a conductive film on a surface opposite to the element forming surface; The second wiring pattern and the first wiring pattern are connected to each other in a state where the element forming surface of the first substrate faces the main surface of the substrate, and the first ground pattern is formed of the first ground pattern. A semiconductor device having an opening in a region of a wiring pattern facing an element forming surface of the semiconductor chip. 6. The method according to claim 1, wherein the first wiring pattern and the second wiring pattern are connected via a bump having a thickness of 5 μm or less. The semiconductor device according to claim 1. 7. The semiconductor device according to claim 1, wherein an operating frequency of said high-frequency transistor is 10 GHz or more. 8. The semiconductor device according to claim 1, wherein the semiconductor chip is an MMIC having at least one high-frequency transistor and at least one passive element. Semiconductor device. 9. A first substrate having a space portion formed of a concave portion or a hole portion on a main surface thereof and having a first wiring pattern made of a conductive film, wherein the main surface faces a main surface of the first substrate. And a second substrate provided so as to straddle the space portion of the first substrate, and a second wiring pattern including a ground pattern, a dielectric film, and a conductor film is sequentially formed on a main surface of the second substrate; A semiconductor chip having a high-frequency transistor and a third wiring pattern made of a conductive film connected to the high-frequency transistor on the element formation surface; The semiconductor chip is provided so as to be located in the space of the first substrate. The first wiring pattern and the second wiring pattern are connected to each other. The third Wherein a that are connected to each other with a line pattern. 10. The semiconductor device according to claim 9, wherein said first wiring pattern and said second wiring pattern are connected via bumps. 11. The semiconductor device according to claim 9, wherein the first substrate and the second substrate are fixed to each other with a photocurable resin material. 12. The semiconductor device according to claim 9, wherein said first substrate is made of a film containing polyimide as a main component. 13. The semiconductor device according to claim 9, wherein the first substrate further has an external lead electrically connected to the first wiring pattern. 14. A semiconductor chip in which a main surface is provided on a first substrate so as to be located on a side opposite to the first substrate, and a high-frequency transistor or a high-frequency circuit is formed on the main surface; A second substrate having a first wiring pattern electrically connected to the chip; and a second substrate provided on the first substrate such that a main surface is located on a side opposite to the first substrate. A third substrate having a second wiring pattern on a surface thereof, an end of the second substrate adjacent to the third substrate on a main surface of the second substrate and a main surface of the third substrate, and A semiconductor device provided so as to straddle an end of the substrate and electrically connecting the first wiring pattern and the second wiring pattern. . 15. The semiconductor device according to claim 14, wherein said connection means comprises a conductive lead. 16. The semiconductor according to claim 15, wherein the leads are connected to the first wiring pattern and the second wiring pattern via bumps, respectively. apparatus. 17. The semiconductor device according to claim 15, wherein said leads are fixed to said first wiring pattern and said second wiring pattern, respectively, by a photocurable resin material. 18. The semiconductor device according to claim 14, wherein said connection means comprises a connection semiconductor chip and a third wiring pattern provided on said connection semiconductor chip. 19. The semiconductor device according to claim 18, wherein the third wiring pattern is connected between the first wiring pattern and the second wiring pattern via bumps. 3. The semiconductor device according to claim 1. 20. The semiconductor according to claim 18, wherein the third wiring pattern is fixed to the first wiring pattern and the second wiring pattern by a photocurable resin material. apparatus. 21. The semiconductor device according to claim 18, wherein said connecting semiconductor chip further has an element connected to said third wiring pattern. 22. The semiconductor device according to claim 18, wherein said connection semiconductor chip further has a filter circuit connected to said third wiring pattern. 23. The semiconductor device according to claim 14, wherein said connection means comprises a film made of resin and a third wiring pattern provided on said film. 24. The semiconductor device according to claim 23, wherein the third wiring pattern is connected between the first wiring pattern and the second wiring pattern via bumps. 3. The semiconductor device according to claim 1. 25. The semiconductor according to claim 23, wherein the third wiring pattern is fixed to the first wiring pattern and the second wiring pattern by a photocurable resin material. apparatus. 26. The semiconductor device according to claim 23, wherein the third wiring pattern is a coplanar line. 27. The semiconductor device according to claim 14, wherein the third substrate further has a high-frequency transistor or a high-frequency circuit on a main surface. 28. A high-frequency transistor or a high-frequency circuit, and the high-frequency transistor or the high-frequency circuit are provided on the first substrate such that a main surface is located on a side opposite to the first substrate. A second substrate having a first wiring pattern electrically connected thereto; a second substrate provided on the first substrate such that a main surface is located on a side opposite to the first substrate; A third substrate having a second wiring pattern, an end of the second substrate adjacent to the third substrate on a main surface of the second substrate and a main surface of the third substrate, A semiconductor device, comprising: a plate-like connecting means provided so as to straddle an end and electrically connecting the first wiring pattern and the second wiring pattern. 29. The semiconductor device according to claim 28, wherein said connection means comprises a conductive lead. 30. The semiconductor device according to claim 28, wherein said connection means comprises a connection semiconductor chip and a third wiring pattern provided on said connection semiconductor chip. 31. The semiconductor device according to claim 28, wherein said connecting means comprises a film made of resin and a third wiring pattern provided on said film. 32. A first substrate having a first wiring pattern on a main surface thereof, and an element forming surface provided to face a main surface of the first substrate, wherein the first substrate has a first wiring pattern. A semiconductor chip having a high-frequency transistor or a high-frequency circuit electrically connected to the wiring pattern; and a main surface of the first substrate, one end of which is electrically connected to the first wiring pattern and the other end of which is guided. A conductor member provided to be located inside the tube. 33. A first substrate having a high-frequency transistor or a high-frequency circuit on a main surface thereof, and a first wiring pattern connected to the high-frequency transistor or the high-frequency circuit; and a main surface of the first substrate, A semiconductor device, comprising: a conductor member having one end electrically connected to the first wiring pattern and the other end provided to be located inside the waveguide. 34. The semiconductor device according to claim 32, wherein the conductor member has a plate shape or a needle shape.