JP4646969B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a high-frequency semiconductor device from a quasi-millimeter wave band to a millimeter wave band, and more particularly to a semiconductor device that reduces parasitic effects.

  In recent years, technological progress in the information communication field has been remarkable, and the frequency band handled by communication equipment has been developed from a microwave band to a millimeter wave band to a higher frequency band. Along with this, the speed of transistor elements used in communication equipment has been remarkably increased. Recently, devices having a cutoff frequency exceeding 100 GHz have been realized in heterojunction transistor elements using compound semiconductors such as III-V groups. Yes. However, in a communication device that handles such a high frequency band from the microwave band to the millimeter wave band, the mounting method of the semiconductor chip constituting the circuit becomes a problem as well as the element characteristics of the transistor. For example, new parasitic capacitance and parasitic inductance (= parasitic reactance) often occur in a circuit after the mounting process, and the influence of this parasitic reactance on a communication device is proportional to the frequency handled by the communication device. Therefore, it is necessary to suppress the parasitic reactance component as the frequency increases. In addition, in communication equipment that handles the frequency band from the microwave band to the millimeter wave band described above, the dimensions of the connection parts that connect the elements constituting the circuit or between the circuits are close to the wavelength of the signal. When doing so, it is necessary to fully consider the dimensions of the connecting parts.

  As a first conventional example for solving such a problem, there is an MMIC (= Monolithic Microwave IC) in which a transistor element and a passive circuit are manufactured on a semiconductor substrate using a semiconductor process. In this MMIC, a transistor and a peripheral circuit are integrated in one semiconductor chip, and the number of connecting parts is reduced by the integration, so that a parasitic reactance component is reduced. In addition, since a semiconductor process excellent in microfabrication is used, high-precision machining can be realized, and a reduction in manufacturing cost can be expected due to the mass production effect of the semiconductor process.

  As a second conventional example, an MFIC (Millimeter) disclosed in Non-Patent Document 1 or the like that realizes a semiconductor integrated circuit from a quasi-millimeter wave band to a millimeter-wave band with further low cost and high performance and wide application range. -Wave Flip-chip IC). This MFIC is an IC module technology that suppresses parasitic effects by using a flip-chip mounting method called micro bump bonding method (hereinafter referred to as MBB method), and is designed while taking advantage of precision and mass productivity of semiconductor processes. The feature is that a high-performance millimeter-wave band semiconductor IC can be realized at low cost while also ensuring flexibility.

  Hereinafter, the MFIC according to the second conventional example will be described with reference to the drawings.

FIG. 10 shows a cross-sectional configuration of a conventional MFIC. As shown in FIG. 10, a GND plane 102 made of Au, a dielectric film 103 made of SiO _2, and a wiring pattern 104 made of a conductor film are sequentially formed on the main surface of a substrate 101 made of Si or the like. The wiring pattern 104, the dielectric film 103, and the GND plane 102 constitute a microstrip line. On the wiring pattern 104 on the substrate 101, a semiconductor chip 105 made of a compound semiconductor or the like and having a high-frequency transistor on the element formation surface uses a photocurable insulating resin 106 with the element formation surface facing the wiring pattern 104. It is fixed. Electrode pads 107 are selectively formed on the element forming surface of the semiconductor chip 105, and bonding pads 104a are selectively formed on the wiring pattern 104, and are electrically connected to each other with micro bumps 108 interposed therebetween.

As described above, the MFIC according to the second conventional example can reduce the thickness of the bump 108 to several μm, so that the parasitic inductor component of the bump 108 can be ignored. In addition, since the wiring pattern 104 can be manufactured by using a semiconductor process, patterning with much higher accuracy can be realized as compared with a normal hybrid IC that performs wiring by using a printing technique on an alumina substrate or the like. Furthermore, compared to the MMIC according to the first conventional example using the same semiconductor process, this MFIC can form a passive circuit on an inexpensive substrate 101 made of Si or the like instead of on a compound semiconductor substrate, so that the cost is significantly reduced. Can be realized.
39th Proceedings of the 1994 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers Proceedings of the 1997 IEICE General Conference Electronics 1st volume, page 68 (lecture number C-2-13)

  However, in the MMIC according to the first conventional example, it is extremely difficult to integrate all the circuits of the communication device into a single-chip semiconductor IC at present. It is necessary to divide the MMIC into different MMICs, and to provide a different function for each divided MMIC, and to configure a predetermined circuit by combining the MMICs.

  Thus, flip chip mounting has been attempted as an MMIC mounting method. However, there is a problem described in Non-Patent Document 2, for example, in MMIC flip chip mounting. This problem will be described with reference to the drawings.

  FIG. 11 shows a cross-sectional configuration of a semiconductor device in which a conventional MMIC is flip-chip mounted. As shown in FIG. 11, the first wiring pattern 112 is formed on the main surface of the insulating substrate 111, the first GND plane 113 is formed on the surface opposite to the main surface, and the first wiring pattern is formed. 112 and the first GND plane 113 constitute a first microstrip line, and the first wiring pattern 112 is grounded through a first via hole 114 appropriately provided in the insulating substrate 111.

  On the main surface of the insulating substrate 111, an MMIC chip 115 having an element formation surface facing the main surface is mounted with bumps 116 interposed therebetween. A high frequency transistor (not shown) and a second wiring pattern 117 are formed on the element formation surface of the MMIC chip 115, and the second wiring pattern 117 and the second microstrip line are formed on the surface opposite to the element formation surface. A second GND plane 118 is formed, and the second wiring pattern 117 is grounded through a second via hole 119 appropriately provided on the substrate.

  As described above, in the flip chip mounting using the conventional MMIC 115, the insulating substrate 111 and the MMIC chip 115 each have the GND planes 113 and 118, and these are spatially separated. May not be stable and may cause unexpected troubles such as resonance and unnecessary oscillation. Further, as shown in FIG. 11, a pseudo closed space including the first GND plane 113, the first via hole 114, the first wiring 112, the bump 116, the second via hole 119, and the second GND plane 118. The closed space is easily excited by a signal propagating through the microstrip line, and causes cavity resonance. As a result, when the resonant frequency of the cavity resonance approaches the operating frequency depending on the materials and dimensions of the insulating substrate 111 and the MMIC chip 115, there is a problem that the circuit operation is unexpectedly influenced greatly. .

  On the other hand, in the MFIC shown in FIG. 10 as well, at present, it is impossible to integrate all the circuits of the communication device on the substrate 101. Like the MMIC described above, the MFIC is integrated into one MFIC for each function. A method of realizing the function of the entire circuit by connecting these MFICs having different functions to each other is realistic. Accordingly, as with the MMIC, how to connect the MFIC chips to each other or between the MFIC chip and another substrate remains unsolved. Moreover, as shown in FIG. 10, unlike the MMIC chip, in the case of the MFIC chip, since the semiconductor chip 105 is already provided on the substrate 101, there is a problem that it cannot be mounted only by extending the technology of the MMIC. .

  In view of the above-described conventional problems, the first object of the present invention is to realize an MMIC that is less likely to cause resonance and unnecessary oscillation even when flip-chip mounting is performed and that has a small parasitic effect. The second object of the present invention is to enable flip chip mounting in a semiconductor device for a high-frequency circuit to be used, and a third object is to realize a mounting method instead of flip chip mounting.

  A first semiconductor device according to the present invention is an MMIC that achieves the first object, wherein a ground pattern made of a conductor film, a dielectric film, and a first wiring pattern made of a conductor film are formed on a main surface. A substrate formed sequentially, and a semiconductor chip having a second wiring pattern made of a high-frequency transistor and a conductor film connected to the high-frequency transistor on an element formation surface, the element formation surface of the semiconductor chip being a main substrate The second wiring pattern and the first wiring pattern are connected to each other in a state of facing the surface, and the microstrip line of the semiconductor chip is configured by the second wiring pattern, the dielectric film, and the ground pattern. Yes.

  According to the first semiconductor device, the second wiring pattern of the semiconductor chip, the dielectric film provided on the substrate, and the ground are only in a state where the element formation surface of the semiconductor chip on the substrate faces the main surface of the substrate. Since the microstrip line of the semiconductor chip comprising the pattern is configured, it is not necessary to provide a ground pattern on the surface opposite to the element formation surface of the semiconductor chip. Therefore, since the microstrip line is formed on the semiconductor chip without providing a ground pattern on the surface opposite to the element formation surface of the semiconductor chip, the microstrip line does not form a pseudo closed space.

  A second semiconductor device according to the present invention is an MMIC that achieves the first object, having a first wiring pattern made of a conductor film on a main surface and a ground pattern on a surface opposite to the main surface. And a semiconductor chip having a second wiring pattern made of a high-frequency transistor and a conductor film connected to the high-frequency transistor on the element formation surface, wherein the element formation surface of the semiconductor chip is the main surface of the substrate. The second wiring pattern and the first wiring pattern are connected to each other in a state of facing the surface, and the microstrip line of the semiconductor chip is configured by the second wiring pattern, the dielectric film, and the ground pattern. Yes.

  According to the second semiconductor device, only when the element formation surface of the semiconductor chip on the substrate is opposed to the main surface of the substrate, the microchip of the semiconductor chip including the second wiring pattern of the semiconductor chip, the substrate, and the ground pattern is provided. Since the strip line is formed, it is not necessary to provide a ground pattern on the surface of the semiconductor chip opposite to the element formation surface. Accordingly, since the microstrip line is formed on the semiconductor chip without providing a ground pattern on the surface opposite to the main surface of the semiconductor chip, the microstrip line does not form a pseudo closed space.

  A third semiconductor device according to the present invention is an MMIC that achieves the first object, and includes a first ground pattern comprising a conductor film, a dielectric film, and a conductor film on a main surface. It has a substrate on which wiring patterns are sequentially formed, a second wiring pattern comprising a high-frequency transistor and a conductor film connected to the high-frequency transistor on the element formation surface, and a conductor film on the surface opposite to the element formation surface. A semiconductor chip having a second ground pattern, and the second wiring pattern and the first wiring pattern are connected to each other with the element formation surface of the semiconductor chip facing the main surface of the substrate, The first ground pattern has an opening in a region facing the element formation surface of the semiconductor chip in the first wiring pattern.

  According to the third semiconductor device, even if the semiconductor chip having the element formation surface facing the main surface of the substrate has the second ground pattern on the surface opposite to the element formation surface, the first ground pattern on the substrate is provided. Has an opening in a region facing the element formation surface of the semiconductor chip in the first ground pattern, so that the first ground pattern forms a pseudo closed space with the second wiring pattern of the semiconductor chip. There is no configuration.

  In the first or second semiconductor device, the dielectric film is preferably made of BCB or polyimide.

  A fourth semiconductor device according to the present invention is an MMIC that achieves the first object, having a first wiring pattern made of a conductor film on a main surface and a first surface on a surface opposite to the main surface. A substrate made of a dielectric having a ground pattern, a second wiring pattern made of a high-frequency transistor and a conductor film connected to the high-frequency transistor on the element formation surface, and a conductor film on the surface opposite to the element formation surface And the second wiring pattern and the first wiring pattern are connected to each other with the element forming surface of the semiconductor chip facing the main surface of the substrate. The first ground pattern has an opening in a region facing the element formation surface of the semiconductor chip in the first wiring pattern.

  According to the fourth semiconductor device, even if the semiconductor chip having the element formation surface facing the main surface of the substrate has the second ground pattern on the surface opposite to the element formation surface, Since the first ground pattern provided on the surface has an opening in a region facing the element formation surface of the semiconductor chip in the first ground pattern, the first ground pattern is the second ground pattern of the semiconductor chip. It does not constitute a pseudo closed space with the wiring pattern.

  In the first to fourth semiconductor devices, it is preferable that the first wiring pattern and the second wiring pattern are connected via a bump having a thickness of 5 μm or less.

  In the first to fourth semiconductor devices, the operating frequency of the high frequency transistor is preferably 10 GHz or more.

  In the first to fourth semiconductor devices, the semiconductor chip is preferably an MMIC having at least one high-frequency transistor and at least one passive element.

  A fifth semiconductor device according to the present invention is an MFIC that achieves the second object, and includes a first wiring pattern that includes a space formed of a recess or a hole on the main surface and a conductive film. A second substrate comprising a ground pattern, a dielectric film, and a conductor film on the main surface, the main surface being provided so that the main surface faces the main surface of the first substrate and straddles a space portion of the first substrate; A second substrate on which the wiring patterns are sequentially formed, an element formation surface is provided to face the main surface of the second substrate, and the element formation surface includes a high-frequency transistor and a conductor film connected to the high-frequency transistor. A semiconductor chip having a third wiring pattern, and the semiconductor chip is provided so as to be positioned in a space portion of the first substrate, and the first wiring pattern and the second wiring pattern are connected to each other. Second wiring pattern When connected to each other and the third wiring pattern.

  According to the fifth semiconductor device, the second substrate whose main surface is opposed to the element formation surface of the semiconductor chip is such that the main surface straddles a space formed by a recess or a hole provided in the first substrate. Oppositely, the semiconductor chip provided on the main surface of the second substrate is provided so as to be positioned in the space of the first substrate, so that the second substrate is flipped with respect to the first substrate. When chip mounting is performed, the semiconductor chip provided on the main surface of the second substrate is not hindered.

  In the fifth semiconductor device, it is preferable that the first wiring pattern and the second wiring pattern are connected via bumps.

  In the fifth semiconductor device, it is preferable that the first substrate and the second substrate are fixed to each other by a photocurable resin material.

  In the fifth semiconductor device, the first substrate is preferably made of a film containing polyimide as a main component.

  In the fifth semiconductor device, it is preferable that the first substrate further includes an external lead electrically connected to the first wiring pattern.

  A sixth semiconductor device according to the present invention is an MFIC that achieves the third object, and is provided on a first substrate so that a main surface is located on a side opposite to the first substrate. A semiconductor chip on which a high-frequency transistor or a high-frequency circuit is formed, a second substrate having a first wiring pattern electrically connected to the semiconductor chip, and a main surface on the first substrate. A third substrate provided on the opposite side of the first substrate and having a second wiring pattern on the main surface; and on the main surface of the second substrate and the main surface of the third substrate; Plate-like connecting means provided so as to straddle the end portion of the second substrate and the end portion of the third substrate that are adjacent to each other, and electrically connect the first wiring pattern and the second wiring pattern; It has.

  According to the sixth semiconductor device, the second main surface is provided on the first substrate so that each main surface is located on the opposite side of the first substrate, and the main surface includes the semiconductor chip and the first wiring pattern. Since the substrate and the third substrate having the second wiring pattern on the main surface are electrically connected by the plate-like connecting means, the second substrate and the third substrate are flip-flop mounted. Can be combined without any problems. Further, since the connecting means has a plate shape, the mechanical strength is improved as compared with the bonding wire or ribbon.

  In the sixth semiconductor device, the connecting means is preferably made of a conductive lead.

  In the sixth semiconductor device, it is preferable that the lead is connected to the first wiring pattern and the second wiring pattern via bumps.

  In the sixth semiconductor device, it is preferable that the lead is fixed to the first wiring pattern and the second wiring pattern by a photocurable resin material.

  In the sixth semiconductor device, it is preferable that the connecting means includes a connecting semiconductor chip and a third wiring pattern provided on the connecting semiconductor chip.

  In the sixth semiconductor device, it is preferable that the connecting semiconductor chip further includes an element connected to the third wiring pattern.

  In the sixth semiconductor device, it is preferable that the connecting semiconductor chip further includes a filter circuit connected to the third wiring pattern.

  In the sixth semiconductor device, the connecting means preferably comprises a film made of a resin and a third wiring pattern provided on the film.

  In the sixth semiconductor device, the third wiring pattern is preferably a coplanar line.

  In the sixth semiconductor device, it is preferable that the third substrate further includes a high-frequency transistor or a high-frequency circuit on the main surface.

  A seventh semiconductor device according to the present invention is an MMIC that achieves the third object, and is provided on a first substrate so that a main surface is located on the side opposite to the first substrate. A high-frequency transistor or high-frequency circuit on the surface, a second substrate having a first wiring pattern electrically connected to the high-frequency transistor or high-frequency circuit, and a main surface opposite to the first substrate on the first substrate And a second substrate adjacent to each other on the main surface of the second substrate and on the main surface of the third substrate. And a plate-like connection means for electrically connecting the first wiring pattern and the second wiring pattern. The plate-shaped connection means is provided so as to straddle the end of the substrate and the end of the third substrate.

  According to the seventh semiconductor device, each main surface is provided on the first substrate so as to be opposite to the first substrate, and the main surface has the high-frequency transistor or the high-frequency circuit and the first wiring pattern. Since the second substrate and the third substrate having the second wiring pattern on the main surface are electrically connected by the plate-like connecting means, the second substrate and the third substrate are flip-flops. Can be combined without using an implementation. Further, since the connecting means has a plate shape, the mechanical strength is improved as compared with the bonding wire or ribbon.

  An eighth semiconductor device according to the present invention is an MFIC that achieves the second or third object, wherein the first substrate having the first wiring pattern on the main surface and the element formation surface are the first. A semiconductor chip having a high-frequency transistor or a high-frequency circuit that is provided so as to face the main surface of the substrate and is electrically connected to the first wiring pattern on the element formation surface, and one end on the main surface of the first substrate A conductor member that is electrically connected to the first wiring pattern and is provided so that the other end is positioned inside the waveguide.

  According to the eighth semiconductor device, one end is connected to the first wiring pattern on the first substrate having the first wiring pattern and the semiconductor chip electrically connected to the first wiring pattern on the main surface. Since the conductor member provided so that the other end is located inside the waveguide is provided, the semiconductor chip and the waveguide are easily and reliably connected, so that in a higher frequency band It becomes possible to operate.

  A ninth semiconductor device according to the present invention is an MMIC that achieves the second or third object, wherein the first surface is connected to a high-frequency transistor or a high-frequency circuit and a high-frequency transistor or a high-frequency circuit on a main surface. A first substrate having a wiring pattern, and a conductor provided on the main surface of the first substrate so that one end is electrically connected to the first wiring pattern and the other end is located inside the waveguide And a member.

  According to the ninth semiconductor device, one end of the high-frequency transistor or high-frequency circuit formed on the main surface and a first wiring pattern connected to the high-frequency transistor or high-frequency circuit is connected to the first wiring. Since the conductor member is provided so that the other end is located inside the waveguide and connected to the pattern, the semiconductor chip and the waveguide are easily and reliably connected, so that a higher frequency It is possible to operate in a band.

  In the eighth or ninth semiconductor device, the conductor member is preferably plate-shaped or needle-shaped.

  According to the first or second semiconductor device of the present invention, the semiconductor chip on the substrate is not on the second wiring pattern of the semiconductor chip and the substrate until the element formation surface and the main surface of the substrate are opposed to each other. Since the microstrip line composed of the provided dielectric film and the ground pattern is configured, it is not necessary to provide the ground pattern on the surface opposite to the element formation surface of the semiconductor chip. As a result, a microstrip line is formed without providing a grounding pattern on the surface opposite to the element formation surface of the semiconductor chip, so that the microstrip line does not constitute a pseudo-closed space. Oscillation does not occur, and stable and high-performance flip chip mounting can be realized on the semiconductor chip.

  According to the third or fourth semiconductor device of the present invention, even if the semiconductor chip whose element formation surface faces the main surface of the substrate has the second ground pattern on the surface opposite to the element formation surface, the substrate Since the upper first ground pattern has an opening in a region facing the element formation surface of the semiconductor chip in the first ground pattern, the first ground pattern of the substrate is the second ground of the semiconductor chip. Since the pattern and the pseudo closed space are not formed, resonance and unnecessary oscillation do not occur, and stable and high-performance flip chip mounting can be realized on the semiconductor chip.

  In the first or third semiconductor device, when the dielectric film is made of BCB or polyimide, a microstrip line having desired characteristics can be reliably formed.

  In the first to fourth semiconductor devices, when the first wiring pattern and the second wiring pattern are connected via a bump having a thickness of 5 μm or less, the thickness is 5 μm even if the bump is interposed. Therefore, an increase in parasitic inductance due to the thickness of the bump can be ignored.

  In the first to fourth semiconductor devices, when the operating frequency of the high frequency transistor is 10 GHz or more, a high frequency semiconductor device from the quasi-millimeter wave band to the millimeter wave band can be obtained with certainty.

  In the first to fourth semiconductor devices, when the semiconductor chip is an MMIC having at least one high-frequency transistor and at least one passive element, flip-chip mounting of a multifunctional and high-performance MMIC chip is generally realized. it can.

  According to the fifth semiconductor device of the present invention, when the second substrate having the semiconductor chip flip-chip mounted on the main surface is flip-chip mounted on the first substrate, the semiconductor chip is attached to the first substrate. Since it enters the space part which consists of the provided recessed part or hole, even if the semiconductor chip protrudes on the 2nd board | substrate, it can mount reliably.

  In the fifth semiconductor device, when the first wiring pattern and the second wiring pattern are connected via bumps, the electrical connection between the first wiring pattern and the second wiring pattern can be stabilized. And it can be performed reliably.

  In the fifth semiconductor device, when the first substrate and the second substrate are fixed to each other by the photocurable resin material, the first substrate and the second substrate are fixed more firmly, The reliability of the device is improved.

  In the fifth semiconductor device, when the first substrate is made of a film containing polyimide as a main component, the manufacturing cost can be reduced without sacrificing the characteristics of the device.

  In the fifth semiconductor device, when the first substrate further includes an external lead electrically connected to the first wiring pattern, it can be easily connected to another semiconductor device.

  According to the sixth or seventh semiconductor device of the present invention, each main surface is provided on the first substrate so as to be located on the opposite side of the first substrate, and the second connection is made by the plate-like connection means. Since the substrate and the third substrate are electrically connected, different substrates can be combined without using flip-flop mounting. In addition, since the plate-like connection means having a mechanical strength higher than that of the bonding wire or ribbon is used for the electrical connection between the second substrate and the third substrate, the impedance is not disturbed at the connection portion. Inductance can also be reduced.

  In the sixth or seventh semiconductor device, when the connecting means is made of a conductive lead, electrical connection can be easily and reliably made, and the inductance is smaller than that of the bonding wire.

  In the sixth or seventh semiconductor device, when the leads are connected to the first wiring pattern and the second wiring pattern via the bumps, wiring patterns on different substrates can be easily connected to each other. And stable connection.

  In the sixth or seventh semiconductor device, when the connecting means includes a connecting semiconductor chip and a third wiring pattern provided on the connecting semiconductor chip, the shape of the connecting means main body and the shape of the third wiring pattern Therefore, the shape of the third wiring pattern can be optimized without sacrificing the mechanical strength of the connection means main body.

  In the sixth or seventh semiconductor device, when the connection semiconductor chip further includes an element connected to the third wiring pattern, for example, a capacitor element, a resistance element, an inductor, or the like is provided on the connection semiconductor chip. Therefore, it is possible to provide various functions by providing an impedance matching circuit composed of passive elements, or by providing passive elements, so that the degree of freedom in designing a high-frequency semiconductor device can be improved.

  In the sixth or seventh semiconductor device, if the connecting semiconductor chip further includes a filter circuit connected to the third wiring pattern, only a signal having a desired frequency can be transmitted. The configuration of a circuit formed on the second substrate or the third substrate can be simplified.

  In the sixth or seventh semiconductor device, when the connection means is composed of a film made of resin and a third wiring pattern provided on the film, the shape of the connection means main body and the shape of the third wiring pattern are independently set. Therefore, the shape of the third wiring pattern can be optimized without sacrificing the mechanical strength of the connection means main body, and this optimization can be performed at a lower cost than when a semiconductor chip is used.

  In the sixth or seventh semiconductor device, when the third wiring pattern is a coplanar line, the connection can be made without disturbing the characteristic impedance between the second substrate side and the third substrate side.

  In the sixth or seventh semiconductor device, when the third substrate further includes a high-frequency transistor or a high-frequency circuit on the main surface, a multistage high-frequency semiconductor device can be obtained easily and reliably.

  According to the eighth or ninth semiconductor device of the present invention, one end is connected to the first wiring pattern and the other end is guided to the first substrate on which the semiconductor chip provided with the high frequency transistor or the like is flip-chip mounted. Since the conductor member located inside the wave tube is provided, the semiconductor chip and the waveguide are easily and reliably connected, so that it is possible to operate in a higher frequency band.

(First embodiment)
The first embodiment of the present invention relates to an MMIC that enables flip chip mounting.

  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1A shows a cross-sectional configuration of the semiconductor device according to the first embodiment. As shown in FIG. 1A, on the main surface of a substrate 11 made of Si or glass, for example, a GND plane 12 in which titanium (Ti) and gold (Au) are laminated and benzocyclobutene (BCB). And a first wiring pattern 14 formed by laminating Ti and Au are sequentially formed, and the first wiring pattern 14, the dielectric film 13 and the GND plane 12 constitute a microstrip line. Has been. The first wiring pattern 14 is connected to the GND plane 12 through a via hole (not shown) at a location requiring grounding.

  On the substrate 11, an MMIC chip 22 made of gallium arsenide (GaAs) having a high-frequency transistor (not shown) having an operating frequency of 30 GHz and a second wiring pattern 21 connected to the high-frequency transistor formed on the element formation surface. However, the element forming surface and the main surface of the substrate 11 are opposed to each other, and the photocurable resin material 23 is filled in the gap between the element 11 and the substrate 11 and fixed.

  The second wiring pattern 21 of the MMIC chip 22 is provided with a plurality of electrode pads 21a at appropriate positions. The second wiring pattern 21 and the first wiring pattern 14 of the substrate 11 are connected to the electrode pads 21a. Bumps 24 are respectively interposed between the first wiring patterns 14 and are electrically connected using the MBB method.

  In the MMIC chip 22 according to the present embodiment, when the MMIC chip 22 is flip-chip mounted, a microstrip line is formed by the second wiring pattern 21, the dielectric film 13 provided on the substrate 11, and the GND plane 12. Therefore, it is not necessary to provide a GND plane on the surface of the MMIC chip 22 opposite to the element formation surface.

  That is, the second wiring pattern 21 of the MMIC chip 22 is previously made of the material and film thickness of the dielectric film 13 of the substrate 11, the height of the bump 24, and the material of the member positioned between the MMIC chip 22 and the substrate 11. The microstrip line having desired characteristics is obtained in a state in which the MMIC chip 22 is flip-chip mounted on the substrate 11 in consideration of the types and distances.

  When the flip-chip mounting of the MMIC chip 22 is performed using the MBB method, the inventors of the present application use a BCB film having a thickness of, for example, 26 μm as the dielectric film 13 so that the line width of the MMIC chip 22 is reduced to about 70 μm. For example, it has been found that a line having a characteristic impedance of 50Ω can be obtained.

  As described above, the semiconductor device according to the present embodiment normally functions as a high-frequency circuit only after the MMIC chip 22 is flip-chip mounted on the substrate 11, and is originally considered to have a negative effect as a parasitic effect during mounting. The dielectric film 13 on the 11th side and the GND plane 12 are positively used as part of the circuit on the MMIC chip 22 side. Thereby, since the GND plane is not provided on the surface (back surface) opposite to the main surface of the MMIC chip 22, the microstrip line does not form a pseudo closed space with the via hole or the bump, so that cavity resonance does not occur. As a result, a high-frequency circuit with stable operation can be obtained.

  Further, when forming the MMIC chip 22, adjustment of the thickness of the entire chip, backside metallization for forming the GND plane, and formation of a via hole for electrically connecting the GND plane and the wiring pattern of the element formation surface are performed. Since each of them becomes unnecessary, the manufacturing cost can be reduced as compared with a normal MMIC chip having a GND plane on the back surface.

  Further, as shown in a modification of FIG. 1B, a substrate 11 </ b> A made of ceramic may be used instead of the substrate 11. Here, in FIG.1 (b), description is abbreviate | omitted by attaching | subjecting the same code | symbol to the structural member same as the structural member shown to Fig.1 (a). In this case, as shown in FIG. 1B, the GND plane 12 is formed on the surface opposite to the main surface of the substrate 11A, and the first wiring pattern 14 is formed on the main surface to form the substrate 11A. A microstrip line using itself as a dielectric is formed.

  Even in such a configuration, the same effect as that of the present embodiment can be obtained by designing the shape of the second wiring pattern 21 of the MMIC chip 22 in consideration of the thickness of the substrate 11A and the dielectric constant. it can.

  In this embodiment and each of the embodiments described later, the bumps 24 are not necessarily required, and the wiring patterns 14, 21 and the electrode pads 21a, etc. are directly bonded or simply brought into contact with each other, and a shrinkable resin material is used. It may be used to fix the MMIC chip 22 and the substrate 11 together.

(Second Embodiment)
The second embodiment of the present invention relates to a substrate structure that enables flip chip mounting of a normal MMIC.

  Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

  FIG. 2A shows a cross-sectional configuration of the semiconductor device according to the second embodiment. In FIG. 2A, the same components as those shown in FIG. An opening 12a is provided in a region of the first GND plane 12A on the substrate 11 facing the element formation surface of the semiconductor chip 22A, and the MMIC chip 22A has a second surface opposite to the element formation surface. The GND plane 25 has a normal MMIC configuration.

  Thus, according to this embodiment, since the opening 12a is provided in the region of the first GND plane 12A on the substrate 11 that faces the element formation surface of the semiconductor chip 22A, the microstrip line is a conductor film. Since the enclosed pseudo closed space is not formed, cavity resonance does not occur, and as a result, a high-frequency circuit with stable operation can be realized.

  In general, in flip-chip mounting using a high-frequency circuit, a conductive surface having a relatively large area of a GND plane on the substrate side is provided in the vicinity of the microstrip line constituting the circuit of the semiconductor chip. The electromagnetic wave radiated from the microstrip line of the chip may be reflected on the conductor surface, thereby affecting the operation of the circuit of the semiconductor chip. Accordingly, the closer the conductor surface is to the microstrip line of the semiconductor chip, the greater the influence. Therefore, for example, by utilizing the features of the MBB method, the bump height is reduced to reduce the parasitic effect of the bump portion. However, the influence of the reflection of electromagnetic waves from the conductor surface is increased, which may deteriorate the circuit characteristics.

  However, in this embodiment, since the region facing the element formation surface of the MMIC chip 22A in the first GND plane 12A is removed, there is no need to consider the influence of reflection from the first GND plane 12A. The optimal bump height can be selected.

  2B, a substrate 11A made of ceramic may be used instead of the substrate 11. Here, in FIG.2 (b), description is abbreviate | omitted by attaching | subjecting the same code | symbol to the structural member same as the structural member shown to Fig.2 (a). In this case, as shown in FIG. 2B, the GND plane 12A is formed on the surface opposite to the main surface of the substrate 11A, and the first wiring pattern 14 is formed on the main surface. A microstrip line using itself as a dielectric is formed.

  Even with such a configuration, the same effects as those of the second embodiment can be obtained. However, if there is another conductor near the lower side of the substrate 11A, the effect of providing the opening 12a in the first GND plane 12A cannot be obtained sufficiently, so care must be taken.

(Third embodiment)
The third embodiment of the present invention relates to a substrate structure that enables flip chip mounting of MFIC.

  Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

  FIG. 3 shows a cross-sectional configuration of the semiconductor device according to the third embodiment. As shown in FIG. 3, the first substrate 31 made of ceramic or the like and having a space portion 31 a made of a concave portion on the main surface has a first wiring pattern 32 formed by stacking Ti and Au on the main surface. A first GND plane 33 formed by laminating Ti and Au is formed on the surface opposite to the main surface, and the first wiring pattern 32, the first substrate 31, and the first GND plane 33 are connected to the first GND plane 33. The microstrip line 34 is configured. The first wiring pattern 32 is grounded through a via hole (not shown) appropriately provided in the first substrate 31.

  A second substrate 41 made of Si is flip-chip mounted on the main surface of the first substrate 31 so as to straddle the space 31 a of the first substrate 31. Further, on the main surface of the second substrate 41, for example, a semiconductor chip 42 made of GaAs or the like on which a high-frequency transistor (not shown) having an operating frequency of 30 GHz or the like is formed is a space formed by a recess of the first substrate 31. The second substrate 41 and the MFIC chip 40 are configured by flip chip mounting so as to enter the portion 31a.

  On the main surface of the second substrate 41, a second GND plane 43a formed by stacking Ti and Au, a dielectric film 43b formed by BCB, and a second wiring pattern 43c formed by stacking Ti and Au are formed. The second microstrip line 43 is formed by sequentially forming the second GND plane 43a, the dielectric film 43b, and the second wiring pattern 43c. The second wiring pattern 43c is electrically connected to the first wiring pattern 32 of the first substrate 31 and the semiconductor chip 42 with bumps 44 interposed therebetween. Here, if the connection part of the 1st board | substrate 31 and the 2nd board | substrate 41, ie, the vicinity of bump 44, is fixed using a photocurable resin material, it can connect still more firmly.

  As described above, according to the present embodiment, since the first substrate 31 is provided with the space portion 31 a formed of the concave portion, the semiconductor chip 42 provided on the main surface of the second substrate 41 in the MFIC chip 40. If it enters into the space 31a provided on the first substrate 31, flip-chip mounting can be ensured.

  In the present embodiment, the MFIC chip 40 having one semiconductor chip 42 is flip-chip mounted on the second substrate 41. However, the MFIC chip 40 having a plurality of semiconductor chips 42 may be used. In this case, on the main surface of the first substrate 31, a space portion 31 a may be provided over the entire surface in a region facing the MFIC chip 40, and a plurality of space portions 31 a are formed for each region facing each semiconductor chip 42. It may be provided.

  In the present embodiment, the line provided on the first substrate 31 is the microstrip line 34, but may be another form of line such as a coplanar line.

  Further, the first substrate 31 may be provided with a space portion formed of a hole portion penetrating the recess portion instead of the space portion 31a formed of the recess portion.

(Fourth embodiment)
The fourth embodiment of the present invention relates to a substrate structure that enables flip chip mounting of MFIC.

  Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

  FIG. 4 shows a cross-sectional configuration of the semiconductor device according to the fourth embodiment. In FIG. 4, the same components as those shown in FIG. As shown in FIG. 4, the difference from the semiconductor device according to the third embodiment is that a film base 31A having a space portion 31b made of polyimide or the like and having a hole portion is used as the first substrate. . Therefore, the semiconductor chip 42 provided on the main surface of the second substrate 41 in the MFIC chip 40 is flip-chip mounted so as to enter the space portion 31b provided in the first substrate 31A.

  In the present embodiment, an inexpensive and easy-to-process film is used as the material for the substrate on which the MFIC chip 40 is mounted. In general, it is difficult to form a recess by mechanically processing a high-hardness substrate made of ceramic or the like, and the cost tends to be high, but in the case of the film base 31A made of polyimide or the like as in this embodiment, If a punch or the like is used, the space portion 31b made of a hole can be easily formed, so that the MFIC chip 40 can be mounted very easily.

  In addition, you may provide the space part which consists of a recessed part in 31 A of film bases instead of the space part 31b which consists of a hole.

(Fifth embodiment)
The fifth embodiment of the present invention relates to MFIC packaging.

  Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

  FIGS. 5A and 5B show a semiconductor device according to the fifth embodiment, in which FIG. 5A shows a cross-sectional configuration, and FIG. 5B shows a state before mounting the MFIC chip along the II line in FIG. The plane configuration is shown. As shown in FIG. 5 (a), the package housing 51 has a recess 52a and a first wiring pattern 53 made of a conductor film on the main surface, and a conductor film on the surface opposite to the main surface. A package base 52 made of ceramic as a first substrate on which the GND plane 54 made of is formed is fitted, and the wiring pattern 53, the package base 52 and the GND plane 54 constitute a microstrip line.

  On the main surface of the package base 52, the MFIC chip 40 including the second substrate 41 and the semiconductor chip 42 flip-chip mounted on the second substrate 41 shown in the third embodiment is the package base 52. Flip chip mounting is performed so as to straddle the recess 52a and allow the semiconductor chip 42 to enter the recess 52a. The wiring pattern 53 is connected to the internal lead 55 inside the casing 51, and the internal lead 55 is connected to the external lead 56 extending to the outside of the casing. Here, the internal lead 55 and the external lead 56 may be integrally formed.

  As shown in FIG. 5B, on the main surface of the package base 52, on the left end side and the right end side in the drawing around the rectangular recess 52a, and on both sides of the wiring pattern 53, respectively. Four ground patterns 57 are formed at intervals, and each ground pattern 57 is connected to the GND plane 54 via a via hole (not shown) penetrating the package base 52.

  The package of the semiconductor device according to the present embodiment extracts a high frequency signal from the external lead 56 on the side where the ground pattern 57 shown in FIG. 5B is formed, and extracts a bias signal from the external lead 56 on the other side. It has a configuration suitable for. Therefore, for example, if a GND plane is formed on the wiring pattern on the MFIC chip 40 side like a coplanar line, grounding can be performed on the same plane as the wiring pattern, so that disturbance of impedance is reduced even in a higher frequency band. be able to.

  As described above, according to the present embodiment, since the MFIC chip 40 is packaged by flip chip mounting with a small parasitic effect, it can be easily connected to another substrate while taking advantage of the excellent high frequency characteristics of the MFIC. Can do.

(Sixth embodiment)
The sixth embodiment of the present invention is a mounting method instead of flip-chip mounting, and relates to a mounting structure for mounting an MFIC or MMIC on a mother board.

  Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings.

  FIG. 6A shows a cross-sectional configuration of the semiconductor device according to the sixth embodiment. As shown in FIG. 6A, for example, a second substrate 71 made of Si and both sides of the second substrate 71 are formed on a first substrate 61 made of brass or the like and having conductivity. The third substrate 81 made of ceramic is fixed using, for example, a conductive paste so that the main surface is located on the opposite side of the first substrate.

  The second substrate 71 includes a first GND plane 72a formed by laminating Ti and Au on the main surface, a dielectric film 72b composed of BCB, and a first wiring pattern 72c formed by laminating Ti and Au sequentially. The first microstrip line 72 is formed by the first GND plane 72a, the dielectric film 72b, and the first wiring pattern 72c. The first wiring pattern 72c is grounded through a via hole (not shown) appropriately provided in the second substrate 71.

  On the second substrate 71, an MMIC chip 73 having a high-frequency transistor or a high-frequency circuit (not shown) having an operating frequency of 30 GHz on the element formation surface is flip-chip mounted by the MBB method using the micro bumps 74. The MFIC chip 70 is configured together with the second substrate 71.

  Each of the third substrates 81 is provided with a second wiring pattern 82 made of copper, titanium, gold or the like on the main surface, and a second wiring pattern 82 made of copper, titanium or gold on the surface opposite to the main surface. A GND plane 83 is formed, and a second microstrip line is formed from the second wiring pattern 82, the third substrate 81, and the second GND plane 83 to constitute a circuit board 80. Further, a passive element may be provided on the third substrate 81.

  Here, the height position of the upper surface of the first wiring pattern 72 c of the MFIC chip 70 and the height position of the upper surface of the second wiring pattern 82 of the circuit board 80 with respect to the substrate surface of the first substrate 61. Are substantially the same, and the first wiring pattern 72c and the second wiring pattern 82 are connected to each other by using conductive leads 84 as plate-like connecting means.

  The lead 84 is made of, for example, a metal whose surface is gold-plated, and the connection portions of the first wiring pattern 72c and the second wiring pattern 82 are connected by, for example, thermocompression bonding. In addition, micro bumps made of Au may be interposed by using the MBB method, and a stronger connection can be obtained by fixing using a photo-curing resin material.

  According to the present embodiment, the MFIC chip 70 and the circuit board 80 are fixed on the first substrate 61 and are electrically connected to each other using the leads 84. Therefore, compared to the case of using a normal bonding wire or ribbon, since the lead 84 itself is strong and less deformed, it is possible to realize a connection structure in which impedance is not disturbed in a connection portion that electrically connects substrates.

  In addition, the width dimension of the lead 84 can be designed in advance so that it becomes a microstrip line having an appropriate impedance with respect to the GND planes 72a and 83 of the MFIC chip 70 and the circuit board 80. It is possible to form a low-loss connection portion optimized for each. That is, the width dimension of the lead 84 is not the same width, but is matched with the wiring width of the first wiring pattern 72c of the MFIC chip 70 on or near the MFIC chip 70, and on or near the circuit board 80. By adjusting to the wiring width of the second wiring pattern 82 of the circuit board 80, it is possible to provide an impedance adjustment function that matches the first wiring pattern 72c and the second wiring pattern 82, respectively.

  In the present embodiment, the height of the upper surface of the first wiring pattern 72c of the MFIC chip 70 and the upper surface of the second wiring pattern 82 of the circuit board 80 from the substrate surface of the first substrate 61 is substantially the same. However, the total film thickness of the second substrate 71 and the first macrostrip line 72 in the MFIC chip 70, the third substrate 81, the second wiring pattern 82 and the second in the circuit substrate 80. Even if the total film thickness of the GND plane 83 is different, the film thickness on the lower side of the MFIC chip 70 and the film thickness on the lower side of the circuit board 80 on the first substrate 61 are changed to the first wiring pattern. What is necessary is just to process and adjust so that the upper surface of 72c and the upper surface of the 2nd wiring pattern 82 may become substantially the same height.

  In order to clarify the positional relationship among the MFIC chip 70, the circuit board 80, and the leads 84 on the drawing, gaps are provided on the side surfaces of the MFIC chip 70 and the circuit board 80 adjacent to each other. The device does not necessarily require this gap.

  Further, as shown in the first modification of FIG. 6B, a configuration may be adopted in which a plurality of MFIC chips 70 are electrically connected to each other using leads 84 on the first substrate 61. In this way, a multistage high-frequency circuit can be obtained easily and reliably.

  Further, as shown in the second modification example in FIG. 6C, an MMIC chip 75 may be provided on the first substrate 61 instead of the MFIC chip 70. The MMIC chip 75 includes, for example, a high-frequency transistor portion 77 having a high-frequency transistor with an operating frequency of 30 GHz and a first wiring pattern 78 on the element formation surface of the second substrate 76 made of GaAs, and is opposite to the element formation surface. A first GND plane 79 is formed on this surface.

  As described above, the MMIC chip 75 can be directly provided on the first substrate 61. As can be easily inferred from FIGS. 6A, 6B, and 6C, on the first substrate 61, One or more of the MFIC chip 70, the MMIC chip 75, and the circuit board 80 may be appropriately combined so as to obtain desired characteristics.

(Seventh embodiment)
The seventh embodiment of the present invention is a mounting method instead of flip-chip mounting, and relates to a mounting structure for mounting an MFIC or MMIC on a mother board.

  The seventh embodiment of the present invention will be described below with reference to the drawings.

  FIG. 7 shows a cross-sectional configuration of a semiconductor device according to the seventh embodiment. In FIG. 7, the same components as those shown in FIG. 6A are denoted by the same reference numerals and the description thereof is omitted. As shown in FIG. 7, the connecting semiconductor chip 85 is used as a plate-like connecting means for electrically connecting the MFIC chip 70 and the circuit board 80.

  The connecting semiconductor chip 85 has the main surface opposed to the second and third substrates 71 and 81 so that the main surface extends over the second substrate 71 of the MFIC chip 70 and the third substrate 81 of the circuit board 80. The third wiring pattern 86 is formed on the main surface. The third wiring pattern 86 is connected to the first wiring pattern 72c of the second substrate 71 and the second wiring pattern 82 of the third substrate 81 through bumps 87, respectively. Here, if the connecting semiconductor chip 85 and the second substrate 71 and the third substrate 81 are fixed using a photo-curing resin material, the connecting semiconductor chip 85 and the second and third substrates 71, 71, The mutual electrical connection with 81 is further ensured, and the long-term reliability of the device is improved.

  In this embodiment, a connecting semiconductor chip 85 is used in place of the lead 84 as an electrical connection means between the MFIC chip 70 and the circuit board 80. For this reason, in the case of the lead 84, the shape of the lead 84 is limited due to the mechanical strength limitation. In the case of the connecting semiconductor chip 85, the third wiring pattern 86 provided on the connecting semiconductor chip 85 is used. Is used to electrically connect the MFIC chip 70 and the circuit board 80, the shape of the third wiring pattern 86 can be designed independently of the mechanical strength.

  Furthermore, it is possible to provide the connection means with various functions by providing an impedance matching circuit including a passive element such as a capacitive element, a resistive element or an inductor, or by providing a passive element.

  Further, it is possible to form a filter circuit using the third wiring pattern 86 on the connecting semiconductor chip 85 and to provide a connecting means for transmitting only a desired frequency band.

  Further, an MMIC chip including an appropriate active element may be used as the connection semiconductor chip 85, and in this case, various functions can be provided.

  Also in this embodiment, as shown in the sixth embodiment, one or more MFIC chips 70, MMIC chips 75, and circuit boards 80 can each have desired characteristics on the first substrate 61. Needless to say, they can be combined appropriately.

(Eighth embodiment)
The eighth embodiment of the present invention is a mounting method instead of flip-chip mounting, and relates to a mounting structure in which an MFIC or MMIC is simply mounted on a mother board.

  Hereinafter, an eighth embodiment of the present invention will be described with reference to the drawings.

  FIG. 8A shows a cross-sectional configuration of the semiconductor device according to the eighth embodiment. In FIG. 8A, the same components as those shown in FIG. As shown in FIG. 8A, a connection film 88 made of a resin such as polyimide is used for plate-like connection means for electrically connecting the MFIC chip 70 and the circuit board 80.

  The connection film 88 is provided so as to straddle the second substrate 71 of the MFIC chip 70 and the third substrate 81 of the circuit board 80, and the surface facing the substrate side is shown in the plan view of FIG. As shown, a coplanar line 89 is formed as a third wiring pattern including a signal line 89A and two ground lines 89B spaced from each other on both sides of the signal line 89A.

  The coplanar line 89 can obtain a predetermined impedance by appropriately selecting the line width of the signal line 89A and the distance between the side portions of the signal line 89A and the ground line 89B. The coplanar line 89 has a first wiring pattern 72c on the second substrate 71 and a second line on the third substrate 81 with bumps 90 provided at both ends of the signal line 89A and each ground line 89B. Each is connected to the wiring pattern 82. Here, if the connection film 88 is fixed to the second substrate 71 and the third substrate 81 using a photocurable resin material, the connection semiconductor chip 85 and the second and third substrates 71 and 81 are fixed. The connection with each other is further ensured.

  Thus, according to the present embodiment, the connection film 88 is used in place of the lead 84 or the connection semiconductor chip 85 as an electrical connection means between the MFIC chip 70 and the circuit board 80. For this reason, the degree of freedom of the wiring shape of the connecting means and the addition of various functions can be realized more easily and at a lower cost than when the connecting semiconductor chip 85 is used.

  The wiring pattern on the connection film 88 is not limited to the coplanar line 89. For example, when impedance matching is performed without using the coplanar line 89, the line width of the wiring pattern on the connection film 88 is the same as that of the first wiring pattern 72c in the region on the MFIC chip 70 side, and The region on the circuit board 80 side may be the same as the second wiring pattern 82.

  Also in this embodiment, as shown in the sixth embodiment, one or more MFIC chips 70, MMIC chips 75, and circuit boards 80 can each have desired characteristics on the first substrate 61. Needless to say, they can be combined appropriately.

(Ninth embodiment)
The ninth embodiment of the present invention relates to packaging that can use MFIC or MMIC in a higher frequency band.

  The ninth embodiment of the present invention will be described below with reference to the drawings.

  FIG. 9 shows a cross-sectional configuration of a semiconductor device according to the ninth embodiment. In FIG. 9, the same components as those shown in FIG. 6A are denoted by the same reference numerals, and the description thereof is omitted. As shown in FIG. 9, a housing 91 made of a conductor is provided with a mounting stage portion 91a for mounting a semiconductor device and a waveguide portion 91b to be a waveguide on a part thereof. The mounting stage portion 91a has the MFIC chip 70 and the circuit board 80, which are electrically connected using the connection leads 84A, fixed thereto using a conductive paste or the like. The first wiring of the MFIC chip 70 An antenna lead 94 having one end electrically connected to the first wiring pattern 72c and the other end positioned on the waveguide 91b is provided at the end of the pattern 72c opposite to the circuit board 80.

  The waveguide portion 91b has a dimension that becomes a waveguide for an electromagnetic wave having a desired frequency, and the end portion of the antenna lead 94 is placed inside the waveguide portion 91b. The radio wave signal propagating through 91b can be transmitted to the MFIC chip 70.

  As described above, according to the present embodiment, as is well known as a waveguide design technique, by optimizing the position of the terminal end of the waveguide 91b and the position of the antenna lead 94, a desired frequency band can be obtained. Signal transmission with low loss is possible.

  Note that the housing 91 may be directly connected to a waveguide circuit (not shown), and radio waves can be emitted into the space using the opening of the waveguide portion 91b.

  In this embodiment, the antenna lead 94 is used for the antenna, but a needle-like member made of a conductor may be used.

  Further, although the connection lead 84A is used as an electrical connection means between the MFIC chip 70 and the circuit board 80, the connection semiconductor chip 85 shown in FIG. 7 or the connection film 88 shown in FIG. 8 may be used.

  Further, on the mounting stage portion 91a of the casing 91, as shown in the sixth embodiment, one or more MFIC chips 70, MMIC chips 75, and a circuit board 80 are combined so as to obtain desired characteristics. Alternatively, the flip chip mounted MFIC chip 40 shown in the third or fourth embodiment may be used.

1A is a structural cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. FIG. 1B is a sectional view showing a configuration of a semiconductor device according to a modification of the first embodiment of the present invention. FIG. 5A is a structural cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. FIG. 2B is a structural cross-sectional view showing a semiconductor device according to a modification of the second embodiment of the present invention. It is a structure sectional view showing a semiconductor device concerning a 3rd embodiment of the present invention. It is a structure sectional view showing a semiconductor device concerning a 4th embodiment of the present invention. (A) And (b) is a semiconductor device which concerns on 5th Embodiment, (a) is a structure sectional drawing, (b) is before mounting of the MFIC chip in the II line of (a). It is a top view. (A) is a cross-sectional view showing a semiconductor device according to a sixth embodiment of the present invention. FIG. 6B is a structural cross-sectional view showing a semiconductor device according to a first modification of the sixth embodiment of the present invention. FIG. 6C is a structural cross-sectional view showing a semiconductor device according to a second modification of the sixth embodiment of the present invention. It is a structure sectional view showing a semiconductor device concerning a 7th embodiment of the present invention. (A) And (b) is a semiconductor device which concerns on 8th Embodiment, (a) is a structure sectional drawing, (b) is a top view of the connection means of (a). It is a semiconductor device which concerns on the 9th Embodiment of this invention, Comprising: It is a fragmentary sectional view which shows the package which mounted the MFIC chip | tip. It is a structure sectional view showing the conventional MFIC. It is a structure sectional view showing a semiconductor device in which a conventional MMIC is flip-chip mounted.

Explanation of symbols

11 Substrate 11A Substrate (Dielectric)
12 GND plane (ground pattern)
12A 1st GND plane 12a Opening 13 Dielectric film 14 1st wiring pattern 21 2nd wiring pattern 21a Electrode pad 22 MMIC chip (semiconductor chip)
22A MMIC chip (semiconductor chip)
23 Photocurable resin material 24 Bump 25 Second GND plane 31 First substrate 31A Film base (first substrate)
31a Space (recess)
31b Space (hole)
32 First wiring pattern 33 First GND plane 34 First microstrip line 40 MFIC chip 41 Second substrate 41
42 Semiconductor chip 43 Second microstrip line 43a Second GND plane 43b Dielectric film 43c Second wiring pattern 44 Bump 51 Housing 52 Package base (first substrate)
52a Recess 53 Wiring pattern 54 GND plane 55 Internal lead 56 External lead 57 Ground pattern 61 First substrate 70 MFIC chip 71 Second substrate 72 First microstrip line 72a First GND plane 72b Dielectric film 72c First Wiring pattern 73 MMIC chip 74 Micro bump 75 MMIC chip 76 Second substrate 77 High-frequency transistor section 78 First wiring pattern 79 First GND plane 80 Circuit board 81 Third substrate 82 Second wiring pattern 83 Second GND plane 84 lead (connection means)
84A Connection lead 85 Connection semiconductor chip (connection means)
86 Third wiring pattern 87 Bump 88 Connection film (connection means)
89 Coplanar line (third wiring pattern)
89A Signal line 89B Ground line 90 Bump 91 Housing 91a Mounting stage part 91b Waveguide part (waveguide)
94 Antenna lead (conductor member)

Claims (6)

A substrate on which a first ground pattern made of a conductor film, a dielectric film, and a first wiring pattern made of a conductor film are sequentially formed on the main surface;
A semiconductor chip having a second wiring pattern made of a high-frequency transistor and a conductor film connected to the high-frequency transistor on the element formation surface, and a second ground pattern made of a conductor film on the surface opposite to the element formation surface And
With the element formation surface of the semiconductor chip facing the main surface of the substrate, the second wiring pattern and the first wiring pattern are connected to each other,
The semiconductor device according to claim 1, wherein the first ground pattern has an opening in a region facing an element formation surface of the semiconductor chip. It said dielectric layer is a semiconductor device according to claim 1, wherein the BC B or Ranaru. A substrate made of a dielectric having a first wiring pattern made of a conductor film on a main surface and having a first ground pattern on a surface opposite to the main surface;
A semiconductor chip having a second wiring pattern made of a high-frequency transistor and a conductor film connected to the high-frequency transistor on the element formation surface, and a second ground pattern made of a conductor film on the surface opposite to the element formation surface And
With the element formation surface of the semiconductor chip facing the main surface of the substrate, the second wiring pattern and the first wiring pattern are connected to each other,
The semiconductor device according to claim 1, wherein the first ground pattern has an opening in a region facing an element formation surface of the semiconductor chip. Wherein the first wiring pattern and the second wiring pattern, a semiconductor device according to claim 1 or 3, characterized in that it is connected via the bus amplifier.   The semiconductor device according to claim 1, wherein an operating frequency of the high-frequency transistor is 10 GHz or more.   The semiconductor device according to claim 1, wherein the semiconductor chip is an MMIC including at least one high-frequency transistor and at least one passive element.

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