JP2005116927A - Substrate for semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a substrate for a semiconductor device which builds therein coexisting passive components including not only a resistive element but also fine wiring and a fine and accurate passive element associated therewith, and also to provide a method for manufacturing the semiconductor device. <P>SOLUTION: The substrate for a semiconductor device having passive components built therein has a two-layer structure of a first conductor layer having a thin conductor thickness at least in the vicinity of a passive component formation region, and a second conductor layer having a thick conductor thickness formed on the first conductor layer. In forming a passive component of the two-layer structure, ends of patterns of the first and second conductor layers are arranged so that the end of the first conductor layer directly determines dimension of the passive component, or the end of the first conductor layer determines the end position of the second conductor layer, and a distance between the ends of the first conductor layer determines the element dimensions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a substrate for a semiconductor device having fine and high-density wiring of an electric circuit and a passive element built in the substrate, and a method for manufacturing the same.

  Several types of conventional passive component-embedded substrates are known. As an example, a resistive element built-in substrate is a type in which a finished chip component is arranged and embedded in the substrate, a type in which a resistive paste is printed to form a thick film resistor on the substrate, and a thin resistive element by electroless plating A type in which a pattern is formed and a type in which a special base material having a thin resistance layer under a copper foil is used to form a resistance element at the time of pattern formation are known (see Non-Patent Document 1).

  5A and 5B are partial views of a conventional substrate for a semiconductor device, in which FIG. 5A is a plan view, FIG. 5B is a side sectional view of a wiring portion, and FIG. 5C is a side sectional view of a thin film resistor element portion. FIG. In FIG. 5A, wirings are arranged on the left and right on the substrate 1, and a thin film resistance element is formed between the wirings. The wiring is formed by the conductor layer 40. The thin film resistance element is formed by a thin film resistance layer 2. An electric circuit is formed by connecting the wiring on the left side of the drawing and the wiring on the right side through passive components of a thin film resistance element. In the drawing, a cross-sectional view taken along the line yy is shown in FIG. 5B, and a cross-sectional view taken along the line xx is shown in FIG. 5C. FIG. 5B shows a cross section of the wiring portion, and has a structure in which the thin film resistor layer 2 and the conductor layer 40 are stacked in order on the substrate 1. In the wiring, since the conductor layer thickness of the conductor layer 40 is sufficiently thick like a normal printed wiring board, the direct current resistance is small. FIG. 5C shows the vicinity of the passive component of the thin film resistance element, and the element dimension in the length direction of the thin film resistance element is regulated by the distance between the left and right conductor layers 40. In the element of the thin film resistance layer 2, there are end portions of the conductor layer 40 on the left and right sides of the drawing and an exposed portion of the thin film resistance layer 2 in the center, and a symmetrical valley is formed around the thin film resistance layer. In order to ensure the accuracy of the thin film resistance element, the thin film resistance element is often formed in a wider and larger area than the wiring.

  FIG. 6 is a process diagram of a side sectional view for explaining a conventional method of manufacturing a substrate for a semiconductor device. Note that the inside of the dotted line frame on the right side of FIG. 6 is a plan view. The thin film resistance layer 2 and the conductor layer 40 are sequentially laminated on the substrate 1 (see FIG. 6A). A resist 30 is patterned on the conductor layer 40 (see FIG. 6B). The conductor layer 40 and the thin film resistance layer 2 are simultaneously removed by etching. The resist is stripped (see FIG. 6C). In the first etching process, the dimensional accuracy in the width direction of the wiring is regulated. A resist 31 is patterned again on the conductor layer 40 (see FIG. 6D). Only the conductor layer 40 of the thin film resistance element portion is removed by etching (see FIG. 6E). The resist is stripped (see FIG. 6F). In the second etching process, the accuracy of the element dimensions of the thin film resistance element is regulated. As described above, in the first etching step, the conductor layer 40 and the thin-film resistance layer 2 are simultaneously etched, and in the second time, only the conductor layer 40 is etched. That is, in the shape pattern (thin film resistance element) of the thin film resistance layer 2, the finishing accuracy becomes unstable. In addition, when removing other than the pattern to be left as copper by etching, the thin film resistance layer is left on the entire surface, only the portion to be formed as the thin film resistance element is covered with another resist, and only the exposed thin film resistance layer is covered. There is also a method of removing and obtaining a desired circuit pattern.

On the other hand, the type in which the chip component is embedded requires an apparatus for mounting the chip component, or the size of the chip component itself is large. For example, a microchip component called 0402 that has recently been used is 400 μm × 200 μm. The size is still large compared to the wiring of the substrate for the semiconductor device, and the thickness is also very large compared to other types, so many chip parts must be mounted on the substrate for the semiconductor device. Was difficult. Also, in the type in which a resistance paste is printed to form a thick film resistor, it is difficult to control the film thickness and dimensions of the paste to be printed. In Patent Document 1, an insulator dam is provided in advance around the resistor, and the resistor is provided therein by printing. In order to prevent dimensional changes due to blurring or the like, it has been devised. However, with the type that prints paste, it is difficult to control the film thickness, and the accuracy of the element is greatly affected, and it is difficult to further reduce the size of the element. On the other hand, a method of forming a thin film pattern mainly composed of nickel by electroless plating has recently been attracting attention, but the composition of the film is likely to change depending on the plating conditions, and the sheet resistance value of the obtained film is highly accurate. It was difficult to control. Therefore, for semiconductor device substrates that require high-precision resistance elements, use a type in which a resistance element is made using a special base material having a thin resistance layer under a copper foil as in Non-Patent Document 2. In other words, the resistance element pattern was corrected by laser trimming for each element while measuring the resistance value.

The known literature is described below.
JP-A-11-168282 Electronics Packaging Technology 2003.3.1 (Vol.19 No.1) 20-25 PRODUCT LINE Copper Foil Integrated Thin Film Resistor (Gould Electronics Inc.)

  As described above, for a substrate that requires a high-precision resistance element, a method of creating a resistance element using a special base material having a thin resistance layer under a copper foil has been used. In the manufacturing of, for example, a nickel-phosphorous layer having a thickness of 1 μm or less is formed on a mat surface of a copper foil having a thickness of 18 μm by electroless plating, or a nickel-chrome layer is formed by sputtering to form a resistance layer. However, since the original copper foil thickness is determined to be 18 μm or the like and the copper foil thickness cannot be freely selected, it is difficult to form a conductor pattern having a pitch of, for example, 30 μm or less, which is required for a substrate for a semiconductor device in recent years. The bottom of the conductor that determines the resistance value accuracy with a slight difference in the etching amount because the insulation of the wiring is likely to occur and the shape of the bottom of the wiring becomes uneven due to the unevenness of the roughened copper foil surface. Since the dimensions change, it is difficult to control.

On the other hand, as a flexible substrate material, a type of material in which a nickel-chromium thin film resistance layer is formed on a polyimide base film and a copper layer is formed thereon by sputtering and electrolytic plating has emerged. When this material is used, since a free copper thickness can be obtained by plating, it is more advantageous for forming a fine pattern than a material using a copper foil. However, in the case of forming a pattern using a photo process method, in the case of a subtractive method in which a pattern is formed after forming a copper layer thickly by plating, in the same manner as in the case of using the copper foil, a resistance pattern is formed. There is almost no difference in the accuracy of the parts. On the other hand, the process of forming the conductor pattern and the resistance pattern by the semi-additive method is roughly divided into two types. The first method is to perform electrolytic copper plating on both the resistance pattern forming portion and the conductor pattern forming portion to form a copper pattern having a required thickness, and then etching the copper in the resistance pattern forming portion to form a resistance element. It is a method of forming. In this method, the dimensional accuracy in the width direction is higher than that in the subtractive method, but since the resistance pattern accuracy in the length direction is not improved because it is formed by etching, the accuracy of the obtained resistance element cannot be improved so much. The second method is to electroplat only the conductor pattern part, then mask the resistance element formation part with a resist and simultaneously etch the thin film copper layer and the thin film resistive layer, and after removing the resist, remove the copper thin film on the resistive layer Or a method of removing the thin film copper layer after electrolytic plating and then removing the surrounding thin film resistance layer by masking the resistance element forming portion with a resist. However, in this method, it is necessary to fill the step between the copper pattern and the thin film copper layer or the thin film resistance layer, and the resist to be used must be made sufficiently thick. Therefore, it is difficult to improve the dimensional accuracy of the resist pattern to be formed. Even with this method, the accuracy to the point corresponding to fine wiring could not be obtained. Therefore, the method of creating a resistance element using a special base material having a thin resistance layer under the copper foil, which is known as a method for obtaining the highest resistance value accuracy according to the prior art, is highly accurate. In order to obtain a resistance element, there is a problem that a large resistance element has to be obtained to a size close to that of a chip component.

  That is, in order to cope with fine wiring, it is necessary to reduce the size of the resistance pattern, but even if the size is simply reduced, the pattern formation accuracy itself is hardly improved. The accuracy only worsened.

  When the resistance element is formed in this way, for example, in the case of a resistance element having a width of 100 μm and a length of 200 μm, both the width and length accuracy of the element dimensions are about ± 10 μm, and the resistance value accuracy in that case is Although it is about ± 10 to 15%, if the dimension of the resistance element is to be formed with a width of 15 μm and a length of 30 μm, the dimensional accuracy with respect to the element size is relatively lowered even if the element dimensional accuracy is improved to ± 5 μm. Therefore, the accuracy of about ± 40 to 50% is finally reached.

  In order to improve the resistance element accuracy, the element size itself must be increased, but conversely, if the element size is increased, not only the high-density wiring is disturbed, but also the high frequency characteristics of the resistance element are deteriorated. For this reason, there is an increasing number of cases where it cannot be used for a substrate for a semiconductor device in which speeding up has progressed.

  In order to cope with this, there is a method of performing laser trimming for each element while measuring the resistance value. However, if the number of elements is large, trimming time and cost become enormous, and there is a strong demand for using without trimming. In addition, the minimum size of a resistance element that seems to be a standard is about 200 μm in width or larger, but a resistance element having a width of 50 μm or less is required due to an improvement in wiring density. However, when the size is 100 μm or less, it becomes difficult to perform trimming with high accuracy using a laser having a beam diameter of several tens of μm.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a substrate for a semiconductor device including a passive component in which not only a resistive element but also a fine wiring and a corresponding fine and highly accurate passive element coexist, and a manufacturing method thereof.

  As a result of considering the above problems, the invention according to claim 1 of the present invention provides a semiconductor device substrate incorporating a passive component, wherein the first conductor layer having a thin conductor at least in the vicinity of the passive component forming portion, The conductor formed on the first conductor layer has a two-layer structure with a second conductor layer having a large thickness, and the formation of the passive component having the two-layer structure has a first conductor with a small thickness. The substrate for a semiconductor device is characterized in that the element size of the passive component is determined by the size of the pattern formed on the conductor layer.

  At least the conductor in the vicinity of the passive component forming portion is composed of a two-layer structure of a first conductor layer having a small thickness and a second conductor layer formed on the first conductor layer, depending on the dimensions of the first conductor layer. A device was devised to determine the element dimensions of the passive component. That is, a two-layer structure of a thin first conductor layer and a thick second conductor layer is used, and the element dimensions are determined by the first conductor layer that is thin and easy to form with high precision. This is a semiconductor device substrate having a structure in which the DC resistance is reduced by the two conductor layers and the electrical characteristics of the element are not easily lowered.

  Specifically, when forming the resistance element, the first conductor layer can be formed with high precision by providing the thin first conductor layer in contact with the thin film resistance layer, and the second conductor having the necessary thickness is formed thereon. The conductors were stacked. In addition, with this structure, it is possible to improve the accuracy other than the resistance elements such as capacitors and coils. For example, when applied to a capacitor as a passive component, it is possible to increase the capacitance accuracy by improving the dimensional accuracy of the counter electrode, and when applied to a coil, the wiring of the coil forming part can be formed minutely and with high accuracy. Thus, a coil having a high value of inductance can be built with high accuracy.

  In the invention according to claim 2 of the present invention, the end portions of the pattern of the first conductor layer having a small thickness and the second conductor layer having a large conductor thickness are located at different positions, and the first conductor layer having a small thickness. The structure in which the element size of the passive component is directly determined by one conductor layer, or the end position of the second conductor layer having a thick conductor is determined by the end of the first conductor layer, and the first conductor layer 2. The semiconductor device substrate according to claim 1, wherein an element size is determined by a distance between the end portions.

  In the invention according to claim 3 of the present invention, the first conductor layer and the second conductor layer of the semiconductor device substrate are made of copper, and at least part of the conductor surface is made of gold, nickel, platinum, rhodium, palladium, 3. The semiconductor device substrate according to claim 1, wherein a conductive material made of silver, tin, an alloy containing these, or carbon is formed.

  This is a mode in which the first conductor layer and the second conductor layer are formed of copper having good electrical conductivity, and the connection terminal portion to the semiconductor element or the wiring board is protected by a noble metal or the like whose contact resistance is not easily lowered. It is a thing.

  According to a fourth aspect of the present invention, a conductor having a width of 15 μm or less and a conductor adjacent thereto are formed on at least a part of the substrate for a semiconductor device by a gap of 15 μm or less and narrower than the width of the conductor. 4. The semiconductor device substrate according to claim 1, wherein the substrate is a semiconductor device substrate.

  This shows that the manufacturing process of the present invention is particularly suitable for manufacturing a conductor with a fine pitch, and the fine conductors obtained as a result can be formed wider than adjacent gaps.

  In the invention according to claim 5 of the present invention, the element of the passive component built in the substrate for a semiconductor device is a resistance element having at least one of a width and a length of 50 μm or less and a thickness of 1 μm or less. 5. The substrate for a semiconductor device according to claim 1, wherein the width of the resistance element is the same as or narrower than that of the conductor layer 1 of the conductor to be connected.

  According to the present invention, a thin film resistive element having a particularly large effect is finely formed and can coexist with a fine wiring. The width of the resistive element is reduced so as not to obstruct the fine wiring by arranging the resistive element. The first conductor layer is the same as or thinner than the first conductor layer.

  The invention according to claim 6 of the present invention includes a first conductor layer having a thin conductor at least in the vicinity of the passive component forming portion and a second conductor having a thick conductor formed on the first conductor layer. In a method for manufacturing a substrate for a semiconductor device, which has a two-layer structure with a conductive layer of the semiconductor device and includes a passive component formed from the two-layer structure, a first conductor layer pattern is formed on an insulating base material by a subtractive method. 6. The semiconductor device according to claim 1, further comprising a step of forming a second conductor layer pattern on the first conductor layer pattern by electrolytic plating or electroless plating. A method for manufacturing a substrate.

The invention according to claim 7 of the present invention is the method for manufacturing a substrate for a semiconductor device according to claim 6, wherein at least the first conductor layer pattern includes a step of forming by a semi-additive method. A method for manufacturing a substrate.

  The present invention makes it possible to obtain a substrate for a semiconductor device in which the fine wiring required for the substrate for a semiconductor device is finer and more accurate than the conventional general passive element built-in substrate. A large number of passive elements can be incorporated in a semiconductor device substrate having a small area. In particular, when the resistance element is formed, not only the primary effect such as the improvement of the wiring density and the increase in the number of parts accommodated due to the reduction of the element size but also the secondary effect, particularly the electrical characteristics in the high frequency region. It was greatly improved, and we were able to obtain the characteristics that can cope with the future speedup of the mounted semiconductor elements.

  1A and 1B are partial views of a substrate for a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view, FIG. 1B is a side sectional view of a wiring portion, and FIG. It is a sectional side view of an element part. Wirings are disposed on the substrate 1 on the left and right sides, and a thin film resistance element is formed between the wirings. The wiring is formed on the first conductor layer 3 by a two-layer structure of the second conductor layer 4. The thin film resistance element is formed by a pattern composed of the thin film resistance layer 2. The shape of the thin-film resistance layer 2 is determined by the pattern shape of the first conductor layer. An electric circuit is formed on the left wiring and the right wiring in the drawing through a passive component of a thin film resistance element formed of the thin film resistance layer 2. In the drawing, a cross-sectional view taken along the line yy is shown in FIG. 1B, and a cross-sectional view taken along the line xx is shown in FIG. FIG. 1B shows a cross section of the wiring portion, and the thin film resistor layer 2, the first conductor layer 3, and the second conductor layer 4 are sequentially stacked on the substrate 1. The thin-film resistance layer 2 is restricted by the wiring width of the upper first conductor layer 3. In the wiring, the conductor layer thickness of the second conductor layer 4 is sufficiently increased to reduce the DC resistance. FIG. 1C shows the vicinity of the passive component of the thin film resistance element, and the element size of the thin film resistance element is regulated by the distance between the left and right first conductor layers 3. In the element of the thin film resistance layer 2, the end of the second conductor layer 4 is exposed from the left side of the drawing, the end of the first conductor layer 3 is further exposed inside, and the thin film resistance layer 2 is exposed in the center. A symmetrical valley is formed. Between the end portions of the left and right first conductor layers 3 is an element size. That is, the pattern forming process of the first conductor layer with a thin conductor is important.

  In an example of the method for manufacturing a substrate for a semiconductor device of the present invention, the pattern formation of the first conductor layer having a thin conductor is formed on the insulating base material by a subtractive method. The method prepares the board | substrate which formed the thin film resistance layer 2 and the 1st conductor layer with thin conductor thickness in order on board | substrates 1, such as a polyimide film. After the resist 30 is formed on the substrate, a resist pattern is formed by an exposure process and a development process by a photo process method. Next, an etching process is performed on a portion exposed from the resist. In the etching process, only the first conductor layer 3 having a thin conductor is removed. In a special case, it is possible to remove the two layers of the thin-film resistance layer 2 and the first conductor layer 3. The difference is that of the etching treatment liquid, the former being an ammonium chloride liquid system and the latter being a ferric chloride liquid system. In the above manufacturing method, the thinner the etching layer, the higher the accuracy of the first conductor layer pattern.

In one example of the method for manufacturing a substrate for a semiconductor device of the present invention, pattern formation of the first conductor layer with a thin conductor is formed by a semi-additive method. The method prepares the board | substrate which formed the thin film resistance layer 2 and the thin film copper layer (not shown) used as the bottom part of a 1st conductor layer on board | substrates 1, such as a polyimide film. After forming the resist 30 on the substrate, a resist pattern is formed by an exposure process and a development process by a photo process method. A first conductor layer pattern is formed on the exposed portion of the thin film copper layer by electrolytic copper plating. After removing the resist, the surrounding thin film copper layer and thin film resistance layer are removed. In the above manufacturing method, the higher the accuracy of the resist pattern, the higher the accuracy of the first conductor layer pattern is completed.
<Example 1>
FIG. 2 is a process diagram of a side sectional view for explaining the first embodiment of the present invention. 2 is a plan view inside the dotted frame on the right side of FIG. A 9 μm thick copper foil formed by plating an alloy layer of nickel and phosphorus as the thin film resistive layer 2 is bonded to a 75 μm thick polyimide film substrate 1 with a 12 μm thick adhesive with the thin film resistive layer 2 inside. It was. After the adhesive was cured, it was immersed in a sulfuric acid-hydrogen peroxide solution and etched until the surface copper foil thickness was about 3 μm, and this was used as the first conductor layer 3 (see FIG. 2 a). A positive liquid resist (PMER-P (trade name), manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied on the first conductor layer 3 to a thickness of about 2 μm and dried to form a resist 30. Projection exposure is performed with an exposure mask provided with a light-shielding portion having a width of 22 μm and a transmission portion having a width of 18 μm so as to obtain a pitch of 40 μm, and development is performed to include a resist opening having a width of about 22 μm and a resist pattern having a width of about 18 μm. The resist pattern was formed. An ammonium chloride etching solution was sprayed to remove the first conductor layer 3 exposed from the resist opening (see FIG. 2B). The resist 30 was peeled off with a sodium hydroxide solution to form a pattern of the first conductor layer 3 including a copper pattern having a width of about 20 μm and a gap having a width of about 20 μm (see FIG. 2C). At this time, the etched portion of the copper foil exposes the thin-film resistance layer 2 of the underlying nickel-phosphorus alloy layer, and the portion where the thin-film resistance element is to be formed has a length of about 45 μm and the first conductor layer 3 is formed. There is no state.

  A positive liquid resist (PMER-P (trade name), manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied again to a thickness of about 5 μm and dried to form a resist 31. A thin film resistive element having a width of about 20 μm is formed by projecting and developing an exposure mask provided with a light-shielding portion having a width of 15 μm and a length of 60 μm on a portion where the thin film resistive element is to be formed. A resist pattern having a width of about 15 μm and a length of about 60 μm was formed so as to cover the copper patterns on both sides of the part. The film was immersed in a solution in which sodium chloride and copper sulfate were dissolved, and the exposed thin film resistance layer was removed (see FIG. 2D). At this time, when the dimension of the formed thin film resistance element was measured, it was able to be formed with an accuracy within ± 1 μm in both width and length.

  After stripping the resist 31 with a sodium hydroxide solution (see FIG. 2 (e)), a positive liquid resist (PMER-P (trade name), manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied again with a thickness of about 5 μm, A resist 32 was formed by drying (see FIG. 2F). Projection exposure was performed using an exposure mask designed so that a light-shielding portion having a width of 40 μm and a length of 60 μm was placed on a part of the copper pattern adjacent to the resistance element, and developed. The second conductor layer 4 having a thickness of about 10 μm was formed on the exposed first conductor layer by conducting from the lead drawn around (see FIG. 2G).

  After the resist 32 was peeled off with a sodium hydroxide solution, the resistance values of the formed elements were measured, and all showed resistance values within ± 10% with respect to the target 300Ω. Compared to the accuracy of ± 4 to 5 μm when resistance elements are formed using conventional technology, the accuracy of accuracy is ± 20 to 30% when converted to resistance value accuracy. (See FIG. 2 (h)).

  Finally, a thermosetting solder resist was screen printed and cured, and then the exposed copper surface was plated with gold.

Through the above process, a semiconductor device substrate including a thin film resistor element having a width of 15 μm and a length of 45 μm and having a wiring pattern with a pitch of 40 μm was completed.
<Example 2>
FIG. 3 is a process diagram of a side sectional view for explaining the second embodiment of the present invention. In addition, the inside of the dotted line frame on the right side of FIG. 3 is a plan view. An alloy layer of nickel and chromium was formed on one side of a polyimide film substrate 1 having a thickness of 50 μm as a thin film resistance layer 2 by sputtering, and a copper layer having a thickness of 3 μm was formed as a first conductor layer 3 thereon by sputtering and plating. (See FIG. 3 (a)). Using the materials described above, after washing, a positive liquid resist (PMER-P (trade name), manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the first conductor layer 3 to a thickness of about 2 μm, and dried to form a resist 30 Formed. Projection exposure is performed with an exposure mask provided with a transmissive portion having a width of 102 μm and a light-shielding portion having a width of 108 μm so as to have a pitch of 200 μm, and development is performed to include a resist opening having a width of about 102 μm and a resist pattern having a width of about 108 μm. The resist pattern was formed. Ammonium chloride-based etchant is sprayed to remove the first conductor layer 3 exposed from the resist opening (see FIG. 3B), the resist 30 is peeled off with a sodium hydroxide solution, and a copper pattern having a width of about 100 μm. A pattern of the first conductor layer 3 including a gap with a width of about 100 μm was formed (see FIG. 3C). At this time, the underlying thin film resistive layer 2 is exposed at the etched portion of the copper foil, and the portion where the thin film resistive element is to be formed is about 300 μm long and the first conductor layer 3 is not present.

  A negative type cover resist (PSR-4000 (trade name), manufactured by Taiyo Ink Co., Ltd.) was applied to a thickness of about 15 μm and dried to form a resist 31. A thin film resistive element having a width of about 100 μm is formed by projecting and developing an exposure mask provided with a light shielding portion having a width of 150 μm and a length of 350 μm on a portion where the thin film resistive element is to be formed. A resist pattern having a width of about 150 μm and a length of about 350 μm was formed so as to cover the copper patterns on both sides of the part. The cover resist was cured by heating at 130 ° C. for 2 hours and then immersed in a permanganic acid solution to remove the exposed thin film resistance layer 2 (see FIG. 3D). At this time, when the dimension of the formed thin film resistor was measured, the length could be formed with an accuracy within ± 1 μm. Although the accuracy in the width direction is lower than that and about ± 20 μm, in this structure, the dimensional accuracy in the width direction is not required as compared with the length direction.

  Further, a second conductor layer 4 having a thickness of 10 μm was formed by electrolytic copper plating. When the resistance value of the element formed at this time was measured, the resistance value was within ± 10% for the target of 150Ω.

  Finally, a thermosetting solder resist was screen printed and cured, and then the exposed copper surface was plated with gold.

Through the above process, a semiconductor device substrate including a thin film resistance element having a width of 100 μm and a length of 300 μm and having a wiring pattern of 200 μm pitch was completed.
<Example 3>
FIG. 4 is a process diagram of a side sectional view for explaining a third embodiment of the present invention. In addition, the inside of the dotted line frame on the right side of FIG. 4 is a plan view. An alloy layer of nickel and chromium was formed as a thin film resistive layer 2 on one surface of a polyimide film substrate 1 having a thickness of 50 μm by sputtering, and a copper layer having a thickness of 2 μm was formed as a first conductor layer 3 thereon by sputtering and plating. (See FIG. 4 (a)). After using the above materials and cleaning, a positive liquid resist (PMER-P (trade name), manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the first conductor layer 3 to a thickness of about 2 μm and dried to form a resist 30. Formed. Projection exposure is performed with an exposure mask provided with a light-shielding portion having a width of 10 μm and a transmission portion having a width of 10 μm so as to obtain a pitch of 20 μm, and development is performed to include a resist opening having a width of about 10 μm and a resist pattern having a width of about 10 μm. The resist pattern was formed. By spraying a ferric chloride solution, the first conductor layer 3 and the thin-film resistance layer 2 exposed from the resist opening are removed, and the resist 30 is peeled off with a sodium hydroxide solution to obtain a copper pattern having a width of about 8 μm and a width of about 12 μm. A pattern of the first conductor layer 3 including the gap was formed (see FIG. 4C). At this time, the underlying polyimide substrate 1 is exposed in the etched portion of the copper foil, and the first conductor layer 3 remains in the portion where the thin film resistance element is to be formed.

A positive liquid resist (PMER-P (trade name), manufactured by Tokyo Ohka Kogyo Co., Ltd.) was applied again to a thickness of about 5 μm and dried to form a resist 31. A resist pattern having a width of about 15 μm and a length of about 60 μm across the wiring is projected and developed on an exposure mask provided with a light-shielding portion having a width of 15 μm and a length of 60 μm on the portion where the thin film resistance element is to be formed. (See FIG. 4D).

  Conducting from the lead drawn out to the periphery, the second conductor layer 4 having a thickness of about 7 μm was formed on the exposed first conductor layer, followed by nickel plating having a thickness of about 1 μm (see FIG. 4E). ). After stripping the resist 31 with a sodium hydroxide solution (see FIG. 4 (f)), the first conductor layer 3 on the resistance element was removed with an ammonium persulfate solution (see FIG. 4 (g)).

  The resistance values of the formed elements all showed resistance values within ± 8% with respect to the target of 125Ω.

  Finally, a thermosetting solder resist was screen printed and cured, and then the exposed copper surface was plated with gold.

Through the above process, a semiconductor device substrate including a thin film resistor element having a width of 10 μm and a length of 50 μm and having a wiring pattern with a pitch of 20 μm was completed.
<Example 4>
A fourth embodiment of the present invention will be described with reference to FIG. An alloy layer of nickel and chromium was formed as a thin film resistive layer 2 on one surface of a polyimide film substrate 1 having a thickness of 50 μm by sputtering, and a copper layer having a thickness of 2 μm was formed as a first conductor layer 3 thereon by sputtering and plating. (See FIG. 4 (a)). After using the above materials and cleaning, a positive liquid resist (PMER-P (trade name), manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied on the first conductor layer 3 to a thickness of about 2 μm and dried to form a resist 30. Formed. Projection exposure is performed with an exposure mask provided with a light-shielding portion having a width of 10 μm and a transmission portion having a width of 10 μm so as to obtain a pitch of 20 μm, and development is performed to include a resist opening having a width of about 10 μm and a resist pattern having a width of about 10 μm. The resist pattern was formed. The ferric chloride solution was sprayed to remove the first conductor layer 3 and the thin-film resistance layer 2 exposed from the resist opening. Subsequently, the portion where the thin film resistor was to be formed was projected and developed with an exposure mask provided with a light shielding portion having a width of 15 μm and a length of 60 μm. As a result, the underlying polyimide substrate 1 is exposed at the portion where the first conductor layer 3 is etched, the first conductor layer is exposed at the portion where the wiring is to be formed, and the portion where the thin film resistance element is to be formed is In this state, the first conductor layer 3 and the resist 31 remain (see FIG. 4D).

  The second conductor layer 4 having a thickness of about 7 μm was formed on the exposed first conductor layer by conducting from the lead drawn around (see FIG. 4E). After stripping the resist 31 with a sodium hydroxide solution (see FIG. 4F), the first conductor layer 3 on the resistance element was removed with a sulfuric acid-hydrogen peroxide solution (see FIG. 4G).

  The resistance values of the formed elements all showed resistance values within ± 10% with respect to the target of 125Ω. Finally, a thermosetting solder resist was screen printed and cured, and then the exposed copper surface was plated with gold.

  Through the above process, a semiconductor device substrate including a thin film resistor element having a width of 10 μm and a length of 50 μm and having a wiring pattern with a pitch of 20 μm was completed.

2A and 2B are partial views of a substrate for a semiconductor device according to the present invention, in which FIG. 1A is a plan view, FIG. 2B is a side cross-sectional view of a wiring portion, and FIG. It is process drawing of the side sectional view explaining Example 1 of the present invention. It is process drawing of the side sectional view explaining Example 2 of the present invention. It is process drawing of the side sectional view explaining Example 3 and 4 of the present invention. FIG. 2 is a partial view of a conventional substrate for a semiconductor device, in which (a) is a plan view, (b) is a side section of a wiring section, and (c) is a side section view of a thin film resistance element section. It is process drawing of the side sectional view explaining the manufacturing method of the conventional board | substrate for semiconductor devices.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Thin film resistive layer 3 ... 1st conductor layer 4 ... 2nd conductor layer 10 ... Wiring pattern 20 ... Passive component 30 ... Resist 31 ... Resist 32 ... Resist 40 ... Conductor layer

Claims (7)

  In a semiconductor device substrate incorporating a passive component, at least a first conductor layer having a thin conductor near the passive component forming portion and a second conductor having a large thickness formed on the first conductor layer. In the formation of a passive component having the two-layer structure, the element size of the passive component is determined by the size of the pattern formed on the first conductor layer having a thin conductor thickness. A substrate for a semiconductor device.   The end portions of the pattern of the first conductor layer having a small thickness and the second conductor layer having a large conductor thickness are located at different positions, and the element dimensions of the passive component are directly measured by the first conductor layer having a small thickness. The end position of the second conductor layer having a thick conductor is determined by the end of the first conductor layer or the end of the first conductor layer, and the element size is determined by the distance between the end portions of the first conductor layer. The semiconductor device substrate according to claim 1.   The first conductor layer and the second conductor layer of the substrate for a semiconductor device are made of copper, and gold, nickel, platinum, rhodium, palladium, silver, tin, or an alloy containing these at least part of the conductor surface, or 3. A semiconductor device substrate according to claim 1, wherein a conductive material made of carbon is formed.   4. The semiconductor device substrate according to claim 1, wherein a conductor having a width of 15 μm or less and a conductor adjacent thereto are formed on at least a part of the substrate by a gap of 15 μm or less and narrower than the width of the conductor. The substrate for a semiconductor device according to any one of claims.   The element of the passive component incorporated in the substrate for a semiconductor device is a resistance element having at least one of a width and a length of 50 μm or less and a thickness of 1 μm or less. 5. The substrate for a semiconductor device according to claim 1, wherein the width is the same as or narrower than that of the conductor layer.   It has a two-layer structure of a first conductor layer having a thin conductor at least near the passive component forming portion and a second conductor layer having a thick conductor formed on the first conductor layer, In a method for manufacturing a substrate for a semiconductor device incorporating a passive component formed from the two-layer structure, a step of forming a first conductor layer pattern on an insulating base material by a subtractive method, and a step of forming on the first conductor layer pattern 6. The method for manufacturing a substrate for a semiconductor device according to claim 1, further comprising a step of forming the second conductor layer pattern by electrolytic plating or electroless plating.   7. The method for manufacturing a semiconductor device substrate according to claim 6, further comprising a step of forming at least the first conductor layer pattern by a semi-additive method.

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