JP2005116753A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2005116753A
JP2005116753A JP2003348567A JP2003348567A JP2005116753A JP 2005116753 A JP2005116753 A JP 2005116753A JP 2003348567 A JP2003348567 A JP 2003348567A JP 2003348567 A JP2003348567 A JP 2003348567A JP 2005116753 A JP2005116753 A JP 2005116753A
Authority
JP
Japan
Prior art keywords
mask
semiconductor device
manufacturing
resist mask
polysilicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2003348567A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005116753A5 (https=
Inventor
Hideki Oguma
英樹 小熊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2003348567A priority Critical patent/JP2005116753A/ja
Priority to US10/958,587 priority patent/US20050106826A1/en
Publication of JP2005116753A publication Critical patent/JP2005116753A/ja
Publication of JP2005116753A5 publication Critical patent/JP2005116753A5/ja
Abandoned legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/01Manufacture or treatment
    • H10D64/013Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326Aspects related to lithography, isolation or planarisation of the conductor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/71Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials

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  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2003348567A 2003-10-07 2003-10-07 半導体装置の製造方法 Abandoned JP2005116753A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003348567A JP2005116753A (ja) 2003-10-07 2003-10-07 半導体装置の製造方法
US10/958,587 US20050106826A1 (en) 2003-10-07 2004-10-06 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003348567A JP2005116753A (ja) 2003-10-07 2003-10-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2005116753A true JP2005116753A (ja) 2005-04-28
JP2005116753A5 JP2005116753A5 (https=) 2006-11-02

Family

ID=34540725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003348567A Abandoned JP2005116753A (ja) 2003-10-07 2003-10-07 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US20050106826A1 (https=)
JP (1) JP2005116753A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100847831B1 (ko) 2006-12-29 2008-07-23 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0621018A (ja) * 1992-06-29 1994-01-28 Sony Corp ドライエッチング方法
US6362111B1 (en) * 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
JP2002025986A (ja) * 2000-07-06 2002-01-25 Matsushita Electric Ind Co Ltd ドライエッチング方法
US6689687B1 (en) * 2001-02-02 2004-02-10 Advanced Micro Devices, Inc. Two-step process for nickel deposition
US6551941B2 (en) * 2001-02-22 2003-04-22 Applied Materials, Inc. Method of forming a notched silicon-containing gate structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100847831B1 (ko) 2006-12-29 2008-07-23 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법

Also Published As

Publication number Publication date
US20050106826A1 (en) 2005-05-19

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