JP2005116453A - Plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel capable of stably and quickly performing a writing operation while restraining a writing voltage, and enabled to have higher definition. <P>SOLUTION: The plasma display panel comprises scanning electrodes 22 and sustaining electrodes 23 arranged in parallel with each other on a front face panel 21; priming electrodes 36 arranged on a back face panel 31 in parallel with the scanning electrodes 22; a first dielectric layer 33a covering the priming electrodes 36; data electrodes 32 arranged on the first dielectric layer 33a in a direction crossing the scanning electrodes 22; vertical walls 34a and lateral walls 34b formed on the front face panel 31 demarcating main discharge cells 40 formed of the scanning electrodes 22, the sustaining electrodes 23, and the data electrodes 32 from priming discharge cells 41a formed of the scanning electrodes 22 and the priming electrodes 36; and supplemental vertical walls 34c formed so as to cover the data electrodes 32 in the priming discharge cells 41a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a plasma display panel used for a wall-mounted television, a large monitor and the like.

  A plasma display panel (hereinafter abbreviated as PDP or panel) is a display device with excellent visibility characterized by a large screen, a thin shape, and a light weight. A typical AC surface discharge type panel as a PDP is formed by forming a large number of discharge cells between a front plate and a back plate arranged to face each other. The front plate is formed with a plurality of pairs of display electrodes composed of scan electrodes and sustain electrodes on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs formed on the back side in parallel with the data electrodes. A phosphor layer is formed on the side surface of the partition wall. The front plate and the back plate are opposed and sealed so that the display electrode and the data electrode cross three-dimensionally, and a discharge gas is sealed in the internal discharge space. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Here, each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is simultaneously performed in all the discharge cells, the history of wall charges for the individual individual discharge cells is erased, and wall charges necessary for the subsequent address operation are formed. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing the discharge delay and stably generating the address discharge. In the address period, a scan pulse is sequentially applied to the scan electrode, an address pulse corresponding to an image signal to be displayed is applied to the data electrode, and an address discharge is selectively generated between the scan electrode and the data electrode. Selective wall charge formation is performed. In the subsequent sustain period, a predetermined number of sustain pulses are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light.

  Thus, in order to display an image correctly, it is important to reliably perform selective address discharge in the address period. However, due to restrictions on the circuit configuration, a high voltage cannot be used for the address pulse, There are many factors that increase the discharge delay with respect to the address discharge, such as the fact that the phosphor layer formed on the layer makes it difficult for the discharge to occur. Therefore, priming for generating the address discharge stably is very important.

  However, the priming caused by the discharge decreases rapidly with time. For this reason, in the above-described panel driving method, the address discharge after a long time has passed from the initialization discharge, the priming caused by the initialization discharge is insufficient, the discharge delay becomes large, and the address operation becomes unstable. There has been a problem that the image display quality deteriorates. Alternatively, there is a problem in that the writing time is set long in order to perform the writing operation stably, and as a result, the time spent in the writing period becomes too long.

In order to solve these problems, a panel and a driving method thereof have been proposed in which priming is generated using an auxiliary discharge cell formed by providing an auxiliary discharge electrode on the front plate of the panel to reduce the discharge delay (for example, Patent Document 1).
JP 2002-297091 A

  However, in the above-described panel, since the individual auxiliary discharge cells are relatively large, the distance between the discharge cells for image display cannot be reduced, and as a result, there is a problem that high definition is difficult. .

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a plasma display panel that can perform a writing operation stably and at high speed and can achieve high definition.

  The plasma display panel of the present invention includes a first substrate, a scan electrode and a sustain electrode arranged in parallel with each other on the first substrate, and a second substrate disposed opposite to the first substrate across the discharge space. A priming electrode disposed on the second substrate in parallel with the scanning electrode, a first dielectric layer covering the priming electrode, and a data electrode disposed on the first dielectric layer in a direction intersecting the scanning electrode Are formed on the second substrate so as to partition a main discharge cell configured such that the scan electrode, the sustain electrode, and the data electrode face each other, and a priming discharge cell configured such that the scan electrode and the priming electrode face each other. And a second dielectric covering a region on the data electrode in the priming discharge cell. With this configuration, it is possible to provide a plasma display panel that can perform a writing operation stably and at high speed while suppressing an increase in the writing voltage, and can achieve high definition.

  Further, the second dielectric may be configured not to cover at least a part of the region on the priming electrode in the priming discharge cell. This configuration enables more stable priming discharge.

  The second dielectric may be a partition formed in a region on the data electrode. According to this configuration, the mechanical strength of the barrier ribs increases the accuracy of the discharge cells, so that the uniformity of the display image can be improved.

  According to the present invention, it is possible to provide a plasma display panel that can perform a writing operation stably and at high speed while suppressing an increase in the writing voltage, and can achieve high definition.

  Hereinafter, a plasma display panel according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing the structure of a plasma display panel according to an embodiment of the present invention, and FIG. 2 is a plan view of the rear substrate of the panel as viewed from the front substrate side.

  As shown in FIG. 1, a glass front substrate 21 as a first substrate and a rear substrate 31 as a second substrate are arranged to face each other with a discharge space therebetween, and ultraviolet rays are radiated to the discharge space by discharge. A gas mixture of neon and xenon is enclosed.

  A plurality of scan electrodes 22 and sustain electrodes 23 are formed in parallel with each other on the front substrate 21. At this time, two electrodes are alternately arranged so as to be sustain electrode 23 -scan electrode 22 -scan electrode 22 -sustain electrode 23-. Scan electrode 22 and sustain electrode 23 are each composed of transparent electrodes 22a and 23a and metal bus bars 22b and 23b formed on transparent electrodes 22a and 23a, respectively. Here, a light absorption layer 28 made of a black material is provided between scan electrode 22 and scan electrode 22 and between sustain electrode 23 and sustain electrode 23. Of the scanning electrodes 22, the protruding portion 22 b ′ of the metal bus 22 b of one scanning electrode 22 is formed to protrude onto the light absorption layer 28. A dielectric layer 24 and a protective layer 25 are formed so as to cover the scan electrode 22, the sustain electrode 23, and the light absorption layer 28.

  On the back substrate 31, a plurality of priming electrodes 36 are formed in parallel with the scanning electrodes 22, and a first dielectric layer 33 a is formed so as to cover the priming electrodes 36. On the first dielectric layer 33a, a plurality of data electrodes 32 are formed in parallel to each other in a direction crossing the scan electrode 22 and the sustain electrode 23. The first dielectric layer 33 a insulates between the data electrode 32 and the priming electrode 36.

  A dielectric layer 33b is formed so as to cover the data electrode 32, and a partition wall 34 for partitioning the main discharge cell 40 is further formed thereon. As shown in FIGS. 1 and 2, the partition wall 34 forms a main discharge cell 40 with a vertical wall portion 34a extending in a direction parallel to the data electrode 32 and an auxiliary vertical wall portion 34c as a second dielectric, and It is comprised by the horizontal wall part 34b which forms the clearance gap part 41 between the main discharge cells 40. FIG. Every other gap portion 41 has a priming electrode 36 to form a priming discharge cell 41a. The gap 41b is a gap 41 that does not have a priming electrode. The auxiliary vertical wall 34c as the second dielectric is formed on the dielectric layer 33b on the data electrode 32 so as to cover the data electrode 32 in the priming discharge cell 41a. At this time, as shown in FIG. 2, in the priming discharge cell 41a, the auxiliary vertical wall portion 34c is not formed in a region where the priming electrode 36 does not intersect with the data electrode 32.

  A phosphor layer 35 is provided on the surface of the dielectric layer 33 b corresponding to the main discharge cells 40 partitioned by the barrier ribs 34 and on the side surfaces of the barrier ribs 34. In FIG. 1, the phosphor layer 35 is not formed on the gap 41 side, but a configuration in which a phosphor layer is formed may be employed.

  When the front substrate 21 and the rear substrate 31 are arranged to face each other and sealed, a protruding portion 22b ′ protruding on the light absorption layer 28 among the metal bus bars 22b of the scanning electrode 22 formed on the front substrate 21, and the rear substrate Alignment is performed so that the priming electrode 36 formed on the substrate 31 faces the priming discharge cell 41a in parallel. The priming discharge is performed between the protruding portion 22b 'formed on the front substrate 21 side and the priming electrode 36 formed on the rear substrate 31 side.

  In the embodiment of the present invention, the dielectric layer 33b is formed so as to cover the data electrode 32. However, the dielectric layer 33b may not be formed.

FIG. 3 is an electrode array diagram of the plasma display panel in accordance with the exemplary embodiment of the present invention. Data electrodes D _{1 to} D _m (data electrodes 32 in FIG. 1) in the column direction are arranged, and n rows of scan electrodes SC _{1 to} SC _n (scan electrodes 22 in FIG. 1) and n rows in the row direction are arranged. sustain electrodes SU ₁ to SU _n (sustain electrodes 23 in FIG. 1) and the sustain electrodes SU ₁ - scan electrode SC ₁ - scan electrode SC ₂ - sustain electrode SU ₂ - · · · and so as to alternately arranged two by two Has been. In the embodiment of the present invention, n / 2 priming electrodes PR are arranged so as to face the protruding portions of the odd-numbered scan electrodes SC ₁ , SC ₃ ,... (The protruding portion 22 b ′ in FIG. 1). ₁ , PR ₃ ,... (Priming electrode 36 in FIG. 1) are arranged.

A discharge cell C _{i, j} (main discharge cell of FIG. 1) including a pair of scan electrodes SC _i , sustain electrodes SU _i (i = 1 to n) and one data electrode D _j (j = 1 to _m ). 40) are formed in the discharge space. In addition, priming discharge cells PS _i (priming discharge cells 41a in FIG. 1) including protruding portions of scan electrodes SC _i and priming electrodes PR _i are formed in odd-numbered rows among 1 to n rows.

  Next, driving waveforms and timings for driving the panel will be described.

  FIG. 4 is a drive waveform diagram of the plasma display panel in accordance with the exemplary embodiment of the present invention. In the embodiment of the present invention, one field period is composed of a plurality of subfields having an initialization period, an address period, and a sustain period, and each subfield has a different number of sustain pulses in the sustain period. Since the other operations are almost the same, only the operation for one subfield will be described.

In half of the initializing period, data electrodes D ₁ to D _m, sustain electrodes SU ₁ to SU _n and priming electrodes PR ₁ ~PR _n-1 respectively kept 0 (V), to the scan electrodes SC ₁ to SC _n from voltage Vi ₁ of the discharge start voltage or less with respect to sustain electrodes SU ₁ to SU _n, and applies the ramp waveform voltage gradually rises toward the voltage Vi ₂ that exceeds the discharge start voltage. While the ramp waveform voltage rises, the scan electrodes SC _{1 to} SC _n and the sustain electrodes SU _{1 to} SU _n , the data electrodes D _{1 to} D _m , and the priming electrodes PR _{1 to} PR _n-1 are each first time. A weak initializing discharge occurs. Then, negative wall voltage is accumulated on scan electrodes SC _{1 to} SC _n , and on data electrodes D _{1 to} D _m , sustain electrodes SU _{1 to} S _n and priming electrodes PR _{1 to} PR _n−1 . Accumulates positive wall voltage. Here, the wall voltage at the top of the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode.

In the second half of the initializing period, maintaining the sustain electrodes SU ₁ to SU _n to a positive voltage Ve, the scan electrodes SC ₁ to SC _n, the voltage Vi ₃ to be equal to or less than the discharge starting voltage with respect to sustain electrodes SU ₁ to SU _n Is applied with a ramp waveform voltage that gradually falls toward voltage Vi ₄ exceeding the discharge start voltage. During this time, the second weak initializing discharge is generated between the scan electrodes SC _{1 to} SC _n and the sustain electrodes SU _{1 to} SU _n , the data electrodes D _{1 to} D _m , and the priming electrodes PR _{1 to} PR _n−1. Occur. Then, the negative wall voltage above scan electrodes SC ₁ -SC _n and the positive wall voltage above sustain electrodes SU ₁ -SU _n are weakened, and the positive wall voltage above data electrodes D ₁ -D _m is used for the write operation. The positive wall voltage above the priming electrodes PR _{1 to} PR _n-1 is also adjusted to a value suitable for the priming operation. This completes the initialization operation.

In the address period, scan electrodes SC _{1 to} SC _n are temporarily held at voltage Vc. Then, the voltage Vq is applied to the priming electrodes PR _{1 to} PR _n−1 .

First, in the address operation of the discharge cells C _{p, 1 to} C _{p, m} (p = odd number) in the odd-numbered rows, the scan pulse voltage Va is applied to the scan electrode SC _p and the data corresponding to the image signal to be displayed. A positive address pulse Vd is applied to the electrode D _k (k is an integer of 1 to m). The scan electrodes SC _p of odd rows are scanning electrodes for writing with generating the priming discharge in accordance with the self-scanning. Accordingly, priming discharge is generated between the priming electrode PR _p and the scanning electrode SC _p by the application of the scan pulse voltage Va, and the discharge cells C _{p, 1 to} C _{p, m} and the discharge cells C _{p + 1,1 to} C Priming is supplied inside _{p + 1, m} . The discharge at this time is easy to discharge the priming discharge cell, and the voltage Vq can be set high. Therefore, the discharge becomes a fast and stable priming discharge with a small discharge delay.

Subsequently, an address discharge is generated in the discharge cell C _{p, k} corresponding to the data electrode D _k to which the address pulse voltage is applied. At this time, the discharge of the discharge cell C _{p, k} is generated while the priming is supplied from the priming discharge generated between the scan electrode SC _p and the priming electrode PR _p , so that the discharge delay is small and the discharge is stable. Due to this address discharge, a positive voltage is accumulated on the scan electrode SC _p of the discharge cell C _{p, k} and a negative voltage is accumulated on the sustain electrode SU _p, and the address operation in the odd-numbered rows is completed.

Next, in the address operation of the discharge cells C _{p + 1,1 to} C _{p + 1, m in} the even-numbered rows, the scan electrode voltage Va is applied to the scan electrode SC _{p + 1} in the p + 1 row, and at the same time, the data electrode D applying a positive write pulse voltage Vd to data electrode D _k corresponding to the image signal to be displayed on the p + 1 th row of the ₁ to D _m. As a result, a discharge is generated at the intersection between the data electrode D _k and the scan electrode SC _{p + 1} . At this time, in the discharge cell C _{p + 1, k} , the discharge occurs in a state where sufficient priming has already been supplied from the priming discharge generated between the scan electrode SC _p and the priming electrode PR _p , so the discharge of the address discharge The delay is very small and stable discharge. Due to this address discharge, a positive voltage is accumulated above scan electrode SC _{p + 1} of discharge cell C _{p + 1, k} and a negative voltage is accumulated above sustain electrode SU _{p + 1.} To do.

Thereafter, the same address operation is performed until the discharge cell C _{n, k} in the _n- th row _, and the address operation is completed.

In the sustain period, after returning once to the scan electrodes SC ₁ to SC _n and sustain electrodes SU ₁ to SU _n to 0 (V), applies a positive sustain pulse voltage Vs to scan electrodes SC ₁ to SC _n. At this time, the voltage between the discharge cell C _i having generated the address _discharge, the scan electrode SC _i top in _k and sustain electrode SU _i top, in addition to the positive sustain pulse voltage Vs, the scan in the address periods electrode SC _i is subject to accumulated wall voltage and sustain electrode SU _i upper, larger than the discharge start voltage. As a result, a sustain discharge occurs in the discharge cells C _{i, k} . Hereinafter, similarly, by applying a sustain pulse alternately to the scan electrodes SC ₁ to SC _n and sustain electrodes SU ₁ to SU _n, the number of times of sustain pulse discharge cell C _i having generated the address _discharge, for _k The sustain discharge is continuously performed.

As described above, in the embodiment of the present invention, the priming electrode PR _p provided on the back substrate 31 side and the front surface in the address operation of the discharge cells C _{p, 1 to} C _{p, m} (p = odd number) in the odd-numbered rows. A priming discharge is generated between the scanning electrode SC _p provided on the substrate 21 side, and the inside of the discharge cells C _{p, 1 to} C _{p, m} and the discharge cells C _{p + 1,1 to} C _{p + 1, m} By supplying priming to the, it is possible to realize a fast and stable address discharge with a small discharge delay.

  As shown in FIG. 1, the scanning electrode 22 and the data electrode 32 are arranged to face each other across the discharge space, as in the conventional panel in which the priming electrode 36 does not exist. Therefore, the discharge start voltage between the scan electrode 22 and the data electrode 32 is the same as that of the conventional panel by setting the distance of the discharge space, the thickness of the dielectric layer 24 and the dielectric layer 33b, and the like as in the conventional panel. The voltage can be set to Further, by designing the interelectrode distance between the scan electrode 22 and the sustain electrode 23 to be the same interelectrode distance as that of the conventional panel, the discharge start voltage between the scan electrode 22 and the sustain electrode 23 is also the same as the conventional voltage. Can be set. Therefore, the panel according to the embodiment of the present invention can be driven by applying the same drive voltage waveform as that of the conventional panel to each electrode except the priming electrode 36, and unlike the conventional panel, the discharge delay is different. Is small and high speed and stable address discharge can be realized.

  In addition, a priming discharge is generated between the priming electrode 36 and the scanning electrode 22 in the priming discharge cell 41a. At this time, a second dielectric is formed on the data electrode 32 so as to cover the data electrode 32. Therefore, the address pulse voltage applied to each data electrode 32 does not affect the electric field in the priming discharge cell 41a. Therefore, stable priming discharge depending on the voltage applied to the priming electrode 36 and the scanning electrode 22 is possible. Furthermore, dielectric breakdown on the data electrode 32 in the priming discharge cell 41a can be prevented. Here, the height of the auxiliary vertical wall portion 34c may be set freely. However, by setting the height of the auxiliary vertical wall portion 34c lower than that of the vertical wall portion 34a or the horizontal wall portion 34b, the auxiliary vertical wall portion 34c is set in a direction parallel to the priming electrode 36 in the priming discharge cell 41a. Therefore, the priming discharge cell 41a can be more easily discharged.

  In the embodiment of the present invention, the auxiliary vertical wall 34c is provided at the position shown in FIG. 1, but the plasma display panel of the present invention is not limited to this structure. FIG. 5 is a view showing another embodiment of the plasma display panel of the present invention. FIG. 5A shows an example in which the auxiliary vertical wall portion 34c is provided not only in the gap portion 41 that forms the priming discharge cell 41a but also in the gap portion 41b that does not form the priming discharge cell. With this configuration, since the partition walls 34 are connected vertically and horizontally, the mechanical strength of the partition walls 34 is improved. As a result, the accuracy of the main discharge cells 40 is improved and the uniformity of the display image is improved.

  FIG. 5B shows an example in which the auxiliary vertical wall portion 34c is provided on the same line as the vertical wall portion 34a by moving the position of the data electrode 32 in the priming discharge cell 41a. According to this structure, since the partition walls 34 are formed by being connected in a vertical and horizontal lattice shape, the mechanical strength of the partition walls 34 can be further improved.

  Further, in the above description, the auxiliary vertical wall portion 34c is formed in the region on the data electrode 32 as the second dielectric, but the second dielectric covers the region on the data electrode 32. As long as it is an insulator other than the partition wall, for example, a material similar to that of the dielectric layer 24, the first dielectric layer 33a, or the like may be used to cover the region on the data electrode 32.

  The plasma display panel according to the present invention can provide a plasma display panel capable of performing a writing operation stably and at high speed while suppressing an increase in writing voltage, and capable of high definition. This is useful for plasma display panels used for monitors and the like.

1 is an exploded perspective view showing a structure of a plasma display panel in an embodiment of the present invention. A plan view of the rear substrate of the panel viewed from the front substrate side Electrode arrangement of the panel Drive waveform diagram of the panel The figure which shows the other Example of the plasma display panel in this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 Front substrate 22 Scan electrode 22a, 23a Transparent electrode 22b, 23b Metal bus line 22b 'Protruding part 23 Maintenance electrode 24 Dielectric layer 25 Protection layer 28 Light absorption layer 31 Back substrate 32 Data electrode 33a 1st dielectric layer 33b Dielectric Layer 34 Partition 34a Vertical wall portion 34b Horizontal wall portion 34c Auxiliary vertical wall portion 35 Phosphor layer 36 Priming electrode 40 Main discharge cell 41 Gap portion 41a Priming discharge cell 41b (no priming electrode) gap portion

Claims (3)

A first substrate;
A scan electrode and a sustain electrode disposed in parallel with each other on the first substrate;
A second substrate disposed opposite to the first substrate across a discharge space;
A priming electrode disposed on the second substrate in parallel with the scanning electrode;
A first dielectric layer covering the priming electrode;
A data electrode disposed on the first dielectric layer in a direction intersecting the scan electrode;
The main discharge cell configured to face the scan electrode, the sustain electrode, and the data electrode, and the priming discharge cell configured to face the scan electrode and the priming electrode. Partition walls formed on the substrate of 2;
A plasma display panel, comprising: a second dielectric covering a region on the data electrode in the priming discharge cell. The plasma display panel according to claim 1, wherein the second dielectric does not cover at least a part of a region on the priming electrode in the priming discharge cell. 3. The plasma display panel according to claim 1, wherein the second dielectric is a partition formed in a region on the data electrode.

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