JP2006085964A - Plasma display panel and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel which can generate write-in discharges stably without narrowing a drive voltage margin of write-in actions, and to provide a driving method thereof. <P>SOLUTION: A pair of display electrodes on a front substrate 21 comprising a scanning electrode 22 and a sustaining electrode 23, and a data electrode 32 which is formed on a rear substrate 31, are arranged facing each other to define a main discharge cell 40. A plurality of the main discharge cells 40 are arranged in connection along the arrangement of the pairs of the display electrodes to form a main discharge cell line, and barrier ribs 34 are formed on the rear substrate 31 so that a gap 41 is formed in each portion between adjacent main discharge cell lines. A plurality of priming electrodes 29 are formed on the front substrate 21, which are arranged in parallel with the scanning electrodes 22 in a priming discharge cell 41a formed in the gap 41 on a side where two scanning electrodes 22 adjoin. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a plasma display panel used for a wall-mounted television, a large monitor, and the like and a driving method thereof.

  A plasma display panel (hereinafter abbreviated as “panel”) is a display device with excellent visibility characterized by a large screen, a thin shape, and a light weight.

  In a typical AC surface discharge type panel as a panel, a large number of discharge cells are formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each formed of a scan electrode and a sustain electrode are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs formed on the back side in parallel with the data electrodes. A phosphor layer is formed on the side surface of the partition wall. Then, the front plate and the rear plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by this ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Here, each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is simultaneously performed in all the discharge cells, the history of wall charges for the individual individual discharge cells is erased, and wall charges necessary for the subsequent address operation are formed. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing discharge delay and generating address discharge stably. In the address period, a scan pulse voltage is sequentially applied to the scan electrodes, and an address pulse voltage corresponding to an image signal to be displayed is applied to the data electrodes, and an address discharge is selectively performed between the scan electrodes and the data electrodes. And selective wall charge formation. In the subsequent sustain period, a predetermined number of sustain pulse voltages are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light.

  As described above, in order to correctly display an image, it is important to reliably perform selective address discharge in the address period. However, a high voltage cannot be used for the address pulse voltage due to restrictions on the circuit configuration. There are many factors that increase the discharge delay with respect to the address discharge, such as the fact that the phosphor layer formed above makes it difficult for the discharge to occur. Therefore, priming for generating the address discharge stably is very important.

  However, the priming caused by the discharge decreases rapidly with time. For this reason, in the above-described panel driving method, the address discharge after a long time has passed from the initialization discharge, the priming caused by the initialization discharge is insufficient, the discharge delay becomes large, and the address operation becomes unstable. There has been a problem that the image display quality deteriorates. Alternatively, there is a problem in that the writing time is set long in order to perform the writing operation stably, and as a result, the time spent in the writing period becomes too long.

In order to solve these problems, a panel and a driving method thereof have been proposed in which a priming electrode is provided to generate priming to reduce a discharge delay (for example, Patent Document 1).
JP-A-9-245627

  However, in the above-mentioned panel, adjacent discharge cells are likely to cause mutual interference, and in particular, in the address period, there is a possibility that erroneous writing or writing failure may occur due to the influence of priming that occurs due to the address discharge of the adjacent discharge cells. Therefore, there is a problem that the drive voltage margin of the write operation is narrowed.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a plasma display panel capable of stably generating an address discharge without narrowing the drive voltage margin of the address operation and a method for driving the plasma display panel. .

  A plasma display panel according to the present invention includes a scan electrode and a sustain electrode that are arranged in parallel on a first substrate and that constitute a display electrode pair, and a second substrate that is disposed opposite to the first substrate across a discharge space. A data electrode which is arranged in a direction intersecting with the scanning electrode and forms a main discharge cell with a display electrode pair, and a main discharge cell row which divides the main discharge cell and a plurality of main discharge cells are connected along the display electrode pair And a barrier rib provided between adjacent main discharge cell rows, and two scan electrodes on the first substrate at positions corresponding to the adjacent gap portions in parallel with the scan electrodes A priming electrode is arranged. With this configuration, it is possible to provide a plasma display panel that can stably generate an address discharge without narrowing the drive voltage margin of the address operation.

  Further, the plasma display panel driving method of the present invention is the plasma display panel driving method described above, wherein one field is composed of a plurality of subfields having an initialization period, an address period, and a sustain period. A scan pulse voltage is sequentially applied to the scan electrode, and a priming discharge is generated between the priming electrode and the data electrode before the scan pulse voltage is applied to the priming electrode adjacent to the scan electrode to which the scan pulse voltage is applied. For this purpose, a priming pulse voltage is applied. By this method, it is possible to provide a plasma display panel driving method capable of stably generating address discharge without narrowing the driving voltage margin of the address operation.

  In the plasma display panel driving method of the present invention, there is an overlap between the time during which the scan pulse voltage is applied to the scan electrode and the time during which the priming pulse voltage is applied to the priming electrode in the address period. desirable. By this method, since priming discharge is also performed while performing address discharge, it is not necessary to newly provide time for priming discharge, and address discharge can be stably generated without changing the length of the address period.

  In the plasma display panel driving method of the present invention, after applying the priming pulse voltage to the priming electrode, the scanning pulse voltage is first applied among the scanning electrodes adjacent to the priming electrode to which the priming pulse voltage is applied. The pulse width of the scan pulse voltage of the electrode may be set narrower than the pulse width of the scan pulse voltage of the scan electrode to which the scan pulse voltage is next applied. By this method, the address period can be shortened while the address discharge is stably generated.

  ADVANTAGE OF THE INVENTION According to this invention, the plasma display panel which can generate | occur | produce address discharge stably, without narrowing the drive voltage margin of address operation, and its drive method can be provided.

  Hereinafter, a panel and a driving method thereof according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of the panel according to Embodiment 1 of the present invention, and FIG. 2 is a sectional view of the panel. A glass front substrate 21 which is a first substrate and a rear substrate 31 which is a second substrate are arranged opposite to each other with a discharge space interposed therebetween, and a mixed gas of neon and xenon which emits ultraviolet rays by discharge in the discharge space. Is enclosed.

  On the front substrate 21, a plurality of display electrode pairs composed of the scan electrodes 22 and the sustain electrodes 23 are formed in parallel to each other. At this time, for example, the display electrode pair adjacent to the display electrode pair configured in the order of scan electrode 22 -sustain electrode 23 is configured in the order of sustain electrode 23 -scan electrode 22. A priming electrode 29 is formed in parallel with the display electrode pair on the side facing the scanning electrode 22 between adjacent display electrode pairs. Therefore, on front substrate 21, sustain electrode 23-scan electrode 22-priming electrode 29-scan electrode 22-sustain electrode 23-sustain electrode 23-scan electrode 22-priming electrode 29-scan electrode 22-sustain electrode 23-.・ It is arranged so that Scan electrode 22 and sustain electrode 23 are each composed of transparent electrodes 22a and 23a and metal bus bars 22b and 23b formed on transparent electrodes 22a and 23a, respectively. A light absorption layer 28 made of a black material is provided between scan electrode 22 and scan electrode 22 and between sustain electrode 23 and sustain electrode 23, and priming electrode 29 is provided between scan electrode 22 and scan electrode 22. A metal bus is used on the light absorption layer 28. A dielectric layer 24 and a protective layer 25 are formed so as to cover the scan electrode 22, the sustain electrode 23, the priming electrode 29, and the light absorption layer 28.

  On the rear substrate 31, a plurality of data electrodes 32 are formed in parallel to each other in a direction intersecting with the scanning electrodes 22, and a dielectric layer 33 is formed so as to cover the data electrodes 32. A partition wall 34 for partitioning the main discharge cell 40 is formed on the dielectric layer 33.

  The partition wall 34 includes a vertical wall portion 34 a extending in a direction parallel to the data electrode 32, and a horizontal wall portion 34 b that forms the main discharge cell 40 and forms a gap portion 41 between the main discharge cells 40. As a result, the barrier ribs 34 form a main discharge cell row in which a plurality of main discharge cells 40 are connected along a pair of display electrodes including the scan electrode 22 and the sustain electrode 23, and a gap is formed between adjacent main discharge cell rows. Part 41 is produced. A priming electrode 29 is formed on the front substrate 21 of the gap portion on the side where the two scanning electrodes 22 are adjacent to each other in the gap portion 41, and this gap portion serves as a priming discharge cell 41a. In other words, every other gap portion 41 is a priming discharge cell 41 a having the priming electrodes 29. The gap 41b is a gap located on the side where the two sustain electrodes 23 are adjacent to each other.

  The tops of the partition walls 34 are formed flat so as to contact the front substrate 21. This is to prevent mutual interference between the adjacent main discharge cells 40, and in particular prevents malfunction such as erroneous writing due to the influence of priming that occurs due to the address discharge of the adjacent main discharge cells 40 in the address period. Because. Furthermore, this is to prevent malfunction such as a write failure due to a decrease in wall charges of the main discharge cell 40 adjacent to the priming discharge cell 41a accompanying the priming discharge.

  A phosphor layer 35 is provided on the surface of the dielectric layer 33 corresponding to the main discharge cells 40 partitioned by the barrier ribs 34 and on the side surfaces of the barrier ribs 34. In FIG. 1, the phosphor layer 35 is not formed on the gap 41 side, but the phosphor layer 35 may be formed.

  In the above description, the dielectric layer 33 is formed so as to cover the data electrode 32. However, the dielectric layer 33 may not be formed.

FIG. 3 is an electrode array diagram of the panel according to Embodiment 1 of the present invention. M columns of data electrodes D _{1 to} D _m (data electrodes 32 in FIG. 1) are arranged in the column direction, and n rows of scan electrodes SC _{1 to} SC _n (scan electrodes 22 in FIG. 1) and n rows of data electrodes are arranged in the row direction. Sustain electrodes SU _{1 to} SU _n (sustain electrode 23 in FIG. 1) and n / 2 rows of priming electrodes PR _{1 to} PR _n-1 (priming electrode 29 in FIG. 1) are sustain electrodes SU ₁ -scan electrode SC _1-. priming electrodes PR ₁ - scan electrode SC ₂ - sustain electrode SU ₂ - sustain electrode SU ₃ - scan electrode SC ₃ - priming electrode PR ₃ - scan electrode SC ₄ - sustain electrode _SU 4 - are arranged so as to ... Yes. A main discharge cell C _{i, j} (main discharge in FIG. 1) including a pair of scan electrodes SC _i , sustain electrodes SU _i (i = 1 to n) and one data electrode D _j (j = 1 to _m ). M × n cells 40) are formed in the discharge space. In addition, n / 2 priming discharge cells PS _p (priming discharge cells 41a in FIG. 1) including priming electrodes PR _p (p is an odd number) and data electrodes D _{1 to} D _m are formed in the discharge space. The details will be described later, the priming generated in the write period in the priming discharge cell PS _p, the main discharge cell _C p adjacent to priming discharge cell _{PS p, 1 ~C p, m} , C p + 1,1 ~C p + 1 _{, M.}

  FIG. 4 is a block diagram showing an example of a circuit configuration of the plasma display device using the panel according to Embodiment 1 of the present invention. The display device 100 includes an image signal processing circuit 101, a data electrode driving circuit 102, a timing control circuit 103, a scanning electrode driving circuit 104, a sustain electrode driving circuit 105, and a priming electrode driving circuit 106. The image signal and the synchronization signal are input to the image signal processing circuit 101. The image signal processing circuit 101 outputs to the data electrode driving circuit 102 a subfield signal for controlling whether or not each subfield is lit based on the image signal and the synchronization signal. The synchronization signal is also input to the timing control circuit 103. The timing control circuit 103 outputs a timing control signal to the data electrode driving circuit 102, the scan electrode driving circuit 104, the sustain electrode driving circuit 105, and the priming electrode driving circuit 106 based on the synchronization signal.

The data electrode driving circuit 102 applies a predetermined driving waveform voltage to the data electrodes 32 (data electrodes D _{1 to} D _{m in} FIG. 3) of the panel 10 according to the subfield signal and the timing control signal. Scan electrode drive circuit 104 applies a predetermined drive waveform voltage to scan electrode 22 (scan electrodes SC _{1 to} SC _{n in} FIG. 3) of panel 10 according to the timing control signal, and sustain electrode drive circuit 105 receives the timing control signal. Accordingly, a predetermined drive waveform voltage is applied to sustain electrode 23 (sustain electrodes SU _{1 to} SU _{n in} FIG. 3) of panel 10. The priming electrode driving circuit 106 applies a predetermined driving waveform voltage to the priming electrodes 29 (priming electrodes PR _{1 to} PR _{n-1 in} FIG. 3) of the panel 10 according to the timing control signal. The data electrode driving circuit 102, the scan electrode driving circuit 104, the sustain electrode driving circuit 105, and the priming electrode driving circuit 106 are supplied with necessary power from a power supply circuit (not shown).

  Next, driving waveforms and timing for driving the panel will be described together with the operation of the panel. FIG. 5 is a drive waveform diagram of the panel in accordance with the first exemplary embodiment of the present invention. In the first embodiment of the present invention, one field period is composed of a plurality of subfields having an initialization period, an address period, and a sustain period, and the initialization period of the first subfield is all the main fields related to image display. Perform all-cell initializing operation to generate initializing discharge in the discharge cells, and the second and subsequent subfields are selectively initialized with respect to the main discharge cells that have been sustained in the sustain period of the immediately preceding subfield. It is assumed that the selective initialization operation for generating The all-cell initialization period is divided into two for convenience and will be referred to as the first half and the second half.

In half of the initializing period of the first subfield, data electrodes _D 1 to D _m, holds the sustain electrodes _SU 1 to SU _n in each 0 (V), the scan electrodes _SC 1 to SC _n from the voltage _{V i1} , applying a ramp waveform voltage gradually rises toward the voltage _{V i2} that exceeds the discharge start voltage with respect to sustain electrodes _SU 1 to SU _n and the data electrodes _D 1 to D _m. Further, the same ramp waveform voltage as that of the scan electrodes SC _{1 to} SC _n is applied to the priming electrodes PR _{1 to} PR _n−1 . Then, in the main discharge cells C _{i, j} , the scan electrodes SC _{1 to} SC _n and the sustain electrodes SU _{1 to} SU _n , the scan electrodes SC _{1 to} SC _n and the data electrodes D _{1 to} D _m are weak. Initializing discharge occurs, and weak initializing discharge occurs between the priming electrodes PR _{1 to} PR _n−1 and the data electrodes D _{1 to} D _m inside the priming discharge cell. Negative wall voltage is accumulated on scan electrodes _SC 1 to SC _n upper and priming electrode _{PR 1 ~PR n-1} upper, data electrodes _D 1 to to D _m and sustain electrodes _SU 1 to SU _n upper Accumulates positive wall voltage. Here, the wall voltage at the top of the electrode represents a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

In the second half of the initializing period, maintaining the sustain electrodes _SU 1 to SU _n to a positive voltage Ve, the scan electrodes _SC 1 to SC _n, the discharge with respect to sustain electrodes _SU 1 to SU _n and the data electrodes _D 1 to D _m A ramp waveform voltage that gently falls from a voltage V _{i3 that} is equal to or lower than the start voltage to a voltage V _i4 that exceeds the discharge start voltage is applied. Further, the same ramp waveform voltage as that of the scan electrodes SC _{1 to} SC _n is applied to the priming electrodes PR _{1 to} PR _n−1 . Then, scan electrodes SC _{1 to} SC _n and sustain electrodes SU _{1 to} SU _n , scan electrodes SC _{1 to} SC _n and data electrodes D _{1 to} D _m , priming electrodes PR _{1 to} PR _n-1 and data electrodes D _{1 to} D _A weak initializing discharge occurs between each and _m . Then, negative wall voltage and sustain electrodes _SU 1 to SU _n positive wall voltage on scan electrodes _SC 1 to SC _n upper are weakened, positive wall voltage on data electrodes _D 1 to D _m upper address operation The wall voltage above the priming electrodes PR _{1 to} PR _n−1 is also adjusted to a value suitable for the priming operation. Thus, the all-cell initialization operation for initializing all the discharge cells involved in image display is completed.

In the address period, scan electrodes SC _{1 to} SC _n and priming electrodes PR _{1 to} PR _n−1 are temporarily held at voltage Vc. This is because unnecessary discharge is not generated with application of an address pulse voltage Vd described later. Then, applying a negative priming pulse voltage Vp to priming electrode PR ₁ of the first row. Priming pulse voltage at this time is large pulse amplitude, regardless of the presence of the write pulse voltage applied to the data electrodes D ₁ to D _m, between the priming electrode PR ₁ and the data electrodes D ₁ to D _m Priming discharge occurs. Then, priming is supplied to the main discharge cells C _{1,1 to} C _{1, m in the} first row and the main discharge cells C _{2,1 to} C _{2, m in the} second row. Positive wall voltage is accumulated in the priming electrodes PR ₁ upper This discharge.

Then, to apply a negative scan pulse voltage Va to scan electrodes SC ₁ of the first row. At the same time, a positive write pulse voltage Vd is applied to the data electrode D _k (k represents an integer of 1 to _m ) corresponding to the image signal to be displayed in the first row among the data electrodes D _{1 to} D _m. . Then, during the discharge occurs at the intersection of the data electrode D _k of applying a write pulse voltage Vd and scan electrodes SC _1, and the sustain electrodes SU ₁ corresponding main discharge cells C _{1, k} and the scan electrodes SC ₁ Progresses to discharge. The main discharge cell C _{1, k} positive wall voltage on scan electrodes SC ₁ top of are accumulated negative wall voltage on sustain electrodes SU ₁ upper is accumulated, the first line of the write operation is terminated. Here, the address discharge of the main discharge cells C _{1 and k} occurs after the priming is supplied from the priming discharge generated between the priming electrode PR ₁ and the data electrodes D _{1 to} D _m , so that the discharge delay is small and stable. Discharge.

Next, scan pulse voltage Va is applied to the second line scan electrode SC _2. At the same time, applying a positive write pulse voltage Vd to data electrode D _k corresponding to the image signal to be displayed on the second line of the data electrodes D ₁ to D _m. Then, discharge occurs at the intersection of the data electrode D _k and scan electrode SC _2, develop into a discharge between the corresponding sustain electrode SU ₂ main discharge cell C _{2, k} and scan electrode SC _2. The main discharge cell C _{2, k} a positive wall voltage to the scan electrodes SC ₂ top of the accumulated negative wall voltage on sustain electrode SU ₂ top is stored, the second line of the write operation is terminated. Here, the main discharge cell C _{2, k} of the writing discharge is also small discharge delay because occurs after priming is supplied from the generated priming discharge between the priming electrode PR ₁ and the data electrodes D ₁ to D _m Stable discharge.

At the same time when applying a scan pulse voltage Va in the second row to the scan electrodes SC _2, applies a priming pulse voltage Vp to priming electrode PR _3. Then regardless of the presence of the write pulse voltage applied to the data electrodes _D 1 to D _m, priming discharge occurs between priming electrode PR ₃ and the data electrodes _D 1 to D _m. Then, priming is supplied to the main discharge cells C _{3,1 to} C _{3, m in the third} row and the main discharge cells C _{4,1 to} C _{4, m in the} fourth row. Positive wall voltage is accumulated priming electrode PR ₃ top by the discharge.

Thereafter, the same address operation is performed until reaching the main discharge cells C _{n, k} in the _n- th row, and the address operation is completed. The address discharge of each main discharge cell C _{i, j} is generated after the priming is supplied from the adjacent priming discharge cell, so that it becomes a stable discharge with a small discharge delay.

In the sustain period, scan electrodes SC _{1 to} SC _n , priming electrodes PR _{1 to} PR _n−1 and sustain electrodes SU _{1 to} SU _n are temporarily returned to 0 (V). Then, applying a positive sustain pulse voltage Vs to scan electrodes _SC 1 to SC _n. At this time, the voltage between the upper portion of scan electrode SC _{i and} upper portion of sustain electrode SU _i in main discharge cell C _{i, j where} address discharge has occurred is in addition to sustain pulse voltage Vs, and the upper portion of scan electrode SC _i in the address period. Since the wall voltage accumulated on the sustain electrode SU _i is added, the discharge start voltage is exceeded and a sustain discharge occurs. Thereafter, in the same manner, sustain pulse voltages are alternately applied to scan electrodes SC _{1 to} SC _n and sustain electrodes SU _{1 to} SU _n to thereby generate sustain pulses for main discharge cells C _{i, j} that have undergone address discharge. The sustain discharge is continuously performed by the number of times.

As shown in FIG. 4, sustain pulse voltages similar to those of scan electrodes SC _{1 to} SC _n are applied to priming electrodes PR _{1 to} PR _n−1 . Since a positive wall voltage is accumulated on the top of the priming electrodes PR _{1 to} PR _n−1 in the address period, a discharge occurs inside the priming discharge cell when the first sustain pulse voltage is applied, but after that a discharge occurs. do not do.

In subsequent initializing period of the subfield, the sustain electrodes _SU 1 to SU _n held at the positive voltage Ve, is slowly toward voltage Vi ₄ to the scan electrodes _SC 1 to SC _n and the priming electrode _{PR 1 ~PR n-1} Apply a falling ramp waveform voltage. Then, between the scan electrodes SC _{1 to} SC _n and the sustain electrodes SU _{1 to} SU _n and the data electrodes D _{1 to} D _m of the main discharge cells C _{i, k} that have undergone the sustain discharge, and the priming electrodes PR _{1 to} PR _{n −1} and a weak initializing discharge occur between the data electrodes D _{1 to} D _m , respectively. Then, scan electrodes _SC 1 to SC _n and sustain electrodes _SU 1 to SU _n top of the wall voltage is weakened, positive wall voltage on data electrodes _D 1 to D _m upper is adjusted to a value suitable for the write operation, The positive wall voltage above the priming electrodes PR _{1 to} PR _n−1 is also adjusted to a value suitable for the priming operation.

  The subsequent writing period, sustain period, and subsequent subfield drive waveforms and panel operation are the same as described above.

As described above, during the initialization period and the sustain period, substantially the same drive waveform voltage as that of the scan electrodes SC _{1 to} SC _n is applied to the priming electrodes PR _{1 to} PR _n−1 . This is because scan electrodes SC _p , SC _{p + 1} and the priming electrode PR _p are close to each other, so that unnecessary discharge is not generated between the electrodes. In addition, a discharge not related to image display is generated inside the priming discharge cell when the first sustain pulse voltage is applied in the address period and the sustain period. However, since the light absorption layer 28 is provided in the priming discharge cell, it occurs at this time. The emitted light does not leak outside the panel. In the address period, the address discharge of each main discharge cell C _{i, j} occurs after the priming is supplied from the adjacent priming discharge cell, so that the discharge becomes a stable discharge with a small discharge delay.

Further, since there is an overlap between the time during which the scan pulse voltage is applied to the scan electrode SC _p-1 and the time during which the priming pulse voltage is applied to the priming electrode PR _p , the priming discharge in the first row is excluded. It is not necessary to newly provide time for priming discharge. In the first embodiment, an address discharge is generated between scan electrode SC _p-1 and data electrode D _k , and at the same time, a priming discharge is generated between priming electrode PR _p and data electrodes D _{1 to} D _m . Thus, it is possible to generate priming discharge without extending the panel driving time.

  In the above description of the operation, the initializing period of the first subfield performs all-cell initializing operation in which initializing discharge is performed in all main discharge cells, and the sustaining discharge is performed in the initializing period after the next subfield. Although it has been described that the selective initializing operation for selectively initializing the main discharge cells is performed, these initializing operations may be arbitrarily combined.

(Embodiment 2)
The panel structure in the second embodiment of the present invention is the same as that in the first embodiment. Also in the driving method, performed in the write period, to generate a priming discharge in the adjacent priming discharge cell, main discharge cells C _i, main discharge cells after providing the priming _j C _i, also writing discharges _j This is the same as the first embodiment. The second embodiment is different from the first embodiment in that, in order to further ensure the address discharge, after applying the priming pulse voltage to the priming electrode, the scan electrode adjacent to the priming electrode is first The pulse width of the scan pulse voltage applied to is set to be narrower than the pulse width of the scan pulse voltage to be applied next. That is, in the second embodiment, the address time of the address discharge of the odd-numbered main discharge cells is set short, and the address time of the address discharge of the even-numbered main discharge cells is set long. Further, the operation of the priming discharge cell is stabilized by increasing the amplitude of the sustain pulse voltage first applied to the priming electrode during the sustain period. Furthermore, the drive waveform applied to the priming electrode in the latter half of the initialization period has been devised so that the priming pulse voltage can be set equal to the scanning pulse voltage.

  Next, driving waveforms and timing for driving the panel will be described together with the operation of the panel. FIG. 6 is a drive waveform diagram of the panel according to the second embodiment of the present invention.

  Since the first half of the initializing period of the first subfield is the same as that of the first embodiment, the description thereof is omitted.

In the second half of the initializing period, maintaining the sustain electrodes _SU 1 to SU _n to a positive voltage Ve, the scan electrodes _SC 1 to SC _n, the discharge with respect to sustain electrodes _SU 1 to SU _n and the data electrodes _D 1 to D _m A ramp waveform voltage that gently falls from a voltage V _{i3 that} is equal to or lower than the start voltage to a voltage V _i4 that exceeds the discharge start voltage is applied. Then, weak initializing discharge occurs between scan electrodes SC _{1 to} SC _n and sustain electrodes SU _{1 to} SU _n , and scan electrodes SC _{1 to} SC _n and data electrodes D _{1 to} D _m , respectively. Then, negative wall voltage and sustain electrodes _SU 1 to SU _n positive wall voltage on scan electrodes _SC 1 to SC _n upper are weakened, positive wall voltage on data electrodes _D 1 to D _m upper address operation It is adjusted to a suitable value. Further, the same ramp waveform voltage as that of scan electrodes SC _{1 to} SC _n is applied to priming electrodes PR _{1 to} PR _n−1 , but in the second embodiment, before reaching voltage V _i4 as shown in FIG. The voltage is reduced only to the voltage V _ip of. Also in this case, a weak initializing discharge occurs between the priming electrodes PR _{1 to} PR _n−1 and the data electrodes D _{1 to} D _m , but a large negative voltage is present on the priming electrodes PR _{1 to} PR _n−1 . Wall voltage remains.

In the subsequent address period, scan electrodes SC _{1 to} SC _n are once held at voltage Vc, and priming electrodes PR _{1 to} PR _n−1 are once held at voltage Vc ′. This is because, as in the first embodiment, these voltages do not cause unnecessary discharge with the application of the address pulse voltage Vd. Then, applying a negative priming pulse voltage Vp 'to the priming electrode PR _1. At this time, since the large negative wall voltage formed in the initialization period remains above the priming electrodes PR _{1 to} PR _n−1 , the voltage of the priming pulse voltage Vp ′ is the priming pulse voltage Vp in the first embodiment. It can be set shallower. In the second embodiment, the circuit configuration is simplified by sharing the power supply by setting the voltage equal to the scan pulse voltage Va described later. The priming electrode PR ₁ and the data electrodes _D 1 to D _m to generate a priming discharge between the first row of the main discharge cells _C 1, 1 _{-C 1, m} and the second line of the main discharge cells _{C 2 , 1 to} C _{2, m} diffuses priming inside. Positive wall voltage is accumulated priming electrodes PR ₁ upper This discharge.

Then, similarly, performed in the first row writing operation by applying a negative scan pulse voltage Va to scan electrodes SC ₁ of the first row in the first embodiment. Thereafter, by applying a scan pulse voltage Va in the second row to the scan electrodes SC ₂ to perform the second row of the write operation, but in the second embodiment that time, is applied in the first row to the scan electrodes SC ₁ the pulse width of the scan pulse voltage is set narrower than the pulse width of the scan pulse voltage applied to the scan electrodes SC ₂ of the second row. This is because the address discharge of the main discharge cells C _{1,1 to} C _{1, m in} the first row is generated immediately after the priming discharge, resulting in a discharge with a small discharge delay, and stable address can be performed even if the address time is shortened. Because. Furthermore, this is also for shortening the time interval between the address discharge and the priming discharge of the main discharge cells C _{2,1 to} C _{2, m in} the second row as much as possible. On the other hand, since there is some time interval between the address operation of the main discharge cells C _{2,1 to} C _{2, m in} the second row and the priming discharge, the main discharge cells C _{2,1 to} C in the second row. The discharge delay of the address discharge of _{2, m} tends to be larger than the address discharge of the main discharge cells C _{1,1 to} C _{1, m in} the first row. Therefore, and sets the pulse width of the scan pulse voltage applied to the scan electrodes SC ₂ of the second row in order to complete the writing discharge surely somewhat longer. In the second embodiment, the pulse width of each scanning pulse voltage is set to 1.0 μs and 1.2 μs, for example, but these values are preferably set optimally depending on the panel characteristics and driving conditions. By this method, the address time can be optimized, and as a result, the address period can be shortened while stably generating the address discharge.

Then, as in Embodiment 1 also performed in the second embodiment, by applying a scan pulse voltage Va in the second row to the scan electrodes SC ₂ to perform the second row of the write operation at the same time, also to priming electrode PR ₃ A priming discharge is generated by simultaneously applying the priming pulse voltage Vp ′. Then, priming is supplied to the main discharge cells C _{3,1 to} C _{3, m in the third} row and the main discharge cells C _{4,1 to} C _{4, m in the} fourth row. Thereafter, the same address operation is performed until reaching the main discharge cells C _{n, k} in the _n- th row, and the address operation is completed. Also in the second embodiment _, the address discharge of each main discharge cell C _{i, j} is generated after the priming is supplied from the adjacent priming discharge cell, so that it becomes a stable discharge with a small discharge delay.

Also in the sustain period, as in the first embodiment, by applying the sustain pulse voltage alternately to the scan electrodes SC ₁ to SC _n and sustain electrodes SU ₁ to SU _n, main discharge cell having caused the address discharge C _Sustain discharge is continuously performed for _{i and j} by the number of sustain pulses. On the other hand, as shown in FIG. 6, sustain pulse voltages similar to those of scan electrodes SC _{1 to} SC _n are applied to priming electrodes PR _{1 to} PR _n-1 , but the first sustain pulse voltage is higher than sustain pulse voltage Vs. A larger voltage Vs ′ is applied. The reason is as follows. In the write period, but to generate a priming discharge between the priming electrode PR _p and the data electrodes D ₁ to D _m, this time, in the data electrodes D ₁ to D _m is applied address pulse voltage Vd And those not applied are mixed. After the priming discharge, the wall voltage of the applied data not electrodes D ₁ to D _m upper address pulse voltage Vd is less than the applied data electrodes D ₁ to D _m top of the wall voltage of the write pulse voltage Vd It may have become. Therefore, the voltage of the first sustain pulse is set large so that the discharge can be reliably generated even when the wall voltage is small.

It followed initializing period of sub-fields, as well as the all-cell second half of the initializing period, maintaining the sustain electrodes _SU 1 to SU _n to a positive voltage Ve, the scan electrodes _SC 1 to SC _n, the sustain electrodes _SU 1 to SU A ramp waveform voltage that gradually falls from voltage V _{i3 that} is equal to or lower than the discharge start voltage to voltage V _i4 that exceeds the discharge start voltage is applied to _n and data electrodes D _{1 to} D _m . However, as in the latter half of the initializing period of the first subfield, the voltage is reduced only to the voltage V _ip before reaching the voltage V _i4 in the priming electrodes PR _{1 to} PR _n−1 . Then, a large negative wall voltage is left on the priming electrodes PR _{1 to} PR _n−1 .

  The subsequent writing period, sustain period, and subsequent subfield drive waveforms and panel operation are the same as described above.

  In the second embodiment, in addition to the effects obtained in the first embodiment, the address period can be shortened while the address discharge is stably generated.

  INDUSTRIAL APPLICABILITY Since the present invention can stably generate an address discharge without narrowing the drive voltage margin for the address operation, it is useful as a panel used for a wall-mounted television, a large monitor, and the like and a method for driving the panel.

The disassembled perspective view which shows the structure of the panel in Embodiment 1, 2 of this invention. Cross section of the panel Electrode arrangement of the panel The block diagram which shows an example of the circuit structure of the plasma display apparatus using the panel Drive waveform diagram of panel in embodiment 1 of the present invention Drive waveform diagram of panel in embodiment 2 of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 Front substrate 22 Scan electrode 23 Sustain electrode 24 Dielectric layer 25 Protection layer 28 Light absorption layer 29 Priming electrode 31 Back substrate 32 Data electrode 33 Dielectric layer 34 Partition 35 Phosphor layer 40 Main discharge cell 41 Gap part 41a Priming discharge cell

Claims (4)

A scan electrode and a sustain electrode arranged in parallel on the first substrate and constituting a display electrode pair;
A data electrode disposed in a direction intersecting the scan electrode on a second substrate disposed opposite to the first substrate across a discharge space and constituting a main discharge cell with the display electrode pair;
Partitioning the main discharge cells to form a main discharge cell row in which the main discharge cells are connected together along the display electrode pair, and a partition wall provided with a gap between adjacent main discharge cell rows;
A plasma display panel in which a priming electrode is arranged in parallel with the scan electrode at a position corresponding to the gap between the two scan electrodes adjacent to each other on the first substrate. A method for driving a plasma display panel according to claim 1,
One field is composed of a plurality of subfields having an initialization period, an address period, and a sustain period,
In the address period, a scan pulse voltage is sequentially applied to the scan electrode, and the priming electrode and the data are applied to the priming electrode adjacent to the scan electrode to which the scan pulse voltage is applied prior to the application of the scan pulse voltage. A driving method of a plasma display panel, characterized by applying a priming pulse voltage for generating a priming discharge with an electrode. 3. The plasma display panel according to claim 2, wherein in the address period, there is an overlap between a time during which the scan pulse voltage is applied to the scan electrode and a time during which the priming pulse voltage is applied to the priming electrode. Driving method. After applying the priming pulse voltage to the priming electrode, the scan pulse voltage of the scan electrode to which the scan pulse voltage is first applied among the scan electrodes adjacent to the priming electrode to which the priming pulse voltage is applied is 4. The method of driving a plasma display panel according to claim 2, wherein the pulse width of the scan pulse voltage of the scan electrode to which the scan pulse voltage is applied is set to be narrower.

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