JP2005101270A - Packaging structure of semiconductor device - Google Patents

Packaging structure of semiconductor device Download PDF

Info

Publication number
JP2005101270A
JP2005101270A JP2003333099A JP2003333099A JP2005101270A JP 2005101270 A JP2005101270 A JP 2005101270A JP 2003333099 A JP2003333099 A JP 2003333099A JP 2003333099 A JP2003333099 A JP 2003333099A JP 2005101270 A JP2005101270 A JP 2005101270A
Authority
JP
Japan
Prior art keywords
semiconductor element
pad
pads
conductive material
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003333099A
Other languages
Japanese (ja)
Inventor
Kenichi Kato
謙一 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2003333099A priority Critical patent/JP2005101270A/en
Publication of JP2005101270A publication Critical patent/JP2005101270A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To provide a packaging structure of a semiconductor device in which a difference in a bonding strength between a conductive material and the semiconductor device and between the conductive material and a substrate can be reduced, and the bonding strength between the conductive material and the substrate can be increased. <P>SOLUTION: In the packaging structure of the semiconductor device, a plurality of electrode pads 5 are disposed on a substrate 1 in which a plurality of connection pads 3 are disposed to form a semiconductor device 4, which is arranged so that the connection pads 3 faces the electrode pads 5, and the both are connected to each other by a conductive material 6. Regarding the electrode pads 5 and the connection pads 3 which face each other, one pad area is made larger than the other, and also a size relation of both is alternately reversed along the arrangement of the pad. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は回路基板上にフェースダウンボンディングにて実装される半導体素子の実装構造体に関するものである。  The present invention relates to a semiconductor element mounting structure mounted on a circuit board by face-down bonding.

従来より、半導体素子をフェースダウンボンディングにて実装したものが知られている。
このフェースダウンボンディングに使用される半導体素子の下面には、高密度に形成された電子回路以外に複数個の電極パッドが設けられており、これらの端子を回路基板の接続パッドに半田等の導電材を介して接続することにより半導体素子を回路基板上に実装させるようになっている。
Conventionally, a semiconductor element mounted by face-down bonding is known.
In addition to the electronic circuit formed with high density, a plurality of electrode pads are provided on the lower surface of the semiconductor element used for the face-down bonding, and these terminals are connected to the connection pads of the circuit board by a conductive material such as solder. A semiconductor element is mounted on a circuit board by connecting via a material.

尚、接続パッドは、回路導体の一端部に、導電材の濡れ性を向上させるために金やニッケル等を1μm〜5μmの厚みに被着させて成り、この接続パッドを介して半導体素子の電極パッドと回路基板上の回路導体を導電材で接合することにより両者の接続をより確実なものとなすようにしている。   The connection pad is formed by depositing gold, nickel or the like on one end portion of the circuit conductor to a thickness of 1 μm to 5 μm in order to improve the wettability of the conductive material. The connection between the pads and the circuit conductor on the circuit board is made more reliable by bonding them with a conductive material.

ところで、サーマルヘッドやLEDヘッド等のヘッド駆動用ICとして用いられる半導体素子の電極パッドと、回路基板上の接続パッドとは、その面積が電極パッド側もしくは接続パッド側のいずれか一方で大きく、他方で小さく形成されているのが一般的である。
特開平1−179425号公報 特開平10−129024号公報
By the way, the electrode pad of a semiconductor element used as a head driving IC such as a thermal head or an LED head and the connection pad on the circuit board have a large area on either the electrode pad side or the connection pad side, In general, it is formed small.
JP-A-1-179425 JP-A-10-129024

しかしながら、上述の特許文献1や特許文献2のような構成では、パッド面積が電極パッド側もしくは接続パッド側のいずれか一方で常に大きくなっているため、導電材−半導体素子間の接合強度と導電材−回路基板間の接合強度とのバランスが悪くなる。例えば、特許文献1の如く、半導体素子側でパッド面積が小さいと、導電材と電極パッドとの接触面積が導電材と接触パッドとの接触面積よりも大幅に小さくなり、導電材と電極パッドとの接合強度が不足しがちになる。このため、半導体素子と回路基板との接合部に外力が印加された場合、導電材と電極パッドとの境界部にひび割れや亀裂等が生じやすい問題があった。   However, in the configurations as described in Patent Document 1 and Patent Document 2 described above, the pad area is always increased on either the electrode pad side or the connection pad side, so that the bonding strength between the conductive material and the semiconductor element and the conductivity are increased. The balance with the bonding strength between the material and the circuit board is deteriorated. For example, as in Patent Document 1, when the pad area is small on the semiconductor element side, the contact area between the conductive material and the electrode pad is significantly smaller than the contact area between the conductive material and the contact pad. The joint strength tends to be insufficient. For this reason, when an external force is applied to the junction between the semiconductor element and the circuit board, there is a problem that cracks, cracks, and the like are likely to occur at the boundary between the conductive material and the electrode pad.

本発明は上記問題点に鑑み案出されたものであり、その目的は導電材−半導体素子間、並びに導電材−回路基板間の接合強度の差を小さくし、半導体素子と回路基板との接合強度を高くすることが可能な半導体素子の実装構造体を提供することにある。   The present invention has been devised in view of the above problems, and its purpose is to reduce the difference in bonding strength between the conductive material and the semiconductor element and between the conductive material and the circuit board, and to bond the semiconductor element and the circuit board. An object of the present invention is to provide a semiconductor element mounting structure capable of increasing strength.

本発明の半導体素子の実装構造体は、複数の接続パッドが配列された基板上に、複数の電極パッドが配列された半導体素子を、前記接続パッド及び前記電極パッドが対向するように配設させ、両者を導電材で接続して成る半導体素子の実装構造体において、互いに対向する前記電極パッド及び前記接続パッドのうち、一方のパッド面積を他方に比べて大きくするとともに、両者のパッド面積の大小関係をパッドの配列に沿って交互に反転させたことを特徴とする。   According to the semiconductor element mounting structure of the present invention, a semiconductor element having a plurality of electrode pads arranged on a substrate on which a plurality of connection pads are arranged is arranged so that the connection pads and the electrode pads face each other. In the semiconductor element mounting structure in which the two are connected by a conductive material, one of the electrode pads and the connection pads facing each other has a larger pad area than the other, and the size of the two pad areas is large or small. The relationship is alternately reversed along the arrangement of the pads.

また本発明の半導体素子の実装構造体は、上述した半導体素子の実装構造体において、前記導電材が断面台形状を成していることを特徴とする。   The semiconductor element mounting structure according to the present invention is characterized in that, in the above-described semiconductor element mounting structure, the conductive material has a trapezoidal cross section.

更に本発明の半導体素子の実装構造体は、上述した半導体素子の実装構造体において、前記電極パッド及び前記接続パッドは複数列に配列されており、隣接する列同士で対向する電極パッド及び接続パッドの大小関係が反転していることを特徴とする。   Further, the semiconductor element mounting structure of the present invention is the above-described semiconductor element mounting structure, wherein the electrode pads and the connection pads are arranged in a plurality of rows, and the electrode pads and the connection pads facing each other in adjacent rows. It is characterized in that the magnitude relation of is reversed.

本発明の半導体素子の実装構造体によれば、互いに対向する半導体素子の電極パッド及び基板上の接続パッドのうち、一方のパッド面積を他方に比べて大きくするとともに、両者のパッド面積の大小関係をパッドの配列に沿って交互に反転させたことから、導電材と電極パッドとの接触面積、並びに導電材と接続パッドとの接触面積の差を従来よりも小さくすることができる。従って、導電材−半導体素子間、導電材−基板間の接合強度の差を小さくし、いずれか一方の接合強度が極端に弱くなることを有効に防止でき、半導体素子と基板との接合強度を高めることが可能となる。   According to the semiconductor element mounting structure of the present invention, among the electrode pads of the semiconductor elements facing each other and the connection pads on the substrate, one of the pad areas is made larger than the other, and the relationship between the two pad areas is large or small. Are alternately inverted along the arrangement of the pads, so that the difference in the contact area between the conductive material and the electrode pad and the contact area between the conductive material and the connection pad can be made smaller than before. Accordingly, it is possible to reduce the difference in bonding strength between the conductive material and the semiconductor element and between the conductive material and the substrate, and to effectively prevent any one of the bonding strengths from becoming extremely weak, and to reduce the bonding strength between the semiconductor element and the substrate. It becomes possible to raise.

また本発明の半導体素子の実装構造体によれば、前記電極パッド及び前記接続パッドは複数列に配列されており、隣接する列同士で対向する電極パッド及び接続パッドの大小関係を反転させたことから、導電材−電極パッド間、並びに導電材−接続パッド間の接合強度の差を従来よりも更に小さくすることができる。   According to the semiconductor element mounting structure of the present invention, the electrode pads and the connection pads are arranged in a plurality of rows, and the size relationship between the electrode pads and the connection pads facing each other in the adjacent rows is reversed. Therefore, the difference in bonding strength between the conductive material and the electrode pad and between the conductive material and the connection pad can be further reduced as compared with the conventional case.

以下、本発明を添付図面に基づいて詳細に説明する。図1は本発明の実装構造体をサーマルヘッドに適用した形態を示す断面図、図2は図1のサーマルヘッドの要部拡大図、図3は図1のサーマルヘッドに搭載される半導体素子を一主面側から見た平面図であり、1は基板、2は回路導体、3は接続パッド、4は半導体素子、5は電極パッド、6は導電材、7は封止材である。   Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment in which the mounting structure of the present invention is applied to a thermal head, FIG. 2 is an enlarged view of a main part of the thermal head in FIG. 1, and FIG. 3 shows a semiconductor element mounted on the thermal head in FIG. 1 is a plan view seen from one main surface side, where 1 is a substrate, 2 is a circuit conductor, 3 is a connection pad, 4 is a semiconductor element, 5 is an electrode pad, 6 is a conductive material, and 7 is a sealing material.

基板1は、アルミナセラミックスやガラス等の電気絶縁性材料や表面に絶縁膜が形成された半導体材料等の種々の材料により四角形状に形成されており、その上面で複数の発熱素子Rや複数の回路導体2や接続パッド3,半導体素子4,封止材7等を支持するようになっている。   The substrate 1 is formed in a quadrangular shape by various materials such as an electrically insulating material such as alumina ceramics and glass and a semiconductor material having an insulating film formed on the surface, and a plurality of heating elements R and a plurality of heating elements R are formed on the upper surface thereof. The circuit conductor 2, the connection pad 3, the semiconductor element 4, the sealing material 7 and the like are supported.

基板1は、例えばアルミナセラミックスから成る場合、アルミナ,シリカ,マグネシア等のセラミック原料粉末に適当な有機溶媒、有機溶剤を添加・混合して泥漿状に成すとともに、これを従来周知のドクターブレード法等を採用することによってセラミックグリーンシートを得、しかる後、該セラミックグリーンシートに所定形状に打ち抜いた上、これを高温(約1600℃)で焼成することにより製作される。   When the substrate 1 is made of, for example, alumina ceramics, an appropriate organic solvent or an organic solvent is added to and mixed with ceramic raw material powder such as alumina, silica, magnesia, etc. to form a slurry, and this is made into a conventionally known doctor blade method or the like. Is used to obtain a ceramic green sheet, and thereafter, the ceramic green sheet is punched into a predetermined shape and then fired at a high temperature (about 1600 ° C.).

また基板1の上面に被着・形成される回路導体2は、例えばサーマルヘッドに適用する場合、半導体素子4(ヘッド駆動用IC)の電極パッド5より発せられる出力を発熱素子Rに印加するための給電配線や外部からの印画信号等を半導体素子4に供給するための信号配線としての作用を為す。   The circuit conductor 2 deposited and formed on the upper surface of the substrate 1 applies an output generated from the electrode pad 5 of the semiconductor element 4 (head driving IC) to the heating element R when applied to, for example, a thermal head. This serves as a signal wiring for supplying the semiconductor element 4 with a power supply wiring and an external print signal.

このような回路導体2は、例えばアルミニウム等の金属を従来周知の薄膜手法、具体的にはスパッタリングやフォトリソグラフィー技術,エッチング技術等を採用することによって基板1の上面に所定厚み、所定パターンに被着・形成される。   Such a circuit conductor 2 is formed by coating a metal such as aluminum with a predetermined thickness and a predetermined pattern on the upper surface of the substrate 1 by adopting a conventionally well-known thin film technique, specifically, sputtering, photolithography technique, etching technique or the like. Wear and form.

また、これら複数の回路導体2の一部上面には、各々が略四角形状を有する複数の接続パッド3が被着されている。   A plurality of connection pads 3 each having a substantially quadrangular shape are attached to some upper surfaces of the plurality of circuit conductors 2.

この接続パッド3は後述する半導体素子4の長辺に沿って複数列に配列されており、横方向(半導体素子4の長辺に沿った方向)、縦方向(半導体素子4の長辺に直交する方向)の各方向について大面積パッドと小面積パッドとが交互に配置されている。   The connection pads 3 are arranged in a plurality of rows along the long side of the semiconductor element 4 to be described later, and are arranged in the horizontal direction (direction along the long side of the semiconductor element 4) and in the vertical direction (perpendicular to the long side of the semiconductor element 4). Large area pads and small area pads are alternately arranged in each direction.

これらの接続パッド3は、導電材6を介して半導体素子4の電極パッド5に電気的に接続されるものであり、導電材6に対する濡れ性の良好な金属、例えば導電材6が半田から成る場合、金やニッケル等を回路導体2の一端部に1μm〜5μmの厚みに被着して形成される。従って、半導体素子4を実装する際、導電材6が良好に濡れるようになり、半導体素子4の電極パッド5と基板1上の接続パッド3との接続がより確実になる。   These connection pads 3 are electrically connected to the electrode pads 5 of the semiconductor element 4 through the conductive material 6, and a metal having good wettability to the conductive material 6, for example, the conductive material 6 is made of solder. In this case, gold, nickel, or the like is formed on one end of the circuit conductor 2 to a thickness of 1 μm to 5 μm. Therefore, when the semiconductor element 4 is mounted, the conductive material 6 gets wet well, and the connection between the electrode pad 5 of the semiconductor element 4 and the connection pad 3 on the substrate 1 becomes more reliable.

尚、接続パッド3は従来周知の無電解めっき法等を採用することにより回路導体2の一部表面に所定厚み、所定パターンをなすように被着・形成される。   The connection pads 3 are deposited and formed on a part of the surface of the circuit conductor 2 so as to have a predetermined thickness and a predetermined pattern by employing a conventionally known electroless plating method or the like.

そして、上述した複数の接続パッド3には、半導体素子4の一主面に設けた複数の電極パッド5が導電材6を介して接続される。   A plurality of electrode pads 5 provided on one main surface of the semiconductor element 4 are connected to the plurality of connection pads 3 described above via a conductive material 6.

半導体素子4は、単結晶シリコンからなる長方形状の板体の一主面に、長方形状を成す複数の電極パッド5を基板1上の接続パッド3に対応させるようにして形成した構造を有している。   The semiconductor element 4 has a structure in which a plurality of rectangular electrode pads 5 are formed on one main surface of a rectangular plate made of single crystal silicon so as to correspond to the connection pads 3 on the substrate 1. ing.

この半導体素子4上の電極パッド5は、半導体素子4の長辺に沿って複数列に配列されており、横方向(半導体素子4の長辺に沿った方向)、縦方向(半導体素子4の長辺に直交する方向)に関して大面積パッドと小面積パッドとが交互に配置されている。   The electrode pads 5 on the semiconductor element 4 are arranged in a plurality of rows along the long side of the semiconductor element 4, and are arranged in the horizontal direction (direction along the long side of the semiconductor element 4) and the vertical direction (of the semiconductor element 4. Large area pads and small area pads are alternately arranged in the direction orthogonal to the long side.

このような電極パッド5を有する半導体素子4は、従来周知のフェースダウンボンディングによって基板1上に実装されており、互いに対向する半導体素子4上の電極パッド5と基板1上の接続パッド3とを導電材6を介して電気的に接続させている。   The semiconductor element 4 having such an electrode pad 5 is mounted on the substrate 1 by conventionally known face-down bonding, and the electrode pad 5 on the semiconductor element 4 and the connection pad 3 on the substrate 1 facing each other are connected. It is electrically connected through the conductive material 6.

そしてここで重要なことは、互いに対向する電極パッド5及び接続パッド3のうち、一方のパッド面積を他方に比べて大きくし、且つ両者のパッド面積の大小関係をパッド3,5の配列に沿って交互に反転させたことであり、かかる形態とすべく、大面積の電極パッド5が小面積の接続パッド3に、小面積の電極パッド5が大面積の接続パッド3にそれぞれ対向するように配置させている。   What is important here is that one of the opposing electrode pads 5 and connection pads 3 has a larger pad area than the other, and the relationship between the two pad areas is in accordance with the arrangement of the pads 3 and 5. In order to adopt such a configuration, the large-area electrode pad 5 is opposed to the small-area connection pad 3 and the small-area electrode pad 5 is opposed to the large-area connection pad 3. It is arranged.

このため、導電材6は、接続パッド3側に向かって広がる断面台形状のものと、電極パッド5側に向かって広がる断面台形状ものとが隣接するパッド同士で交互に配置されることとなり、導電材6と電極パッド5との接触面積、並びに導電材6と接続パッド3との接触面積の差を従来よりも小さくすることができる。従って、導電材6−半導体素子4間、導電材6−基板1間の接合強度の差が小さくなり、いずれか一方の接合強度が極端に弱くなることが良好に防止され、半導体素子4と基板1との接合強度を高めることができる。   For this reason, the conductive material 6 is alternately arranged in the shape of a trapezoidal cross section that expands toward the connection pad 3 side and the cross-sectional trapezoidal shape that expands toward the electrode pad 5 side. The difference in the contact area between the conductive material 6 and the electrode pad 5 and the contact area between the conductive material 6 and the connection pad 3 can be made smaller than before. Therefore, the difference in bonding strength between the conductive material 6 and the semiconductor element 4 and between the conductive material 6 and the substrate 1 is reduced, and it is satisfactorily prevented that either one of the bonding strengths becomes extremely weak. The bonding strength with 1 can be increased.

しかも、本実施形態においては、縦横双方の方向に関して、パッド面積の大小関係が交互に反転しているため、導電材6−半導体素子4間、並びに導電材6−基板1間の接合強度の差を従来よりも更に小さくすることができる。   In addition, in this embodiment, since the size relationship of the pad area is alternately reversed in both the vertical and horizontal directions, a difference in bonding strength between the conductive material 6 and the semiconductor element 4 and between the conductive material 6 and the substrate 1 is obtained. Can be made smaller than before.

なお、上述の半導体素子4は、まず、従来周知のチョコラルスキー法を採用することにより単結晶シリコンからなるインゴット(塊)を得るとともに、これをダイヤモンドカッター等を用いて板状にスライスし、しかる後、従来周知の半導体製造技術を用いてスイッチング素子、ラッチ、シフトレジスタ等の電子回路や電極パッド5等を高密度に集積することによって形成される。   The semiconductor element 4 described above first obtains an ingot (lumps) made of single crystal silicon by adopting a conventionally known chocolate ski method, and slices it into a plate shape using a diamond cutter or the like. After that, it is formed by integrating electronic circuits such as switching elements, latches, and shift registers, electrode pads 5 and the like with high density using a conventionally well-known semiconductor manufacturing technique.

また半導体素子4を基板1上に実装するには、導電材6が半田から成る場合、まず、従来周知のスクリーン印刷法により半田ペーストを半導体素子4の電極パッド5上に塗布するとともに、これを所定の温度(200℃〜270℃)の温度で溶融させることにより、電極パッド5上に略球状の半田バンプを形成する。次に、パッド面積の大きな電極パッド5がパッド面積の小さな接続パッド3に、パッド面積の小さな電極パッド5がパッド面積の大きな接続パッド3にそれぞれ対応するように半導体素子4 を基板上面の所定位置に載置させる。最後に、上述のハンダバンプを加熱・溶融させ、該溶融した半田でもって電極パッド5と接続パッド3とを電気的・機械的に接続することで実装作業が完了する。   In order to mount the semiconductor element 4 on the substrate 1, when the conductive material 6 is made of solder, first, a solder paste is applied onto the electrode pad 5 of the semiconductor element 4 by a well-known screen printing method. By melting at a predetermined temperature (200 ° C. to 270 ° C.), a substantially spherical solder bump is formed on the electrode pad 5. Next, the semiconductor element 4 is placed at a predetermined position on the upper surface of the substrate so that the electrode pad 5 having a large pad area corresponds to the connection pad 3 having a small pad area, and the electrode pad 5 having a small pad area corresponds to the connection pad 3 having a large pad area. To be placed. Finally, the above-described solder bump is heated and melted, and the mounting operation is completed by electrically and mechanically connecting the electrode pad 5 and the connection pad 3 with the melted solder.

そして半導体素子4や導電材6はビスフェノール型エポキシ樹脂から成る封止材7により被覆されている。   The semiconductor element 4 and the conductive material 6 are covered with a sealing material 7 made of a bisphenol type epoxy resin.

封止材7は半導体素子4を大気中に含まれている水分等の接触による腐食等から保護するためのものであり、ビスフェノール型エポキシ樹脂は適度な分子量を有するビスフェノールAを主原料とするため、これを毛細管現象によって基板1と半導体素子4との間隙に良好に導入することができ、これによって導電材6を封止材7で完全に被覆することが可能となる。   The sealing material 7 is for protecting the semiconductor element 4 from corrosion caused by contact with moisture contained in the atmosphere, and the bisphenol type epoxy resin is mainly composed of bisphenol A having an appropriate molecular weight. This can be satisfactorily introduced into the gap between the substrate 1 and the semiconductor element 4 by a capillary phenomenon, whereby the conductive material 6 can be completely covered with the sealing material 7.

尚、封止材7は、ビスフェノール型エポキシ樹脂のワニスをディスペンサー等を用いて半導体素子4が実装されている基板1 の上面所定領域に塗布し、これを150℃〜200℃の温度で加熱・重合させることにより半導体素子全体を被覆した状態で形成される。このとき、ビスフェノール型エポキシ樹脂のワニスは前述した如く毛細管現象により半導体素子4と基板1との間隙にも良好に導入されるため、導電材6は封止材7でもって完全に被覆されることとなる。このワニスの粘度は100ポイズ以下に設定しておくのが好ましく、この範囲内となしておくことにより前述の毛細管現象をより良好に発揮させることができる。   The sealing material 7 is a bisphenol-type epoxy resin varnish applied to a predetermined region on the upper surface of the substrate 1 on which the semiconductor element 4 is mounted using a dispenser or the like, and heated at a temperature of 150 ° C. to 200 ° C. It is formed in a state where the entire semiconductor element is covered by polymerization. At this time, since the varnish of the bisphenol type epoxy resin is satisfactorily introduced into the gap between the semiconductor element 4 and the substrate 1 by the capillary phenomenon as described above, the conductive material 6 is completely covered with the sealing material 7. It becomes. The viscosity of the varnish is preferably set to 100 poises or less, and by making it within this range, the above-described capillary phenomenon can be exhibited better.

本発明の実装構造体は上述の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良等が可能である。   The mounting structure of the present invention is not limited to the above-described embodiment, and various changes and improvements can be made without departing from the gist of the present invention.

例えば上述の形態では接続パッド3や電極パッド5の形状を略四角形状になしたが、これに代えて五角形状や六角形状,円形状等になしても良い。   For example, in the above-described embodiment, the connection pad 3 and the electrode pad 5 are formed in a substantially square shape, but may be replaced with a pentagonal shape, a hexagonal shape, a circular shape, or the like.

また上述の実施形態においては、全ての接続パッド3及び電極パッド5に関して、パッド面積の大小関係が隣接するパッド同士で反転するようにしたが、一部の接続パッド3及び電極パッド5に関してについてパッド面積の大小関係が隣接するパッド同士で反転した形となっていれば良い。ただし、本発明の効果を奏するためには、前者の方が好ましい。   In the above-described embodiment, the pad area size relationship is reversed between adjacent pads for all the connection pads 3 and electrode pads 5, but the pads for some of the connection pads 3 and electrode pads 5 are also reversed. It suffices that the size relationship is reversed between adjacent pads. However, the former is preferable in order to achieve the effects of the present invention.

また上述の形態において接続パッド3と回路導体2との間に、両者間の密着力をより高くなすために、パラジウム等の金属から成る密着層を介在させておいても良い。   In the above-described embodiment, an adhesion layer made of a metal such as palladium may be interposed between the connection pad 3 and the circuit conductor 2 in order to increase the adhesion between them.

更に上述の形態においては接続パッド3を単一の金属により形成したが、これに代えて接続パッド3を2種類以上の金属、例えばニッケルから成る第1接続パッド上に金から成る第2接続パッドを積層して2層構造の接続パッド3となしたり、或いは3種類以上の金属を順次積層した多層構造の接続パッド3となしても良い。   Furthermore, in the above-described embodiment, the connection pad 3 is formed of a single metal. Instead, the connection pad 3 is formed of a second connection pad made of gold on a first connection pad made of two or more kinds of metals, for example, nickel. May be used to form a connection pad 3 having a two-layer structure, or a connection pad 3 having a multilayer structure in which three or more kinds of metals are sequentially stacked.

図1は本発明の実装構造体をサーマルヘッドに適用した形態を示す断面図である。FIG. 1 is a cross-sectional view showing a form in which the mounting structure of the present invention is applied to a thermal head. 図2は図1のサーマルヘッドの要部拡大図である。FIG. 2 is an enlarged view of a main part of the thermal head of FIG. 図3は図1のサーマルヘッドに搭載される半導体素子を一主面側から見た平面図である。FIG. 3 is a plan view of a semiconductor element mounted on the thermal head of FIG. 1 as viewed from one main surface side.

符号の説明Explanation of symbols

1・・・基板
2・・・回路導体
3・・・接続パッド
4・・・半導体素子
5・・・電極パッド
6・・・導電材
7・・・封止材
R・・・発熱素子
DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Circuit conductor 3 ... Connection pad 4 ... Semiconductor element 5 ... Electrode pad 6 ... Conductive material 7 ... Sealing material R ... Heating element

Claims (3)

複数の接続パッドが配列された基板上に、複数の電極パッドが配列された半導体素子を、前記接続パッド及び前記電極パッドが対向するように配設させ、両者を導電材で接続して成る半導体素子の実装構造体において、
互いに対向する前記電極パッド及び前記接続パッドのうち、一方のパッド面積を他方に比べて大きくするとともに、両者のパッド面積の大小関係をパッドの配列に沿って交互に反転させたことを特徴とする半導体素子の実装構造体。
A semiconductor device in which a semiconductor element on which a plurality of electrode pads are arranged is arranged on a substrate on which a plurality of connection pads are arranged so that the connection pads and the electrode pads face each other, and both are connected by a conductive material. In the element mounting structure,
Among the electrode pads and the connection pads facing each other, one of the pad areas is made larger than the other, and the magnitude relation between the two pad areas is alternately inverted along the arrangement of the pads. Semiconductor element mounting structure.
前記導電材が断面台形状を成していることを特徴とする請求項1に記載の半導体素子の実装構造体。 The semiconductor element mounting structure according to claim 1, wherein the conductive material has a trapezoidal cross section. 前記電極パッド及び前記接続パッドは複数列に配列されており、隣接する列同士で対向する電極パッド及び接続パッドの大小関係が反転していることを特徴とする請求項1または請求項2に記載の半導体素子の実装構造体。 The electrode pad and the connection pad are arranged in a plurality of rows, and the size relationship between the electrode pad and the connection pad facing each other in adjacent rows is reversed. Mounting structure of semiconductor element.
JP2003333099A 2003-09-25 2003-09-25 Packaging structure of semiconductor device Pending JP2005101270A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003333099A JP2005101270A (en) 2003-09-25 2003-09-25 Packaging structure of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003333099A JP2005101270A (en) 2003-09-25 2003-09-25 Packaging structure of semiconductor device

Publications (1)

Publication Number Publication Date
JP2005101270A true JP2005101270A (en) 2005-04-14

Family

ID=34461204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003333099A Pending JP2005101270A (en) 2003-09-25 2003-09-25 Packaging structure of semiconductor device

Country Status (1)

Country Link
JP (1) JP2005101270A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149836A (en) * 2005-11-25 2007-06-14 Toshiba Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007149836A (en) * 2005-11-25 2007-06-14 Toshiba Corp Semiconductor device
JP4528715B2 (en) * 2005-11-25 2010-08-18 株式会社東芝 Semiconductor device and manufacturing method thereof

Similar Documents

Publication Publication Date Title
JP6791719B2 (en) Substrate for mounting electronic components, electronic devices and electronic modules
US10699993B2 (en) Wiring board, electronic device, and electronic module
JP6767204B2 (en) Boards for mounting electronic components, electronic devices and electronic modules
JP6698826B2 (en) Substrate for mounting electronic parts, electronic device and electronic module
JP2023071984A (en) Wiring board, electronic device, and electronic module
JP3537699B2 (en) Semiconductor element mounting structure
JP2005101270A (en) Packaging structure of semiconductor device
JP3492919B2 (en) Semiconductor element mounting structure
JP6933716B2 (en) Substrate for mounting electronic components, electronic devices and electronic modules
CN110326101B (en) Wiring substrate, electronic device, and electronic module
JP2005322659A (en) Wiring board, its manufacturing method and semiconductor device
JP2007173429A (en) Wiring circuit board
JPH09180973A (en) Semiconductor device and manufacture thereof
JP2004288661A (en) Wiring board
JP4217151B2 (en) Wiring board
JP2004281470A (en) Wiring board
JP6818457B2 (en) Wiring boards, electronics and electronic modules
JP2004119909A (en) Wiring board
JP4416269B2 (en) Electronic equipment
JP2004259801A (en) Wiring board
JP6595308B2 (en) Electronic component mounting substrate, electronic device and electronic module
JP2002299514A (en) Electronic part mounting board
JP6441696B2 (en) Wiring board, electronic device and electronic module
JP2004259802A (en) Wiring board
JP2003068920A (en) Wiring board

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060912

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20080514

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080520

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080924