JP3492919B2 - Semiconductor element mounting structure - Google Patents
Semiconductor element mounting structureInfo
- Publication number
- JP3492919B2 JP3492919B2 JP21771598A JP21771598A JP3492919B2 JP 3492919 B2 JP3492919 B2 JP 3492919B2 JP 21771598 A JP21771598 A JP 21771598A JP 21771598 A JP21771598 A JP 21771598A JP 3492919 B2 JP3492919 B2 JP 3492919B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- connection pads
- insulating substrate
- resin material
- mounting structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
【０００１】
【発明の属する技術分野】本発明は各種電子デバイスに
使用される半導体素子の実装構造体に関するものであ
る。
【０００２】
【従来の技術及びその課題】従来より、半導体素子の実
装方法として、フェースダウンボンディングが知られて
いる。
【０００３】このフェースダウンボンディングに使用さ
れる半導体素子の下面には電子回路以外に複数個の端子
が設けられており、これらの端子を回路基板の回路導体
に半田等の導電性接着材を介して接合することにより半
導体素子の実装が行われる。
【０００４】尚、前記半導体素子の端子が半田接合され
る回路導体の表面には半田ぬれ性を向上させるために金
メッキやニッケルメッキ等から成る接続パッドが１μｍ
〜５μｍの厚みに被着されており、この接続パッドを介
して半導体素子の端子と回路基板上の回路導体とを半田
接合させることにより両者を確実に接続するようにして
いる。
【０００５】そして前記半導体素子は、該半導体素子を
大気中に含まれている水分等の接触による腐食等から保
護する目的で、樹脂材により被覆される。この樹脂材
は、例えば液状に成したエポキシ樹脂等の前駆体をディ
スペンサー等を用いて半導体素子が実装されている回路
基板上面の所定領域に塗布し、これを高温で加熱・硬化
させることによって半導体素子等を被覆するように形成
される。
【０００６】ところで、サーマルヘッドやＬＥＤヘッド
等のヘッド駆動用ＩＣとして用いられる半導体素子には
６４〜１４４個もの多数の出力端子が設けられており、
これらの出力端子は、通常、半導体素子の一辺に沿って
配列される。
【０００７】しかしながら、このような多数の出力端子
を半導体素子の一辺に沿って一列に並べると、隣接する
出力端子間の間隔やこれら出力端子に対応した接続パッ
ド間の間隔が極めて狭くなることから、出力端子と回路
導体とを半田接合する際に両者を接合する半田が隣の半
田と短絡してしまい、半導体素子の接続信頼性を著しく
低下させる欠点を有していた。
【０００８】そこで上記欠点を解消するために、図４に
示す如く回路導体１２上の接続パッド１３を千鳥状（ジ
グザク状）に配列させ、これら接続パッド１３に対応す
る出力端子についても同様の千鳥状（ジグザク状）に配
置させておくことにより、隣接する接続パッド１３−１
３間の間隔や隣接する出力端子間の間隔に余裕を持た
せ、半田同士の短絡を防止することが提案されている。
【０００９】ところが、前記接続パッド１３は、通常、
四角形状に形成されていることから、このような接続パ
ッド１３を千鳥状に配列させると、半導体素子上に樹脂
材の前駆体を塗布した際、該前駆体を半導体素子と回路
基板との間隙から半導体素子の直下領域に流し込もうと
しても、前駆体の流れが隣接する接続パッド１３の最近
接部で接続パッド１３の角部に引っ掛かって止まり、樹
脂材を半導体素子と回路基板との間に良好に充填させる
ことができなかった。その結果、半導体素子と回路基板
との間には大きな気泡が残存することとなり、このよう
な気泡に前駆体を硬化させる際の熱やサーマルヘッドの
使用時の熱などが印加されると、気泡の熱膨張によって
半導体素子の位置ズレや半田接合部の破損が誘発され、
結局、半導体素子の接続信頼性を低下させる欠点が誘発
される。
【００１０】
【課題を解決するための手段】本発明は上記欠点に鑑み
案出されたもので、本発明の半導体素子の実装構造体
は、絶縁基板の上面に、一端部にメッキにより形成され
た接続パッドを有する複数個の回路導体を前記接続パッ
ドが千鳥状となるように被着・配列させるとともに前記
回路導体の接続パッドに半導体素子の端子を導電性接着
材を介してフェースダウンボンディングにて直接接続さ
せ、かつ該半導体素子の外表面を樹脂材で被覆するとと
もに該樹脂材の一部を半導体素子と絶縁基板との間隙に
充填してなる半導体素子の実装構造体であって、前記接
続パッドは、該接続パッドの配列に対して斜め方向（千
鳥方向）に隣接する接続パッド間に平面状の側面を対向
させた状態で千鳥状に配列していることを特徴とする。
【００１１】
【発明の実施の形態】以下、本発明を添付図面に基づい
て詳細に説明する。図１は本発明の一形態にかかる実装
構造体に使用される回路基板の平面図、図２は図１をＸ
方向から見た斜視図、図３は本発明の一形態にかかる実
装構造体の断面図であり、１は絶縁基板、２は回路導
体、３は接続パッド、４は半導体素子、５は端子、６は
半田、７は樹脂材である。
【００１２】前記絶縁基板１は、アルミナセラミックス
やガラス等の電気絶縁性材料から成り、その上面で複数
個の回路導体２や接続パッド３，半導体素子４，樹脂材
７等を支持するようになっている。
【００１３】前記絶縁基板１は、例えばアルミナセラミ
ックスから成る場合、アルミナ，シリカ，マグネシア等
のセラミック原料粉末に適当な有機溶媒、有機溶剤を添
加・混合して泥漿状に成すとともに、これを従来周知の
ドクターブレード法等を採用することによってセラミッ
クグリーンシートを得、しかる後、該セラミックグリー
ンシートに打ち抜き加工法により所定形状となし、これ
を高温（約1600℃）で焼成することによって製作され
る。
【００１４】またこのような絶縁基板１の上面には、複
数個の回路導体２が所定パターンに被着・形成される。
【００１５】前記回路導体２は、例えばサーマルヘッド
に適用する場合、その多くが半導体素子４（ドライバＩ
Ｃ）の端子５より発せられる出力を発熱素子に印加する
給電配線としての作用を為し、例えばアルミニウム等の
金属を従来周知のスパッタリング法やフォトリソグラフ
ィー技術，エッチング技術等を採用することによって絶
縁基板１の上面に所定パターンに被着・形成される。
【００１６】また前記回路導体２の一端部には、金メッ
キやニッケルメッキにより形成された厚み１μｍ〜５μ
ｍの接続パッド３が、回路導体２の配列方向にわたっ
て、例えば３列で千鳥状に配列するようにして被着・形
成される。
【００１７】各々の接続パッド３には、隣接する接続パ
ッド３−３間の最近接部に、互いに対向する一対の平面
状の側面３ａが形成されており、この側面間の領域３ａ
−３ａを介して後述する樹脂材７の前駆体が半導体素子
４と絶縁基板１との間隙に導入される。
【００１８】これらの接続パッド３は、回路導体表面の
半田ぬれ性を向上させて回路導体２の一端部に半導体素
子４の端子５を良好に半田接合させるためのものであ
り、該接続パッド３を前述の金メッキやニッケルメッキ
等で形成しておくことにより、半導体素子４の端子５を
回路導体２の接続パッド３に半田７を介して確実に接続
させることができる。
【００１９】尚、前記接続パッド３を千鳥状に配列する
のは、隣接する接続パッド３，３間の間隔に余裕を持た
せて、これら接続パッド３に接合される半田同士の短絡
を有効に防止するためであり、この千鳥配列の形態は、
本形態の如く３列とする場合に限られるものではなく、
２列であっても、４列以上であっても同様の目的を達成
することができる。
【００２０】このような接続パッド３は従来周知の電界
メッキ法等を採用し、各回路導体２の一端部に金（Ａ
ｕ）やニッケル（Ｎｉ）等の半田ぬれ性が良好な金属を
所定厚みに被着させることによって隣接する接続パッド
３，３の最近接部に対向する一対の側面３ａを設けるよ
うにして形成される。
【００２１】そして、このような接続パッド３や回路導
体２等が設けられている絶縁基板１の上面には半導体素
子４が従来周知のフェースダウンボンディングにて実装
される。
【００２２】前記半導体素子４は、例えばサーマルヘッ
ドに適用する場合、発熱素子の発熱を個別に制御するド
ライバＩＣとしての作用を為し、この場合、矩形状を成
すように形成される半導体素子４の下面には一方の長辺
に沿って６４〜１４４個の多数の出力用端子５が、他方
の長辺側には各種信号用端子やグランド用端子等が４〜
２０個程度設けられ、これらの端子５を絶縁基板上面の
対応する回路導体２に接続パッド３を介して半田接合さ
せることにより半導体素子４が絶縁基板１上に実装され
る。
【００２３】尚、半導体素子下面の一方の長辺に沿って
配列された多数の出力用端子５は、半導体素子４を絶縁
基板上面の所定位置に載置させた際、各端子５が対応す
る接続パッド３に対面するように配置される。従って、
回路導体２の接続パッド３が上述した如く３列で千鳥状
に配列されている場合、出力端子５も接続パッド３と全
く同じピッチで３列の千鳥状に配列されることとなる。
【００２４】そしてこのような半導体素子４はエポキシ
樹脂やシリコン樹脂等から成る樹脂材７によって被覆さ
れる。前記樹脂材７は、半導体素子４を大気中に含まれ
ている水分等の接触による腐食等から保護するためのも
のであり、例えばエポキシ樹脂から成る場合、液状に成
したエポキシ樹脂の前駆体をディスペンサー等を用いて
半導体素子４が実装されている絶縁基板１の上面所定領
域に塗布し、これを１５０〜２００℃の温度で加熱・硬
化させることにより半導体素子４を被覆するようにして
形成される。
【００２５】このとき、半導体素子４の直下に配されて
いる回路導体２の接続パッド３は、隣接する接続パッド
３，３間の最近接部に、対向する側面３ａ，３ａを有し
ているため、半導体素子４上に塗布された樹脂材７の前
駆体は、毛細管現象により、この側面間の領域３ａ−３
ａを介して半導体素子４の中心部に向けて良好に流れ込
むとともに半導体素子４の直下に大量に導入され、その
結果、半導体素子４と絶縁基板１との間に残存する気泡
の量が少なくなる。従って、液状前駆体を硬化させる際
等に外部から熱が印加されても半導体素子４を所定位置
に良好に取着・実装させておくことが可能となり、これ
によって半導体素子の接続信頼性が著しく向上される。
【００２６】尚、隣接する接続パッド３の最近接部に形
成される一対の側面間の間隔３ａ−３ａは１０μｍ〜５
０μｍの範囲内に設定するのが好ましく、この範囲内に
設定しておくことにより樹脂材７の前駆体の粘度が１０
０ポイズ以下の場合に前述の毛細管現象をより良好に発
揮させることができ、樹脂材７の前駆体を半導体素子４
と絶縁基板１との間に極めて良好に充填させることが可
能となる。
【００２７】本発明は上述の形態に限定されるものでは
なく、本発明の要旨を逸脱しない範囲において種々の変
更、改良等が可能である。
【００２８】例えば、上述の形態では３列で千鳥状に配
列する接続パッド３のうち、中央の列の接続パッドを六
角形とし、両側の列の接続パッドを五角形としたが、こ
のような形状に限られるものではなく、隣接する接続パ
ッドの最近接部に互いに対向して配置される一対の側面
が設けられている限り、接続パッドの形状は三角形や四
角形、八角形等であっても構わない。
【００２９】また上述の形態において接続パッド３と回
路導体２との間に、両者間の密着力を高く維持するため
に、従来周知の無電界メッキ法等によってパラジウム
（Ｐｄ）層などを介在させておいても良い。
【００３０】更に上述の形態においては接続パッド３を
単一の金属により形成したが、これに代えて、接続パッ
ド３を２種類以上の金属、例えばＮｉから成る第１接続
パッド上にＡｕから成る第２接続パッドを積層して２層
構造の接続パッド３となしたり、或いは３種類以上の金
属を順次積層した多層構造の接続パッド３となしても良
い。
【００３１】また更に上述の形態において絶縁基板１の
表面がガラスにより形成されている場合、絶縁基板１と
回路導体２との間に窒化珪素（Ｓｉ3 Ｎ4 ）やサイアロ
ン（Ｓｉ−Ａｌ−Ｏ−Ｎ）等から成る絶縁層を０．１μ
ｍ〜０．２μｍ程度の厚みに介在させておけば、回路導
体２を従来周知のエッチング技術等によって形成する際
に絶縁基板表面のガラスが浸食されるのを有効に防止す
ることができ、接続パッド３を回路導体２の表面により
強固に被着させておくことができる。従って絶縁基板１
の表面がガラスにより形成されている場合、絶縁基板１
と回路導体２との間に窒化珪素（Ｓｉ3 Ｎ4 ）やサイア
ロン（Ｓｉ−Ａｌ−Ｏ−Ｎ）等から成る絶縁層を０．１
μｍ〜０．２μｍ程度の厚みに介在させておくことが好
ましい。
【００３２】
【発明の効果】本発明によれば、半導体素子の端子に接
続される接続パッドが、斜め方向（千鳥方向）に隣接す
る接続パッド間に、平面状の側面同士を対向させた状態
で千鳥状に配列されているため、半導体素子を樹脂材で
被覆する際、樹脂材の一部を毛細管現象により対向する
平面状の側面間の領域を介して半導体素子の中心部に向
けて良好に流し込み、半導体素子と絶縁基板との間に残
存する気泡の量を少なくすることができる。従って、樹
脂材に外部から熱が印加されても半導体素子を所定位置
に良好に取着・実装させておくことが可能となり、これ
によって半導体素子の接続信頼性が著しく向上される。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure used for various electronic devices. 2. Description of the Related Art Face-down bonding has been conventionally known as a method for mounting a semiconductor device. A plurality of terminals other than an electronic circuit are provided on the lower surface of the semiconductor element used for the face-down bonding, and these terminals are connected to circuit conductors of a circuit board via a conductive adhesive such as solder. The semiconductor element is mounted by bonding. The surface of the circuit conductor to which the terminals of the semiconductor element are soldered is provided with a connection pad made of gold plating, nickel plating or the like of 1 μm in order to improve the solder wettability.
It is attached to a thickness of about 5 μm, and the terminals of the semiconductor element and the circuit conductor on the circuit board are soldered to each other via the connection pads so that they can be reliably connected to each other. The semiconductor element is coated with a resin material for the purpose of protecting the semiconductor element from corrosion caused by contact with moisture or the like contained in the air. This resin material is applied to a predetermined region of the upper surface of the circuit board on which the semiconductor element is mounted using a dispenser or the like, using a precursor such as a liquid epoxy resin, and heated and cured at a high temperature. It is formed so as to cover elements and the like. A semiconductor element used as a head driving IC such as a thermal head or an LED head is provided with a large number of output terminals of 64 to 144.
These output terminals are usually arranged along one side of the semiconductor device. However, when such a large number of output terminals are arranged in a line along one side of the semiconductor element, the interval between adjacent output terminals and the interval between connection pads corresponding to these output terminals become extremely narrow. In addition, when the output terminal and the circuit conductor are joined by soldering, the solder for joining them is short-circuited with the adjacent solder, which has a disadvantage that the connection reliability of the semiconductor element is significantly reduced. In order to solve the above-mentioned drawback, the connection pads 13 on the circuit conductor 12 are arranged in a zigzag pattern as shown in FIG. 4, and the output terminals corresponding to the connection pads 13 are similarly staggered. By arranging them in a zigzag shape, the adjacent connection pads 13-1
It has been proposed to provide a margin in the space between the three terminals and the space between adjacent output terminals to prevent a short circuit between solders. However, the connection pad 13 is usually
Since such connection pads 13 are arranged in a staggered manner because they are formed in a square shape, when the precursor of the resin material is applied on the semiconductor element, the precursor is applied to the gap between the semiconductor element and the circuit board. , The flow of the precursor stops at the corner of the connection pad 13 at the nearest point of the adjacent connection pad 13, and the resin material flows between the semiconductor element and the circuit board. Could not be filled well. As a result, large bubbles remain between the semiconductor element and the circuit board, and when heat such as curing the precursor or heat during use of the thermal head is applied to such bubbles, the bubbles are removed. The thermal expansion of the semiconductor element causes misalignment of the semiconductor element and breakage of the solder joint,
As a result, a drawback that lowers the connection reliability of the semiconductor device is induced. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and a mounting structure of a semiconductor device according to the present invention is formed on an upper surface of an insulating substrate by plating on one end. A plurality of circuit conductors having connection pads are attached and arranged so that the connection pads are staggered, and the terminals of the semiconductor element are connected to the connection pads of the circuit conductors by face-down bonding via a conductive adhesive. A semiconductor element mounting structure, wherein the semiconductor element is directly connected, and the outer surface of the semiconductor element is covered with a resin material, and a part of the resin material is filled in a gap between the semiconductor element and the insulating substrate. The connection pads are characterized in that they are arranged in a staggered manner such that planar side faces are opposed to connection pads obliquely (in a staggered direction) to the arrangement of the connection pads. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a plan view of a circuit board used for a mounting structure according to one embodiment of the present invention, and FIG.
FIG. 3 is a cross-sectional view of a mounting structure according to one embodiment of the present invention, wherein 1 is an insulating substrate, 2 is a circuit conductor, 3 is a connection pad, 4 is a semiconductor element, 5 is a terminal, Reference numeral 6 denotes a solder, and 7 denotes a resin material. The insulating substrate 1 is made of an electrically insulating material such as alumina ceramics or glass, and has a top surface supporting a plurality of circuit conductors 2, connection pads 3, semiconductor elements 4, resin material 7, and the like. ing. When the insulating substrate 1 is made of, for example, alumina ceramics, an appropriate organic solvent or an organic solvent is added to and mixed with a ceramic raw material powder of alumina, silica, magnesia or the like to form a slurry. A ceramic green sheet is obtained by employing the doctor blade method described above, and then the ceramic green sheet is formed into a predetermined shape by a punching method, and is fired at a high temperature (about 1600 ° C.). On the upper surface of the insulating substrate 1, a plurality of circuit conductors 2 are attached and formed in a predetermined pattern. When the circuit conductor 2 is applied to, for example, a thermal head, most of the circuit conductor 2 is a semiconductor element 4 (driver I).
C) acts as a power supply wiring for applying an output generated from the terminal 5 to the heating element. For example, a metal such as aluminum is applied to the insulating substrate by employing a conventionally known sputtering method, photolithography technology, etching technology, or the like. 1 is adhered and formed in a predetermined pattern on the upper surface of the substrate 1. One end of the circuit conductor 2 has a thickness of 1 μm to 5 μm formed by gold plating or nickel plating.
The m connection pads 3 are attached and formed in a staggered manner, for example, in three rows over the arrangement direction of the circuit conductors 2. Each connection pad 3 is formed with a pair of opposing planar side surfaces 3a at the closest portion between the adjacent connection pads 3-3, and a region 3a between the side surfaces.
The precursor of the resin material 7 described later is introduced into the gap between the semiconductor element 4 and the insulating substrate 1 through the substrate 3a. These connection pads 3 are used to improve the solder wettability of the surface of the circuit conductor so that the terminal 5 of the semiconductor element 4 can be satisfactorily soldered to one end of the circuit conductor 2. Is formed by the above-described gold plating or nickel plating, the terminal 5 of the semiconductor element 4 can be reliably connected to the connection pad 3 of the circuit conductor 2 via the solder 7. The connection pads 3 are arranged in a zigzag pattern so that the space between the adjacent connection pads 3 has a margin so that short-circuiting between the solders connected to the connection pads 3 can be effectively performed. In order to prevent this, the form of this staggered arrangement is
It is not limited to the case of three rows as in this embodiment,
The same purpose can be achieved with two rows or four or more rows. Such connection pads 3 employ a conventionally known electrolytic plating method or the like, and gold (A) is applied to one end of each circuit conductor 2.
u) or a metal having good solder wettability, such as nickel (Ni), is applied to a predetermined thickness to form a pair of side surfaces 3a opposed to the closest portions of the adjacent connection pads 3, 3. You. A semiconductor element 4 is mounted on the upper surface of the insulating substrate 1 on which the connection pads 3 and the circuit conductors 2 are provided by a conventionally known face-down bonding. When the semiconductor element 4 is applied to, for example, a thermal head, the semiconductor element 4 functions as a driver IC for individually controlling the heat generation of the heating elements. In this case, the semiconductor element 4 is formed in a rectangular shape. On the lower surface of the device, a large number of 64-144 output terminals 5 are provided along one long side, and on the other long side, various signal terminals and ground terminals are provided.
Approximately twenty terminals are provided, and these terminals 5 are soldered to the corresponding circuit conductors 2 on the upper surface of the insulating substrate via the connection pads 3 so that the semiconductor element 4 is mounted on the insulating substrate 1. The plurality of output terminals 5 arranged along one long side of the lower surface of the semiconductor element correspond to the respective terminals 5 when the semiconductor element 4 is placed at a predetermined position on the upper surface of the insulating substrate. It is arranged so as to face the connection pad 3. Therefore,
When the connection pads 3 of the circuit conductor 2 are arranged in three rows in a staggered manner as described above, the output terminals 5 are also arranged in three rows in a staggered manner at the same pitch as the connection pads 3. The semiconductor element 4 is covered with a resin material 7 made of epoxy resin, silicon resin or the like. The resin material 7 is for protecting the semiconductor element 4 from corrosion caused by contact with moisture or the like contained in the air. For example, when the resin material 7 is made of an epoxy resin, a liquid epoxy resin precursor is used. It is formed so as to cover the semiconductor element 4 by applying it to a predetermined area on the upper surface of the insulating substrate 1 on which the semiconductor element 4 is mounted by using a dispenser or the like, and heating and curing this at a temperature of 150 to 200 ° C. You. At this time, the connection pad 3 of the circuit conductor 2 disposed immediately below the semiconductor element 4 has opposing side surfaces 3a at the closest part between the adjacent connection pads 3,3. Therefore, the precursor of the resin material 7 applied on the semiconductor element 4 is formed in the region 3a-3 between the side surfaces by a capillary phenomenon.
a, and flows well into the center of the semiconductor element 4 through the a, and is introduced in large quantities immediately below the semiconductor element 4. As a result, the amount of bubbles remaining between the semiconductor element 4 and the insulating substrate 1 is reduced. . Therefore, even when heat is applied from the outside when the liquid precursor is cured or the like, the semiconductor element 4 can be satisfactorily attached and mounted at a predetermined position, thereby significantly improving the connection reliability of the semiconductor element. Be improved. The distance 3a-3a between a pair of side surfaces formed at the closest part of the adjacent connection pad 3 is 10 μm to 5 μm.
It is preferable that the viscosity is set within the range of 0 μm.
In the case of 0 poise or less, the above-mentioned capillary phenomenon can be exhibited more favorably, and the precursor of the resin material 7 is
And the insulating substrate 1 can be filled very well. The present invention is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the gist of the present invention. For example, in the above-described embodiment, among the connection pads 3 arranged in a staggered manner in three rows, the connection pads in the center row are hexagonal, and the connection pads in both rows are pentagonal. The shape of the connection pad may be triangular, quadrangular, octagonal, or the like, as long as a pair of side surfaces arranged opposite to each other are provided at the nearest portion of the adjacent connecting pad. Absent. In the above-described embodiment, a palladium (Pd) layer or the like is interposed between the connection pad 3 and the circuit conductor 2 by a conventionally known electroless plating method or the like in order to maintain a high adhesion between them. You can keep it. In the above embodiment, the connection pad 3 is formed of a single metal. Alternatively, the connection pad 3 may be formed of Au on a first connection pad of two or more metals, for example, Ni. The second connection pads may be stacked to form a connection pad 3 having a two-layer structure, or a connection pad 3 having a multilayer structure in which three or more types of metals are sequentially stacked. In the above embodiment, when the surface of the insulating substrate 1 is formed of glass, silicon nitride (Si 3 N 4 ) or sialon (Si—Al—O) is provided between the insulating substrate 1 and the circuit conductor 2. −N) etc.
When the circuit conductor 2 is interposed at a thickness of about m to 0.2 μm, it is possible to effectively prevent the glass on the surface of the insulating substrate from being eroded when the circuit conductor 2 is formed by a conventionally known etching technique. The pad 3 can be firmly adhered to the surface of the circuit conductor 2. Therefore, the insulating substrate 1
Is formed of glass, the insulating substrate 1
An insulating layer made of silicon nitride (Si 3 N 4 ) or sialon (Si-Al-ON) is
It is preferable to interpose a thickness of about μm to 0.2 μm. According to the present invention, the connection pads to be connected to the terminals of the semiconductor element are arranged such that the flat side surfaces are opposed to each other between the connection pads adjacent to each other in an oblique direction (staggered direction). When the semiconductor element is covered with the resin material, a part of the resin material is favorably directed toward the center of the semiconductor element via a region between the opposed flat side surfaces due to a capillary phenomenon. And the amount of air bubbles remaining between the semiconductor element and the insulating substrate can be reduced. Therefore, even when heat is applied to the resin material from the outside, the semiconductor element can be satisfactorily attached and mounted at a predetermined position, thereby significantly improving the connection reliability of the semiconductor element.
【図面の簡単な説明】
【図１】本発明の一形態にかかる半導体素子の実装構造
体に使用される絶縁基板の要部を示す平面図である。
【図２】図１をＸ方向から見た斜視図である。
【図３】本発明の一形態にかかる実装構造体の断面図で
ある。
【図４】従来の半導体素子の実装構造体に使用される回
路基板の要部を示す平面図である。
【符号の説明】
１・・・絶縁基板
２・・・回路導体
３・・・接続パッド
４・・・半導体素子
５・・・端子
６・・・半田（導電性接着材）
７・・・樹脂材BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a main part of an insulating substrate used for a mounting structure of a semiconductor element according to one embodiment of the present invention. FIG. 2 is a perspective view of FIG. 1 viewed from an X direction. FIG. 3 is a cross-sectional view of a mounting structure according to one embodiment of the present invention. FIG. 4 is a plan view showing a main part of a circuit board used for a conventional semiconductor element mounting structure. [Description of Signs] 1 ... Insulating substrate 2 ... Circuit conductor 3 ... Connection pad 4 ... Semiconductor element 5 ... Terminal 6 ... Solder (conductive adhesive) 7 ... Resin Lumber
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 311 H01L 21/60 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 311 H01L 21/60
Claims (1)
形成された接続パッドを有する複数個の回路導体を前記
接続パッドが千鳥状となるように被着・配列させるとと
もに前記回路導体の接続パッドに半導体素子の端子を導
電性接着材を介してフェースダウンボンディングにて直
接接続させ、かつ該半導体素子の外表面を樹脂材で被覆
するとともに該樹脂材の一部を半導体素子と絶縁基板と
の間隙に充填してなる半導体素子の実装構造体であっ
て、前記接続パッドは、該接続パッドの配列に対して斜
め方向に隣接する接続パッド間に平面状の側面を対向さ
せた状態で千鳥状に配列していることを特徴とする半導
体素子の実装構造体。(57) Claims: 1. A plurality of circuit conductors having connection pads formed by plating on one end thereof are attached on an upper surface of an insulating substrate so that the connection pads are staggered. Align and connect the terminals of the semiconductor element directly to the connection pads of the circuit conductor by face-down bonding via a conductive adhesive, and cover the outer surface of the semiconductor element with a resin material. A mounting structure of the semiconductor element in which a part of the resin material is filled in a gap between the semiconductor element and the insulating substrate, wherein the connection pads are inclined with respect to the arrangement of the connection pads.
A mounting structure for a semiconductor element, wherein the semiconductor element mounting structures are arranged in a staggered manner with planar side surfaces opposed between connection pads adjacent in a direction .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21771598A JP3492919B2 (en) | 1998-07-31 | 1998-07-31 | Semiconductor element mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21771598A JP3492919B2 (en) | 1998-07-31 | 1998-07-31 | Semiconductor element mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000049193A JP2000049193A (en) | 2000-02-18 |
| JP3492919B2 true JP3492919B2 (en) | 2004-02-03 |
Family
ID=16708612
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21771598A Expired - Fee Related JP3492919B2 (en) | 1998-07-31 | 1998-07-31 | Semiconductor element mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3492919B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4510961B2 (en) * | 1999-10-19 | 2010-07-28 | Ｏｋｉセミコンダクタ株式会社 | Optical module |
| JP2002334901A (en) * | 2001-05-08 | 2002-11-22 | Nec Corp | Semiconductor device |
| JP2004349343A (en) | 2003-05-20 | 2004-12-09 | Seiko Epson Corp | Method for manufacturing semiconductor device and electronic device |
| JP5395407B2 (en) * | 2008-11-12 | 2014-01-22 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device for driving display device and manufacturing method of semiconductor integrated circuit device for driving display device |
| JP2011054797A (en) * | 2009-09-02 | 2011-03-17 | Renesas Electronics Corp | Tcp-type semiconductor device |
-
1998
- 1998-07-31 JP JP21771598A patent/JP3492919B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000049193A (en) | 2000-02-18 |
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