JP2005100924A - Switching circuit and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simply constructed switching circuit which provides the precision switching and compensates a relay contact for open failures by employing a switch circuit in which a standard relay having one-make contact structure and an SSR (solid state relay) are parallelly connected. <P>SOLUTION: The switching circuit is provided with a switch driving means 2 which operates the SSR (solid state relay) 4 at the switch-on time and the switch-off time based on driving pulses SD, while conducting the drive control to operate a relay (contact) 5A in the on-intermediate region of switching other than parts of the switch-on time and the switch-off time. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a switching circuit in which an SSR (Solid State Lily) and one make relay (contact) are connected in parallel, and more particularly to a switching circuit that controls an on-time and an off-time that match the period of a drive pulse. .

  Originally, SSR (Solid State Relay) has a feature that it has a long life with respect to switching ON / OFF. On the other hand, a relay (contact point) allows a large current to flow with respect to switching ON. Since the contact resistance of the (contact) is low, there is a feature that power loss is small.

  On the other hand, a switching circuit in which a semiconductor switching element and a relay (contact) are connected in parallel and an AC power supply to be supplied to a load is intermittent is disclosed in “Patent Document 1”. FIG. 11 shows a configuration diagram of a conventional switching circuit. In FIG. 11, the switching circuit 50 is configured by a relay RL having a contact r1 and a contact r2 having different operation timings and a three-terminal thyristor T such as an SCR triac, and controls the thyristor T by the contact r1 that operates first. The contact r2 and the thyristor T operating in parallel are connected in parallel.

  The operation sequence of the contacts r1 and r2 is such that, when the switching circuit 50 is turned on, the contact r1 is made (on) after the contact r1 is made, and when the switching circuit 50 is turned off, the contact r2 is broken (off). Later, the contact r1 breaks.

  When the switching circuit 50 is turned on, the contact r1 is made first, the thyristor T is turned on, and the load current Ir flows from the AC power supply AC via the load L. Subsequently, when the contact r2 is made at the time delay t1, the load current Ir flows to the contact r2, so that the current flowing through the thyristor T becomes equal to or less than the holding current, and the thyristor T enters a cutoff state.

  On the other hand, when the switching circuit 50 is turned off, the contact r2 breaks first, but since the contact r1 is made, the thyristor T is turned on again and the load current Ir flows. However, when the contact r1 breaks at the time delay t2, the thyristor T Is turned off, and the load current Ir is cut off.

  As described above, the conventional switching circuit 50 includes the two contacts r1 and r2 and the thyristor T having different operation timings. After the thyristor T is turned on by the make (on) operation of the contact r1, the thyristor T is connected in parallel. Since the contact r2 is operated to make (ON) and the contact r2 is made to break (OFF), the thyristor T is turned OFF by the break (OFF) operation of the contact r1, so that the switching ON / OFF operation is performed by the thyristor. The order is T on → contact r2 on → contact r2 off → thyristor T off. However, the thyristor T is cut off during the ON period of the contact r2.

  The operation sequence of the contact r2 and the thyristor T avoids arc discharge generated at the contact r2 of the relay when the high-voltage AC power supply AC is turned on / off, and the electric power caused by the load current Ir flowing through the on-resistance of the thyristor T. Loss can be suppressed.

Further, the switching circuit 50 includes a thermal fuse H in series with a parallel circuit of the contact r2 and the thyristor T, and dust or the like adheres to the contact r2 to cause a contact failure (open failure of the contact r2), and a load is applied to the thyristor T. The current Ir flows continuously, and heat is prevented from rising and the temperature rising.
Japanese Patent Publication No. 60-30048

  Although the switching circuit disclosed in “Patent Document 1” can solve the problems of heat generation and contact deterioration, a relay having a special structure with two contacts having different operation timings is necessary, and this leads to an increase in cost. There is a big problem.

  In the switching circuit disclosed in “Patent Document 1”, the relay RL is turned on and the contact r1 is turned on (make), and then the contact r2 is turned on (make) at a time delay t1, and the relay RL is driven off. Since the contact r1 is turned off (break) at a time delay t2 after the contact r2 is turned off (break), switching of equipment (for example, a temperature controller) that requires an accurate on-time (duty ratio) is required. The application has a problem that the on-time of the switching circuit is longer than the on-time of the drive pulse (duty ratio changes), and high-accuracy switching cannot be performed.

  Furthermore, the switching circuit disclosed in "Patent Document 1" requires a thermal fuse that cuts off the load current in order to prevent heat generation due to an open contact failure. There is a problem that the replacement work occurs.

  The present invention has been made to solve such problems, and its purpose is to adopt a switch circuit in which a standard relay having a single make contact configuration and a SSR (solid state relay) are connected in parallel to achieve high-precision switching. Another object of the present invention is to provide a switching circuit having a simple configuration capable of compensating for an open failure of a relay contact.

  In order to solve the above problems, a switching circuit according to the present invention is a switching circuit comprising a switch circuit in which an SSR and a relay are connected in parallel, and a switch driving means for driving the SSR and the relay. When ON and OFF, the SSR is operated, and in the ON intermediate region excluding a part when switching is ON and OFF, the relay is operated, and the ON / OFF cycle of the switch circuit is supplied from the outside. It is characterized by comprising switch driving means for matching the on / off period of the pulse.

  The switching circuit according to the present invention operates the SSR when the switching of the switch circuit is on and off, and operates the relay in the on-intermediate region excluding a part when the switching is on and off. Since it has switch drive means that matches the on / off cycle of the circuit with the on / off cycle of the externally supplied drive pulse, it takes advantage of the characteristics of SSR (Solid State Relay) and relay, and arc discharge of relay contacts In addition, it is possible to realize high-accuracy switching that suppresses heat generation of the SSR and compensation for open failure of the relay contact.

  The switch driving means according to the present invention comprises a delay means for delaying the drive pulse by a predetermined time, a first pulse generating means for generating a first pulse by the delay pulse and the drive pulse supplied from the delay means, A second pulse generating means for generating a second pulse by the first pulse and the driving pulse supplied from the one pulse generating means, and driving the relay with the first pulse from the first pulse generating means; The SSR is driven by the second pulse from the pulse generating means.

  The switch driving means according to the present invention comprises a delay means for delaying a drive pulse by a predetermined time, a first pulse generating means for generating a first pulse of a delay pulse and a drive pulse supplied from the delay means, and a first pulse generation A first pulse supplied from the first means and a second pulse generating means for generating a second pulse of the drive pulse, driving the relay with the first pulse from the first pulse generating means, and from the second pulse generating means Since the SSR is driven by the second pulse, when the switching is on, the SSR is turned on and then the relay (contact) is turned on (make). In the middle region of switching, the SSR is turned off and the relay (contact) is turned on. Keep on (make), and when switching off, turn on SSR, turn off relay (contact), then turn off SSR It can be.

  Furthermore, the second pulse generating means according to the present invention outputs a single pulse for a predetermined time using the rising edge of the first pulse as a trigger, and a single pulse for a predetermined time using the falling edge of the drive pulse as a trigger. The time interval from the rising edge of the first single pulse to the falling edge of the second single pulse is equal to the pulse width of the drive pulse.

  The second pulse generating means according to the present invention outputs a single pulse for a predetermined time using the rising edge of the first pulse as a trigger, and outputs a single pulse for a predetermined time using the falling edge of the drive pulse as a trigger. In addition, since the time interval from the rising edge of the first single pulse to the falling edge of the second single pulse is equal to the pulse width of the driving pulse, switching on and off can be accurately set by the SSR. it can.

  The switch driving means according to the present invention includes a first delay means for delaying the drive pulse by a predetermined time, and a logical product means for outputting a logical product pulse of the first delay pulse and the drive pulse supplied from the first delay means. And a second delay means for delaying the AND pulse supplied from the AND means by the same amount as a predetermined time, and an exclusive OR pulse of the second delay pulse and the AND pulse supplied from the second delay means is output. And an exclusive OR means for driving the relay with an AND pulse from the AND means and driving an SSR with an exclusive OR pulse from the exclusive OR means.

  The switch driving means according to the present invention includes a first delay means for delaying the drive pulse by a predetermined time, a logical product means for outputting a logical product pulse of the first delay pulse and the drive pulse supplied from the first delay means, A second delay means for delaying the logical product pulse supplied from the logical product means by the same time as the predetermined time, and an exclusive for outputting an exclusive logical sum pulse of the second delay pulse and the logical product pulse supplied from the second delay means. Logical OR means, and the relay is driven by the logical product pulse from the logical product means and the SSR is driven by the exclusive logical sum pulse from the exclusive logical sum means. After that, the relay (contact) is turned on (make), and in the on-intermediate region of switching, the SSR is turned off and the relay (contact) is kept on (make). During off, can the After SSR ON is not a relay (contact) from OFF (break), turn off the SSR.

  Further, the exclusive OR means according to the present invention outputs one exclusive OR pulse at the rising edge and falling edge of the AND pulse, and two from the rising edge of the first exclusive OR pulse. The time interval until the fall of the exclusive OR pulse of the eye is equal to the pulse width of the drive pulse.

  The exclusive OR means according to the present invention outputs one exclusive OR pulse at the rising edge and falling edge of the AND pulse, and outputs the second one from the rising edge of the first exclusive OR pulse. Since the time interval until the fall of the exclusive OR pulse is equal to the pulse width of the drive pulse, switching on and off can be accurately set by the SSR.

  The SSR according to the present invention according to the present invention is characterized by including a semiconductor switching element such as a thyristor, a triac, a transistor, or a MOSFET.

  Since the SSR according to the present invention includes a semiconductor switching element such as a thyristor, a triac, a transistor, or a MOSFET, it is possible to perform an on / off operation without arc discharge in high voltage switching.

  Furthermore, the relay according to the present invention is characterized in that it has one make relay contact having a normal break contact configuration.

  Since the relay according to the present invention includes a single make relay contact having a normal break contact configuration, an on-characteristic with no heat generation can be realized with a standard relay.

  A switching circuit driving method according to the present invention is a switching circuit driving method comprising a switch circuit in which an SSR and a relay are connected in parallel, and a switch driving means for driving the SSR and the relay, wherein the driving pulse is transmitted. A step S1 for generating a first delayed pulse delayed by a predetermined time, a step S2 for outputting a logical product pulse of the first delayed pulse and the drive pulse, and a second delayed pulse obtained by delaying the logical product pulse by the predetermined time. Step S3 to be generated, Step S4 to generate an exclusive OR pulse of the second delay pulse and the AND pulse, Step S5 to drive the SSR with the exclusive OR pulse, and Step to drive the relay with the AND pulse And S6.

  The switching circuit drive method according to the present invention includes a step S1 for generating a first delay pulse obtained by delaying a drive pulse by a predetermined time, a step S2 for outputting a logical product pulse of the first delay pulse and the drive pulse, and a logical product. Step S3 for generating a second delay pulse obtained by delaying the pulse by a predetermined time, Step S4 for generating an exclusive OR pulse of the second delay pulse and the AND pulse, and driving the SSR with the exclusive OR pulse Step S5 and step S6 for driving the relay with the AND pulse, so that the arc discharge of the relay (contact point) is prevented by turning on the SSR with the pulse width of the delay time when switching on / off. In other switching-on areas, the relays (contacts) are turned on to prevent heat generation due to on-resistance, and It may incorporate switching circuit connected in parallel to chromatography (contact) to the various devices.

  The switching circuit according to the present invention operates the SSR when the switching of the switch circuit is on and off, and operates the relay in the on-intermediate region excluding a part when the switching is on and off. Since it has switch drive means that matches the on / off cycle of the circuit with the on / off cycle of the externally supplied drive pulse, it takes advantage of the characteristics of SSR (Solid State Relay) and relay, and arc discharge of relay contacts In addition, it is possible to realize high-accuracy switching that suppresses heat generation of the SSR and compensation for open failure of the relay contact, and it is possible to improve convenience with a simple configuration.

  The switch driving means according to the present invention comprises a delay means for delaying the drive pulse by a predetermined time, a first pulse generating means for generating a first pulse by the delay pulse and the drive pulse supplied from the delay means, A second pulse generating means for generating a second pulse by the first pulse and the driving pulse supplied from the one pulse generating means, and driving the relay with the first pulse from the first pulse generating means; Since the SSR is driven by the second pulse from the pulse generating means, when switching is on, the relay (contact) is turned on (make) after turning on the SSR, and the SSR is turned off in the on-intermediate region of switching. (Contact) is kept on (make), and when switching is turned off, the SSR is turned on and then the relay (contact) is turned off (break). R can be turned off, arc discharge of the relay (contact) generated when switching is turned on / off can be prevented, heat generation of SSR generated in the on-intermediate region of switching can be prevented, and relay (contact) Even if an open failure occurs, heat generation due to the on-resistance of the SSR can be prevented.

  Furthermore, the second pulse generating means according to the present invention outputs a single pulse for a predetermined time using the rising edge of the first pulse as a trigger, and a single pulse for a predetermined time using the falling edge of the drive pulse as a trigger. Since the time interval from the rising edge of the first single pulse to the falling edge of the second single pulse is equal to the pulse width of the driving pulse, switching on and off is accurately set by the SSR. Therefore, high-accuracy switching that matches the cycle of the drive pulse can be performed.

  The switch driving means according to the present invention includes a first delay means for delaying the drive pulse by a predetermined time, and a logical product means for outputting a logical product pulse of the first delay pulse and the drive pulse supplied from the first delay means. And a second delay means for delaying the AND pulse supplied from the AND means by the same amount as a predetermined time, and an exclusive OR pulse of the second delay pulse and the AND pulse supplied from the second delay means is output. And the SSR is driven by the exclusive OR pulse from the exclusive OR means, and at the time of switching on, the SSR is driven. After turning on the relay, the relay (contact) is turned on (make). In the middle region of switching, the SSR is turned off and the relay (contact) is kept on (make). When ching is turned off, the SSR can be turned off after the SSR is turned on and then the relay (contact) is turned off (break). This prevents arcing of the relay (contact) that occurs when switching is turned on / off. In addition, it is possible to prevent heat generation of the SSR generated in the on-intermediate region of switching, and to prevent heat generation due to the ON resistance of the SSR even if an open failure of the relay (contact) occurs.

  Further, the exclusive OR means according to the present invention outputs one exclusive OR pulse at the rising edge and falling edge of the AND pulse, and two from the rising edge of the first exclusive OR pulse. Since the time interval until the fall of the exclusive OR pulse of the eye is equal to the pulse width of the drive pulse, switching on and off can be set accurately with the SSR, and the high precision that matches the cycle of the drive pulse Switching can be performed.

  In addition, the SSR according to the present invention according to the present invention includes a semiconductor switching element such as a thyristor, triac, transistor, or MOSFET, and therefore can perform an on / off operation without arc discharge in high voltage switching, The switching circuit can be incorporated in various devices.

  Furthermore, since the relay according to the present invention has a one-make relay contact with a normal break contact configuration, it is possible to realize an on-characteristic that does not generate heat with a standard relay, and a variety of switching circuits with a simple configuration. Can be built in.

  The switching circuit drive method according to the present invention includes a step S1 for generating a first delay pulse obtained by delaying a drive pulse by a predetermined time, a step S2 for outputting a logical product pulse of the first delay pulse and the drive pulse, Step S3 for generating a second delayed pulse obtained by delaying the logical product pulse by the same time as a predetermined time, Step S4 for generating an exclusive logical sum pulse of the second delayed pulse and the logical product pulse, and SSR by the exclusive logical sum pulse. The step S5 for driving the relay and the step S6 for driving the relay with the logical product pulse are provided. Therefore, when switching is turned on / off, the SSR is turned on with the pulse width of the delay time, thereby causing arc discharge of the relay (contact). In other switching-on areas, the relay (contact point) is turned on to prevent heat generation due to the on-resistance, and SS A relay can be incorporated in various devices switching circuit connected in parallel to (contacts), to achieve switching of high accuracy can be made compact device.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the present invention prevents high voltage arc discharge by executing by switching the SSR of the semiconductor switching element on / off at the rising and falling of the switching, and in the ON region other than the rising or falling of the switching, The present invention provides a switching circuit in which an SSR (solid state relay) and a relay (contact) are connected in parallel by preventing heat generation by turning on (making up) the (contact).

  FIG. 1 is a basic block diagram of an embodiment of a switching circuit according to the present invention. In FIG. 1, a switching circuit 1 includes a switch drive unit 2, a switch circuit 3 in which an SSR (solid state relay) 4 and a relay (contact) 5A are connected in parallel. The switch circuit 3 is connected to the external load 6 and the power source 7 at the output terminals A and B, and intermittently switches the load current IL supplied from the power source 7 to the load 6 by switching on / off.

  The switch driving means 2 operates based on the drive pulse SD, operates the SSR 4 when switching is on and off, and the on-intermediate region excluding a part at the time of switching on and off is a relay ( The contact control 5A is operated, and drive control is executed to make the on / off cycle of the switch circuit 3 coincide with the on / off cycle of the drive pulse SD.

  When the SSR (Solid State Relay) 4 is turned on, the SSR current ISR flows to the SSR 4, and when the relay (contact) 5A is turned on (make), the relay contact current IRY flows to the relay (contact) 5A and the load current IL Become.

  FIG. 2 is a diagram related to an embodiment of the drive pulse and load current according to the present invention. (A) shows the drive pulse SD waveform, (b) shows the SSR current ISR waveform, (c) shows the relay contact current IRY waveform, and (d) shows the load current IL waveform. (A) When the switch driving means 2 drives the SSR (solid state relay) 4 to be turned on (switching on time) after a predetermined delay time TD from the rising edge of the driving pulse SD in the figure, SSR (solid state relay) 4 is turned on and (b) the SSR current ISR shown in the figure flows for a certain time (e.g., corresponding to the delay time TD), and then enters the off state.

  Further, when the switch driving means 2 drives on a relay (winding) 5B described later after a predetermined delay time TD from the rise of the drive pulse SD, the relay (contact) 5A is turned on with a delay of the operation time (make: broken line display). Then, the relay contact current IRY shown in FIG.

  Due to the delay of the operation time of the relay (contact) 5A, the relay (contact) 5A is turned on (make: broken line display) in a state where the SSR current ISR flows and the voltage across the SSR 4 is reduced to the SSR on-voltage. Therefore, no arc discharge (spark) occurs between the contacts.

  On the other hand, when the relay (contact) 5A is in the on (make) state, the resistance value between the contacts is sufficiently smaller than the on-resistance value of the SSR 4, so that almost all of the load current IL flows to the relay (contact) 5A side and the relay contact Even if the SSR current ISR flows even though the SSR 4 is in the on state, the current IRY is in a state where only a slight amount flows (the Tα period indicated by hatching).

  In the on-intermediate region where the relay contact current IRY flows when the relay (contact) 5A is on (make), the SSR4 is off, the resistance value between the contacts is sufficiently small, and the resistance value between the relay contact current IRY and the contact Therefore, the SSR on-resistance and heat generation due to the SSR current ISR do not become a problem.

  When the switch driving means 2 drives the SSR (solid state relay) 4 to be turned on again, the SSR (solid state relay) 4 is turned on and (b) the SSR current ISR shown in FIG. (Corresponding to TD) is applied to enter an off state (switching off time).

  At the same time when the SSR (solid state relay) 4 is turned on again, a relay (winding) 5B, which will be described later, is turned off, but the relay (contact) 5A is turned off (break: solid line display) after a return time. Become.

  The return time of the relay (contact point) 5A is almost the same because the SSR 4 is in the ON state and the SSR current ISR flows, but the resistance value between the contacts of the relay (contact point) 5A is sufficiently smaller than the ON resistance value of the SSR 4 Load current IL flows as relay contact current IRY, and SSR current ISR hardly flows (Tβ period indicated by hatching).

  When the relay (contact point) 5A is turned off (break: solid line display), the SSR 4 that is already turned on is turned off after the SSR current ISR flows. It should be noted that the time from when the SSR (solid state relay) 4 is turned on to when the switching is turned off is the time from when the relay (winding) 5B described later is turned off to when the relay (contact) 5A is turned off (break). It is set to be longer than the time Tβ so that the SSR (solid state relay) 4 is turned off after the relay (contact point) 5A is turned off (break).

  Even at the time of switching off, the relay (contact) 5A is in an off (break) state when the SSR (solid state relay) 4 is on and the voltage across the SSR 4 is reduced to the on voltage of the SSR 4. Therefore, no arc discharge (spark) occurs between the contacts.

  (D) The load current IL shown in the figure is the sum of the SSR current ISR shown in (b) and the relay contact current IRY shown in (c) (IL = ISR + IRY). Is controlled so as to coincide with the pulse width T1ON of the drive pulse SD. Note that the switch driving means 2 can accurately match the period from on to off of the load current IL with T2ON even when the pulse width of the drive pulse SD becomes T2ON.

  In addition, as shown in FIG. 5B, since the ON period of the SSR (solid state relay) 4 is limited to a short period when the switching is ON and OFF, an open failure occurs in the relay (contact) 5A due to dust or the like. Even if the SSR occurs, the SSR current ISR flowing through the SSR (solid state relay) 4 is limited to a short period, and the heat generated by the SSR current ISR is suppressed, and the open failure of the relay (contact) 5A can be compensated. it can.

  Furthermore, the switch circuit 3 in which the SSR (Solid State Relay) 4 and the relay (contact) 5A are connected in parallel prevents arc discharge (sparking) of the relay (contact) 5A in switching and SSR (Solid State Relay). Since heat generation due to the on-resistance of 4 can be suppressed, it can be integrated in various devices including the switch driving means 2.

  As described above, the switching circuit 1 according to the present invention operates the SSR 4 when the switching of the switch circuit 3 is on and off, and the on-intermediate region excluding a part when the switching is on and off, Since the switch drive means 2 for operating the relay (contact point) 5A and matching the ON / OFF cycle of the switch circuit 3 with the ON / OFF cycle of the drive pulse SD supplied from the outside, the SSR (Solid State Relay) is provided. ) And relay characteristics, high-accuracy switching that suppresses arc discharge of the relay contact 5A and heat generation of the SSR 4 and compensation for open failure of the relay contact 5A can be realized, and the convenience is improved with a simple configuration. be able to.

  FIG. 3 is a block diagram showing the principal part of one embodiment of the switch driving means according to the present invention. In FIG. 3, the switch drive means 2 includes a delay means 8, a first pulse generation means 9, a second pulse generation means 10, and a relay drive circuit 11.

  The delay means 8 generates a delay pulse PD obtained by delaying the drive pulse SD by a predetermined delay time TD, and supplies the delay pulse PD to the first pulse generation means 9.

  The first pulse generation means 9 generates a first pulse PF generated from the drive pulse SD and the delay pulse PD supplied from the delay means 8, and the first pulse PF is generated as the second pulse generation means 10 and the relay drive circuit. 11 is provided. The first pulse generation means 9 calculates the logical product of the drive pulse SD and the delay pulse PD, and generates the first pulse PF as the logical product pulse.

  The second pulse generation means 10 generates a second pulse PS generated from the drive pulse SD and the first pulse PF provided from the first pulse generation means 9, and the second pulse PS generates an SSR (solid state signal). Relay 4 is driven.

  The second pulse generation means 10 uses a single pulse having a predetermined delay time (pulse width = delay time TD) triggered by the rising edge of the first pulse PF and a predetermined delay time (pulse) triggered by the falling edge of the drive pulse SD. A second pulse PS consisting of two single pulses (one-shot pulse) of a single pulse of width = delay time TD is generated, and SSR (solid state relay) 4 of the switch circuit 3 is generated by the second pulse PS. Is turned on / off.

  The relay drive circuit 11 is constituted by a drive circuit including a relay (winding) 5B, which will be described later. By driving the relay (winding) 5B with the first pulse PF supplied from the first pulse generating means 9, the relay drive circuit 11 is switched. The relay (contact) 5A of the circuit 3 is turned on / off.

  FIG. 4 is a waveform diagram of each part of the embodiment of the switch driving means according to the present invention. The waveform diagrams represent the waveform diagrams SD, PD, PF, PS of the respective parts of the switch driving means 2 shown in FIG. IRY and ISR represent currents flowing through the relay (contact point) 5A and the SSR (solid state relay) 4. (A) The figure shows the drive pulse SD waveform, (b) The figure shows the delayed pulse PD waveform, (c) The figure shows the first pulse PF waveform, (d) The figure shows the relay contact current IRY waveform, (e) The figure shows the second pulse. The PS waveform, (f) shows the SSR current ISR waveform.

  (A) The drive pulse SD shown in the figure is composed of a plurality of cycles in which the ON period T1ON and the OFF period T1OF are one cycle, the ON period T2ON and the OFF period T2OF are one cycle, and any ON period and OFF period are one cycle. This is a pulse train.

  (B) The delay pulse PD shown in the figure is a pulse in which the drive pulse SD is delayed by a predetermined delay time TD, the ON period T1ON, the OFF period T1OF is one cycle, the ON period T2ON, the OFF period T2OF is one cycle,. It is.

  (C) The first pulse PF shown in the figure is composed of a logical product pulse of the drive pulse SD and the delay pulse PD, the rise is the same as the rise of the delay pulse PD, and the fall is the same as the fall of the drive pulse SD. A pulse having a delay time TD shorter than the ON period T1ON is generated.

  (D) The relay contact current IRY shown in the figure drives on a relay (winding) 5B, which will be described later, at the rising edge of the first pulse PF, and drives off the relay (winding) 5B at the falling edge of the first pulse PF. As a result, the relay (contact) 5A turns on (makes) with a delay of the contact operating time TL1 from the rising edge of the first pulse PF, and the relay (contact) 5A is delayed with the contact return time TL2 from the falling edge of the first pulse PF. By turning off (breaking), the load current IL flows as an ON intermediate region and then stops.

  (E) The second pulse PS shown in the figure generates a single pulse whose pulse width is equal to the delay time TD triggered by the rising edge of the delay pulse PD, and has a pulse width delayed by the falling edge of the drive pulse SD as a trigger. Generate two single pulses of a single pulse equal to TD.

  The second pulse PS generates a single pulse triggered by the rising edge of the delay pulse PD, and generates a single pulse whose pulse width is equal to the delay time TD triggered by the falling edge of the drive pulse SD. The time interval TON from the rising edge of the single pulse to the falling edge of the driving pulse SD as the trigger to the falling edge of the single pulse whose pulse width is equal to the delay time TD is equal to the pulse width T1ON of the driving pulse SD. become.

  (F) The SSR current ISR shown in the figure is driven by two single pulses of the second pulse PS, the current flows at the rising edge of the first single pulse, and the current flows at the falling edge of the first single pulse. At the same time, the current flows at the rising edge of the second single pulse, and the current stops at the falling edge of the second single pulse.

  The SSR current ISR flows at the rising edge of the first single pulse and continues for the time interval of the delay time TD. However, the relay contact current IRY is the contact operating time TL1 from the rising edge of the first single pulse. Since the contact resistance (ON resistance) of the relay (contact) 5A is sufficiently smaller than the ON resistance of SSR4, the time interval excluding the contact operating time TL1 in the time interval of the delay time TD (hatched display = TD−TL1) ) Means that the SSR current ISR hardly flows even though the SSR 4 is operating (ON).

  On the other hand, the SSR current ISR continues at the time interval of the delay time TD with the current flowing at the rise of the second single pulse, but the relay contact current IRY is only the contact return time TL2 from the rise of the second single pulse. Since the operation is stopped with a delay, the SSR current ISR hardly flows during the contact return time TL2 (indicated by hatching) in the time interval of the delay time TD even though the SSR4 is operating (ON).

  As described above, the SSR 4 of the switch circuit 3 is turned on for the time interval (2TD) of the delay time TD at the time of switching on and off (actual on time = TL1 + TD−TL2). The heat generated by the SSR current ISR flowing through the on-resistance can be suppressed sufficiently low.

  Further, the relay contact current IRY of the switch circuit 3 turns on / off the relay (contact) 5A in a state where the SSR current ISR flows and the voltage between the relay (contact) 5A is low, so the voltage between the switch circuits 3 is high. However, it is possible to suppress arc discharge (spark) that occurs when the relay (contact point) 5A is turned on / off.

  Further, since the time interval TON from ON to OFF of the SSR 4 can be made coincident with the pulse width T1ON of the drive pulse SD, the switching of the switch circuit 3 is made coincident with the pulse width T1ON to perform highly accurate switching. Can do.

  Even if dust or the like adheres between the contacts of the relay (contact) 5A and a contact failure (normally, contact break state) occurs, the SSR 4 only has a delay time TD (= 2TD) that is twice the ON time of the SSR. Since the current ISR is not passed, it is possible to suppress the heat generated by the SSR current ISR flowing through the on-resistance of the SSR 4.

  As described above, the switch driving means 2 according to the present invention has the delay means 8 for delaying the drive pulse SD by the predetermined time TD, and the first pulse PF by the delay pulse PD and the drive pulse SD supplied from the delay means 8. A first pulse generating means 9 for generating, and a second pulse generating means 10 for generating a second pulse PS by the first pulse PF and the drive pulse SD supplied from the first pulse generating means 9. Since the relay (winding) 5B is driven by the first pulse PF from the generating means 9 and the SSR 4 is driven by the second pulse PS from the second pulse generating means 10, the SSR 4 is turned on when switching is on. The relay (contact) 5A is turned on (make) and the SSR4 is turned off and the relay (contact) 5A is kept on (make) in the middle region of switching. Sometimes, after turning on the SSR 4 and then turning off (breaking) the relay (contact point) 5A, the SSR 4 can be turned off, preventing arc discharge of the relay (contact point) 5A that occurs when switching on / off, Heat generation of the SSR 4 generated in the switching ON intermediate region can be prevented, and heat generation due to the ON resistance of the SSR 4 can be prevented even if an open failure of the relay (contact) 5A occurs.

  The second pulse generation means 10 according to the present invention outputs a single pulse of a predetermined time TD using the rising edge of the first pulse PF as a trigger, and also uses the falling edge of the drive pulse SD as a trigger for a predetermined time. Since a single pulse of TD is output and the time interval TON from the rising edge of the first single pulse to the falling edge of the second single pulse is equal to the pulse width T1ON of the driving pulse SD, The off state can be accurately set by the SSR 4 and high-accuracy switching that matches the cycle of the drive pulse SD can be performed.

  FIG. 5 is a circuit diagram of an embodiment of the switch driving means according to the present invention. In FIG. 5, the switch driving means 12 is an example of hardware, and includes a delay circuit 13, an AND gate 14, a monostable multivibrator 15, a monostable multivibrator 16, an OR gate 17, transistors Q1 and Q2, relays (windings). Line) 5B is provided.

  In contrast to FIG. 3, the delay circuit 13 composed of the resistor R and the capacitor C generates the delay means 8, the AND gate 14 generates the first pulse generation means 9, and a single pulse (one-shot pulse) having a pulse width TD. The monostable multivibrator 15 and the monostable multivibrator 16, and the OR gate 17 for synthesizing (or logically) the single pulse from the monostable multivibrator 15 and the single pulse from the monostable multivibrator 16 is a second pulse generating means. 10, the transistor Q1 and the relay (winding) 5B correspond to the relay drive circuit 11. The transistor Q2 drives a phototriac, a phototransistor, a photodiode, and the like that constitute the input circuit of the SSR4.

  A relay (winding) 5B shown in FIG. 5 is paired with a relay (contact) 5A of the switching circuit 3 shown in FIGS. 1 and 3, and a current flows through the relay (winding) 5B. 4 (d), the relay (contact) 5A is turned on (makes) with a delay of the contact operating time TL1 shown in FIG. 4 (d), and the current of the relay (winding) 5B is stopped, so that FIG. The relay (contact) 5A is turned off (breaks) with a delay of the indicated contact return time TL2.

  In addition, the relay composed of the relay (contact) 5A and the relay (winding) 5B is in a state where the relay (contact) 5A is in a break (off) state when no current flows through the relay (winding) 5B. When flowing, the relay (contact) 5A is configured by a standard relay having one make relay contact of a normal break contact configuration in which the make (ON) state is set.

  FIG. 6 is a block diagram showing the principal part of another embodiment of the switch driving means according to the present invention. In FIG. 6, the switch driving means 18 includes a first delay means 19, a logical product means 20, a second delay means 21, an exclusive OR means 22, and a relay drive circuit 23.

  The first delay means 19 generates a first delay pulse SD1 obtained by delaying the drive pulse SD by a predetermined delay time TD, and supplies the first delay pulse SD1 to the AND means 20.

  The logical product means 20 calculates the logical product of the drive pulse SD and the first delay pulse SD1 supplied from the first delay means 19 to generate a logical product pulse SAD. The logical product pulse SAD is converted into the second delay means 21, The exclusive ethical means 22 and the relay drive circuit 23 are supplied.

  The second delay means 21 generates a second delay pulse SD2 obtained by delaying the logical product pulse SAD supplied from the logical product means 20 by the delay time TD, and supplies the second delay pulse SD2 to the exclusive ethics means 22. .

  The exclusive ethical sum means 22 calculates the exclusive logical sum of the logical product pulse SAD supplied from the logical product means 20 and the second delayed pulse SD2 supplied from the second delay means 21 to obtain two one-shots. An exclusive OR pulse SEX that is a pulse is generated, and an SSR (solid state relay) 4 of the switch circuit 3 is turned on / off by the exclusive OR pulse SEX.

  The relay drive circuit 23 is constituted by a drive circuit including a relay (winding) 5B described later, and the switch circuit 3 is driven by driving the relay (winding) 5B with an AND pulse SAD supplied from the AND means 20. The relay (contact) 5A is turned on / off.

  FIG. 7 is a waveform diagram of each part of the embodiment of the switch driving means according to the present invention. The waveform diagrams show the waveform diagrams SD, SD1, SAD, SD2, SEX of the respective parts of the switch driving means 18 shown in FIG. IRY and ISR represent currents flowing through the relay (contact point) 5A and the SSR (solid state relay) 4. (A) shows the drive pulse SD waveform, (b) shows the first delayed pulse SD1 waveform, (c) shows the AND pulse SAD waveform, (d) shows the relay contact current IRY waveform, and (e) shows the first waveform. 2 delay pulse SD2 waveform, (f) figure shows exclusive OR pulse SEX waveform, (g) figure shows SSR current ISR waveform.

  (A) The drive pulse SD shown in the figure has a plurality of cycles in which an ON period T1ON and an OFF period T1OF are one cycle, an ON period T2ON and an OFF period T2OF are one cycle, and an arbitrary ON period and an OFF period are one cycle. This is a pulse train.

  (B) The first delay pulse SD1 shown in the figure includes an ON period T1ON in which the drive pulse SD is delayed by a predetermined delay time TD, an OFF period T1OF in one cycle, an ON period T2ON, an OFF period T2OF in two cycles,. Pulse.

  (C) The logical product pulse SAD shown in the figure calculates the logical product of the drive pulse SD and the first delay pulse SD1, the rise is the same as the rise of the first delay pulse SD1, and the fall is the fall of the drive pulse SD. A pulse having an on period shorter than T1ON by a delay time TD is generated.

  (D) The relay contact current IRY shown in the figure is a result of driving the relay (winding) 5B on at the rise of the AND pulse SAD and turning off the relay (winding) 5B at the falling of the AND pulse SAD. Relay (contact) 5A turns on (makes) with a delay of contact operation time TL1 from the rise of AND pulse SAD, and relay (contact) 5A turns off with a contact return time TL2 after the fall of AND pulse SAD (Break) causes the load current IL to flow as an on-intermediate region and then stops.

  (E) The second delay pulse SD2 shown in the figure delays the AND pulse SAD by the delay time TD, and generates a pulse having the same ON period as the AND pulse SAD (which is shorter than the ON period T1ON by the delay time TD). .

  (F) The exclusive OR pulse SEX shown in the figure is obtained by calculating the exclusive OR of the AND pulse SAD shown in (c) and the second delay pulse SD2 shown in (e). Two single pulses (one-shot pulses) each having a pulse width of delay time TD are generated at the rising edge and the falling edge.

  Note that exclusive OR means that when both two inputs are at the same logic level (for example, H level or L level), the L level is output and the two inputs are at different logic levels (for example, H level). And L level), the output is H level.

  In addition, since a single pulse (one-shot pulse) generated at the falling edge of the AND pulse SAD has a delay time TD, 2 pulses from the rising edge of the first single pulse (exclusive OR pulse). The time interval (TON) until the fall of the first single pulse (exclusive OR pulse) is longer than the pulse width of the AND pulse SAD by the delay time TD, and the pulse width of the drive pulse SD (ON period T1ON) ).

  By driving the SSR (solid state relay) 4 with two one-shot pulses of the exclusive OR pulse SEX, the SSR current ISR flowing through the SSR (solid state relay) 4 is changed in pulse width (ON period TON). (= ON period T1ON) can be limited (set) only to two times between the delay time TD at the rising edge and between the delay time TD until the falling edge.

  (G) The SSR current ISR shown in the figure flows corresponding to the pulse width TD of the two one-shot pulses shown in (f), but the first single pulse (exclusive OR pulse) width TD Since the relay (contact) 5A is turned on (makes) after the contact operating time TL1 from the rise of the relay, the relay contact current IRY dominates and does not flow regardless of the SSR4 being turned on (the hatched line after the contact operating time TL1) Part).

  Also, since the SSR current ISR continues to flow from the rise of the second single pulse (exclusive OR pulse) width TD to the contact return time TL2, the relay contact current IRY continues to flow, so that the SSR4 is also in the ON state. Regardless, the relay contact current IRY dominates and does not flow (shaded portion of the contact return time TL2), flows after the contact return time TL2, and stops at the single pulse width TD.

  During a period corresponding to the pulse width (T1ON) of the drive pulse SD, the load current IL flowing through the load 6 is the sum of the SSR current ISR and the relay contact current IRY (IL = ISR + IRY), but first the SSR4 is turned on. When the SSR current ISR flows and the voltage across the switch circuit 3 decreases to the ON voltage of the SSR4, the relay (contact) 5A is turned on (make), the relay contact current IRY flows, and the relay contact current IRY SSR4 is turned off after.

  Subsequently, while the relay contact current IRY is flowing, the SSR 4 is turned on again, and while the SSR 4 is in the on state, the relay (contact) 5A is turned off (break), and the SSR current ISR flows.

  Thereafter, at the time corresponding to the fall of the drive pulse SD, the SSR 4 is turned off, the SSR current ISR is stopped, and the load current IL is stopped.

  That is, SSR4 is on (SSR current ISR flows) → relay (contact) 5A is on (relay contact current IRY flows: SSR current ISR stops) → SSR4 off (relay contact current IRY continues to flow) → relay (contact ) 5A ON (Relay contact current IRY continues to flow) → SSR4 ON again (Relay contact current IRY continues to flow) → Relay (contact) 5A OFF (Relay contact current IRY stops and SSR current ISR Flow) → SSR 4 off (SSR current ISR is stopped).

  Accordingly, when the relay (contact) 5A at the time of switching on / off is turned on (make) / off (break), the SSR4 is already in the on state, and the voltage between the contacts of the relay (contact) 5A is on. Since the voltage is reduced, arc discharge (spark) is not generated, and contact wear can be avoided.

  On the other hand, in the switching on-intermediate region excluding the switching on / off time, the SSR 4 is in the off state and only the relay (contact) 5A is in the on (make) state, so the contact resistance (on resistance value) of the contact is Is extremely small and the voltage drop is small, so that generation of heat can be avoided.

  Further, since the on period of the SSR 4 is two short periods at the time of switching on / off, the SSR current ISR flows even if dust or the like adheres between the contacts of the relay (contact) 5A and an open failure occurs. Since the period is only the ON period of the SSR 4, heat generation due to the ON resistance and the SSR current ISR can be avoided.

  By avoiding arc discharge of the relay (contact) 5A and avoiding heat generation of the ON resistance of the SSR 4, the switch circuit 3 in which the relay (contact) 5A and the SSR 4 are connected in parallel can be incorporated in various devices.

  4 and 7, the pulse width T1ON of the drive pulse SD has been described, but the same applies to any pulse width of the drive pulse SD.

  Further, the switch driving means 2 and the switch driving means 18 may be configured by hardware, or may be configured by using a microprocessor and software. When software is used, since the pulse width of the drive pulse can be recognized in advance, it is possible to perform switching in synchronization with the drive pulse without the need for delay means.

  As described above, the switch driving means 18 according to the present invention includes the first delay means 19 that delays the drive pulse SD by the predetermined time TD, and the first delay pulse SD1 and the drive pulse SD supplied from the first delay means 19. The logical product means 20 for outputting the logical product pulse SAD, the second delay means 21 for delaying the logical product pulse SAD supplied from the logical product means 20 by the predetermined time TD, and the second delay means 21 are provided. And an exclusive OR means 22 for outputting an exclusive OR pulse SEX of the second delay pulse SD2 and the AND pulse SAD, and a relay (relay (winding) 5B) by the AND pulse SAD from the AND means 20 , And the SSR 4 is driven by the exclusive OR pulse SEX from the exclusive OR means 22. Therefore, when switching is on, the SSR 4 is turned on before the relay (relay (contact 5A) is turned on (make), and in the on-intermediate region of switching, SSR4 is turned off and the relay (relay (contact) 5A) is kept on (make), and when switching is turned off, SSR4 is turned on and then relay ( The SSR 4 can be turned off after the relay (contact) 5A) is turned off (break), and arcing of the relay (contact) that occurs when switching is turned on / off is prevented, and is generated in the on-intermediate region of switching. Heat generation of the SSR can be prevented, and heat generation due to the ON resistance of the SSR can be prevented even if an open failure of the relay (contact) occurs.

  Further, the exclusive OR means 22 according to the present invention outputs one exclusive OR pulse SEX at the rising edge and falling edge of the AND pulse SAD, respectively, and outputs the first exclusive OR pulse SEX. Since the time interval (TON) from the rising edge to the falling edge of the second exclusive OR pulse SEX is equal to the pulse width T1ON of the driving pulse SD, switching on and off can be accurately set by SSR4. High-accuracy switching that matches the cycle of the drive pulse can be performed.

  FIG. 8 is a circuit diagram of another embodiment of the switch driving means according to the present invention. In FIG. 8, the switch driving means 24 is an example of a hardware configuration, and includes a delay circuit 25, an AND gate 26, a delay circuit 27, an exclusive OR gate 28, transistors Q1 and Q2, and a relay (winding) 5B. .

  In contrast to FIG. 6, the delay circuit 25 composed of the resistor R and the capacitor C is the first delay means 19, the AND gate 26 is the logical product means 20, and the delay circuit 27 composed of the resistor R and the capacitor C is the second delay circuit 27. The delay means 21, the exclusive OR gate 28 correspond to the exclusive ethical sum means 22, and the transistor Q1 and the relay (winding) 5B correspond to the relay drive circuit 23. The transistor Q2 drives a phototriac, a phototransistor, a photodiode, and the like that constitute the input circuit of the SSR4.

  The relay (winding) 5B shown in FIG. 8 forms a relay in pairs with the relay (contact) 5A of the switch circuit 3 shown in FIGS. 1 and 6, and a current flows through the relay (winding) 5B. 7 (d), the relay (contact) 5A is turned on (makes) with a delay of the contact operating time TL1 shown in FIG. 7 (d), and the current of the relay (winding) 5B is stopped. The relay (contact) 5A is turned off (breaks) with a delay of the indicated contact return time TL2.

  In addition, the relay composed of the relay (contact) 5A and the relay (winding) 5B is in a state where the relay (contact) 5A is in a break (off) state when no current flows through the relay (winding) 5B. When flowing, the relay (contact) 5A is configured by a standard relay having one make relay contact of a normal break contact configuration in which the make (ON) state is set.

  As described above, the relay according to the present invention is provided with one make relay contact (relay (contact) 5A) having a normal break contact configuration. Therefore, a standard relay can realize an on-characteristic that does not generate heat, and is simple. The switching circuit 3 can be built in various devices with a simple configuration.

  FIG. 9 is a block diagram of an SSR (solid state relay) according to the present invention. (A) The figure is composed of phototriac and triac, (b) The figure is composed of phototransistor, power transistor and diode bridge, (c) The figure is composed of photodiode and two power MOSFETs connected in series, (d) The figure shows an SSR (Solid State Relay) 4 composed of a photodiode, a power MOSFET, and a diode bridge.

  The phototriac, phototransistor, and photodiode forming the input circuit electrically isolate (insulate) the power supply (for example, a DC power supply) of various devices and the power supply 7 (for example, an AC power supply) that drives the load 6.

  As described above, since the SSR 4 according to the present invention includes a semiconductor switching element such as a thyristor, a triac, a transistor, or a MOSFET, an on / off operation without arc discharge can be performed in high voltage switching, and a switch circuit 3 can be built into various devices.

  Next, a method for driving the switching circuit will be described. FIG. 10 is an operation flowchart of the main part of one embodiment of the switching circuit driving method according to the present invention. The operation flow will be described with reference to FIGS.

  A switching circuit driving method comprising a switch circuit in which an SSR and a relay are connected in parallel, and a switch driving means for driving the SSR and the relay. In step S1, a first delay pulse in which the driving pulse is delayed by a predetermined time. Is generated. The operation of step S1 is executed by the first delay means 19.

  In step S2, a logical product pulse of the first delay pulse and the drive pulse is output. The operation of step S2 is executed by the logical product means 20.

  In step S3, a second delay pulse is generated by delaying the logical product pulse by the same amount as a predetermined time. The operation of step S3 is executed by the second delay means 21.

  In step S4, an exclusive OR pulse of the second delay pulse and the AND pulse is generated. The operation of step S4 is executed by the exclusive ethical means 22.

  In step S5, the SSR is driven with an exclusive OR pulse. The operation of step S5 is executed by the exclusive ethical means 22.

  In step S6, the relay is driven with a logical product pulse. The operation of step S6 is executed by the logical product means 20 and the relay drive circuit 23.

  As described above, the switching circuit driving method according to the present invention includes the step S1 for generating the first delay pulse obtained by delaying the driving pulse by a predetermined time, and the step S2 for outputting the logical product pulse of the first delay pulse and the driving pulse. A step S3 for generating a second delayed pulse obtained by delaying the logical product pulse by a predetermined time, a step S4 for generating an exclusive logical sum pulse of the second delayed pulse and the logical product pulse, and an exclusive logical sum pulse. The step S5 for driving the SSR and the step S6 for driving the relay with the logical product pulse are provided. Therefore, when the switching is turned on / off, the SSR is turned on with the pulse width of the delay time, thereby By preventing the arc discharge and turning on the relay (contact) in the other switching-on area, the heat generated by the on-resistance is prevented. A switching circuit connected in parallel to SSR and relay (contact) can be incorporated in various devices, to realize switching of high accuracy can be made compact device.

  The switching circuit according to the present invention employs a switch circuit in which a standard relay with a single make contact configuration and an SSR (solid state relay) are connected in parallel, and can compensate for high-precision switching and relay contact open failure. It can be applied to any device that is driven by a high-voltage power supply and requires high-precision switching.

Basic block configuration diagram of a switching circuit according to an embodiment of the present invention One Embodiment Related Diagram of Drive Pulse and Load Current According to the Present Invention Block diagram of essential parts of an embodiment of switch driving means according to the present invention Waveform diagram of each part of the embodiment of the switch driving means according to the present invention 1 is a circuit configuration diagram of an embodiment of switch driving means according to the present invention. Block diagram of essential parts of another embodiment of the switch driving means according to the present invention Waveform diagram of each part of the embodiment of the switch driving means according to the present invention Circuit configuration diagram of another embodiment of switch driving means according to the present invention Configuration diagram of SSR (solid state relay) according to the present invention 1 is a flow chart illustrating the operation of a main part of a switching circuit driving method according to an embodiment of the present invention. Configuration diagram of conventional switching circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Switching circuit 2, 12, 18, 24 Switch drive means 3 Switch circuit 4 SSR
5A relay (contact)
5B Relay (winding)
6 Load 7 Power supply 8 Delay means 9 First pulse generation means 10 Second pulse generation means 11, 23 Relay drive circuit 13, 25, 27 Delay circuit 14, 26 AND gate 15, 16 Monostable multivibrator 17 OR gate 19 1st Delay means 20 Logical product means 21 Second delay means 22 Exclusive OR means 28 Exclusive OR gates Q1, Q2 Transistors SD Drive pulse PD Delay pulse PF First pulse PS Second pulse SD1 First delay pulse SD2 Second delay Pulse SAD AND pulse SEX Exclusive OR pulse IRY Relay contact current ISR SSR current I
IL Load current relay TD Delay time TL1 Contact operating time TL2 Contact recovery time

Claims (8)

A switching circuit comprising: a switch circuit in which an SSR and a relay are connected in parallel; and a switch driving unit that drives the SSR and the relay,
When the switching of the switch circuit is on and off, the SSR is operated, and in the on-intermediate region excluding a part at the time of switching on and off, the relay is operated to turn on / off the switch circuit. A switching circuit comprising switch driving means for matching an off period with an on / off period of a driving pulse supplied from outside. The switch driving means includes a delay means for delaying the drive pulse by a predetermined time, a first pulse generating means for generating a first pulse by the delay pulse supplied from the delay means and the drive pulse, and the first A second pulse generating means for generating a second pulse by the first pulse and the drive pulse supplied from a pulse generating means;
2. The switching circuit according to claim 1, wherein the relay is driven by the first pulse from the first pulse generating means, and the SSR is driven by the second pulse from the second pulse generating means. . The second pulse generation means outputs a single pulse for a predetermined time using the rising edge of the first pulse as a trigger, and outputs a single pulse for a predetermined time using the falling edge of the driving pulse as a trigger. 3. The switching circuit according to claim 2, wherein a time interval from the rising edge of the first single pulse to the falling edge of the second single pulse is equal to the pulse width of the driving pulse. The switch driving means; a first delay means for delaying the drive pulse by a predetermined time; a logical product means for outputting a logical product pulse of the first delay pulse supplied from the first delay means and the drive pulse; A second delay means for delaying the logical product pulse supplied from the logical product means by the same time as the predetermined time; an exclusive logical sum of the second delay pulse supplied from the second delay means and the logical product pulse; An exclusive OR means for outputting a pulse,
2. The switching circuit according to claim 1, wherein the relay is driven by the logical product pulse from the logical product means and the SSR is driven by the exclusive logical sum pulse from the exclusive logical sum means. . The exclusive OR means outputs one exclusive OR pulse at each rise and fall of the AND pulse, and outputs a second one from the rise of the first exclusive OR pulse. 4. The switching circuit according to claim 3, wherein a time interval until the exclusive OR pulse falls is equal to a pulse width of the drive pulse. The switching circuit according to claim 1, wherein the SSR includes a semiconductor switching element such as a thyristor, a triac, a transistor, or a MOSFET. The switching circuit according to claim 1, wherein the relay includes a single make relay contact having a normal break contact configuration. A switching circuit drive method comprising: a switch circuit in which an SSR and a relay are connected in parallel; and a switch drive means for driving the SSR and the relay,
Generating a first delayed pulse obtained by delaying the drive pulse by a predetermined time; and
Outputting a logical product pulse of the first delay pulse and the drive pulse;
Generating a second delayed pulse obtained by delaying the AND pulse by a predetermined time; and
Generating an exclusive OR pulse of the second delay pulse and the AND pulse;
Step S5 for driving the SSR with an exclusive OR pulse;
Step S6 for driving the relay with AND pulses;
A method for driving a switching circuit, comprising:

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