JP2005099927A - Computer system, electronic apparatus and device-bus interconnection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a power-maintained device from malfunctioning even if a device whose power is interrupted in a power saving mode and the device whose power is maintained even in a power saving mode are connected to the same bus. <P>SOLUTION: When an MPU 11, a power circuit, devices powered by the power circuit and interrupted in power supply in a power saving mode, and an option board 41 that is a device powered by the power circuit and uninterrupted in power supply in a power saving mode are connected to the same local bus 30, the option board 41 is connected to the local bus 30 via gate circuits 421, 422, 41A0 to 41Am, 41D0 to 41Dk, etc. for permitting electrical connections of input/output terminals including connections to the local bus 30 except in a power saving mode and interrupting electrical connections of the input/output terminals including connections to the local bus 30 in a power saving mode to maintain a high impedance state. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is a computer system in which various devices connected by a bus operate using a processor as a control center, and various electronic devices incorporating such a computer system, and saves power as a power saving state when not in operation. The present invention relates to such a computer system and various electronic devices incorporating such a computer system, and also relates to a device-bus connection circuit.

  In various electronic devices using a computer system in which various devices are connected via buses with a processor as a control center, such as an electrophotographic printer, only a fixing device that consumes the most power for heat fixing In addition, a configuration has been proposed in which power saving from a power source to devices such as a CPU and a ROM is stopped to save power as a hibernation state (see, for example, Patent Document 1).

However, in a facsimile apparatus incorporating an electrophotographic printer as described above, for example, a communication-related device (for example, a LAN board) for facsimile reception cannot be put into a dormant state. There will be a mix of devices and non-devices. In such a case, if both are connected to a single bus, the state of the input / output terminals of the device for which power supply is stopped becomes indeterminate, and the device for which power supply is maintained may malfunction. There was a problem.
JP 7-156512 A

  Under these circumstances, the above-described problems can be avoided by adopting a configuration in which a device in which power supply is stopped in the hibernation state and a device in which power supply is maintained in the hibernation state are connected to different buses. There were many cases to do. However, when such a configuration is adopted, at least two buses are required, and the arrangement positions of the devices are restricted by the buses to which the devices are connected, so that the degree of freedom in equipment design is reduced.

  The present invention has been made in view of the circumstances as described above, and even if a device in which power supply is stopped in the hibernation state and a device in which power supply is maintained in the hibernation state are connected to the same bus, Incorporating such a computer system and a computer system that does not cause such a problem that the state of the input / output terminals of the device for which power supply is stopped becomes unstable and the device for which power supply is maintained malfunctions The present invention relates to various electronic devices, and also relates to a device-bus connection circuit.

  A computer system according to a first aspect of the present invention includes a processor, a power source, and a plurality of devices that are powered from the power source and connected to the same bus, and the plurality of devices according to a predetermined instruction issued by the processor. In the computer system that stops the power supply from the power source to devices other than the predetermined device, and enters the power saving state, the predetermined device is connected to the bus in the first state. Input / output terminal connection means for permitting a general connection and disconnecting the electrical connection of the input / output terminals including the connection with the bus in the second state to maintain a high impedance state, and when receiving the predetermined instruction And switching means for switching the input / output terminal connection means to the second state.

  In such a computer system of the first invention, the electrical connection of the input / output terminals including the connection with the bus is permitted in the first state of the predetermined device whose power supply is not stopped in the power saving state, and the second state Then, the input / output terminal connection means for maintaining the high impedance state by disconnecting the electrical connection of the input / output terminals including the connection with the bus is switched when the predetermined instruction for entering the power saving state is received from the processor. Switches to the second state.

  A computer system according to a second aspect of the present invention is the computer system of the first aspect, wherein the predetermined device includes means for generating an interrupt signal for requesting cancellation of a power saving state, and the processor includes the interrupt signal. The switching means is configured to switch the input / output terminal connecting means to the first state when receiving an instruction to release the power saving state. It is characterized by being.

  In such a computer system of the second invention, in the computer system of the first invention, a predetermined device whose power supply is not stopped in the power saving state generates an interrupt signal requesting the cancellation of the power saving state. When the processor receives the instruction, the processor issues a predetermined instruction for releasing the power saving state, and the switching means switches the input / output terminal connection means to the first state in response to this.

  A computer system according to a third aspect of the present invention is the computer system of the first or second aspect, wherein the predetermined device determines whether or not it can enter a power saving state when inquired from the processor. Means for notifying the processor of the result, wherein the processor issues the predetermined instruction when notified that the power-saving state can be entered from the predetermined device. And

  In such a computer system of the third invention, in the computer system of the first or second invention, when a predetermined device whose power supply is not stopped in the power saving state makes an inquiry from the processor to enter the power saving state, Determines whether or not it can enter the power saving state, notifies the processor of the determination result, and issues a predetermined instruction to enter the power saving state when the processor is notified that the device can enter the power saving state. To do.

  A device-bus connection circuit of a computer system according to a fourth invention comprises a processor, a power supply, and a plurality of devices that are fed from the power supply and connected to the same bus, and the processor issues a predetermined A device-bus of a computer system that connects the predetermined device and the bus of the computer system that stops power supply from the power supply to devices other than the predetermined device among the plurality of devices according to instructions and enters a power saving state In the inter-connection circuit, in the first state, the electrical connection of the input / output terminals including the connection with the bus is permitted, and in the second state, the electrical connection of the input / output terminals including the connection with the bus is disconnected. The input / output terminal connecting means for maintaining the high impedance state and the input / output terminal connecting means when the predetermined instruction is received. The switching, when receiving an instruction to cancel the power-saving state in which said processor issues, is characterized in that a means for switching said output terminal connection means to said first state.

  In the device-bus connection circuit of the computer system according to the fourth aspect of the invention, electrical connection of input / output terminals including connection with the bus is permitted in the first state, and connection with the bus in the second state. The input / output terminal connecting means for maintaining the high impedance state by disconnecting the electrical connection of the input / output terminals including is switched to the second state when receiving a predetermined instruction for entering the power saving state from the processor, When an instruction for canceling the power saving state is received from the processor, the state is switched to the first state.

  An electronic apparatus according to a fifth aspect of the present invention includes a processor, a power source, and a plurality of devices that are powered from the power source and connected to the same bus, and the plurality of devices are in accordance with a predetermined instruction issued by the processor. In an electronic device that enters a power saving state by maintaining power supply from the power source to a device that cannot be put into a hibernation state by stopping power supply from the power source to a device with a large amount of power consumption in A device that is not put into a sleep state in the power saving state permits electrical connection of an input / output terminal including connection to the bus in the first state, and includes an input / output terminal including connection to the bus in the second state. Input / output terminal connection means for disconnecting electrical connection and maintaining a high impedance state, and switching the input / output terminal connection means to the second state when receiving the predetermined instruction Characterized by comprising a stage.

  In the electronic device according to the fifth aspect of the present invention, the electrical connection of the input / output terminals including the connection with the bus is permitted in the first state, and the bus that is not in the hibernation state in the first state is permitted. The input / output terminal connection means for maintaining the high impedance state by disconnecting the electrical connection of the input / output terminal including the connection to the input terminal is switched when the predetermined means for entering the power saving state is received from the processor. Switch to state 2.

  An electronic device according to a sixth invention is the electronic device according to the fifth invention, wherein the device that is not put into a hibernation state during the power saving state includes means for generating an interrupt signal requesting release of the power saving state, and the processor Issuing an instruction to release the power saving state when the interrupt signal is received, and the switching means sets the input / output terminal connecting means to the first state when receiving an instruction to release the power saving state. It is characterized by switching to.

  In such an electronic device of the sixth invention, in the electronic device of the fifth invention, a device that is not put into the hibernation state during the power saving state generates an interrupt signal requesting the cancellation of the power saving state, and receives this interrupt signal. In this case, the processor issues an instruction to cancel the power saving state, and the switching means switches the input / output terminal connection means to the first state in response to this.

  An electronic device according to a seventh aspect is the electronic device according to the fifth or sixth aspect, wherein a device that is not put into a hibernation state during the power saving state can enter the power saving state when inquired by the processor. And a means for notifying the processor of the determination result, wherein the processor issues the predetermined instruction when notified from the device that it is possible to enter a power saving state. It is characterized by that.

  In such an electronic device of the seventh invention, in the electronic device of the fifth or sixth invention, when there is an inquiry from the processor to enter the power saving state in the electronic device of the fifth or sixth invention, the power saving state is not obtained. The processor notifies the processor of the determination result, and issues a predetermined instruction for entering the power saving state when the processor is notified that the device can enter the power saving state.

  An electronic device device-bus connection circuit according to an eighth aspect of the present invention includes a processor, a power source, and a plurality of devices that are fed from the power source and connected to the same bus, and the processor issues a predetermined According to the instruction, power supply from the power supply to a device that consumes a large amount of power among the plurality of devices is stopped to be in a dormant state, and power supply from the power supply to a device that cannot be in a dormant state is maintained to save power. In the device-bus connection circuit of the electronic device that connects the device of the electronic device entering the state and the bus, in the first state, the electrical connection of the input / output terminals including the connection with the bus is permitted, In the state of 2, the input / output terminal connection means for maintaining the high impedance state by disconnecting the electrical connection of the input / output terminals including the connection with the bus, and when receiving the predetermined instruction, Means for switching the input / output terminal connection means to the first state when receiving an instruction to switch the entry output terminal connection means to the second state and release the power saving state issued by the processor. It is characterized by that.

  In the device-bus connection circuit of the electronic device according to the eighth aspect of the present invention, electrical connection of input / output terminals including connection with the bus is permitted in the first state, and connection with the bus in the second state. The input / output terminal connecting means for maintaining the high impedance state by disconnecting the electrical connection of the input / output terminals including is switched to the second state when receiving a predetermined instruction for entering the power saving state from the processor, When an instruction for canceling the power saving state is received from the processor, the state is switched to the first state.

  As described above in detail, according to the computer system of the first invention, when the switching means receives a predetermined instruction for entering the power saving state from the processor, the bus of the predetermined device whose power supply is not stopped in the power saving state. Since the electrical connection of the input / output terminal including the connection to the power supply is cut and the high-impedance state is maintained, it is not affected by the input / output terminal that is in an indeterminate state of the device that stops power supply in the power saving state, and prevents malfunction Is done.

  According to the computer system of the second invention, in the computer system of the first invention, an interrupt signal for requesting cancellation of the power saving state is generated from a predetermined device side in which power supply is not stopped in the power saving state, and the power saving state is set. In addition, the electrical connection of the input / output terminals including the connection with the bus of a predetermined device whose power supply is not stopped in the power saving state is returned to the normal connection state.

  According to the computer system of the third invention, in the computer system of the first or second invention, when a predetermined device whose power supply is not stopped in the power saving state receives an inquiry from the processor as to whether or not to enter the power saving state. The processor issues a predetermined instruction to enter the power saving state only when it is notified that the power saving state can be entered. It will not enter the power saving state until is finished.

  According to the device-bus connection circuit of the computer system of the fourth invention, the electrical connection of the input / output terminals including the connection with the bus is cut off when a predetermined instruction for entering the power saving state is received from the processor. The high impedance state is maintained, and when an instruction to release the power saving state is received from the processor, the electrical connection of the input / output terminals including the connection with the bus is permitted, and the normal state can be restored. .

  According to the electronic device of the fifth aspect of the invention, when the switching means receives a predetermined instruction for entering the power saving state from the processor, the input / output terminal including the connection with the bus of the device that cannot be put into the sleep state Since the electrical connection is disconnected and the high impedance state is maintained, there is no influence from the input / output terminals that cause the power supply to be stopped in the power saving state due to the high power consumption, and the malfunction is prevented. .

  According to the electronic device of the sixth invention, in the electronic device of the fifth invention, the power saving state can be canceled by generating an interrupt signal requesting the cancellation of the power saving state from the device side that cannot be put into the hibernation state. At the same time, the electrical connection of the input / output terminals including the connection with the bus of the device whose power supply is not stopped in the power saving state due to the large power consumption is returned to the normal connection state.

  According to the electronic device of the seventh invention, in the electronic device of the fifth or sixth invention, when the device that cannot be put into the hibernation state receives an inquiry from the processor as to whether or not to enter the power saving state, the electronic device enters the power saving state. The processor issues a predetermined instruction to enter the power saving state only when it is notified that it can enter, so that the device that cannot be put into the sleep state does not enter the power saving state until the process being executed is completed. Absent.

  According to the device-bus connection circuit of the electronic device according to the eighth aspect of the present invention, when the switching means receives a predetermined instruction for entering the power-saving state from the processor, Since the electrical connection of the input / output terminals including the connection of the power supply is cut and the high impedance state is maintained, the power consumption is high, and therefore the power supply is affected by the input / output terminals that are indeterminate in the power saving state. The malfunction is prevented.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. FIG. 1 is a block diagram showing an example of the internal configuration of a multifunction peripheral as an embodiment of an electronic apparatus incorporating the computer system of the present invention. Although details will be described later, a plurality of devices are bus-connected to the multi-function peripheral as the computer system of the present invention, but power for stopping power supply to some of these devices for power saving. Execution of save mode is possible.

  The multifunction machine as a computer system of the present invention has functions such as reading of a document image, copy output (printout) and transmission by facsimile communication, and printout of data received by facsimile communication. Various functions as described above are realized in accordance with a computer program stored in the (read-only memory) 12.

  The internal configuration of the MFP as the computer system of the present invention shown in FIG. 1 includes a system bus 20 directly connected to the MPU 11 as a processor as a control center, a local bus 30 to which the MPU 11 is not directly connected, and A plurality of buses are connected to the panel bus 50, and the buses 20, 30, and 50 are connected by a gate array 21 to switch data transfer between the buses.

  The MPU 11 is connected to the above-described ROM 12 and SRAM 14 used as various information holding memories via a system bus 20. The MPU 11 is also connected to the gate array 21 via the system bus 20.

  The gate array 21 is connected to the SDRAM 22 used as an image memory, and is connected to the system bus 20, the panel bus 50, and the local bus 30 described above.

  The system bus 20 further includes a modem 23, an NCU 24, a reading image processing circuit 36, and the like. The panel bus 50 includes an operation panel 51. The local bus 30 includes a printing image processing circuit 31, a printing memory controller 33, A print codec 34, a read memory controller 38, a read codec 39, and the like are connected. An option board 41 is retrofitted to the local bus 30. Although details of the option board 41 will be described later, in the present embodiment, the board has a function that cannot stop power supply even in the power save mode, for example, a LAN interface function.

  The operation panel 51 includes character keys, numeric keys, abbreviated dial keys, one-touch dial keys, various function keys, a display device such as an LCD, and the like that are necessary for operating the multi-function peripheral that is the computer system of the present invention.

  A printer engine 32 and the above-described memory controller 33 are connected to the print image processing circuit 31 connected to the local bus 30. In addition to being directly connected to the local bus 30, the memory controller 33 is also connected to an SDRAM 35 that is used as a work area for printing.

  The printer engine 32 is provided in a printing unit (printer) (not shown). The encoded image data is sent from the local bus 30 to the print codec 34 to be decoded (decoded) into the print data, and then supplied from the print image processing circuit 31 to the printer engine 32 via the memory controller 33. .

  A CCD 37 and the memory controller 38 are connected to the reading image processing circuit 36 connected to the system bus 20. The memory controller 38 is directly connected to the local bus 30 and is also connected to an SDRAM 40 used as a work area for reading.

  The CCD 37 is provided in a reading unit (scanner) (not shown). The signal read by the CCD 37 is processed by the reading image processing circuit 36 and converted into, for example, monochrome binary image data. The converted image data is sent from the memory controller 38 to the reading codec 39 and coded (encoded), and then output to the local bus 30.

  The modem 23 and the NCU 24 are connected to the gate array 21 via the system bus 20, but are also connected to each other. The modem 23 is a facsimile modem capable of facsimile communication. The NCU 24 is hardware that performs operations for closing and opening an analog line with the public switched telephone network (PSTN). The NCU 24 connects the modem 32 to the public switched telephone network as necessary, and communicates with other facsimile apparatuses. Controls facsimile communication.

  Reference numeral 60 denotes a power supply circuit that supplies power to each of the above-described components, but power supply is stopped in the power save mode. For example, power supply to the print codec 34, the read codec 39, and the like is indicated by broken lines and v. For example, the power supply to the option board 41 is maintained even in the power save mode.

  The option board 41 is a LAN interface in the present embodiment, and includes a gate array 42, an MPU 44 connected to the gate array 42 by a bus, and components for LAN communication (not shown). Further, the gate array 42 of the option board 41 includes a DPRAM (dual port RAM) 43 used as a buffer memory for data input / output.

  An interrupt signal (/ INT) is output from the MPU 44 of the option board 41 and is given to the MPU 11.

  By the way, as indicated by a solid line and V in this option board 41, power supply is maintained even in the power save mode. On the other hand, a print codec 34 and a read codec 39 are also connected to the local bus 30 to which the option board 41 is connected. These devices are indicated by broken lines and v as described above. In the power save mode, power supply is stopped. That is, in the multi-function peripheral as the computer system of the present invention, the power supply is maintained even in the power save mode, and the print codec 34 and the read codec 39 that are stopped in the power save mode for one local bus 30. The option board 41 is connected together.

  A typical operation of the multi-function peripheral which is the computer system of the present invention having the above-described configuration is as follows.

  Facsimile image data received by the modem 23 via the NCU 24 by facsimile communication from another facsimile apparatus via the public telephone exchange network is output to the system bus 20 and stored in the SDRAM 22 via the gate array 21. Further, the image data read by the CCD 37 of the reading unit and converted by the reading image processing circuit 36 is supplied from the memory controller 38 to the reading codec 39 and encoded, and then output to the local bus 30 and the gate array 21. It is stored in the SDRAM 22 via.

  When facsimile image data stored in the SDRAM 22 is transmitted by facsimile, the facsimile image data is output to the system bus 20 via the gate array 21 and transmitted to the public telephone exchange network via the modem 23 and NCU 24. When the facsimile image data stored in the SDRAM 22 is printed out, the facsimile image data is output to the local bus 30 via the gate array 21 and decoded by the print codec 34 from the print image processing circuit 31 to the printer. It is output to the engine 32 and printed out.

  Input / output of data to / from the SDRAM 22 as described above is performed without intervention of the MPU 11 by DMA transfer by the DMA controller (DMAC) 215 provided in the gate array 21 (see FIG. 2).

  When image data is transmitted / received via the LAN, the image data is input / output to / from the local bus 30 via the option board 41 functioning as a LAN interface and processed in the same manner as described above.

  By the way, the power saving mode can be executed in the MFP as the computer system of the present invention having the above-described configuration. Hereinafter, signals related to the execution of the power save mode will be described.

  However, in the following description, as an example, the print codec 34 and the read codec 39 in which power supply is stopped in the power save mode and the option board 41 in which power supply is maintained in the power save mode are connected in common. The local bus 30 will be described. A signal having “/” added to the head of the signal name means that it is low active (significant when it is low level).

  When executing the power save mode, the low active power save signal (/ PS) output from the gate array 21 is asserted (made significant, specifically, set to the low level) according to an instruction from the MPU 11. ).

  The MPU 11 outputs an MPU chip select signal (/ MPU_CS), an MPU read signal (/ MPU_RD), an MPU write signal (/ MPU_WR), and other chip select signals, for example. After the MPU read signal (/ MPU_RD) and MPU write signal (/ MPU_WR) are input to the gate array 21, the IO write signal (/ IO_WR) and IO read signal (/ Only IO_RD) is shown.

  Specifically, IO reading from the gate array 21 to the print image processing circuit 31, print codec 34, both memory controllers 33 and 38, the read codec 39, the read image processing circuit 36, and the gate array 42 of the option board 41 Signals (/ IO_WR) and IO write signal (/ IO_RD) are provided.

  Therefore, the gate array 21 outputs a chip select signal (/ IO_CSn) for selecting each device according to the address of the chip select signal supplied from the MPU 11 (set to low level), and at the same time, an IO read signal (/ IO_RD) or By outputting the IO write signal (/ IO_WR) (low level) to cause the device selected by the chip select signal to read or write data, the above-described operation can be performed. It becomes possible.

  When the power save signal (/ PS) output from the gate array 21 is activated (low level), the power supply circuit 60 supplies power to several devices including the print codec 34 and the read codec 39. And power supply to several devices including the option board 41 is maintained. As a result, the power save mode is executed.

  Next, the configuration of the gate array 21 will be described with reference to the block diagram of FIG.

  In the gate array 21, an internal bus 210 includes a system bus interface (I / F) 211, an SDRAM interface (I / F) 213, a local bus interface (I / F) 214, a DMAC (direct memory access controller). ) 215, an address decoder 216, a signal generation circuit 217, and the like are connected.

  The system bus I / F 211 is an interface between the system bus 20 and the gate array 21. The MPU chip select signal (/ MPU_CS), MPU write signal (/ MPU_WR), and MPU read signal (/ MPU_RD) is also input.

  The address decoder 216 receives and decodes an address signal for chip selection output from the MPU 11 and input from the internal bus 210 via the system bus I / F 211 in synchronization with the MPU chip select signal (/ MPU_CS). Thus, any one of the 0th to nth chip select signals (/ IO_CS0 to / IO_CSn) for selecting each device (chip) is made active (low level). However, each chip select signal (/ IO_CS0 to / IO_CSn) is output to the outside of the gate array 21 via the gate circuits 2160 to 216n, respectively. Each gate circuit 2160 to 216n electrically disconnects the signal line of each chip select signal (/ IO_CS0 to / IO_CSn) from the gate array 21 when the power save signal (/ PS) is activated.

  The signal generation circuit 217 outputs a power save signal (/ PS) according to an instruction given from the MPU 11 via the bus, and also outputs an MPU chip select signal (/ MPU_CS) and an MPU read signal (/ MPU_RD) output from the MPU 11. , MPU write signal (/ MPU_WR) is converted into IO write signal (/ IO_WR) and IO read signal (/ IO_RD), respectively, and output to the outside of gate array 21. However, the IO write signal (/ IO_WR) and the IO read signal (/ IO_RD) are output to the outside of the gate array 21 via the gate circuits 2170 and 2171, respectively. Each gate circuit 2171 and 2171 electrically disconnects the signal lines of the IO write signal (/ IO_WR) and the IO read signal (/ IO_RD) from the gate array 21 when the power save signal (/ PS) is activated. .

  The connection between the local bus I / F 214 and the local bus 30 is divided into an address bus and a data bus. With respect to the address bus, gate circuits 21A0 to 21Am are interposed in each address signal line, and a power save signal (/ PS ) Is given as a control signal for these gate circuits 21A0 to 21Am. Therefore, when the power save signal (/ PS) is activated (low level), these gate circuits 21A0 to 21Am electrically disconnect the respective address signal lines from the gate array 21.

  Regarding the data bus, bidirectional gate circuits 21D0 to 21Dk are interposed in each data signal line, and a negative logic output signal of the AND gate 2140 is given as a control signal for these gate circuits 21A0 to 21Am. The AND gate 2140 has two negative logic input terminals, one of these input terminals is a power save signal (/ PS), and the other is a low active disconnection signal (/ G generated by the signal generation circuit 217). ) Is entered. Therefore, the AND gate 210 provides a low level output signal as a control signal for the gate circuits 21A0 to 21Am when both the power save signal (/ PS) and the disconnection signal (/ G) are active (low level). It is like that.

  FIG. 3 is a block diagram showing a configuration example of a main part of the option board 41, showing the configuration of the device-bus connection circuit of the present invention.

  A power save signal (/ PS), an IO read signal (/ IO_RD), and an IO write signal (/ IO_WR) are input to the gate array 42 of the option board 41, and a local bus 30 is also connected. Specifically, the power save signal (/ PS) is supplied to one positive logic input terminal of the AND gates 421 and 422 in which one input terminal is positive logic, the other input terminal is negative logic, and the output terminal is negative logic. The IO read signal (/ IO_RD) is input to the other negative logic input terminal of the AND gate 421, and the IO write signal (/ IO_WR) is input to the other negative logic input terminal of the AND gate 422.

  In addition, each address signal line of the address bus of the local bus 30 is connected to the other negative logic input terminal of the AND gates 41A0 to 41Am in which one input terminal is positive logic, the other input terminal is negative logic, and the output terminal is negative logic. The power save signal (/ PS) is input to one of the positive logic input terminals of the AND gates 41A0 to 41Am. The data signal lines of the data bus of the local bus 30 are input to the bidirectional gate circuits 41D0 to 41Dk, and the output signal of the AND gate 423 is given to the control terminals of these bidirectional gate circuits 41D0 to 41Dk. It has been. Each of the AND gates 423 has two negative logic input terminals and an output terminal. One negative logic input terminal outputs a power save signal (/ PS), and the other negative logic input terminal outputs the gate array 42 itself. A low active disconnect signal (/ G ′) is input.

  Therefore, when the power save signal (/ PS) is not activated, that is, in a state where the power save mode is not set, each AND gate 421, 422, 41A0 to 41Am outputs the other input signal as it is. When the power save signal (/ PS) is activated, that is, in the power save mode, the AND gates 421 and 422 do not accept the IO read signal (/ IO_RD) and the IO write signal (/ IO_WR), The AND gates 41A0 to 41Am electrically disconnect the gate array 42 of the option board 41 from the local bus 30.

  Further, when the power save signal (/ PS) is not activated, that is, when the power save mode is not set, the output signal of the AND gate 423 becomes high level, so that each of the bidirectional gate circuits 41A0 to 41Am is a local bus. When the power save signal (/ PS) is activated, that is, in the power save mode, and the disconnect signal (/ G ′) is active (low level), Since the output signal of the AND gate 423 is at a low level, the bidirectional gate circuits 41D0 to 41Dk electrically disconnect the gate array 42 of the option board 41 from the local bus 30.

  Note that the MPU 44 of the option board 41 which is a LAN interface generates an interrupt signal (/ INT) from the output port and gives it to the MPU 11 when communication via the LAN is received from outside in the power save mode.

  Next, an operation related to the power save mode of the multi-function peripheral which is the computer system of the present invention having the above-described configuration will be described.

  In the multi-function peripheral which is the computer system of the present invention, for example, when no operation is performed for a predetermined time, it is programmed to enter the power save mode from the normal state to save power. In such a case, a command for inquiring to enter the power save mode is issued from the MPU 11 and is input to the option board 41 via the system bus 20, the gate array 21 and the local bus 30, and the MPU 44 of the option board 41 via the DPRAM 42. Will be notified. At this time, if the MPU 44 of the option board 41 is executing some processing, the power save mode cannot be entered, and a response indicating that fact is transmitted to the MPU 11. In this case, the MPU 11 thereafter repeatedly outputs a command inquiring that the power save mode is entered at predetermined time intervals.

  If the MPU 44 of the option board 41 is in a state in which it can enter the power save mode, a response to approve the command inquiring to enter the power save mode output from the MPU 11 is transmitted to the MPU 11. In this case, the option board 41 can no longer request, for example, a DMA transfer process. Upon receiving a response to approve the power save mode from the MPU 44 of the option board 41, the MPU 11 activates the power save signal (/ PS) (sets it to the low level). When the power save signal (/ PS) is activated, the power supply circuit 60 stops power supply to other power supply destinations except for the option board 41, and maintains power supply to the option board 41.

  Further, when the power save signal (/ PS) is activated, the signal lines outputting the chip select signals (/ IO_CS0 to / IO_CSn) from the address decoder 216 of the gate array 21 are respectively supplied by the gate circuits 2160 to 216n. Electrically disconnected from the outside. The signal lines outputting the IO write signal (/ IO_WR) and the IO read signal (/ IO_RD) from the signal generation circuit 217 of the gate array 21 are electrically disconnected from the outside by the gate circuits 2140 and 2171, respectively. .

  Further, when the power save signal (/ PS) is activated, each signal line of the address signal output from the local bus I / F 214 to the address bus of the local bus 30 is also sent to the local bus by the gate circuits 21A0 to 21Am. 30 and electrically disconnected. Further, when the power save signal (/ PS) is activated, the signal generation circuit 217 sets the disconnect signal (/ G) to active (low level), so that the local bus I / F 214 outputs to the data bus of the local bus 30. The respective signal lines of the data signal are also electrically disconnected from the local bus 30 by the bidirectional gate circuits 21D0 to 21Dk.

  On the other hand, in the option board 41, the power supply from the power supply circuit 60 is maintained, but when the power save signal (/ PS) is activated, the AND gates 421, 422, and 41A0 to 41Am all accept input signals. No state. At the same time, when the power save signal (/ PS) is activated, the MPU 44 of the option board 41 sets the disconnect signal (/ G ′) to active (low level), so both negative logic input terminals of the AND gate 423 The input to becomes low level, and the output signal becomes low level. As a result, the bidirectional gate circuits 41D0 to 41Dk are all turned off, so that each data signal line of the data bus connecting the gate array 42 of the option board 41 and the local bus 30 is electrically connected from the local bus 30. Disconnected.

  As described above, all input / output terminals of the option board 41, that is, input terminals of the chip select signal (/ IO_CS0 to / IO_CSn), the IO write signal (/ IO_WR), and the IO read signal (/ IO_RD), the address bus, and the data Since the bus is electrically disconnected from the gate array 21 or the local bus 30 while being maintained at a high impedance, the codec 34 for printing connected to the same bus, that is, the local bus 30 and whose power supply is stopped, It is not affected by the reading codec 39 and the like, and there is no possibility that the option board 41 malfunctions.

  As described above, in the multi-function peripheral that is the computer system of the present invention, power supply to each device other than the option board 41, which is a LAN interface that requires power supply even in the power save mode, is stopped in the power save mode. Is demonstrated. In order to cancel the power save mode and return to the normal state, there are a case where the power save mode is canceled from the MPU 11 side and a case where the power save mode is canceled by a request from the option board 41 side.

  First, a case where the power save mode is canceled from the MPU 11 side will be described. Specifically, when an operation is performed manually, for example, when any key of the operation panel 51 is operated, or when a document is set on a reading unit (scanner) (not shown) provided with the CCD 37. The MPU 11 detects such a state and starts a process for canceling the power save mode. In this case, the MPU 11 first makes the power save signal (/ PS) non-active (high level), thereby restarting the power supply from the power supply circuit 60 to all devices.

  At the same time, the MPU 11 issues a command indicating that the power save mode has been canceled to the option board 41 that has been supplied with power even in the power save mode. The data is input to the option board 41 via the bus 20, the gate array 21, and the local bus 30, and notified to the MPU 44 of the option board 41 via the DPRAM 42. In response to this, the MPU 44 of the option board 41 outputs a response for approving the cancellation of the power save mode to the local bus 30, and this is transmitted to the MPU 11 through the reverse route.

  Further, when the power save signal (/ PS) is made inactive, the gates interposed in the signal lines outputting the chip select signals (/ IO_CS0 to / IO_CSn) from the address decoder 216 of the gate array 21. The circuits 2160 to 216n are turned on and the connection with the outside is restored. In addition, the gate circuits 2140 and 2171 that are also interleaved with the respective signal lines that output the IO write signal (/ IO_WR) and the IO read signal (/ IO_RD) from the signal generation circuit 217 of the gate array 21 are turned on. Therefore, the connection with the outside is restored.

  Further, when the power save signal (/ PS) is made inactive, the gate circuit 21A0 interposed in each signal line of the address signal output from the local bus I / F 214 to the address bus of the local bus 30. ˜21 Am is also turned on, and the connection with the local bus 30 is restored. Further, when the power save signal (/ PS) is made inactive, the signal generation circuit 217 makes the disconnection signal (/ G) inactive (high level), so that the data bus from the local bus I / F 214 to the local bus 30 is made. The bidirectional gate circuits 21D0 to 21Dk interposed in the respective signal lines of the data signal output to are also turned on and the connection with the local bus 30 is restored.

  On the other hand, when the power save signal (/ PS) is made inactive also in the option board 41, the AND gates 421, 422, and 41A0 to 41Am all receive the input signal. At the same time, when the power save signal (/ PS) is made inactive, the MPU 44 of the option board 41 makes the disconnect signal (/ G ′) inactive (high level). The input to the input terminal becomes high level, and the output signal becomes high level. Accordingly, since the bidirectional gate circuits 41D0 to 41Dk are all turned on, the connection between each data signal line of the data bus connecting the gate array 42 of the option board 41 and the local bus 30 and the local bus 30 is established. Is recovered.

  As described above, all input / output terminals of the option board 41, that is, input terminals of the chip select signal (/ IO_CS0 to / IO_CSn), the IO write signal (/ IO_WR), and the IO read signal (/ IO_RD), the address bus, and the data The bus returns to the normal connection state.

  Next, a case where the power save mode is canceled from the option board 41 side will be described. Specifically, since the option board 41, which is a LAN interface, operates while power supply is maintained even in the power save mode, the MPU 44 receives an interrupt signal ( / INT). This interrupt signal (/ INT) is output to the MPU 11 through a dedicated signal line.

  By inputting the interrupt signal (/ INT) generated by the MPU 44 of the option board 41, the MPU 11 cancels the power save mode. In this case, the MPU 11 first restarts power supply from the power supply circuit 60 to all devices by setting the power save signal (/ PS) to non-active (high level).

  At the same time, the MPU 11 outputs a command indicating that the power save mode has been canceled to the option board 41 that has output the interrupt signal (/ INT). A command for instructing the release of the power save mode is input to the option board 41 via the system bus 20, the gate array 21, and the local bus 30, and notified to the MPU 44 of the option board 41 via the DPRAM 42. On the other hand, the MPU 44 of the option board 41 outputs a response for approving the cancellation of the power save mode to the local bus 30, and this is transmitted to the MPU 11 through the reverse route.

  The subsequent processing is the same as the processing for canceling the power save mode from the MPU 11 described above.

  In the above embodiment, an example in which the computer system of the present invention is incorporated in a multifunction machine has been exemplified as the electronic apparatus of the present invention. In addition, the present invention can also be applied to an electronic device that stops power supply to main components in a standby state such as an AV device such as a DVD player / recorder or a video tape recorder.

1 is a block diagram illustrating an example of an internal configuration of a multifunction machine that is an electrical apparatus as an embodiment of a computer system of the present invention. FIG. 1 is a block diagram illustrating an example of a gate array configuration of a multifunction peripheral that is an electrical apparatus as an embodiment of a computer system of the present invention. FIG. FIG. 2 is a block diagram illustrating a configuration example of a main part of an option board of a multi-function peripheral which is an electric device as an embodiment of a computer system of the present invention, and illustrates a configuration of a device-bus connection circuit of the present invention. .

Explanation of symbols

11 MPU
21 Gate array 30 Local bus 34 Codec for printing (device in hibernation)
39 Codec for reading (device that goes into hibernation)
41 Option board (device that does not enter hibernation)
42 Gate array (of option board 41) 44 MPU (of option board 41)
60 power supply circuit 421, 422, 41A0 to 41Am AND gate 41D0 to 41Dk bidirectional gate circuit / IO_RD read signal / IO_WR write signal / PS power save signal / INT interrupt signal / G, / G 'disconnect signal

Claims (8)

A processor, a power source, and a plurality of devices that are powered from the power source and connected to the same bus, and a predetermined instruction issued by the processor to a device other than the predetermined device among the plurality of devices In a computer system that enters a power saving state by stopping power supply from the power source,
The predetermined device is:
In the first state, the electrical connection of the input / output terminals including the connection with the bus is permitted, and in the second state, the electrical connection of the input / output terminals including the connection with the bus is cut off so that the high impedance state is established. I / O terminal connection means to maintain,
And a switching means for switching the input / output terminal connection means to the second state when receiving the predetermined instruction. The predetermined device includes means for generating an interrupt signal requesting cancellation of the power saving state,
The processor issues an instruction to cancel the power saving state when the interrupt signal is received, and the switching means connects the input / output terminal connecting means to the first when receiving the instruction to cancel the power saving state. The computer system according to claim 1, wherein the computer system is switched to a state of 1. The predetermined device includes means for determining whether or not to enter a power saving state and notifying the determination result to the processor when inquired from the processor.
The computer according to claim 1, wherein the processor issues the predetermined instruction when notified that the power-saving state can be entered from the predetermined device. system. A processor, a power source, and a plurality of devices that are powered from the power source and connected to the same bus, and a predetermined instruction issued by the processor to a device other than the predetermined device among the plurality of devices In a device-to-bus connection circuit of a computer system that connects the predetermined device of the computer system that enters a power saving state by stopping power supply from the power source and the bus,
In the first state, the electrical connection of the input / output terminals including the connection with the bus is permitted, and in the second state, the electrical connection of the input / output terminals including the connection with the bus is cut off so that the high impedance state is established. I / O terminal connection means to maintain,
When the predetermined instruction is received, the input / output terminal connection means is switched to the second state, and when the instruction to cancel the power saving state issued by the processor is received, the input / output terminal connection means is A device-bus connection circuit of a computer system, comprising: means for switching to a first state. A processor, a power source, and a plurality of devices that are powered from the power source and connected to the same bus, and that are configured to issue power to a device that consumes more power among the plurality of devices according to a predetermined instruction issued by the processor In an electronic device that enters a power saving state by maintaining power feeding from the power source to a device that cannot be in a hibernation state by stopping power feeding from the power source,
Devices that are not put into hibernation during the power saving state are:
In the first state, the electrical connection of the input / output terminals including the connection with the bus is permitted, and in the second state, the electrical connection of the input / output terminals including the connection with the bus is cut off so that the high impedance state is established. I / O terminal connection means to maintain,
An electronic device comprising: means for switching the input / output terminal connection means to the second state when receiving the predetermined instruction. The device that is not put into a hibernation state during the power saving state includes means for generating an interrupt signal for requesting cancellation of the power saving state,
The processor issues an instruction to cancel the power saving state when the interrupt signal is received,
6. The electronic apparatus according to claim 5, wherein the switching unit is configured to switch the input / output terminal connection unit to the first state when receiving an instruction to cancel the power saving state. The device that is not put into the hibernation state during the power saving state includes a means for determining whether or not the power saving state can be entered when there is an inquiry from the processor and notifying the processor of the determination result,
The electronic device according to claim 5, wherein the processor is configured to issue the predetermined instruction when notified that the device can enter a power saving state. A processor, a power source, and a plurality of devices that are powered from the power source and connected to the same bus, and that are configured to issue power to a device that consumes more power among the plurality of devices according to a predetermined instruction issued by the processor An electronic device that connects the device and the bus of an electronic device that enters a power saving state while maintaining power supply from the power source to a device that cannot be put into a hibernation state by stopping power feeding from the power source In the device-bus connection circuit of
In the first state, the electrical connection of the input / output terminals including the connection with the bus is permitted, and in the second state, the electrical connection of the input / output terminals including the connection with the bus is cut off so that the high impedance state is established. I / O terminal connection means to maintain,
When the predetermined instruction is received, the input / output terminal connecting means is switched to the second state, and when the instruction to cancel the power saving state issued by the processor is received, the input / output terminal connecting means is A device-bus connection circuit for an electronic device, comprising: means for switching to a first state.

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