JP2011008310A - Data processing device, method and program for controlling power saving, and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing device appropriately coping with illegal access to a module in a power-saving state, a power saving control method, a power saving control program and a recording medium.SOLUTION: An ASIC 16 of a composite device includes a power source control part 25 controlling power supply/stop to a plurality of controllers 30-33 individually, and a proxy replying part 22 detecting the presence of access from a bus master to the controllers 30-33 and making a predetermined proxy reply to the access instead of the controllers 30-33 when there is access from the bus master to the controllers 30-33 which are in the power supply stopped state. The bus master is thereby informed of the occurrence of illegal data access in the stopped state of power supply to the accessed controllers 30-33 to prevent data destruction and continuation of operation based on illegal data.

Description

  The present invention relates to a data processing apparatus, a power saving control method, a power saving control program, and a recording medium, and more particularly, a data processing apparatus and power saving that appropriately cope with unauthorized access to a module whose power supply is stopped in a power saving state. The present invention relates to a control method, a power saving control program, and a recording medium.

  In a data processing apparatus such as a copying apparatus, a facsimile apparatus, a printer apparatus, a scanner apparatus, and a computer, particularly in a composite apparatus in which a plurality of functions such as a copying function, a facsimile function, a printing function, a scanner function, and a data transfer function are incorporated. Even if it is not in use, power consumption is large when power is turned on. Conventionally, in order to reduce power consumption, it is in a standby state without being used after power is turned on. When a certain period of time elapses, requests from the network, operation request operations (button operations such as the power button on the operation display unit, manuscript setting operations on the ADF (Auto Document Feeder), pressure plate opening / closing operations, etc.) are detected. Power saving mode that reduces power consumption by supplying power only to some functional parts such as the return detection unit and stopping the supply of power to other parts. It is equipped with a de.

  In recent years, data processing apparatuses are equipped with a semiconductor integrated circuit such as an ASIC (Application Specific Integrated Circuit) equipped with a plurality of functional modules for performing data processing, and various types of data processing devices are controlled under the control of a main CPU (Central Processing Unit). Data processing is in progress.

  Further, in recent years, in a data processing apparatus equipped with a power saving mode, in addition to the main CPU, in order to further stop power supply to the main CPU and further reduce power consumption, In addition to providing a sub CPU that activates the main CPU when a recovery factor occurs, a non-volatile storage medium that stores the recovery conditions when entering the power saving mode is provided, and power supply to each unit including the main CPU is stopped. However, data processing apparatuses that continue to supply power to sub-CPUs have appeared.

  The ASIC has a plurality of function modules, and there are a function module in which power supply is stopped in the power saving mode and a function module in which power is continuously supplied. In the power saving mode, power supply is stopped. If a processing instruction is executed illegally or mistakenly on a functional module, illegal memory access or register access may occur, which may destroy data or cause a malfunction.

  Therefore, conventionally, a first circuit (such as a functional module) connected to a central processing unit (such as a CPU) via an internal bus and a stop control circuit that selectively stops the operation of the functional module are included. When an instruction to use the functional module is issued from the central processing unit while the operation of the functional module is stopped, the stop control circuit issues an operation stop signal to the central processing unit, and the central processing unit Has been proposed, a technique of starting an instruction execution operation after releasing the operation stop state of the functional module has been proposed (see Patent Document 1).

  However, in the prior art described in the above publication, if an instruction is issued from the central processing unit while the function module is stopped, the instruction execution operation is started after the operation stop state for the function module is released. Therefore, when the above technique is applied to a semiconductor integrated circuit such as an ASIC, when an operation command is issued from the CPU to a functional module whose power supply is stopped in the power saving mode, power supply to the functional module is performed. After the operation is resumed, the functional module is operated.

  However, in an ASIC (semiconductor integrated circuit) equipped with a plurality of function modules, when an operation command is issued to a function module for which power supply is stopped, the supply of power to the function module is simply resumed. When operated, there is a problem that current wraparound unintended by design occurs and the life of the ASIC is shortened.

  In other words, as described above, a semiconductor integrated circuit, for example, an ASIC has a plurality of functional modules, and a functional module in which power supply is stopped in a power saving mode and a functional module in which power supply is continued. In addition, an interruption order and a supply order of power to the functional modules (in particular, a power supply order, hereinafter referred to as a power supply order) are set in advance from the functional type and cost of the functional modules, and the power supply order. A circuit called an isolation cell is inserted to prevent a malfunction from occurring in the functional module only for the power supply operation according to the standard. Therefore, for the power cut-off / power-on operation in accordance with such a preset power supply sequence, the isolation cell is connected to a region where power is supplied from a region where power is cut off. An intermediate potential is applied to the signal line to prevent a current wraparound that is not assumed in the circuit configuration from occurring, thereby preventing the life of the ASIC from being shortened.

  For example, as shown in FIG. 3, the ASIC 100 includes a power supply control unit 101 and three power supply regions RA, RB, and RC each centered on functional modules MA, MB, and MC. An isolation cell 102 is inserted between the signal lines to the MA, and an isolation cell 103 is inserted between the signal lines from the functional module MC to the functional module MB. In the ASIC 100, power is directly supplied to the power control unit 101 and the module MA through the power switch 110, and is supplied to the function module MB and the function module MC through the switch elements 104 and 105, respectively. . Then, the power supply control unit 101 turns on / off the switch element 104 by the control signal PWR_B_CTL to control the supply and interruption of power to the functional module MB, and turns on / off the isolation cell 102 by the control signal ISO_B_CTL. To control. Further, the power supply control unit 101 turns on / off the switch element 103 by the control signal PWR_C_CTL to control the supply and interruption of power to the functional module MC, and turns on / off the isolation cell 103 by the control signal ISO_C_CTL. To control. The isolation cell 102 prevents an intermediate potential from being applied to a signal input from the functional module MB to the functional module MA when the power of the functional module MB is cut off. The isolation cell 103 At the time of interruption, an intermediate potential is prevented from being applied to a signal input from the functional module MC to the functional module MB.

  In the ASIC 100 having such a configuration, as shown in FIG. 4, the power supply / cut-off timing to the functional modules MA to MC is shown. At the timing T1, the power of the entire ASIC 100 is cut off, and the power supply regions RA, RB, and RC are All power is cut off.

  At timing T2, when the power switch 110 of the image forming apparatus is turned on, power is directly supplied to the functional module MA and the power supply region RA is in a power supply state, and the power control unit 101 controls the control signal ISO_C_CTL, The signal PWR_C_CTL, the control signal ISO_B_CTL, and the control signal PWR_B_CTL are turned on, and the functional module MC and its power supply region RC and the functional module MB and its power supply region RB are also in a power supply state.

  Thereafter, when the image forming apparatus shifts to the power saving mode or the like and cuts off the power supply of the ASIC 100, first, at timing T3, the power supply control unit 101 enables (turns off) the isolation cell 103 by the control signal ISO_C_CTL. At timing T4, the switch element 105 is turned off by the control signal PWR_C_CTL to cut off the power supply to the functional module MC. The combination of power supply / cutoff in the ASIC 100 at this timing is such that the power of the functional module MA and its power supply area RA is on, the power of the functional module MB and its power supply area RB is on, and the functional module MC and its power supply area RC. The power is on.

  Next, at timing T5, the isolation cell 102 is enabled (turned off) by the control signal ISO_B_CTL, and at timing T6, the power supply of the functional module MB is cut off by the control signal PWR_B_CTL. The combination of power supply / cutoff in the ASIC 100 at this timing is that the power of the functional module MA and its power supply area RA is on, and the power of the other functional modules MB, its power supply area RB, the functional module MC, and its power supply area RC. Is turned off to enter the power saving mode.

  When any energy saving return factor occurs at timing T7, the power supply control unit 101 first turns on the switch element 104 by the control signal PWR_B_CTL to supply power to the functional module MB. At timing T8, the control is performed. The isolation cell 102 is disabled (turned on) by the signal ISO_B_CTL.

  The combination of power supply / cutoff in the ASIC 100 at this timing is such that the power of the functional module MA and its power supply area RA and the functional module MB and its power supply area RB is ON, and the power of the functional module MC and its power supply area RC is It is in an off state.

  At timing T9, the power supply control unit 101 turns on the switch element 105 by the control signal PWR_C_CTL to supply power to the functional module MC and its power supply region RC. At timing T10, the power supply control unit 101 performs isolation by using the control signal ISO_C_CTL. The cell 103 is disabled (off). In the combination of power supply / cutoff in the ASIC 100 at this timing, the power of all the functional modules MA, MB, MC and their power supply regions RA, RB, RC is turned on and the normal operation state is restored.

  However, when the operation of the function modules MB and MC in the ASIC 100 is stopped by shifting to the power saving mode, the processing execution instruction is improperly or mistakenly applied to the function modules MB and MC whose power supply is stopped. If executed, illegal memory access or register access may occur, and data may be destroyed or malfunction may occur.

  For example, when the function module MA and its power supply area RA are powered on, the function module MB and its power supply area RB, and the function module MC and its power supply area RC are powered off, the CPU is erroneously stopped from supplying power. When an operation command is issued to the functional module MC, in the prior art described in the above publication, the operation is performed after the supply of power to the functional module MC is started.

  However, in the ASIC 100, the power supply order to the function modules MB and MC is set in advance. When power is not supplied in the set order, an illegal signal is sent to the function modules MB and MA. There is a risk of data being corrupted or malfunctioning. In the ASIC 100, as shown in FIG. 4, the power supply order is set so that the function module MB is first and then the power is supplied to the function module MC. As described above, when the CPU issues an operation command to the functional module MC, power is supplied to the functional module MC before the functional module MB, and an unintended current wraparound occurs in the design of the ASIC 100, and the ASIC There is a risk of shortening the life of the product. Therefore, when access is made to a function module whose power supply is stopped from a bus master such as a CPU or DMAC (Direct Memory Access Controller: DMA controller), the power to the function module in which the access has occurred is simply as in the prior art. The operation cannot be resumed by restarting the supply.

  In addition, recent image forming apparatuses such as composite apparatuses and semiconductor integrated circuits (ASIC, etc.) used in the image forming apparatus have complicated software, and therefore, consider convenience for software failure analysis. Therefore, it has become common to incorporate functions for failure analysis into hardware. For example, if the CPU goes out of control due to some sort of malfunction, it has been equipped with a watch dog timer (Watch Dog Timer) that restarts the system. Cannot be specified. In order to investigate the cause of a problem that causes an operation command to be issued to a functional module whose power supply has been stopped, an exception processing routine is executed and an operation log or It is desirable to execute a process that leaves a history of the cause of the failure.

  Therefore, the present invention stops the power supply to the functional operation means when an access to the functional operation means for which power supply is stopped is generated among a plurality of functional operation means for which power is supplied / stopped. Data processing device, power-saving control method, and power saving that prevent the operation from being continued due to data corruption due to illegal memory access or register access or illegal data reading. An object is to provide a power control program and a recording medium.

  In order to achieve the above object, the present invention individually controls the supply / stop of power to a plurality of function operation means that execute various functions upon receiving power supply and operate in response to access from a bus master. When the presence or absence of access from the bus master to the functional operation means is detected, and there is an access from the bus master to the functional operation means for which power supply has been stopped, the predetermined access to the function operation means is determined on behalf of the functional operation means. The above purpose is achieved by performing a proxy response.

  Further, the present invention determines whether or not the bus master that has accessed the functional operation means for which power supply has been stopped is a sub CPU. If the bus master is a sub CPU, An NG response may be made to the CPU.

  Further, according to the present invention, when the bus master that has accessed the function operating means during the power supply stop is a bus master other than the sub CPU, an NG response is made to the bus master as the proxy response, and the function The sub CPU may be notified that the operation means has been illegally accessed, and an OK response is sent to the bus master, and the function operation means has been illegally accessed. It may be characterized by notifying the CPU.

  Further, the present invention may be characterized in that if the access made by the bus master to the function operation means that is stopped supplying power is a read access, an NG response is sent to the bus master as the proxy response. .

  According to the present invention, when access is made to a function operating unit that is in the power supply stop state, the power supply to the function operating unit is stopped. Thus, it is possible to prevent the life from being shortened by maintaining the state, and to appropriately prevent continuation of operation due to data destruction by illegal memory access or register access or illegal data reading.

The principal part block block diagram of the compound apparatus to which one Example of this invention is applied. The detailed block block diagram of ASIC. The block block diagram which shows an example of the ASIC in which the conventional power supply measure is taken. The figure which shows the electric power interruption / supply timing of each function module in the conventional ASIC.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  1 and 2 are diagrams showing an embodiment of a data processing apparatus, a power saving control method, a power saving control program, and a recording medium according to the present invention. FIG. 1 shows a data processing apparatus, power saving control according to the present invention. It is a principal block block diagram of the compound apparatus 1 to which an embodiment of a method, a power saving control program, and a recording medium is applied.

  In FIG. 1, the composite apparatus 1 includes an engine unit 2 and a controller 3, and includes an operation display unit, a facsimile communication unit, a network communication unit, and a hard disk (not shown). The operation display unit includes operation keys for performing various operations, a display for displaying necessary information, and the like, and the facsimile communication unit performs facsimile communication using an external public line or the like. The network communication unit transfers data such as image data via a network such as a LAN (Local Area Network).

  The engine unit 2 is a general term for engines such as scanners and plotters. For example, an image scanner using a CCD (Charge Coupled Device) or the like is used as the scanner, and generally includes an ADF (automatic document feeder). A plurality of documents are set in the ADF, and the ADF feeds the set documents one by one to the document reading position of the scanner 2. The scanner scans the document conveyed from the ADF, reads an image of the document with a predetermined resolution, binarizes it, and outputs it to the controller unit 3. The plotter is, for example, an electrophotographic recording apparatus or the like, and the plotter records and outputs an image of a document read by a scanner or a received image received by a facsimile communication unit or a network communication unit (not shown) on a recording sheet. , Record the necessary report on the recording paper.

  The controller 3 includes a main CPU (Central Processing Unit) 10, an operation display I / F 11, an option I / F 12, a main memory (MEM) 13, a main ROM 14, an NVRAM (Nonvolatile Random Access Memory) 15, an ASIC 16, a sub ROM 17, and the like. The overall control, drawing, communication, control of input data from the operation display unit and display data to the operation display unit, and the like are performed.

  The main ROM 14 stores a basic control program and necessary system data as the composite device 1, and the main memory 13 is configured by a RAM (Random Access Memory) or the like and is used as a work memory of the main CPU 10. Temporary storage of data such as image data. The NVRAM 15 is a memory that retains stored contents even when the power of the multifunction device 1 is turned off, and stores data that needs to be retained even when the power of the multifunction device 1 is turned off under the control of the main CPU 10. Is done. The main CPU 10 uses the main memory 13 as a work memory based on a program in the main ROM 14, controls each part of the composite device 1, and executes processing as the composite device 1.

  An operation display unit is connected to the operation display I / F 11, and the operation display I / F 11 passes input data from the operation display unit to the main CPU 10 and outputs display data from the main CPU 10 to the operation display unit. .

  The option I / F 12 is an interface for connecting an option unit such as a facsimile or a printer application.

  The ASIC 16 includes a sub CPU 21 and, as shown in FIG. 2, a proxy response unit 22, an SRAM (Static RAM) 23, a local bus controller 24, a power supply control unit 25, a UART 26, a GIO 27, an interrupt controller 28, and a timer unit. 29, a network controller 30, a USB device controller 31, a PCIe (Peripheral Component Interconnect Express) controller 32, an encryption controller 33, and the like. The above-described units are connected by an internal bus 34 and various signal lines. The ASIC 16 supplies / powers to the network controller 30, USB (Universal Serial Bus) device controller 31, PCIe controller 32, and encryption controller 33, which are functional operation means, by supplying / stopping power to these controllers. Power supply regions 30RA, 31RA, 32RA, and 33RA for which supply is stopped are formed. In addition, the network controller 30 and the USB device controller 31 have a built-in DMAC and transmit / receive data on the SRAM 23 or the PCIe.

  The sub ROM 17 stores a basic application program executed by the sub CPU 21 of the ASIC 16, a power saving control program of the present invention, and necessary data. The sub CPU 21 is based on the program of the sub ROM 17 when the main CPU 10 stops operation. The entire composite apparatus 1 is controlled.

  The proxy response unit (proxy response means) 22 appropriately performs a proxy response when an access from the bus master whose power supply is stopped to the troller 30, the USB device controller 31, the PCIe controller 32, and the encryption controller 33 occurs. Notify the bus master that there was an unauthorized access.

  Which of the controllers 30 to 33 among the network controller 30, USB device controller 31, PCIe controller 32, and encryption controller 33 is subjected to a proxy response is controlled by a control signal BUS_CTL from the power supply control unit 25.

  The SRAM 23 stores work data and the like of the sub CPU 21, and the local bus controller 24 performs access control to a memory such as the sub ROM 17 and the RAM outside the AISC 16.

  The power control unit (power control means) 25 performs internal and external power control (power control) of the ASIC 16, and in particular, a network controller power supply area 30RA, a USB device controller power supply area 31RA, and a PCIe power supply area 32RA by a control signal PWR_CTL. In addition, control of power supply / supply stop (shut off) to the cryptographic controller power supply region 33RA is performed, and although not shown, the isolation cells between the functional modules 30 to 33 are controlled.

  The power supply control unit 25 controls the start of the operation of the proxy response unit 22 by the control signal BUS_CTL.

  The UART unit 26 performs communication control of a UART (asynchronous serial communication line), and the GIO unit 27 is a general-purpose input / output port. In particular, in the power saving mode, the operation unit presses the power button or the engine unit 2 It has an input port for monitoring whether or not a power saving mode return factor has occurred, such as whether paper is set in the ADF or whether the platen has operated.

  The interrupt controller 28 monitors interrupts from inside and outside of the ASIC 16 and causes the sub CPU 21 to generate interrupt exception processing.

  The timer unit 29 has an interval timer and a watchdog timer function for monitoring the runaway of the sub CPU 21.

  The network controller 30 is connected to a network such as an Ethernet (registered trademark) LAN (Local Area Network), and a personal computer or the like is connected to the network. The network controller 30 performs Ethernet communication control.

  The USB device controller 31 is connected to a USB device such as a personal computer or a memory, and the USB device controller 31 exchanges data with the connected USB device.

  A PCIe bus is connected to the PCIe controller 32, and the PCIe controller 32 performs PCIe communication control using the PCIe bus. In the composite apparatus 1 of this embodiment, the main CPU 10 and the ASIC 16 are connected by a PCIe bus.

The encryption controller 33 performs encryption of plain text data and plain culture of encryption data corresponding to network transmission / reception in an IPsec (Security Architecture for Internet Protocol) environment.
The ASIC 16 is internally separated into a network controller power supply area 30RA, a USB device controller power supply area 31RA, a PCIe power supply area 32RA, an encryption controller power supply area 33RA, and other power supply areas (not shown). The power supply / supply stop of the network controller power supply area 30RA, USB device controller power supply area 31RA, PCIe power supply area 32RA, and encryption controller power supply area 33RA is controlled.

  In the normal operation mode, the ASIC 16 supplies power to all the power supply areas such as all the power supply areas 30RA to 33RA in the ASIC 16, and in the power saving mode, the network controller 30, the USB device controller 31, Whether the power supply to the PCIe controller 32 and the encryption controller 33 is selectively cut off and the power supply to any of the controllers 30 to 33 is cut off depends on the power saving mode of the multifunction apparatus 1.

  The composite apparatus 1 includes a ROM, an EEPROM (Electrically Erasable and Programmable Read Only Memory), an EPROM, a flash memory, a flexible disk, a CD-ROM (Compact Disc Read Only Memory), a CD-RW (Compact Disc Rewritable), and a DVD (Digital Video). A power saving control program for executing the power saving control method of the present invention recorded on a computer-readable recording medium such as a disk (SD), a secure digital (SD) card, or an MO (Magneto-Optical Disc). By installing it in the sub ROM 17 referred to by the sub CPU 21, it is constructed as a data processing device that appropriately performs the corresponding processing when there is an access to the controllers 30 to 33 that are powered off during power saving, which will be described later. ing. This power saving control program is a computer-executable program written in a legacy programming language such as assembler, C, C ++, C #, Java (registered trademark) or an object-oriented programming language, and is stored in the recording medium. And can be distributed.

  Next, the operation of this embodiment will be described. When there is an access to the controllers 30 to 33 whose power supply is interrupted in the power saving mode, the composite apparatus 1 according to the present embodiment appropriately makes a proxy response to the access.

  That is, in the normal state where the main power is turned on, the composite apparatus 1 performs, for example, image data of a document read by the scanner of the engine unit 2 on the controller 3 and then performs the necessary image processing on the engine unit 2. Image processing such as outputting an image on a sheet with a plotter.

  The composite apparatus 1 includes a power saving mode for reducing or stopping the supply of power to the main components when a predetermined waiting time that has been set in advance has passed since the main power supply was turned on and there is no operation request. In the power saving mode, the main CPU 10 is de-energized and the ASIC 16 is energized to the sub CPU 21 so that the sub CPU 21 performs overall control of the composite apparatus 1 required in the power saving mode, and the ASIC 16 Internally, the power supply control unit 25 controls the supply / cutoff of power to the controllers 30 to 33, and the sub CPU 21 or the DMAC or the like accesses the controller 30 to 33 being cut off of power supply by mistake or illegally as a bus master. When this occurs, the proxy response unit 22 changes to the controllers 30 to 33 and makes a proxy response. Perform appropriate measures against.

  That is, when the ASIC 16 shifts to the power saving mode, the sub CPU 21 accesses the power control unit 25 and negates the power control signal PWR_CTL to the controllers 30 to 33 that cut off the supply of power. -33 and the power supply areas 30RA-33RA are asserted with a control signal BUS_CTL that controls a proxy response to an access to the controllers 30-33 that cut off the power supply to the proxy response path 22 and The operation of the response unit 22 is started.

  For example, when cutting off the power supply to the PCIe controller 32 and the PCIe power supply area 32RA in the power saving mode, the sub CPU 21 accesses the internal register of the power supply control unit 25 and negates the power supply control signal PWR_CTL of the PCIe controller 32. Then, power supply to the PCIe 32 and the PCIe power source area 32RA is cut off. At the same time, the sub CPU 21 causes the power supply control unit 25 to assert the control signal BUS_CTL for controlling the proxy response of the PCIe controller 32 and starts the operation of the proxy response unit 22.

  In this state, when the bus master (sub CPU 21 or DMAC or the like) accesses the register space or the memory space of the controllers 30 to 33, for example, the PCIe controller 32, in which power supply is stopped, the proxy response unit 22 In response, an NG response on the bus protocol or an OK response is returned.

  As described above, in the composite apparatus 1 of this embodiment, the ASIC 16 performs various functions upon receiving power supply, and supplies / stops power to the plurality of controllers 30 to 33 that operate in response to access from the bus master. Are individually controlled by the power supply control unit 25, and the proxy response unit 22 detects the presence or absence of access from the bus master to the controllers 30 to 33, and from the bus master to the controllers 30 to 33 whose power supply has been stopped. When there is an access, a predetermined proxy response is made to the access on behalf of the controllers 30-33.

  Therefore, the internal bus 34 is locked and the operation is not stopped, and the power supply to the controller (functional module) 30 to 33 in which the access has occurred is stopped and the bus master is notified that an illegal data access has occurred. Therefore, it is possible to prevent the data from being destroyed by illegal memory access or register access or illegal data from being read and continuing the operation.

  Further, in the composite apparatus 1, the proxy response unit 22 of the ASIC 16 has a function of determining whether or not the bus master is the sub CPU 21, and the bus master that has accessed the controllers 30 to 33 whose power supply has been stopped. Is the sub CPU 21, and if the bus master is the sub CPU 21, an NG response is returned to the sub CPU 21.

  In this case, the sub CPU 21 recognizes that the access is NG, and executes a process corresponding to the illegal or incorrect access, for example, an exception process. The sub CPU 2 can record a log for elucidating the cause of unauthorized access or incorrect access by executing exception processing.

  Therefore, the proxy response unit 22 returns an NG response to the sub CPU 21 that is the bus master, thereby notifying the sub CPU 21 that an illegal data access by the sub CPU 21 has occurred, and destroying data due to illegal memory access or register access. It is possible to notify that there is a possibility of occurrence of an error or that illegal data has been read out, and it is possible to keep a record of the occurrence of a malfunction.

  For example, when the bus master is the sub CPU 21 and the sub CPU 21 erroneously accesses the PCIe controller 32 in the power saving mode, the proxy response unit 22 makes a proxy response and returns an NG response to the sub CPU 21. When the sub CPU 21 receives the NG response, it internally generates a bus error exception and executes an exception processing routine.

  Furthermore, in the composite apparatus 1 of the present embodiment, the proxy response unit 22 of the ASIC 16 similarly determines whether or not the bus master that has accessed the controllers 30 to 33 whose power supply has been stopped is the sub CPU 21. When the bus master that has accessed the controllers 30 to 33 whose power supply has been stopped is other than the sub CPU 21, an NG response is returned to the bus master other than the sub CPU 21, and a preset value is set for the sub CPU 21. Cause exception handling to occur. The sub CPU 21 records a log for elucidating the cause of unauthorized access or incorrect access by executing this exception processing.

  For example, when the bus master is other than the sub CPU 21, for example, DMAC, when the DMAC erroneously accesses the PCIe controller 32 in the power saving mode, the proxy response unit 22 makes a proxy response and returns an NG response to the DMAC. Then, an exception handling interrupt is generated for the sub CPU 21. The sub CPU 21 executes an exception handling routine by an interrupt from the proxy response unit 22.

  Therefore, the proxy response unit 22 generates an interrupt notifying the sub CPU 21 of the occurrence of an unauthorized access or an incorrect access, thereby notifying the sub CPU 21 that an illegal data access by the bus master has occurred. It is possible to notify that data has been destroyed due to memory access or register access or that illegal data has been read, and a record of the occurrence of a malfunction can be left.

  In the composite apparatus 11 of this embodiment, the proxy response unit 22 determines whether or not the bus master is the sub CPU 21. If the bus master is other than the sub CPU 21, the proxy response unit 22 returns an OK response to the bus master. Then, exception processing is generated for the sub CPU 21. The sub CPU 21 records a log for elucidating the cause of unauthorized access or incorrect access by executing this exception processing.

  Therefore, power is supplied to the controllers (functional modules) 30 to 33 that have been accessed without stopping the operation because the internal bus 34 is locked to the bus master that terminates the operation when an OK response is returned. The bus master that has been accessed can be properly terminated while it is stopped.

  In addition, the proxy response unit 22 determines whether the bus master access to the controllers 30 to 33 whose power supply is stopped is a write access or a read access. The proxy response unit 22 returns an OK response to the bus master in the case of write access, and returns an NG response in the case of read access.

  Therefore, for the bus master that terminates the operation by returning an NG response only in the case of read access, the accessing bus master can be appropriately terminated while the power supply to the controllers 30 to 33 that have been accessed is stopped. it can.

  In addition, as described above, the proxy response unit 22 may cause a problem even if the controller 30 to 33 starts to supply power at the access timing based on the preset power supply order of the controllers 30 to 33. If there is no controller 30 to 33 that does not have a problem even if the controller 30 to 33 that determines that there is no problem even if it starts the supply of power Assert the control signal PWR_REQ to the power supply control unit 25 to notify the controllers 30 to 33 to supply power.

  In this case, even if the power supply is started at the access timing, in the case of the controllers 30 to 33 that are allowed to supply power according to the power supply start order, the controller 30 to the power supply control unit 25. The operation can be continued after the power supply to 33 is requested and the power supply is started.

  Although the invention made by the present inventor has been specifically described based on the preferred embodiments, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  The present invention relates to a data processing apparatus such as a composite apparatus, a copying apparatus, a printer apparatus, a personal computer, or the like equipped with a semiconductor integrated circuit such as an ASIC which stops power supply by stopping power supply to a predetermined functional module in a standby state, The present invention can be used for a power saving control method, a power saving control program, and a recording medium.

DESCRIPTION OF SYMBOLS 1 Compound apparatus 2 Engine part 3 Controller 10 Main CPU
11 Operation display I / F
12 Option I / F
13 Main memory (MEM)
14 Main ROM
15 NVRAM
16 ASIC
17 Sub ROM
21 Sub CPU
22 Proxy response unit 23 SRAM
24 Local Bus Controller 25 Power Supply Control Unit 26 UART
27 GIO
28 Interrupt Controller 29 Timer Unit 30 Network Controller 31 USB Device Controller 32 PCIe Controller 33 Cryptographic Controller 34 Internal Bus

JP 2004-152321 A

Claims (9)

A plurality of functional operation means that perform various functions upon receiving power supply and operate in response to access from the bus master;
Power control means for individually controlling supply / stop of power to the function operation means;
The presence or absence of access from the bus master to the functional operation means is detected, and when there is an access from the bus master to the functional operation means for which power supply is stopped by the power control means, the access is performed instead of the functional operation means. Proxy response means for performing a predetermined proxy response to
A data processing apparatus comprising: The data processing device includes:
A sub CPU that performs various control processes by supplying power even when power supply to the functional operation unit is stopped by the power control unit;
Determining means for determining whether or not the bus master that has accessed the function operating means for which power supply has been stopped is the sub CPU;
Further comprising
When the determination unit determines that the bus master that has accessed the function operation unit that has stopped power supply is the sub CPU, the proxy response unit sends an NG response to the sub CPU as the proxy response. The data processing apparatus according to claim 1, wherein the data processing apparatus performs the processing. The data processing device includes:
A sub CPU that performs various control processes by supplying power even when power supply to the functional operation unit is stopped by the power control unit;
Determining means for determining whether or not the bus master that has accessed the function operating means for which power supply has been stopped is the sub CPU;
Further comprising
When the determination means determines that the bus master that has accessed the function operation means that is not in power supply is a bus master other than the sub CPU, the proxy response means determines that the bus master is NG as the proxy response. 2. The data processing apparatus according to claim 1, wherein a response is made and the sub CPU is notified that the function operating means has been illegally accessed. The data processing device includes:
A sub CPU that performs various control processes by supplying power even when power supply to the functional operation unit is stopped by the power control unit;
Determination means for determining whether or not the bus master that has accessed the functional operation means for which power supply has been stopped is the sub CPU; and
When the determination means determines that the bus master that has accessed the function operation means that is stopped in power supply is a bus master other than the sub CPU, the proxy response means is OK with respect to the bus master as the proxy response. 2. The data processing apparatus according to claim 1, wherein a response is made and the sub CPU is notified that the function operating means has been illegally accessed. The data processing device includes:
An access type determination unit that determines whether or not an access generated from a bus master is a read access to the functional operation unit for which power supply is stopped by the power control unit;
When the access type determination unit determines that the access made by the bus master to the functional operation unit whose power supply is stopped is the read access, the proxy response unit returns NG to the bus master as the proxy response. The data processing apparatus according to claim 1, wherein a response is made. The data processing device includes:
When an access from the bus master occurs to the functional operation means for which power supply has been stopped, starting the power supply to the functional operation means at the timing when the access has occurred means that the power supply is A power supply availability determination unit that determines whether or not a plurality of the function operation units that are stopped is allowed for a preset power supply sequence;
The proxy response unit determines that the power supply availability determination unit determines that the function operation unit is allowed to start supplying power when access is made to the function operation unit that has stopped power supply. Then, the data processing apparatus according to claim 1, wherein the power control unit is requested to supply power to the functional operation unit as the proxy response. A power control processing step for performing various functions in response to power supply and individually controlling supply / stop of power to a plurality of function operating means operating in response to access from the bus master;
The presence or absence of access from the bus master to the functional operation means is detected, and when there is an access from the bus master to the functional operation means for which power supply is stopped by the power control processing step, the functional operation means is replaced with the functional operation means. A proxy response processing step for performing a predetermined proxy response to access;
A power saving control method characterized by comprising: On the computer,
A power control process for performing various functions in response to power supply and individually controlling supply / stop of power to a plurality of function operating means operating in response to access from the bus master;
The presence or absence of access from the bus master to the functional operation means is detected, and when there is an access from the bus master to the functional operation means whose power supply is stopped by the power control processing, the access is performed instead of the functional operation means. Proxy response processing to perform a predetermined proxy response to,
A power-saving control program characterized by causing   A computer-readable recording medium on which the power saving control program according to claim 8 is recorded.

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