JP2005091644A - Manufacturing method and inspection method for electrooptic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To remarkably enhance inspection efficiency by detecting a pixel defect by an electric inspection at a substrate state. <P>SOLUTION: A manufacturing method for an electrooptic device is equipped with: a film deposition step (a step S1) for depositing film of pixel electrode materials on the whole surface of an active matrix substrate; a first patterning step (steps S2 to S4) for depositing electrode material film over a plurality of pixels in a pixel area by patterning the film of pixel electrode materials and a second patterning step (steps S7 to S9) for forming pixel electrodes by patterning the electrode material film for each pixel. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a manufacturing method and an inspection method of an electro-optical device suitable for a liquid crystal substrate having a laminated structure.

  In general, an electro-optical device, for example, a liquid crystal device that performs predetermined display using liquid crystal as an electro-optical material has a configuration in which liquid crystal is sandwiched between a pair of substrates. Among these, in an electro-optical device such as an active matrix driving type liquid crystal device by TFT driving, TFD driving, etc., at each intersection of a large number of scanning lines (gate lines) and data lines (source lines) arranged vertically and horizontally. Correspondingly, a pixel electrode and a switching element are provided on a substrate (active matrix substrate).

  A switching element such as a TFT element is turned on by an on signal supplied to the gate line, and an image signal supplied via the source line is written to the pixel electrode (transparent electrode (ITO)). Thereby, a voltage based on the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode to change the arrangement of the liquid crystal molecules. In this way, the transmittance of the pixel is changed, and light passing through the pixel electrode and the liquid crystal layer is changed according to the image signal to perform image display. In addition, since the supply of such an image signal is performed only for a very short time for each pixel electrode, in order to hold the voltage of the image signal for a much longer time than the time when the image signal is turned on, A storage capacitor is generally added to the pixel electrode.

  An active matrix substrate having a switching element such as a TFT element is formed by laminating a semiconductor thin film, an insulating thin film (interlayer insulating film) or a conductive thin film having a predetermined pattern on a glass or quartz substrate. That is, a TFT substrate and the like are formed by repeating a film forming process of various films and a photolithography process.

  For example, an interlayer insulating film is also formed between the semiconductor layer constituting the TFT element and the upper and lower deposited layers. The source and drain regions in the semiconductor layer and the upper and lower layers are electrically connected through contact holes opened in the interlayer insulating film.

For example, in the case where a capacitor layer is formed between the TFT element and the pixel electrode in order to obtain a sufficient capacity as a storage capacitor, the drain region in the semiconductor layer is connected to the pixel electrode via the capacitor layer in the element layout It may be connected to. In this case, the drain region and the pixel electrode are connected through two contact holes, a contact hole between the drain region and the capacitor layer and a contact hole between the capacitor layer and the pixel electrode. .
JP-A-10-90711

  By the way, in order to detect a pixel defect or the like of the TFT substrate manufactured by repeating the film forming process and the photolithography process, an electrical property inspection is performed on the active matrix substrate in a mother glass substrate state. In this case, with respect to the source region and the storage capacitor, by forming pads (PAD) connected to these on the substrate, it is possible to connect a probe for electrical property inspection to these regions via the PAD. .

  However, since the pixel electrode is extremely small, it is impossible to perform an electrical characteristic inspection in which a probe is connected to each pixel electrode. Therefore, the short-circuit inspection between the pixel electrodes (ITO) is performed by electrically connecting the probe to the source region of adjacent pixels.

  That is, when inspecting a short circuit between a predetermined pixel and a pixel electrode of an adjacent pixel, an ON voltage is applied to the gates of these pixels, and a current flowing from the source region of the predetermined pixel is applied to the adjacent pixels. A short circuit between pixels is detected depending on whether or not it flows into the source region. If no current flows in the source region of the adjacent pixel, the pixel electrodes are not short-circuited and are determined to be non-defective.

  For example, as a method for detecting such a pixel defect, there is one disclosed in Patent Document 1.

  However, even when a defect occurs in the contact between the drain and the pixel electrode, no current flows in the source region of the adjacent pixel. Therefore, in this case, a short circuit of the pixel electrode cannot be detected, and even if the pixel electrode is short-circuited, it may be determined as a non-defective product by this inspection.

  For this reason, in reality, a defect such as a short circuit of the pixel electrode is inspected by visual observation after applying electricity in a state where the TFT substrate and the counter substrate are bonded together and liquid crystal is sealed. Since the probe cannot be directly connected to the pixel electrode, each pixel electrode cannot be inspected by electrical inspection, but is inspected through liquid crystal.

  Such visual inspection requires a great deal of time and effort. In particular, in recent years, a large number of TFT substrates have been formed on a single mother glass substrate, and the visual inspection has a problem that inspection efficiency is extremely low.

  By the way, when the pixel electrode is formed by patterning ITO, the ITO may be peeled off and reattached in a photolithography and etching process, thereby causing a short circuit of the pixel electrode. In order to prevent such a short circuit due to the redeposition of ITO, the W (double) ITO method in which the same patterning for pixel electrode formation is repeated twice may be employed.

  However, in the case of WITO, the edge of the ITO may be lost due to misalignment of the mask during the first and second patterning, and there is a drawback that mass production is difficult when miniaturization is considered.

  The present invention has been made in view of such a problem, and by detecting a defect of each pixel by an electrical inspection in a substrate state, the inspection efficiency can be remarkably improved and mask alignment is performed. An object of the present invention is to provide an electro-optical device manufacturing method and an inspection method capable of reliably preventing a short circuit of a pixel electrode by performing patterning twice without causing a shift.

  The electro-optical device manufacturing method according to the present invention includes a film forming step of forming a film of a pixel electrode material on an entire surface of an active matrix substrate, and patterning the film of the pixel electrode material to form a plurality of pixels in a pixel region. A first patterning step of forming an electrode material film straddling and a second patterning step of patterning the electrode material film for each pixel to form a pixel electrode are provided.

  According to such a configuration, the film of the pixel electrode material is formed on the entire surface of the active matrix substrate in the film forming process. Next, in the first patterning step, the pixel electrode material film is patterned to form an electrode material film straddling a plurality of pixels in the pixel region. Further, in the second patterning step, the electrode material film is applied to each pixel. A pixel electrode is formed by patterning every time. The pixel electrode is obtained by patterning through two patterning steps, and a short circuit due to redeposition after the pixel electrode material is peeled off can be prevented. Further, since the pattern shapes in the two patterning processes are different, there is no mask misalignment, and the mass productivity is excellent even when the pattern is miniaturized. Even if the peeling of the pixel material from the substrate end face after the first patterning is reattached, the first patterning can be made larger than the original pixel size to prevent misalignment and prevent reattachment. . In addition, since the electrode material film straddling a plurality of pixels is formed in the first patterning step, for example, an inspection probe can be electrically connected to the electrode material film. An electrical property inspection using the electrode material film can be performed later.

  Further, the film forming step and the first and second patterning steps are performed on an array substrate on which a plurality of active matrix substrates are formed.

  According to such a configuration, a plurality of active matrix substrates can be manufactured simultaneously.

  The first patterning step is characterized in that a film of the pixel electrode material is patterned for each region including the pixel region in the active matrix substrate forming region on the array substrate.

  According to such a configuration, after the first patterning step, one electrode material film is formed in a region including the pixel region with respect to one active matrix substrate. For example, an electrode on each pixel is formed. By electrically connecting a probe for inspection to the material film, it is possible to inspect electric characteristics of each pixel.

  In the film forming step, the pixel electrode material is filled in a contact hole formed in an insulating film formed in a lower layer of the pixel electrode material film.

  According to such a configuration, after the first patterning step, one electrode material film and the pixel electrode material filled in the plurality of contact holes are electrically connected. For example, the electric material film By electrically connecting an inspection probe to the contact hole, it is possible to perform an electrical characteristic inspection of the contact hole of each pixel.

  The method further includes the step of forming a terminal connected to the electrode material film after the first patterning step.

  According to such a configuration, for example, by electrically connecting the inspection probe to the terminal, the electrode material film and the inspection probe can be electrically connected.

  In the first patterning step, the electrode material film and a terminal connected to the electrode material film are formed at the same time.

  According to such a configuration, an increase in the number of steps can be suppressed.

  The electro-optical device inspection method according to the present invention is formed over a plurality of pixels in a pixel region before an electrode material film is patterned for each pixel and a pixel electrode is formed on an active matrix substrate. In addition, a first electrical characteristic inspection step of inspecting electrical characteristics of each pixel using the electrode material film is provided.

  According to such a configuration, in the first electrical characteristic inspection step, the electrical characteristics of each pixel are inspected using the electrode material film formed on the active matrix substrate across a plurality of pixels in the pixel region. To do. In the first electrical property inspection step, for example, by electrically connecting an inspection probe to the electrode material film, the electrical property of the member connected to the pixel electrode when the active matrix substrate is completed can be inspected. .

  Also, the inspection method for the electro-optical device according to the present invention is a first method for inspecting the electrical characteristics of each pixel using an electrode material film formed on the active matrix substrate across a plurality of pixels in the pixel region. And a second electrical property inspection step for inspecting the electrical property of each pixel in a state in which the electrode material film is patterned for each pixel to form a pixel electrode. To do.

  According to such a configuration, in the first electrical characteristic inspection step, the electrical characteristics of each pixel are inspected using the electrode material film formed on the active matrix substrate across a plurality of pixels in the pixel region. To do. In the first electrical property inspection step, for example, by electrically connecting an inspection probe to the electrode material film, the electrical property of the member connected to the pixel electrode when the active matrix substrate is completed can be inspected. . In the second electrical property inspection step, the electrical property of each pixel is inspected in a state where the electrode material film is patterned for each pixel and the pixel electrode is formed. In the first electrical characteristic inspection step, the electrical characteristics of the member connected to the pixel electrode can be inspected, so that the short circuit of the pixel electrode is inspected by combining with the inspection result of the first electrical characteristic inspection step. Can do.

  The active matrix substrate includes a switching element for driving the pixel electrode, and a contact hole for electrically connecting the pixel electrode and the switching element, and the first electrical characteristic inspection step includes the step of It is characterized in that the contact hole and the switching element are inspected for continuity.

  According to such a configuration, in the first electrical characteristic inspection step, for example, the inspection probe is electrically connected to the electrode material film, and a current is passed from the electrode material film to the contact hole, so that the terminal of the switching element By detecting the current, the continuity of the contact hole and the switching element can be inspected.

  The active matrix substrate includes a switching element for driving the pixel electrode, and a contact hole for electrically connecting the pixel electrode and the switching element, and the first electrical characteristic inspection step includes the step of It is characterized by inspecting leakage of the switching element.

  According to such a configuration, for example, by electrically connecting an inspection probe to the electrode material film, applying a voltage to the electrode material film, and turning off the switching element, the leakage of the switching element is reduced. Can be inspected.

  The active matrix substrate includes a switching element for driving the pixel electrode, a contact hole for electrically connecting the pixel electrode and the switching element, and a storage capacitor connected to the switching element, The first electrical characteristic inspection step is to inspect a short circuit between the switching element and the storage capacitor.

  According to such a configuration, for example, by electrically connecting the inspection probe to the electrode material film, applying a voltage to the electrode material film, and changing the off-voltage of the switching element, A minute leak between the storage capacitors can be inspected.

  Further, the second electrical characteristic inspection step is to inspect the conduction of the switching element.

  According to such a configuration, the continuity of the switching element can be inspected by the second electrical characteristic inspection step. In the case where the switching element and the contact hole are confirmed to be non-conducting by the first electrical characteristic inspection step, if one of the non-conducting portions is one, it is determined whether it is a switching element or a contact hole. Can be detected.

  The second electrical characteristic inspection step is to inspect a short circuit between the pixel electrodes.

  According to such a configuration, in the second electrical characteristic inspection step, for example, the switching element of the adjacent pixel is turned on, and the current flowing from the switching element of one pixel is detected from the switching element of the other pixel. It can be checked whether or not. In this case, when it is confirmed that the switching element and the contact hole are conducted by the first electrical characteristic inspection process, the inspection result of the second electrical characteristic inspection process is that the adjacent pixel electrodes are short-circuited. It will be shown whether or not. Thereby, a defect of the pixel electrode can be detected by electrical inspection on the active matrix substrate.

  In the electro-optical device inspection method of the present invention, the first electrical characteristic inspection step is performed by heating the active matrix substrate.

  With the above configuration, in particular, when detecting a minute leakage current related to Tr between the source and drain, it is characterized in that the electrical characteristics are observed by applying a temperature of about 25 ° C. to 150 ° C. to the stage to be probed. Amplification makes it easy to detect a leak current of a defective pixel.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a flowchart showing a method for manufacturing an electro-optical device according to an embodiment of the present invention. The present embodiment is applied to a manufacturing method of a liquid crystal device using a TFT substrate as an electro-optical device. FIG. 2 is a plan view of the liquid crystal device manufactured according to the present embodiment as viewed from the counter substrate side together with the components formed thereon. FIG. 3 is a cross-sectional view of the liquid crystal device after the assembly process in which the TFT substrate, which is an active matrix substrate, and the counter substrate are bonded together to enclose the liquid crystal is completed, cut along the line HH ′ in FIG. . FIG. 4 is an equivalent circuit diagram of various elements and wirings in a plurality of pixels constituting the pixel region of the liquid crystal device manufactured according to the present embodiment. FIG. 5 is a cross-sectional view showing in detail the pixel structure of the liquid crystal device of FIGS. FIG. 6 is an explanatory diagram for explaining a resist mask used in manufacturing the pixel electrode in the present embodiment. FIG. 7 is an explanatory diagram for explaining an inspection method for an electro-optical device using ITO formed on the entire surface. 8 to 10 are flowcharts specifically showing the inspection method of FIG. FIG. 11 is an explanatory diagram for explaining an inspection method after completion of an active matrix substrate which is an electro-optical device. 12 and 13 are flowcharts specifically showing the inspection method of FIG. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.

  This embodiment is applied to a liquid crystal device using a TFT substrate as an electro-optical device, and shows an example applied to a case where a liquid crystal device is manufactured by an array manufacturing method having excellent productivity. In the array manufacturing method, a plurality of TFT substrates (active matrix substrates) are cut out from one mother glass substrate. That is, a plurality of elements for active matrix substrates are simultaneously formed on the mother glass substrate by repeating the film forming and photolithography processes without dividing the mother glass substrate that is input at the time of manufacture. Then, each active matrix substrate is obtained by dividing the mother glass substrate.

  In the present embodiment, in such an array manufacturing, in the electrical characteristic inspection for a plurality of active matrices formed on the mother glass substrate, an additional inspection is performed with ITO formed on the entire surface of the active matrix substrate. In this way, a defect of each pixel is detected not by visual inspection of the completed liquid crystal device but by electrical inspection in the substrate state.

  In other words, this embodiment can be applied to all devices that display by driving a pixel electrode with a transistor. In the case where a defect in the previous process (mother glass substrate process) flows out to the subsequent process (after bonding of the counter substrate), the defect is reliably judged in the previous process and the outflow of defective products to the subsequent process is prevented. As a result, it is possible to reduce the extra cost of the post-process for defective products. Therefore, this inspection method is unnecessary for an apparatus that does not cause defects on the substrate side to flow out to the subsequent process.

  First, an overall configuration of a liquid crystal device to which the present embodiment is applied will be described with reference to FIGS.

  As shown in FIGS. 2 and 3, the liquid crystal device includes, for example, a quartz substrate, a glass substrate, a TFT substrate 10 using a silicon substrate, and a counter substrate using a glass substrate or a quartz substrate, for example. The liquid crystal 50 is sealed between the two. The TFT substrate 10 and the counter substrate 20 that are arranged to face each other are bonded together by a sealing material 41.

  On the TFT substrate 10, pixel electrodes (ITO) 9a constituting pixels are arranged in a matrix. A counter electrode (ITO) 21 is provided on the entire surface of the counter substrate 20. On the pixel electrode 9a of the TFT substrate 10, an alignment film 16 subjected to an alignment process is provided. On the other hand, an alignment film 22 subjected to an alignment process is also provided on the counter electrode 21 formed over the entire surface of the counter substrate 20. The alignment films 16 and 22 are made of, for example, a transparent organic film or inorganic film such as a polyimide film.

  FIG. 4 shows an equivalent circuit of elements on the TFT substrate 10 constituting the pixel. As shown in FIG. 4, in the pixel region, a plurality of scanning lines 3a and a plurality of data lines 6a are wired so as to intersect with each other, and a pixel electrode is formed in a region partitioned by the scanning lines 3a and the data lines 6a. 9a are arranged in a matrix. A TFT 30 is provided corresponding to each intersection of the scanning line 3 a and the data line 6 a, and the pixel electrode 9 a is connected to the TFT 30.

  The TFT 30 is turned on by the ON signal of the scanning line 3a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. In addition, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 makes it possible to hold the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. The storage capacitor 70 improves the voltage holding characteristic and enables image display with a high contrast ratio.

  A plurality of pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a and scanning lines 3a are provided along the vertical and horizontal boundaries of the pixel electrodes 9a. As will be described later, the data line 6a has a laminated structure including an aluminum film, and the scanning line 3a is made of, for example, a conductive polysilicon film. The scanning line 3a is formed to face a channel region 1a 'described later. That is, the pixel switching TFT 30 is configured by the gate electrode connected to the scanning line 3 a and the channel region 1 a ′ facing each other at the intersection of the scanning line 3 a and the data line 6 a.

  FIG. 5 is a schematic cross-sectional view of a liquid crystal device focusing on one pixel.

  Grooves 11 are formed in a lattice pattern on a transparent substrate 10 ′ such as glass or quartz. A TFT 30 having an LDD (Lightly Doped Drain) structure is formed on the trench 11 via the lower light-shielding film 12 and the first interlayer insulating film 13. The groove 11 facilitates flattening of the boundary surface between the TFT substrate and the liquid crystal 50.

  The TFT 30 includes a scanning line 3a that forms a gate electrode through a gate insulating film 2 on a semiconductor layer 1a in which a channel region 1a ', a source region 1d, and a drain region 1e are formed. The scanning line 3a is formed to be wide at a portion to be a gate electrode, and the channel region 1a ′ is configured in a region where the semiconductor layer 1a and the scanning line 3a face each other.

  A plurality of transparent pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a and scanning lines 3a are provided along the vertical and horizontal boundaries of the pixel electrodes 9a. The lower light-shielding film 12 is provided in a lattice shape corresponding to each pixel along the data line 6a and the scanning line 3a. The light shielding film 12 prevents reflected light from entering the channel region 1 a ′, the source region 1 d, and the drain region 1 e of the TFT 30.

  The lower light-shielding film 12 includes, for example, a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate of at least one of refractory metals such as Ti, Cr, W, Ta, Mo, and Pb. Etc.

  A second interlayer insulating film 14 is stacked on the TFT 30, and an island-shaped first intermediate conductive layer 15 extending in the scanning line 3 a and data line 6 a directions is formed on the second interlayer insulating film 14. On the first intermediate conductive layer 15, the capacitor line 18 is disposed opposite to the dielectric film 17.

  The first intermediate conductive layer 15 acts as a pixel potential side capacitance electrode (lower capacitance electrode) connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a part of the capacitance line 18 serves as a fixed potential side capacitance electrode. Works.

  The capacitor line 18 is disposed opposite to the first intermediate conductive layer 15 with the dielectric film 17 interposed therebetween, thereby constituting a storage capacitor (storage capacitor 70 in FIG. 4). The intermediate conductive layer 15 is formed at a position relatively close to the semiconductor layer 1a, so that irregular reflection of light can be efficiently prevented.

  The capacitor line 18 has a multilayer structure in which an upper capacitor electrode made of, for example, a conductive polysilicon film and a light shielding layer made of a metal silicide film containing a refractory metal are stacked. For example, the capacitor line 18 is constituted by a polycide of a light shielding layer made of silicide of tungsten, molybdenum, titanium, or tantalum and an upper capacitor electrode made of N-type polysilicon. As a result, the capacitor line 18 functions as a fixed potential side capacitor electrode and constitutes a built-in light shielding film that prevents internal reflection of light.

  The first intermediate conductive layer 15 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. The first intermediate conductive layer 15 has a function as a light absorbing layer disposed between the capacitor line 18 as the built-in light shielding film and the TFT 30 as described above, in addition to the function as the pixel potential side capacitor electrode. Further, the pixel electrode 9a and the high concentration drain region 1e of the TFT 30 have a function of relay connection. The first intermediate conductive layer 15 may also be composed of a single layer film or a multilayer film containing a metal or an alloy, like the capacitor line 18.

  The dielectric film 17 disposed between the first intermediate conductive layer 15 as the lower capacitor electrode and the capacitor line 18 constituting the upper capacitor electrode is a relatively thin HTO (High Temperature Oxide) having a thickness of, for example, about 5 to 200 nm. ) Film, silicon oxide film such as LTO (Low Temperature Oxide) film, or silicon nitride film. From the viewpoint of increasing the storage capacity, it is better that the dielectric film 17 is thinner as long as the reliability of the film is sufficiently obtained.

  The capacitor line 18 extends from the image display area in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. As such a constant potential source, a later-described scanning line driving circuit 63 for supplying a scanning signal for driving the TFT 30 to the scanning line 3a and a later-described data line for controlling a sampling circuit for supplying an image signal to the data line 6a. A constant potential source such as a positive power source or a negative power source supplied to the drive circuit 61 may be used, or a constant potential supplied to the counter electrode 21 of the counter substrate 20 may be used. Further, the lower light-shielding film 12 also extends from the image display area to the periphery thereof and is connected to a constant potential source in the same manner as the capacitor line 18 in order to prevent the potential fluctuation from adversely affecting the TFT 30. Good.

  Further, in order to electrically connect the data line 6a and the source region 1d, a second intermediate conductive layer 15b formed of the same layer as the first intermediate conductive layer 15 is formed. The second intermediate conductive layer 15b is electrically connected to the source region 1d through a contact hole 24a penetrating the second interlayer insulating film 14 and the insulating film 2.

  A third interlayer insulating film 19 is disposed on the capacitor line 18, and a data line 6 a is stacked on the third interlayer insulating film 19. The data line 6a is electrically connected to the source region 1d through the contact hole 24b penetrating the third interlayer insulating film 19 and the dielectric film 17 and the second intermediate conductive layer 15b.

  A fourth interlayer insulating film 25 is formed on the third interlayer insulating film 19 and the data line 6a. A pixel electrode 9 a is formed on the fourth interlayer insulating film 25. The pixel electrode 9 a is electrically connected to the first intermediate conductive layer 15 through a contact hole 26 b that penetrates the fourth interlayer insulating film 25, the third interlayer insulating film 19, and the dielectric film 17. The first intermediate conductive layer 15 is electrically connected to the drain region 1 e through a contact hole 26 a that penetrates the second interlayer insulating film 14 and the insulating film 2. An alignment film 16 made of polyimide polymer resin is laminated on the pixel electrode 9a, and is subjected to an alignment process in a predetermined direction.

  When the ON signal is supplied to the scanning line 3a (gate electrode), the channel region 1a 'becomes conductive, the source region 1d and the drain region 1e are connected, and the image signal supplied to the data line 6a becomes a pixel. It is given to the electrode 9a.

  On the other hand, the counter substrate 20 is formed on the transparent substrate 20 ′ in a region facing the data line 6 a, scanning line 3 a, and TFT 30 formation region of the TFT substrate 10, that is, in a non-display region (non-opening region) of each pixel. One light shielding film 23 is provided. The first light shielding film 23 prevents incident light from the counter substrate 20 side from entering the channel region 1 a ′, the source region 1 d, and the drain region 1 e of the TFT 30. A counter electrode (common electrode) 21 is formed over the entire surface of the substrate 20 on the first light shielding film 23. An alignment film 22 made of a polyimide-based polymer resin is laminated on the counter electrode 21 and is subjected to an alignment process in a predetermined direction. A liquid crystal 50 is sealed between the TFT substrate 10 and the counter substrate 20. The TFT 30 writes an image signal supplied from the data line 6a to the pixel electrode 9a at a predetermined timing. Depending on the potential difference between the written pixel electrode 9a and the counter electrode 21, the orientation and order of the molecular assembly of the liquid crystal 50 change, and the light is modulated to enable gradation display.

  As shown in FIGS. 2 and 3, the counter substrate 20 is provided with a light shielding film 42 as a frame for partitioning the display area. The light shielding film 42 is formed of, for example, the same or different light shielding material as the light shielding film 23.

  A sealing material 41 that encloses liquid crystal in a region outside the light shielding film 42 is formed between the TFT substrate 10 and the counter substrate 20. The sealing material 41 is disposed so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other. The sealing material 41 is missing in a part of one side of the TFT substrate 10, and a liquid crystal injection port 78 for injecting the liquid crystal 50 is formed. Liquid crystal is injected into the gap between the bonded TFT substrate 10 and counter substrate 20 from the liquid crystal injection port 78. After the liquid crystal injection, the liquid crystal injection port 78 is sealed with a sealing material 79.

  A data line driving circuit 61 and a mounting terminal 62 are provided along one side of the TFT substrate 10 in a region outside the sealing material 41 of the TFT substrate 10, and scanning lines are provided along two sides adjacent to the one side. A drive circuit 63 is provided. On the remaining side of the TFT substrate 10, a plurality of wirings 64 are provided for connecting the scanning line driving circuits 63 provided on both sides of the screen display area. In addition, a conductive material 65 for electrically connecting the TFT substrate 10 and the counter substrate 20 is provided in at least one corner of the counter substrate 20.

  The TFT substrate 10 and the counter substrate 20 are manufactured separately and bonded together in an assembly process. In the case of array manufacturing, a TFT array substrate in which a plurality of TFT substrates 10 are formed by forming each of the above-described layers on a transparent mother glass substrate that is the base of the transparent substrate 10 is obtained. Then, from the viewpoint of productivity and yield, each counter substrate divided into a single substrate is bonded to each TFT substrate on each TFT substrate arranged in the state of a mother glass substrate, and divided into each TF substrate after enclosing the liquid crystal. In this way, a chip mount method for obtaining a single liquid crystal device is adopted.

  That is, in the assembly process, the sealing material 41 and the conductive material 65 (see FIG. 2) are formed on each TFT substrate 10 after the completion of the alignment process. The TFT substrate 10 and the counter substrate 20 are bonded to each other and bonded while being aligned, and the sealing material 41 is cured. Next, liquid crystal is sealed from a notch provided in a part of the sealing material 41, and the notch is closed to seal the liquid crystal. Finally, the mother glass substrate is divided for each chip configured by bonding the TFT substrate 10 and the counter substrate 20 to obtain a single chip (liquid crystal device).

  Next, a method for inspecting electrical characteristics will be described.

  First, an electrical characteristic inspection when the liquid crystal device of FIG. 5 is manufactured by a conventional manufacturing method will be described. In this case, an electrical property inspection is performed on the completed TFT array substrate.

  As described above, the source of each pixel in the same column is connected to the common data line (source line) 6a. By using the mounting terminal 62 (PAD) connected to the source line 6a, an inspection probe for electrical characteristic inspection can be electrically connected from each source line 6a to the source of the TFT 30 through these PADs. The gates of the pixels in the same row are connected to a common scanning line 3a. An on / off voltage can be applied to the gate of each pixel via the scanning line 3a. The drains of the pixels in the same row are connected in common via the capacitor line 18 that constitutes the storage capacitor 70. By connecting a probe to the PAD, a terminal of an electrical characteristic inspection device (not shown) can be connected to the drain via the storage capacitor 70.

  Now, a short circuit between the pixel electrodes 9a of each TFT substrate 10 is inspected. In this case, as described above, since the probe for electrical characteristic inspection cannot be connected to the pixel electrode 9a, a pad (PAD) formed on each TFT substrate 10 of the TFT array substrate is used. The electrical characteristic inspection probe is electrically connected to the source and drain (capacitor line 18).

  In this state, an on-voltage is applied to the gate of the TFT 30, and it is determined whether a current flows from the source by flowing a current from the source. That is, it is detected that a voltage is applied to the capacitor line 18. Thereby, contact failure in the contact hole 26a can be detected.

  Next, the probe is connected to the sources So1 and So2 of two adjacent pixels. In this state, an on-voltage is applied to the gates G1 and G2 of each pixel, and a current is passed through the source So1 of one pixel. In this case, if a current flows to the pixel electrode 9a-drain D2-channel-source So2 of the other pixel via the source So1-channel-drain D1-pixel electrode 9a of one pixel, the pixel electrodes 9a are short-circuited. Can be determined.

  However, when a contact failure occurs in the contact hole 26b of FIG. 5, even when the pixel electrodes 9a are short-circuited, no current flows through the source So2 of the other pixel. That is, in this case, it cannot be inspected whether the pixel electrodes 9a are short-circuited. For this reason, conventionally, in order to inspect a short circuit or the like of the pixel electrode 9a, the liquid crystal 50 is actually sealed, and a voltage is applied between the pixel electrode 9a and the counter substrate 20 to drive each pixel. Inspected by visual inspection.

  On the other hand, in the present embodiment, by adopting the manufacturing and inspection method shown in FIG. 1, it is possible to detect pixel defects such as a short circuit of the pixel electrode 9a by electrical inspection on the TFT array substrate. I have to. Note that the PAD formation process of FIG. 1 is not necessary when the inspection probe is directly connected to the ITO film.

  Step S1 in FIG. 1 is performed following the step of forming the fourth interlayer insulating film 25 in FIG. In step S1, ITO, which is a transparent pixel electrode material, is formed on the entire surface of the TFT array substrate on which the fourth interlayer insulating film 25 is formed. In the next step S2, a photoresist is formed for each chip formation region. FIG. 6 shows a photoresist formation region in this case by hatching. FIG. 6 shows four chip formation regions 111 among the formation regions (hereinafter referred to as chip formation regions) of the TFT substrates on the mother glass substrate. That is, in step S2, a mask is formed for each chip formation region 111.

  In the next step S3, etching is performed, and as shown by the oblique lines, the ITO on the TFT array substrate is separated for each chip formation region 111 to obtain an ITO film 110 as an electrode material film. In step S4, the resist is stripped and removed. That is, at this time, the contact holes 26b of all the pixels in each chip formation region 111 are electrically connected in common by the ITO film 110 formed on the entire surface of the pixel region 113 (corresponding to the display region described above) for each chip. Is done.

  FIG. 7 schematically shows a cross section of three adjacent pixels in this case. In FIG. 7, the parts corresponding to those in FIG. As shown in FIG. 7, the pixel electrode 9a is not patterned, and the ITO film 110 is connected between adjacent pixels.

  Next, in step S5, the PAD 112 is formed in each chip formation region 111. Each PAD 112 is electrically connected to the ITO film 110 in the chip formation region 111. Thus, as shown in FIG. 7, all the contact holes 26b are electrically connected in common and connected to the PAD 112. The PAD 112 and the ITO film 110 can be simultaneously formed in the same process.

  In the present embodiment, the first electrical characteristic inspection is performed in a state where the ITO film 110 is formed over the entire pixel region 113 for each chip formation region 111 (step S6). The first electrical characteristic inspection includes three inspections, that is, a first contact inspection, a leak inspection, and a first short circuit inspection. FIG. 8 is for explaining the first contact inspection.

  In step S 11 of FIG. 8, first, a current is passed through the ITO film 110 via the PAD 112. Next, in step S12, an on-voltage is applied to the gate G1 shown in FIG. In this state, the current flowing through the source So1 is detected via a PAD (not shown) connected to the data line 6a. That is, the current path in this case is the ITO film 110-contact holes 26b and 26a, the drain region 1e, the channel 1a ', the source region 1d, the contact hole 24a, and the data line 6a. When a current flows through the source So1, it can be seen that the contact holes 26b and 26a of the leftmost pixel in FIG. 7 are conductive. By sequentially detecting the current flowing through the PAD connected to each data line 6a, it is possible to inspect the contact holes 26b, 26a of all pixels in one line.

  Similarly, steps S12 and S13 are repeated for the next pixel. That is, for example, an on-voltage is next applied to the gate G2, and the current flowing through the PAD connected to each data line 6a is sequentially detected. Thereafter, the contact holes 26b and 26a of all the pixels in all the lines are inspected in the same manner.

  As described above, since the ITO film 110 is formed without being separated in the entire pixel region 113 of each chip formation region 111, the ITO film is formed by one PAD 112 for connecting the inspection probe to the ITO film 110. A current can flow directly through 110. In the first contact inspection of the present embodiment, the current from the ITO film 110 is taken out from the data line 6a through the contact holes 26b and 26a and the TFT 30, and the contact holes 26b and 26a are conducted. Can be confirmed.

  Next, the leak test shown in FIG. 9 will be described.

  In step S 21 of FIG. 9, first, a voltage is applied to the ITO film 110 via the PAD 112. Next, in step S22, an off voltage is applied to the gate G1. As a result, the TFT 30 is turned off. In this state, the current flowing through the source So1 is detected via a PAD (not shown) connected to the data line 6a. Since the TFT 30 is off, no current flows through the source So1 unless leakage occurs. Therefore, the leak between the source and the drain can be detected by the current flowing through the source So1.

  Similar to the first contact inspection, the other pixels are also inspected.

  As described above, in the conventional electrical characteristic inspection, since the storage capacitor 70 is connected to the drain via the storage capacitor 70, the storage capacitor 70 cannot pass a direct current component. The leak in between could not be detected.

  On the other hand, in the present embodiment, since the ITO film 110 and the drain are electrically connected directly via the contact holes 26b and 26a, the leak between the source and the drain can be detected. .

  Next, the first short circuit inspection shown in FIG. 10 will be described.

  In step S31 of FIG. 10, first, a voltage is applied to the ITO film 110 via the PAD 112. Next, in step S32, an off voltage is applied to the gate G1. As a result, the TFT 30 is turned off. In this state, the current flowing through the storage capacitor C1 is detected via a PAD (not shown). If the TFT 30 is off and no leak occurs, no current can be detected from the storage capacitor C1 (capacitor line 18). Therefore, the leak between the drain and the storage capacitor C1 (capacitor line 18) can be detected by the current flowing through the storage capacitor C1.

  Similar to the first contact inspection, the other pixels are similarly inspected.

  Next, in step S7 of FIG. 1, a photoresist for patterning the pixel electrode 9a is formed. The mesh lines in FIG. 6 indicate the photoresist pattern formed in step S7. That is, in step S7, a photoresist is formed for each pixel electrode 9a in the pixel region 113 in each chip formation region.

  In the next step S8, etching is performed, and the ITO film 110 on each chip formation region 111 on the TFT array substrate is separated for each pixel, as indicated by the mesh line. In the next step S9, the resist is removed. Thereby, the pixel electrode 9a separated for each pixel in each chip formation region 111 is formed.

  Note that the PAD may be exposed from the TFT substrate 10 before the processing in step S7. In this case, it is necessary to perform patterning for forming a photoresist on the PAD in order to prevent the PAD from being etched in step S7.

  The pixel electrode 9a is electrically connected to the contact hole 26b. FIG. 11 schematically shows a cross section of three adjacent pixels in this case. In FIG. 11, the parts corresponding to those in FIG. As shown in FIG. 11, the ITO film 110 of FIG. 7 is patterned to form a pixel electrode 9a. That is, adjacent pixel electrodes 9a are electrically separated. Through the processes up to step S9, a completed TFT array substrate before the formation of the alignment film is obtained.

  Next, in step S10, a second and third electrical property inspection is performed on the completed TFT array substrate. The second electrical property test is a second contact test, and the third electrical property test is a second short circuit test.

  FIG. 12 is for explaining the second contact inspection.

  In step S41 of FIG. 12, first, a current is supplied from a PAD (not shown) to the source So1 shown in FIG. 11 via the data line 6a. Next, an on voltage is applied to the gate G1 in step S42. Then, the current from the source So1 flows to the drain D1 through the channel below the gate G1 (step S43), and a voltage is generated in the storage capacitor C1 (capacitor line 18) connected to the drain D1. In step S44, the voltage generated in the capacitance line 18 is detected. It can be seen that the contact between the source and the drain is normal due to the voltage generated in the capacitor line 18.

  In the second contact inspection, the inspection is performed for all other pixels as in the first contact inspection.

  This second contact inspection can detect a contact failure from the source to the drain. Therefore, when the results of the first contact inspection are combined, it is determined whether the contact failure is between the source region 1d and the drain region 1e or between the drain region 1e including the storage capacitor 70 and the pixel electrode 9a. can do.

  FIG. 13 is for explaining the second short circuit inspection. FIG. 13 shows an inspection for detecting a short circuit between the pixel electrodes 9a. In the second short circuit inspection, the current flowing through the two adjacent pixels is examined.

  That is, in step S51 of FIG. 13, first, a current is passed from a PAD (not shown) to the source So1 of one of the two adjacent pixels via the data line 6a. Next, in step S52, an on-voltage is applied to the gate G1 of one pixel. If there is no abnormality in the first contact inspection, the source So1 and the pixel electrode 9a are in a conductive state.

  In the next step S53, an on-voltage is applied to the gate G2 of the other pixel. If there is no abnormality in the first contact inspection, the pixel electrode 9a of the other pixel and the source So2 are in a conductive state. In step S54, the current flowing through the source So2 of the other pixel is detected.

  In the first contact inspection, if no abnormality has occurred in the two pixels being inspected, current does not flow through the source So2 unless a short circuit occurs between the pixel electrodes 9a. If a short circuit occurs between them, a current flows through the source So2. That is, if there is no abnormality in one and the other pixels by the first contact inspection, the current from the source So1 is the channel-drain D1 under the gate G1, the contact holes 26a, 26b of one pixel, and the one pixel. The pixel electrode 9a-the other pixel pixel electrode 9a-the other pixel contact holes 26b, 26a, the drain D2-flows through the channel below the gate G2 to the source So2.

  As described above, the second contact inspection makes it possible to reliably detect a short circuit between the pixel electrodes 9a for pixels in which no abnormality has occurred in the first contact inspection.

Incidentally, in FIG. 1, the first electrical characteristic inspection is performed in the process of manufacturing the TFT array substrate before completion. However, by manufacturing the TFT array substrate by the manufacturing method of FIG. 1, it is possible to prevent the ITO from being lost regardless of the presence or absence of the inspection process.

  That is, in FIG. 1, the pixel electrode 9a is formed by patterning twice in steps S2 to S4 and steps S7 to S9. By performing the patterning twice (double ITO), it is possible to prevent defects due to redeposition of ITO in which film peeling has occurred at the edge of the mother glass substrate or the like, as in the past.

  Further, in the present embodiment, the patterning in steps S2 to S4 and the patterning in steps S7 to S9 are performed with different patterns using different masks. That is, in the patterning in steps S2 to S4, the patterning for each chip formation region 111 is performed, and the pixel region 113 is not etched. Then, in the patterning in steps S7 to S9, patterning for forming the pixel electrode 9a for each pixel in the pixel region 113 of each chip forming region 111 is performed.

  That is, patterning for determining the shape of the pixel electrode 9a is performed only once. Accordingly, ITO is not lost due to mask displacement when patterning the pixel electrode 9a, and the pixel electrode 9a can be patterned with high accuracy. As a result, mass production is possible even when miniaturized.

  In the present embodiment, two etching steps S3 and S8 are performed in the vicinity of the edge of each chip formation region 111, and step S8 is performed on the center side of each chip formation region 111. One etching is performed. Therefore, in the liquid crystal device manufactured in this embodiment, as shown in FIG. 3, a step 115 is generated between the portion etched twice and the portion etched once.

  As described above, in the present embodiment, when forming the pixel electrode 9a, the ITO film 110 is inspected on the entire surface including at least the pixel region 113 by forming the ITO film 110 that is not separated for each pixel. Since the inspection probe of the apparatus can be connected, it is possible to electrically conduct the contact inspection of the contact hole of each pixel. Thereby, it is possible to reliably detect a short circuit between the pixel electrodes 9a by conducting a continuity test between two adjacent pixels after the pixel electrode 9a is patterned. Further, by connecting an inspection probe to the ITO film 110, the inspection probe can be electrically connected directly to the drain region, and a leak inspection between the source and the drain is also possible. In addition, since the patterning is performed twice when the pixel electrode 9a is formed, it is possible to prevent reattachment of the ITO that has been peeled off, and different mask patterns are used for the first time and the second time. As a result, misalignment of the masks can be prevented, and the miniaturized electro-optical device can be mass-produced.

  In the above embodiment, the example in which the ITO film 110 that is not divided on the entire surface of the pixel region 113 is formed has been described. However, any inspection probe may be connected to the ITO film on each pixel. For example, an ITO film that is not separated for each pixel may be formed in each divided region by dividing the pixel region 113 into two or four.

  In addition, although an example in which the electrical characteristic inspection is performed three times has been described with reference to FIG. 1, for example, a leak inspection between the source and the drain can be detected only by the first electrical characteristic inspection, and is not necessarily performed a few times. There is no need to conduct an electrical property test.

  In the above embodiment, an example of manufacturing an array in the state of a TFT array substrate has been described. However, the present invention can be similarly applied to the case where only one TFT substrate is formed on a mother glass substrate. It is clear.

  When the active matrix substrate is heated in the first electrical characteristic inspection, a minute leak current can be detected with high sensitivity due to temperature dependence. For example, when a minute leak current is detected with respect to the transistor between the source and the drain, the electrical characteristics are inspected by applying a temperature of about 25 ° C. to 150 ° C. to the stage to be probed. Accordingly, there is an effect of amplifying a minute current, and it is possible to easily detect a leak current of a defective pixel.

  In the above embodiment, the electro-optical device (display device) is applied to a liquid crystal device, that is, a display device in which a pixel electrode is driven using a transistor. However, the present invention is not limited to this. Electroluminescence devices, especially organic electroluminescence devices, inorganic electroluminescence devices, plasma display devices, FED (field emission display) devices, LED (light emitting diode) display devices, electrophoretic display devices, thin cathode ray tubes, liquid crystals Various electro-optical devices such as small televisions using shutters, devices using digital micromirror devices (DMD), and drive display devices using liquid crystals (cell phones, PHS, watches, personal computer screens, PDAs, etc.) ). In particular, this is a useful technique when each pixel of the display device is miniaturized and it is difficult to evaluate by applying a probe needle to each pixel, and the electrical characteristics of the mother substrate alone cannot be detected. .

6 is a flowchart illustrating a method for manufacturing an electro-optical device according to an embodiment of the invention. The top view which looked at the liquid crystal device manufactured by this Embodiment from the counter substrate side with each component formed on it. FIG. 3 is a cross-sectional view of the liquid crystal device after being assembled at a position along line HH ′ in FIG. 2 after the assembly process in which a TFT substrate, which is an active matrix substrate, and a counter substrate are bonded together to enclose liquid crystal therein. FIG. 5 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels constituting a pixel region of a liquid crystal device manufactured according to the present embodiment. FIG. 5 is a cross-sectional view illustrating in detail a pixel structure of the liquid crystal device of FIGS. Explanatory drawing for demonstrating the resist mask used at the time of manufacture of the pixel electrode in this Embodiment. Explanatory drawing for demonstrating the inspection method of the electro-optical apparatus using ITO formed in the whole surface. The flowchart which shows the inspection method of FIG. 7 concretely. The flowchart which shows the inspection method of FIG. 7 concretely. The flowchart which shows the inspection method of FIG. 7 concretely. Explanatory drawing for demonstrating the inspection method after the completion of the active matrix substrate which is an electro-optical device. The flowchart which shows the inspection method of FIG. 11 concretely. The flowchart which shows the inspection method of FIG. 11 concretely.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 1d ... Source region, 1e ... Drain region, 3a ... Gate electrode, 11 ... Scan line, 26a, 26b ... Contact hole, 30 ... TFT, 110 ... ITO film, 111 ... Chip formation region, 112 ... PAD 113 ... Pixel region.

Claims (15)

A film forming step of forming a film of a pixel electrode material on the entire surface of the active matrix substrate;
A first patterning step of patterning the pixel electrode material film to form an electrode material film across a plurality of pixels in a pixel region;
And a second patterning step of forming a pixel electrode by patterning the electrode material film for each pixel. 2. The method of manufacturing an electro-optical device according to claim 1, wherein the film forming step and the first and second patterning steps are performed on an array substrate on which a plurality of active matrix substrates are formed. 3. The pixel pattern material film according to claim 1, wherein in the first patterning step, the pixel electrode material film is patterned for each region including the pixel region in the active matrix substrate forming region on the array substrate. A method for manufacturing the electro-optical device according to any one of the above. 4. The film forming process according to claim 1, wherein the pixel electrode material is filled in a contact hole formed in an insulating film formed in a lower layer of the pixel electrode material film. A method of manufacturing the electro-optical device according to claim. 5. The method of manufacturing an electro-optical device according to claim 1, further comprising a step of forming a terminal connected to the electrode material film after the first patterning step. . 5. The electro-optical device manufacturing method according to claim 1, wherein in the first patterning step, the electrode material film and a terminal connected to the electrode material film are formed at the same time. Method. On the active matrix substrate, before the pixel electrode is formed by patterning the electrode material film for each pixel, the electrode material film formed over a plurality of pixels in the pixel region is used for each pixel. An inspection method for an electro-optical device, comprising a first electrical property inspection step for inspecting electrical properties of the electro-optical device. A first electrical property inspection step for inspecting electrical properties for each pixel using an electrode material film formed on the active matrix substrate across a plurality of pixels in the pixel region;
An inspection method for an electro-optical device, comprising: a second electric characteristic inspection step for inspecting electric characteristics of each pixel in a state where the electrode material film is patterned for each pixel to form a pixel electrode. . The active matrix substrate has a switching element for driving the pixel electrode and a contact hole for electrically connecting the pixel electrode and the switching element,
9. The method for inspecting an electro-optical device according to claim 7, wherein the first electrical characteristic inspection step is to inspect continuity between the contact hole and the switching element. The active matrix substrate has a switching element for driving the pixel electrode and a contact hole for electrically connecting the pixel electrode and the switching element,
9. The electro-optical device inspection method according to claim 7, wherein the first electrical characteristic inspection step is to inspect the leakage of the switching element. The active matrix substrate has a switching element for driving the pixel electrode, a contact hole for electrically connecting the pixel electrode and the switching element, and a storage capacitor connected to the switching element,
9. The inspection of the electro-optical device according to claim 7, wherein the first electrical characteristic inspection step is to inspect a short circuit between the switching element and the storage capacitor. Method. 12. The method for inspecting an electro-optical device according to claim 9, wherein the second electrical characteristic inspection step is to inspect the continuity of the switching element. The inspection method for an electro-optical device according to claim 9, wherein the second electrical characteristic inspection step is to inspect a short circuit between the pixel electrodes. 14. The electro-optical device inspection method according to claim 7, wherein the first electrical characteristic inspection step is performed by heating the active matrix substrate. 15. A method for manufacturing an electro-optical device, comprising the inspection method for an electro-optical device according to claim 7.

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