JP2005077623A - Driving method of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a plasma display panel having a high-quality display performance, by attaining a driving method of a plasma display panel enabling luminance increasing, high gradation and stable operation, and to provide a plasma display device using it. <P>SOLUTION: The driving method of the plasma display panel can shorten the period of maintenance pulse by inserting a data pulse into both the sustaining pulse of the maintenance pulse and the scanning pulse in the driving method which makes an address period and a maintenance period overlap, by dividing the plasma display panel into block units. As the result, the driving method can attain luminance increasing by increasing the number of the maintenance pulses. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for driving a plasma display panel that displays an image by controlling discharge.

  A plasma display panel (PDP) has an advantage that it can be made thin and have a large screen, and displays an image by utilizing light emission during discharge. Various attempts have been made to drive in units of blocks from the viewpoints of cost reduction, prevention of unnecessary radiation of electromagnetic waves, and higher brightness (for example, see Patent Document 1).

  8 to 10 show a method for driving the PDP described in Patent Document 1. FIG.

  FIG. 8 is a block diagram for explaining a conventional method of driving a PDP. The PDP 101, the address driver 102, four scan drivers 131 to 134, four sustain drivers 141 to 144, a discharge control timing generation circuit 105, and an A / A 1 shows a schematic configuration of a plasma display device having a D converter (analog / digital converter) 106, a scanning number conversion unit 107, and a subfield conversion unit 108.

  The A / D converter 106 converts the video signal VD into digital image data, and supplies the image data to the scan number conversion unit 107. The scanning number conversion unit 107 converts the image data into image data having the number of lines corresponding to the number of pixels of the PDP 101, and supplies the image data for each line to the subfield conversion unit 108. The image data for each line is composed of a plurality of pixel data respectively corresponding to a plurality of pixels of each line. The subfield conversion unit 108 divides each pixel data of the image data for each line into a plurality of bits corresponding to a plurality of subfields, and serially converts each bit of each pixel data to the address driver 102 for each subfield. Output.

  Discharge control timing generation circuit 105 generates discharge control timing signals SC1 to SC4 and discharge control timing signals SU1 to SU4 with reference to horizontal synchronizing signal H and vertical synchronizing signal V, and scan control timing signals SC1 to SC4 are scan drivers. 131 to 134, and discharge control timing signals SU1 to SU4 are supplied to sustain drivers 141 to 144, respectively.

  Next, FIG. 9 is a timing chart of the initialization period VST (or pseudo initialization period SST), the address period AD, and the sustain period SUS in each block of the plasma display device shown in FIG. The vertical axis in FIG. 9 indicates the lines from the first line to the 4th L line, and the horizontal axis indicates time. As shown in FIG. 9, the driving of the PDP 101 is performed by dividing the PDP 101 into four regions including the first to fourth blocks, and the discharge timing is controlled as follows. First, in the first subfield SF1, the initialization period VST is started for the first to fourth blocks. After the initialization period VST ends, the address period AD of the first block starts, and after the address period AD of the first block ends, the sustain period SUS of the first block starts. Next, the second block maintenance period SUS is started after the end of the first block maintenance period SUS so that the second block maintenance period SUS is started when half of the first block maintenance period SUS ends. After the address period AD of the second block starts and the address period AD of the second block ends, the sustain period SUS of the second block starts. Thereafter, similarly to the second block, the address period AD and the sustain period SUS of the third and fourth blocks are started.

  Thereafter, similarly to the second block, the pseudo initialization period SST, the address period AD, and the sustain period SUS of the third and fourth blocks are started.

  FIG. 10 shows pulses as drive voltages applied to the address electrode 111, the scan electrode 112, and the sustain electrode 113 when another block performs an address discharge during the sustain period of a certain block in the plasma display device shown in FIG. It is a timing chart which shows an example. As shown in FIG. 10, for example, in the first subfield SF1, the address period AD of the second block is set during the sustain period SUS of the first block. In such a case, as shown in FIG. 10, the scan pulse Psc and the sustain pulse Psu are applied to the scan electrode 112 and the sustain electrode 113 of the block during the sustain period SUS, respectively. On the other hand, the data pulse Pw is applied to the address electrode 111 during the period T in which the scan electrode 112 of the block in the sustain period SUS is low and the sustain electrode 113 is high.

  Thus, even when the address electrode 111 is used in common for each block, it is possible to eliminate the interference of the drive pulse between the blocks, and to stably perform the sustain discharge and the address discharge in parallel.

  In this way, the 4L scan electrodes 112 and the sustain electrodes 113 are divided into four blocks, and the sustain period is set so that the number of the scan electrodes 112 and the sustain electrodes 113 that are simultaneously subjected to the sustain discharge is 2L or less. Since the scan electrode 112 and the sustain electrode 113 are sustain-discharged while being shifted for each block, the level of unnecessary electromagnetic waves can be suppressed to half or less, and the peak current during the sustain period is reduced to half or less to provide a scan driver. The costs of 131 to 134 and the sustain drivers 141 to 144 can be reduced. Further, the address period can be shortened by shifting the address time between the blocks and overlapping the sustain period and the address period. As a result, the address period can be increased and high luminance can be achieved.

That is, in the above-described driving method of the PDP, the sustain period SUS and the address period AD are overlapped to shorten the address period AD. As a result, in principle, the sustain period SUS can be increased and high luminance can be achieved. As a method of inserting the data pulse into the sustain pulse, the data pulse is inserted in synchronization with the sustain pulse so as not to affect the sustain pulse.
JP 2001-265281 A

  However, in the above-described driving method of the PDP, the period of one of the scan pulse and the sustain pulse is extended and the data pulse is applied only during the high period. The number of scan pulses and sustain pulses that can be actually realized is reduced. As a result, there is a problem that the luminance becomes insufficient.

  For example, in FIG. 10, if the width of the scan pulse is 2.5 μs and the width of the data pulse is 2.5 μs, the sustain pulse is 2.5 × 3 = 7.5 μs. At this time, the period of the sustain pulse is 10.0 μs.

  When the number of sustain pulses in this case is calculated, if the panel is driven by HD (1024 × 768 dots, dual scan), the number of scans in one field is 384 lines. Since the data pulse is executed three times with a period of 10 μs, the average address time is 3.3 μs, and it takes 1.28 ms to drive the 384 lines.

  Next, assuming that the initialization period is 160 μs, the minimum period per SF is 1.28 + 0.16 = 1.44 ms. Dividing one field period by this period gives 11.6, and the number of SFs that can be realized is 11. At this time, when the 384 lines are divided into two blocks and simultaneous driving is performed, the address time per SF is 3.3 μs × 192 lines = 640 μs, and the address time for 11 SF is 8.8 ms together with the reset period. Become. The remaining time of one field is a maintenance period, which is 7.87 ms. Since the sustain period is 10 μs, the total number of pulses is 7.87 ms / 0.01 ms = 787 pulses. If the number of pulses is 255 and is defined as 1 time, 787 pulses are 3.1 times.

  That is, in order to secure the same luminance as the conventional one, a multiple of nearly six times is necessary, and this driving method only gives about half the luminance.

  In FIG. 10, if the width of the scan pulse is 2.5 μs and the width of the data pulse is 2.0 μs, the sustain pulse is 2.0 × 3 = 6.0 μs. At this time, the period of the sustain pulse is 8.0 μs.

  As a result of the same calculation when the sustain pulse period is shortened, it has been confirmed that even if the number of SFs is set to 10, the multiple of the sustain pulse increases only to about 4.4 times.

  The present invention has been made in view of the above problems, and has achieved a plasma display panel driving method capable of achieving high brightness, high gradation, and stable operation, and a plasma display having high-quality display performance and use thereof. An object of the present invention is to provide a plasma display apparatus.

  In order to achieve the above object, a driving method of a PDP according to the present invention includes a plurality of row electrode pairs extending in a row direction to form display lines, a plurality of column electrodes arranged to intersect the row electrode pairs, In a driving method of a plasma display panel having a discharge space that forms a light emitting unit at a position where a column electrode and a row electrode pair intersect, a plurality of row electrodes are divided into a plurality of blocks, and each of the blocks includes an address period and The sustain period is separated and sequentially executed, the address periods are shifted so that the address periods of the blocks do not overlap in time, and the data pulse is superimposed on both the scan pulse and the sustain pulse that are sustain pulses of the sustain period Applied.

  The driving method of the PDP according to the present invention increases the sustain period by inserting a data pulse in synchronization with the phase of both sustain pulses (sustain pulse, scan pulse), thereby achieving high brightness, high gradation, and stable operation. It is an object of the present invention to provide a plasma display panel having a high quality display performance and a plasma display apparatus using the plasma display panel by realizing a possible plasma display panel driving method.

  That is, according to the first aspect of the present invention, a plurality of row electrode pairs extending in the row direction to form display lines, a plurality of column electrodes arranged to intersect the row electrode pairs, and the column electrodes In a method for driving a plasma display panel having a discharge space that forms a light emitting unit at a position where a row electrode pair intersects, a plurality of row electrodes are divided into a plurality of blocks, and each of the blocks has an address period and a sustain period Are separated and sequentially executed, the address periods are shifted so that the address periods of the blocks do not overlap in time, and the data pulse is applied to both the scan pulse and the sustain pulse that are the sustain pulses of the sustain period. A method of driving a plasma display panel.

  The invention according to claim 2 is characterized in that, in the invention according to claim 1, the data pulse is raised in synchronism with the rising edge of the scan pulse or sustain pulse which is the sustain pulse of the sustain period. It is.

  The invention described in claim 3 is characterized in that, in the invention described in claim 1, the data pulse is lowered after the sustain emission of the scan pulse or sustain pulse which is the sustain pulse of the sustain period is completed. It is.

  According to a fourth aspect of the present invention, in the first aspect of the present invention, the data pulse falls in synchronization with the fall of the waveform of the scan pulse or sustain pulse that is the sustain pulse of the sustain period. Is.

  The invention described in claim 5 is characterized in that, in the invention described in claim 1, the data pulse is raised after the sustain emission of the scan pulse or the sustain pulse that is the sustain pulse of the sustain period is completed. It is.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a schematic configuration of a plasma display device using a PDP driven by a PDP driving method according to an embodiment of the present invention. The screen of PDP 1 is divided into upper and lower parts with respect to the configuration diagram of FIG. 8 used in the description of the conventional example. Two address drivers 2a, 2b, two sets of scan drivers (SC-1, SC-2), (SC-3, SC-4), two sets of sustain drivers (SU-1, SU-2), (SU-3, SU-4) are provided. In addition, a discharge control timing generation circuit 5 is provided. Reference numeral 14 denotes a light emitting unit.

  Discharge control timing generation circuit 5 generates discharge control timing signals SC-1, SC-2, SC-3, SC-4 with reference to horizontal synchronizing signal H and vertical synchronizing signal V, and discharge control timing signal SC-1 To 4 are supplied to the scan drivers 31 to 34, respectively, and the discharge control timing signals SU1 to SU4 are supplied to the sustain drivers 41 to 44, respectively.

  The PDP 1 includes a plurality of address electrodes 11 (11a, 11b) corresponding to upper and lower column electrodes, and 2K scan electrodes 12 (12a, 12b) corresponding to 2L (L is an arbitrary positive number) row electrodes. Sustain electrode 13 (13a, 13b) is included. In the upper region of the PDP 1, the address electrode 11a is connected to the address driver 2a, and in the lower region of the PDP, the address electrode 11b is connected to the address driver 2b.

  The scan electrodes 12a from the first line to the second K line in the upper area of the PDP 1 are connected to the scan drivers 31 to 32, and the scan electrodes 12b from the first line to the second K line in the lower area of the PDP are connected to the scan drivers 33 to 34. It is connected.

  Similarly, the sustain electrodes 13a from the first line to the second K line in the upper region of the PDP 1 are connected to the sustain drivers 41 to 42, and the sustain electrodes 13b from the first line to the second K line in the lower region of the PDP 1 are connected to the sustain driver 13-42. The drivers 43 to 44 are commonly connected.

  The scan drivers 31 to 32 apply setup pulses, write pulses, and sustain pulses to the K scan electrodes 12a in accordance with the discharge control timing signals SC1 and SC2 supplied from the discharge control timing generation circuit 5. The scan drivers 33 to 34 apply setup pulses, write pulses, and sustain pulses to the K scan electrodes 12b in accordance with the discharge control timing signals SC3 to SC4 supplied from the discharge control timing generation circuit 5.

  The sustain drivers 41 to 42 simultaneously drive the K sustain electrodes 13a according to the discharge control timing signals SU-1 and SU-2 supplied from the discharge control timing generation circuit 5. The sustain drivers 43 to 44 simultaneously drive the K scan electrodes 13b according to the discharge control timing signals SU3 to 4 provided from the discharge control timing generation circuit 5.

  That is, in the plasma display device described above, the PDP 1 is divided into two parts, an upper part and a lower part, and address drivers 2a and 2b, scan drivers 31 to 34, and sustain drivers 41 to 44 are provided for each region. The discharge state can be set, and various discharge states can be combined more easily.

  FIG. 2 is a timing chart of initialization period VST (or pseudo initialization period SST), address period AD, and sustain period SUS in each block of the plasma display device shown in FIG. The vertical axis in FIG. 2 indicates lines from the first line to the 4th L line, and the horizontal axis indicates time.

  As shown in FIG. 2, the scan electrode 12 a (FIG. 1) and the sustain electrode 13 b (FIG. 1) from the first to the L-th line of the PDP 1 (FIG. 1) divided into a total of four divided into upper and lower parts are the first. The scan electrode 12a and the sustain electrode 13a from the (L + 1) th to the 2nd L line become the second block, the scan electrode 12b and the sustain electrode 13b from the 2nd (L + 1) to the 3rd L line become the third block, and the 3L + 1 The scan electrode 12b and the sustain electrode 13b up to the 4th L line form a fourth block.

  The address drivers 2a and 2b (FIG. 1), the scan drivers 31 to 34 (FIG. 1), and the sustain drivers 41 to 44 (FIG. 1) control the discharge timing for each block as follows.

  First, in the first subfield SF1, the initialization period VST is started for the first and third blocks. After the initialization period VST ends, the address period AD of the first and third blocks starts, and after the address period AD of the first and third blocks ends, the sustain period of the first and third blocks SUS is started.

  Next, a predetermined time from the start of the sustain period SUS of the first and third blocks so that the sustain period SUS of the second and fourth blocks starts in the middle of the sustain period SUS of the first and third blocks. After the elapse of time, the address period AD of the second and fourth blocks starts, and after the address period AD of the second and fourth blocks ends, the sustain period SUS of the second and fourth blocks starts. The

  Next, in the second subfield SF2, the pseudo initialization period SST of the first and third blocks is started when the sustain period SUS of the first subfield SF1 of the second and fourth blocks ends. The After the pseudo initialization period SST of the first and third blocks ends, the address period AD of the first and third blocks starts, and after the address period AD of the first and third blocks ends, The maintenance period SUS of the first and third blocks is started.

  Next, when the address period AD of the first and third blocks ends, the pseudo initialization period SST of the second and fourth blocks starts. After the pseudo initialization period SST of the second and fourth blocks ends, the address period AD of the second and fourth blocks starts, and after the address period AD of the second and fourth blocks ends, 2. The sustain period SUS of the fourth block is started.

  Further, the discharge timing is controlled for each block by the address drivers 2a and 2b, the scan drivers 31 to 34, and the sustain drivers 41 to 44, and one field is divided into a plurality of subfields, for example, 12 subfields for each block. It is divided. The sustain period of each subfield is weighted with brightness of 1, 2, 4, 6, 10, 14, 19, 26, 33, 40, 47, 53. The level can be adjusted in 256 steps from 0 to 255, and gradation display is performed.

  The first subfield SF1 is separated into an initialization period (VST), an address period, and a sustain period, and each subfield after the second subfield SF2 includes a pseudo initialization period (SST), an address period, and a sustain period. Separated into maintenance periods.

  As described above, the PDP 1 is divided into a total of 4 blocks of the upper and lower areas and is driven independently. Furthermore, the address period AD can be shortened by shifting the address time between the blocks and overlapping the address period AD and the sustain period SUS. As a result, the sustain period SUS can be increased.

  FIG. 3 is a timing chart showing an example of driving voltages of address pulses, scan pulses, and sustain pulses when another block performs address discharge during the sustain period of a certain block in the plasma display device shown in FIG. .

  For example, as shown in FIG. 2, in the first subfield SF1, the address period AD of the second block is set during the sustain period SUS of the first block. In such a case, as shown in FIG. 3, sustain pulses Psc and Psu are applied to the scan electrode 12 and the sustain electrode 13 of the block during the sustain period SUS, respectively.

On the other hand, a write pulse Pw is applied to the address electrode 11 within the pulse of the scan electrode 12 and the sustain electrode 13 in the block during the sustain period SUS, and the write pulse (data Pulse) is applied.
As a result, even when the address electrode 11 is used in common for each block, it is possible to eliminate the interference of the drive pulse between the blocks and to stably perform the sustain discharge and the address discharge in parallel. Furthermore, since the data pulse is inserted between both sustain pulses, the sustain pulse cycle can be shortened, and high brightness can be realized.

  Next, in the above case, the number of sustain pulses is estimated.

  In FIG. 3, the width of the data pulse is 2.0 μs, the width of the scan pulse is 2.5 μs, and the width of the sustain pulse is 2.5 μs. At this time, the period of the sustain pulse is 5.0 μs.

  When the PDP 1 is driven by HD (1024 × 768 dots, dual scan), the number of scans in one field is 384 lines. Since the data pulse is executed twice with a period of 5 μs, the average address time is 2.5 μs, and it takes 0.96 ms to drive the 384 lines.

  Next, assuming that the reset period is 160 μs, the minimum period per SF is 0.96 + 0.16 = 1.12 ms. When one field period is divided by this period, 14.9 is obtained, and the number of SFs that can be realized is 14. At this time, when the 384 lines are divided into two blocks and simultaneous driving is performed, the address time per SF is 2.5 μs × 192 lines = 480 μs, and the address time for 11 SF is 8.96 ms together with the reset period. Become. The remaining time of one field is a maintenance period, which is 7.7 ms. Since the sustain period is 5 μs, the total number of pulses is 7.87 ms / 0.005 ms = 1541 pulses. If the number of pulses is 255 and defined as 1 time, 1541 pulses are 6.0 times. In order to ensure the predetermined brightness, a multiple of nearly 6 times is required, and it has been confirmed that the brightness can be secured by the driving method according to the present invention. Further, the number of subfields increased from 11 to 14, and it was confirmed that gradation can be expressed with higher accuracy.

  In the above calculation, when the number of SFs is set to 12, the number of sustain pulses is 1797, and the multiple is 7.0. In this case, it is possible to increase the luminance further than the predetermined luminance, and it is possible to realize high luminance.

  As described above, in the driving method in which the screen is divided into blocks and the sustain period and the address period overlap, the data pulse is inserted into both the sustain pulse and the scan pulse, thereby shortening the sustain pulse cycle. can do. As a result, the number of sustain pulses can be increased, and high brightness can be realized.

  In addition, this method has an advantage that stable operation is expected because the individual blocks are driven in the same manner as in the prior art, and stable driving can be performed relatively easily only by synchronizing the blocks.

(Embodiment 2)
Hereinafter, a method of driving a PDP according to an embodiment of the present invention will be described with reference to FIG.

  In the block drive according to the embodiment of the present invention, the address period of another block is overlapped during the maintenance period of a certain block at a certain time. For example, as shown in FIG. In SF1, the address period AD of the second block is set during the sustain period SUS of the first block.

  Here, FIG. 4 shows a timing chart when the address operation and the sustain operation overlap.

  As shown in FIG. 4, a sustain pulse (scan pulse, sustain pulse) is applied to the scan electrode 12 and the sustain electrode 13 of the first block during the sustain period. The sustain pulse has no pause period and is alternately generated.

  The light emission state at that time is converted into an electrical signal by a light receiving diode or the like, and the light emission intensity is measured. This state is shown as a sustained light emission state in FIG. The data pulse is inserted into both the scan pulse and the sustain pulse, and has a timing that does not affect the sustain light emission state.

  Here, since the wall charge state changes due to the voltage fluctuation of the data pulse, if the amount of change of the data pulse is large, the wall potential may fluctuate and the sustain light emission may stop. Therefore, attention is paid to the change point of the data pulse. That is, this is a method of relatively suppressing the amount of change in voltage by synchronizing the rising edge of the data pulse with the rising edge of the sustain pulse.

  On the other hand, since the data pulse is terminated somewhere in the sustain pulse, attention must be paid to the falling position. As shown in FIG. 4, in order not to affect the sustain light emission, the data pulse is lowered after the light emission end point (point a in the figure). As a result, even when the address electrode 11 is used in common for each block, it is possible to eliminate the interference of the drive pulse between the blocks, and to stably perform the sustain discharge and the address discharge in parallel.

  As described above, the period of the sustain pulse can be shortened by inserting the data panel into both of the sustain pulses. As a result, since the number of sustain pulses can be increased, high brightness can be realized.

  Furthermore, since the data pulse can be turned on / off at a phase that does not affect the sustain light emission, the address operation in the other block can be reliably and stably performed during the sustain period of the other block.

(Embodiment 3)
Hereinafter, a method for driving a plasma display panel according to an embodiment of the present invention will be described with reference to FIG.

  As in the case of the second embodiment, a case is considered in which the address period of another block overlaps during the maintenance period of a certain block at a certain time.

  FIG. 5 shows a timing chart when the address operation and the sustain operation overlap. As shown in FIG. 5, the sustain pulses (scan pulse, sustain pulse) have no pause period and are alternately generated.

  The light emission state at that time is converted into an electric signal by a light receiving diode or the like, and the light emission intensity is measured. This state is shown as a sustained light emission state in FIG. The data pulse is inserted into both the scan pulse and the sustain pulse, and has a timing that does not affect the light emission state.

  Here, since the wall charge state changes due to the voltage fluctuation of the data pulse, if the amount of change of the data pulse is large, the wall potential may fluctuate and the sustain light emission may stop. Therefore, attention is paid to the change point of the data pulse. That is, it is a method of relatively suppressing the amount of voltage change by synchronizing the falling edge of the data pulse with the falling edge of the sustain pulse.

  On the other hand, since the data pulse is started somewhere in the sustain pulse, attention must be paid to the rising position. As shown in FIG. 5, in order not to affect the sustain light emission, the data pulse is raised after the light emission end point (point a in the figure). In this way, data pulses are inserted at a phase that does not affect light emission.

  As a result, even when the address electrode 11 is used in common for each block, it is possible to eliminate the interference of the drive pulse between the blocks, and to stably perform the sustain discharge and the address discharge in parallel.

  As described above, the period of the sustain pulse can be shortened by inserting the data panel into both of the sustain pulses. As a result, since the number of sustain pulses can be increased, high brightness can be realized.

  Furthermore, since the data pulse can be turned on / off at a phase that does not affect the sustain light emission, the address operation in the other block can be reliably and stably performed during the sustain period of the other block.

  As shown in FIG. 6, a pulse in which both the rising / falling phases of the sustain pulse (scan pulse and sustain pulse) and the rising / falling phase of the data pulse are synchronized may be used.

  As shown in FIG. 7, in order to further shorten the address period, two or more data pulses are inserted into one sustain pulse (scan pulse, sustain pulse) while maintaining the phase relationship between the pulses. May be. In this case, a part where the ON / OFF state of the sustain pulse and the ON / OFF phase of the data pulse do not match occurs, but the influence can be minimized because the timing is different from the place where the sustain light emission occurs. .

  As described above in Embodiments 1 to 3, according to the PDP driving method of the present invention, in the driving method in which the surface of the PDP is divided into blocks and the sustain period and the address period overlap, The period of the sustain pulse can be shortened by inserting the data pulse into both the sustain pulse and the scan pulse. As a result, the number of sustain pulses can be increased, and high brightness can be realized.

  In addition, the period of the sustain pulse can be shortened by inserting the data pulse into both the sustain pulse and the scan pulse. As a result, since the address time can be shortened, a long sustain period can be secured. As a result, the number of subfields can be increased, and gradation can be realized with high accuracy.

  In addition, since the block drive of the present invention is a drive in which the address operation and the sustain operation are separated in the individual blocks as in the conventional case, stable operation is expected, and it is relatively easy to stabilize only by synchronizing the blocks. There is an advantage that it can be driven.

  In addition, by synchronizing the rising or falling phase of the data pulse with the rising or falling edge of the sustain pulse (scan pulse, sustain pulse), the address can be executed without affecting the sustain light emission. During the period, the address operation in other blocks can be reliably performed stably.

  As described above, the present invention increases the sustain period by inserting the data pulse in synchronism with the sustain pulse (sustain pulse, scan pulse), thereby achieving high brightness, high gradation, and stable operation. A plasma display panel driving method can be realized, and a plasma display having high-quality display performance and a plasma display device using the plasma display can be provided.

1 is a block diagram showing a schematic configuration of a plasma display device using a plasma display panel driven by a plasma display panel driving method according to an embodiment of the present invention. 1 is a timing chart for explaining a driving method of a plasma display panel according to an embodiment of the present invention. 1 is a timing chart showing an example of a driving voltage in a driving method of a plasma display panel according to an embodiment of the present invention. 1 is a timing chart showing an example of a driving voltage in a driving method of a plasma display panel according to an embodiment of the present invention. 1 is a timing chart showing an example of a driving voltage in a driving method of a plasma display panel according to an embodiment of the present invention. 1 is a timing chart showing an example of a driving voltage in a driving method of a plasma display panel according to an embodiment of the present invention. 1 is a timing chart showing an example of a driving voltage in a driving method of a plasma display panel according to an embodiment of the present invention. A block diagram showing a schematic configuration of a plasma display device using a plasma display panel driven by a conventional plasma display panel driving method. Timing chart for explaining a driving method of a conventional plasma display panel Timing chart showing an example of drive voltage in a conventional plasma display panel drive method

Explanation of symbols

1 Plasma display panel (PDP)
2a, 2b Address driver 5 Discharge control timing generation circuit 6 A / D converter 7 Scan number conversion unit 8 Subfield conversion unit 11 (11a, 11b) Address electrode 12 (12a, 12b) Scan electrode 13 (13a, 13b) Sustain electrode 14 Discharge cells 31-34 Scan drivers 41-44 Sustain drivers

Claims (5)

A plurality of row electrode pairs extending in the row direction to form display lines, a plurality of column electrodes arranged to intersect the row electrode pairs, and a light emitting unit are formed at positions where the column electrodes and the row electrode pairs intersect In the method of driving a plasma display panel having a discharge space, a plurality of row electrodes are divided into a plurality of blocks, each of the blocks is sequentially executed by separating an address period and a sustain period, and each address period of the block A method of driving a plasma display panel, wherein the address period is shifted so as not to overlap in time, and the data pulse is applied to both the scan pulse and the sustain pulse that are sustain pulses in the sustain period. 2. The method of driving a plasma display panel according to claim 1, wherein the data pulse is raised in synchronism with the rise of the waveform of the scan pulse or sustain pulse which is a sustain pulse in the sustain period. 2. The method of driving a plasma display panel according to claim 1, wherein the data pulse is lowered after the sustain emission of the scan pulse or the sustain pulse which is the sustain pulse of the sustain period is finished. 2. The method of driving a plasma display panel according to claim 1, wherein the data pulse falls in synchronization with the fall of the waveform of a scan pulse or a sustain pulse which is a sustain pulse of the sustain period. 2. The method of driving a plasma display panel according to claim 1, wherein the data pulse is raised after the sustain emission of the scan pulse or sustain pulse, which is the sustain pulse of the sustain period, is completed.

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