JP2005072625A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a highly reliable semiconductor device. <P>SOLUTION: The method of manufacturing the semiconductor device includes a step of forming a first SiO<SB>x</SB>N<SB>y</SB>film on a glass substrate, a step of forming an island-like semiconductor layer on the SiO<SB>x</SB>N<SB>y</SB>film, and a step of forming a second SiO<SB>x</SB>N<SB>y</SB>film to cover the island-like semiconductor layer. The method also includes a step of forming a gate electrode on the second SiO<SB>x</SB>N<SB>y</SB>film, a step of forming a mask having a broader width than the gate electrode has on the gate electrode, and a step of injecting boron or phosphorus into the island-like semiconductor layer through the mask. In addition, the method also includes a step of injecting boron or phosphorus into the island-like semiconductor layer by using the gate electrode as a mask after the mask is removed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The invention disclosed in this specification relates to a method for manufacturing a semiconductor device using a thin film semiconductor having crystallinity. In particular, the present invention relates to a method for manufacturing a thin film transistor.

  Recently, a technique for manufacturing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that interest in the active matrix liquid crystal display device has increased.

  In an active matrix liquid crystal display device, a TFT is arranged in each of millions of pixels arranged in a matrix, and charges entering and exiting each pixel electrode are controlled by a switching function of the TFT.

  Further, there is an interest in a structure in which a circuit for driving TFTs arranged in a matrix (referred to as a peripheral driving circuit) is integrated with TFTs on the same glass substrate.

  The TFTs arranged in a matrix in the pixel portion can be visually confirmed by the liquid crystal display. For example, in the case of a normally black liquid crystal display, a portion where the TFT does not operate appears as a black dot during white display.

As described above, since the malfunction of the TFT greatly deteriorates the appearance, high reliability is required for all of the millions of TFTs.
In particular, the problem of TFT degradation eventually causes malfunction, and various reliability tests have been conducted among researchers.

  One such reliability test is the BT test. This is a so-called acceleration test, in which a plus / minus bias voltage and heating are applied to the TFT to accelerate its deterioration.

For example, the plus / minus bias voltage accelerates the deterioration of the gate insulating film, the gate insulating film / active layer interface, the contact portion, and the like.
Heating also activates mobile ions and accelerates degradation of the channel / drain boundary region.

  As a result of repeating the reliability test of the TFT by such a BT test, the present applicants have found that the base film formed on the surface of the glass substrate greatly affects the reliability of the TFT.

Corning glass and the like that are often used recently contain some impurities such as Na and K, unlike quartz glass.
When these impurities diffuse around the active layer of the TFT, a parasitic channel is formed at the active layer / underlying film interface or the active layer / gate insulating film interface.
These cause an increase in leakage current during TFT operation. Further, these diffused impurities cause the threshold voltage to shift.

  Therefore, a generally manufactured TFT employs a structure in which an insulating thin film is sandwiched between a glass substrate and a device body. This insulating film (hereinafter referred to as a base film) is required to have an effect of preventing diffusion of impurities from the glass substrate and an effect of improving the adhesion with a thin film deposited on the base film.

  FIG. 1 shows a result of examining a TFT using a generally known TEOS-based silicon oxide film (first TEOS film) as a base film by a BT test.

  In the BT test, a +20 V voltage application and 150 ° C. heating were simultaneously applied to the TFT to be evaluated for 1 hour, a + BT test, and a −20 V voltage application and 150 ° C. heating were simultaneously applied for 1 hour. . Moreover, the evaluation result of only baking at 150 ° C. for 1 hour was also added.

  When the BT test as described above was performed, a shift in threshold voltage was confirmed in both the + BT test and the -BT test. In particular, in the -BT test, it is apparent that the deterioration has progressed considerably.

  Furthermore, in the -BT test, the drain current Id does not rise well in the on region (the region where the TFT is on), and the state of the active layer / gate insulating film interface is poor (the subthreshold coefficient S is large). Can be confirmed.

  In addition, it was confirmed that deterioration was caused only by baking at 150 ° C. for 1 hour. This is presumably because mobile ions have moved through the underlying film.

  Next, FIG. 2 shows the result of examining a TFT using a TEOS-based silicon oxide film (second TEOS film) in the BT test as in FIG. However, this silicon oxide film is a denser film by changing the film forming conditions.

  However, as shown in FIG. 2, the threshold voltage shift and the deterioration of the active layer / gate insulating film interface cannot be improved, and the reliability of the TFT cannot be improved even if the film quality is made dense.

In addition, the present applicants used a silicon nitride film having a high impurity blocking effect as a base film, but the film is peeled off due to large stress strain with the glass substrate and poor adhesion to the glass substrate. It was not possible to adopt due to problems such as.
Further, since the silicon nitride film has Si clusters as charge trapping centers, there is also a problem that the threshold drift is significantly affected in the BT test.

  From the above, TFTs manufactured by processing in the temperature range of 300 to 750 ° C., typically 300 to 650 ° C., require a highly reliable base film with good adhesion to the glass substrate. .

The invention disclosed in this specification provides a technique for solving the above-described problems and preventing the diffusion of impurities from a glass substrate and forming a base film that gives high reliability to the TFT.
Another object of the present invention is to protect the channel formation region, which is the most important part of the TFT, by giving the gate insulating film and the interlayer insulating film a role of a protective film that prevents contamination from the surroundings.

One of the inventions disclosed in this specification is:
An insulated gate field effect semiconductor device,
Having an insulating thin film formed on a glass substrate having an insulating surface;
The insulating thin film is a thin film represented by SiOxNy.

  The thin film represented by SiOxNy (hereinafter abbreviated as SiON film) has an energy band gap of 5.3 to 7.0 eV, a relative dielectric constant of 4 to 6, and x and y are 0 <x < 2, 0 <y <4/3 is satisfied.

The above x and y can be changed depending on manufacturing conditions, and may be set according to the embodiment. In addition, the composition must include N of 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ⁻³ . Further, when H is contained in 1 × 10 ²⁰ to 1 × 10 ²² cm ⁻³ , it is convenient for terminating dangling bonds of the silicon film constituting the active layer and improving crystallinity.

  Further, if chlorosilane or dichlorosilane is used as a source gas when forming the SiON film, chlorine can be added to the film.

In the SiON film having the above composition, N (SiN bond) contained in the film prevents drift of alkali metal (Na, K, etc.) ions and heavy metal (Fe, Ni, Co, etc.) ions, Impurities are prevented from outdiffusing from the glass substrate to the device.
Chlorine has the effect of neutralizing Na ions and Fe ions as NaCl and FeCl.

  Of course, this technique is applicable in all cases where a thin film device is formed on a glass substrate.

  Here, FIG. 3 shows the result of the BT test when the SiON film is used as the base film. The method for measuring the TFT characteristics is the same throughout FIGS.

  Compared with the case of FIG. 1 and FIG. 2 using a TEOS-based silicon oxide film as a base film, it is confirmed from the result of using the SiON film shown in FIG. 3 that the threshold shift is clearly improved. it can.

  Further, when the result of the -BT test is seen, it can be confirmed that the subthreshold coefficient S is small and the state of the active layer / gate insulating film interface is also good.

  The adhesion between the base film and the silicon film can be greatly improved by providing a thin silicon oxide film layer of 1 to 20 nm between the base SiON film and the silicon film constituting the active layer.

Other inventions disclosed in this specification are:
An insulated gate field effect semiconductor device,
In the active layer composed of a silicon film,
The channel forming region of the active layer is characterized by being surrounded by a thin film indicated by SiO _x N _y on the lower side and the upper side thereof.

The channel forming region is in contact with the thin film indicated by SiO _x N _y on the lower side and / or the upper side thereof. In the case of a planar type or stagger type TFT, the base film and the gate insulating film are formed of the SiON film. It is that.

Since the SiON film used in the present invention is a so-called silicon oxide film, the usage is not limited to the base film.
For example, the following has been clarified by the present applicants as an effect when the SiON film is used as the gate insulating film.

(1) It is difficult to cause electrostatic breakdown due to static electricity. (2) It is difficult for charge trapping centers to exist inside it. (3) It is difficult for ions in the active layer to diffuse into the gate insulating film. Difficult to diffuse metal components from the included gate electrode

  Therefore, the structure in which the channel formation region is sandwiched between the base film and the gate insulating film is extremely useful in terms of increasing the reliability of the TFT.

  In particular, a structure in which a thin silicon oxide film having a thickness of 1 to 20 nm is formed on the surface of the base film and the surface of the active layer, the channel formation region is covered with the silicon oxide film, and is further sandwiched between the base film and the gate insulating film made of the SiON film. Is.

  By doing so, the state of the active layer / gate insulating film interface is improved, so that the threshold value of the TFT becomes around 0 V, and the n-ch / p-ch TFT can be normally off.

Other inventions disclosed in this specification are:
An insulated gate field effect semiconductor device,
Having an active layer composed of a silicon film;
In the structure having a gate insulating film formed in contact with the active layer,
The channel forming region having the above structure is characterized in that the lower side and / or the upper side thereof are surrounded by a thin film indicated by SiO _x N _y .

  The gist of the present invention is that the channel forming region including the gate insulating film is surrounded by the base film and the interlayer insulating film in the case of the planar type, reverse planar type, staggered type, and reverse staggered type TFT.

  That is, the object is to protect the channel formation region which is the most important part of the TFT from impurities entering from the outside.

(Function)
According to the present invention, N (SiN bond) contained in the SiON film prevents drift of alkali metal (Na, K, etc.) ions and heavy metal (Fe, Ni, Co, etc.) ions, and impurities are externally introduced. It plays a role in suppressing diffusion to the device.

  That is, a highly reliable TFT that can withstand an accelerated test such as a BT test can be manufactured.

  By using a SiON film as a base film, drift of alkali metal (Na, K, etc.) ions and heavy metal (Fe, Ni, Co, etc.) ions is prevented, and impurities are prevented from diffusing from the glass substrate to the device. I was able to.

  In addition, since the thin silicon oxide film 403 is formed on the surface of the base film 402, adhesion between the base film 402 and the island-shaped semiconductor layer 404 is improved.

Further, by forming the thin silicon oxide film 405 on the surface of the island-shaped semiconductor layer 404, the state of the active layer / gate insulating film interface is improved, the threshold value of the TFT becomes around 0 V, and p-ch / n- Both chTFTs could be normally off.
In addition, the crystallinity of the active layer was improved due to hydrogen termination during this step.

  Further, it has been found that the amount of C (carbon) at the active layer / gate insulating film interface is reduced by an order of magnitude by forming a thin silicon oxide film 405 on the surface of the island-shaped semiconductor layer 404. Therefore, the variation of the threshold value of the TFT is reduced, and display unevenness when used in the pixel portion of the liquid crystal display device can be suppressed.

  It was also confirmed that the impurities from the atmosphere can be prevented by enclosing the channel formation region with the SiON film.

  These improvement measures according to the present invention make it possible to manufacture a highly reliable TFT that can withstand an accelerated test such as a BT test.

This embodiment relates to a manufacturing process of a thin film transistor (TFT) using a SiON film as a base film.
A manufacturing process of a TFT using the present invention is shown in FIG.

  First, a glass substrate 401 having an insulating surface is prepared. Typical glass substrates are Corning 7059 and 1737 substrates. Of course, a quartz substrate may be used. In this embodiment, a Corning 7059 substrate is used.

  Next, a SiON film having a thickness of 50 nm to 1.5 μm is formed as the base film 402. In consideration of optimization, the thickness may be 500 nm or less, but a film thickness of 100 to 500 nm is desirable in consideration of reliability.

The deposition conditions for this SiON film are as follows.
RF power 200W
Gas flow rate SiH ₄ : 10 SCCM N ₂ O: 200 SCCM
Gas pressure 0.3 torr
Deposition temperature 350-400 ° C
Distance between electrodes 25mm (for parallel plate type)
Deposition rate 100nm / min

  The SiON film formed under these conditions is characterized by a high film forming speed and a low etching rate. Table 1 shows the result of comparison with other TEOS silicon oxide films.

A high deposition speed means a good throughput, and a low etching rate means that the film quality is dense.
Therefore, it can be understood that the SiON film is most excellent in that the film forming speed is high and the etching rate is low.

  In this embodiment, the base film 402 is formed by a plasma CVD method in which a high frequency (13.56 MHz) is applied. However, other methods such as an LPCVD method, a photo CVD method, and a plasma CVD method in which a pulse waveform is applied are used. A phase method can be used.

  Next, a thin silicon oxide film 403 is formed on the surface of the base film 402, and this silicon oxide film 403 can be formed continuously from the formation of the base film 402.

In this embodiment, O _{2 is} added to the source gas for the last 1 to 10 seconds when the base film 402 is formed. The amount of O ₂ added is adjusted to be 1 to 20% of N ₂ O.
Then, since the reaction between Si and O ₂ is fast in the plasma, a thin silicon oxide film 403 having a thickness of 1 to 20 nm is formed near the surface of the base film.

Alternatively, the thin silicon oxide film 403 may be formed by a method of performing treatment with O ₂ plasma after forming the base film 402.

  The thin silicon oxide film 403 formed in this manner gives the effect of improving the adhesion with a silicon film formed on the base film 402 later.

  Next, an amorphous silicon film having a thickness of 50 nm (not shown) is formed by a plasma CVD method or a low pressure thermal CVD method, and crystallized by an appropriate crystallization method. This crystallization may be performed by heating or laser light irradiation.

  Next, the crystalline silicon film obtained by crystallizing the amorphous silicon film is patterned to form an island-shaped semiconductor layer 404 constituting the active layer.

Next, plasma treatment is performed on the island-shaped semiconductor layer 404 under the following conditions to form a thin silicon oxide film 405.
RF power 200W
Gas flow rate H ₂ : 100 SCCM O ₂ : 100 SCCM
Gas pressure 0.3 torr
Processing temperature 350-400 ° C
Distance between electrodes 25mm (for parallel plate type)
Processing time 10sec ~ 5min

H ₂ and O ₂ may be used separately, or plasma treatment with H ₂ may be performed first, followed by plasma treatment with O ₂ . The reverse is also possible.

By this plasma treatment, the surface of the island-shaped semiconductor layer 404 is cleaned. Since the thin silicon oxide film layer formed in a clean state exists at the active layer / gate insulating film interface, the interface state is greatly reduced.
Therefore, the threshold value of the TFT becomes around 0 V, and both the p-ch / n-ch TFTs can be normally off.

  Further, since the amount of C (carbon) at the interface between the active layer and the gate insulating film can be reduced by an order of magnitude, variation in the threshold value of the TFT is reduced, and display unevenness when used in the pixel portion of the liquid crystal display device Can be suppressed.

Further, since the dangling bonds in the active layer are hydrogen-terminated by the H ₂ plasma, the crystallinity of the active layer is improved.

  Next, a silicon oxide film 406 that functions as a gate insulating film later is formed to a thickness of 150 nm. The gate insulating film 406 may be a SiON film or a silicon nitride film, but it is desirable to use a SiON film in order to further improve the reliability.

  If a SiON film is used as the gate insulating film 406, the gate insulating film 406 may be formed under the same film formation conditions as the base film.

  Next, a film 407 made of aluminum or a material containing aluminum as a main component is formed to a thickness of 400 nm. This aluminum film 407 functions as a gate electrode later.

Next, anodization is performed in the electrolytic solution using the aluminum film 407 as an anode. As the electrolytic solution, an ethylene glycol solution of 3% tartaric acid neutralized with aqueous ammonia and adjusted to PH = 6.92 is used.
Moreover, it processes as a formation current 5mA and the ultimate voltage 10V by using platinum as a cathode.

  The dense anodic oxide film 408 formed in this way has an effect of improving adhesion with the photoresist later. Further, the thickness of the anodic oxide film 408 can be controlled by controlling the voltage application time. (Fig. 4 (A))

  4A is obtained, the aluminum film 407 is patterned to form a gate electrode (not shown).

  Next, a second anodic oxidation is performed to form a porous anodic oxide film 409. The electrolytic solution is a 3% oxalic acid aqueous solution, which is treated with platinum as a cathode at a formation current of 2 to 3 mA and an ultimate voltage of 8V.

  At this time, anodic oxidation proceeds in a direction parallel to the substrate. Further, the length of the porous anodic oxide film 409 can be controlled by controlling the voltage application time.

  Further, after removing the photoresist with a dedicated stripping solution, a third anodic oxidation is performed to obtain the state of FIG.

  At this time, an electrolytic solution is used in which 3% of an ethylene glycol solution of tartaric acid is neutralized with ammonia water and adjusted to PH = 6.92. And it processes as a formation current 5-6mA and the ultimate voltage 100V by using platinum as a cathode.

  The anodic oxide film 410 formed at this time is very dense and strong. Therefore, it has an effect of protecting the gate electrode 411 from damage caused in a subsequent process such as a doping process.

  Next, an impurity is implanted into the island-shaped semiconductor layer 405 by ion doping. If an N-channel TFT is manufactured, P (phosphorus) is used as an impurity. If a P-channel TFT is manufactured, B (boron) is used as an impurity.

For example, P (phosphorus) is implanted at an acceleration voltage of 60 to 90 kV and a dose of 0.2 to 5 × 10 ¹⁵ atoms / cm ² .
In this embodiment, P (phosphorus) is implanted at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹⁵ atoms / cm ² .

  Then, the gate electrode 411 and the porous anodic oxide film 409 serve as a mask, and regions 412 and 413 to be the source / drain later are formed in a self-aligned manner.

Next, as shown in FIG. 1C, the porous anodic oxide film 409 is removed, and a second doping is performed. The second implantation of P (phosphorus) is performed at an acceleration voltage of 60 to 90 kV and a dose of 0.1 to 5 × 10 ¹⁴ atoms / cm ² .
In this embodiment, the acceleration voltage is 80 kV and the dose is 1 × 10 ¹⁴ atoms / cm ² .

  Then, the gate electrode 411 is used as a mask, and low-concentration impurity regions 414 and 415 having a lower impurity concentration than the source region 412 and the drain region 413 are formed in a self-aligned manner.

  At the same time, since no impurity is implanted immediately below the gate electrode 411, a region 416 functioning as a TFT channel is formed in a self-aligned manner.

  The low-concentration impurity region (or LDD region) 415 thus formed has an effect of suppressing the formation of a high electric field between the channel region 416 and the drain region 413.

Next, the ion-implanted P (phosphorus) is activated by irradiating with a KrF excimer laser at an energy density of 200 to 300 mJ / cm ² .
The activation may be performed by thermal annealing at 300 to 450 ° C. for 2 hours, or laser annealing and thermal annealing may be used in combination.

  Next, as shown in FIG. 4D, a silicon oxide film is formed as an interlayer insulating film 417 to a thickness of 1 μm by plasma CVD. Of course, other insulating films such as a silicon nitride film and an organic resin may be used.

  Next, contact holes are formed. As a procedure, first, the interlayer insulating film 417 is opened using buffer hydrofluoric acid, and the gate insulating film 406 is etched as it is with buffer hydrofluoric acid to complete the source / drain contact hole.

  Next, the anodic oxide film 410 is etched using a chromium mixed acid solution having a composition in which chromic acid, acetic acid, phosphoric acid, and nitric acid are mixed to complete a gate electrode portion contact hole.

Thus, if the gate insulating film 406 is etched first, the anodic oxide film 410 is excellent in buffer hydrofluoric acid resistance, and thus the gate electrode 411 can be protected.
Further, the chromium mixed acid solution hardly etches the surfaces of the source region 412 and the drain region 413.

  When the formation of the contact holes is completed, wiring electrodes 418, 419, and 420 are formed, and annealing is performed at 350 ° C. for 2 hours in a hydrogen atmosphere.

  Through the above steps, the thin film transistor illustrated in FIG. 4D is manufactured.

  The TFT shown in FIG. 4D uses a SiON film as a base film, thereby preventing drift of alkali metal (Na, K, etc.) ions and heavy metal (Fe, Ni, Co, etc.) ions, and impurities from the glass substrate. Spreading to the device can be suppressed.

  In addition, since the thin silicon oxide film 403 is formed on the surface of the base film 402, adhesion between the base film 402 and the island-shaped semiconductor layer 404 is improved.

Further, by forming the thin silicon oxide film 405 on the surface of the island-shaped semiconductor layer 404, the state of the active layer / gate insulating film interface is improved, the threshold value of the TFT becomes around 0 V, and p-ch / n- Both chTFTs could be normally off.
Furthermore, as a result of SIMS analysis, it was confirmed that the amount of C (carbon) at the active layer / gate insulating film interface could be reduced by an order of magnitude.
Therefore, the variation of the threshold value of the TFT is reduced, and display unevenness when used in the pixel portion of the liquid crystal display device can be suppressed.

  This embodiment relates to a manufacturing process of a thin film transistor (TFT) having a structure in which a semiconductor layer and a gate insulating film are sandwiched between SiON films. The manufacturing process of the TFT according to this example is the same as that of Example 1, and will be described with reference to FIG.

  First, a glass substrate 401 having an insulating surface is prepared. In this embodiment, Corning 7059 or 1737 substrate is used.

  Next, SiON is formed to a thickness of 200 nm as the base film 402. The conditions for forming the SiON film have been described in detail in the first embodiment, and are omitted here.

  An amorphous silicon film having a thickness of 50 nm (not shown) is formed thereon by a plasma CVD method or a low pressure thermal CVD method, and crystallized by an appropriate crystallization method. This crystallization may be performed by heating or laser light irradiation.

  Next, the crystalline silicon film obtained by crystallizing the amorphous silicon film is patterned to form an island-shaped semiconductor layer 404 constituting the active layer.

  On top of this, a silicon oxide film 406 that functions as a gate insulating film later is formed to a thickness of 150 nm. The gate insulating film 406 may be a SiON film or a silicon nitride film, but it is desirable to use a SiON film in order to further improve the reliability.

  If a SiON film is used as the gate insulating film 406, the gate insulating film 406 may be formed under the same film formation conditions as the base film.

  Subsequently, the state shown in FIG. 4C is obtained by the same process as in the first embodiment.

  Next, as shown in FIG. 4D, a SiON film having a thickness of 1 μm is formed as the interlayer insulating film 417. The film forming conditions are the same as the film forming conditions for the underlying SiON film shown in the first embodiment.

  Subsequently, a thin film transistor as shown in FIG. 4D is manufactured through a process similar to that of the first embodiment.

  The TFT manufactured according to this embodiment has an effect of not only suppressing impurities from the glass substrate but also preventing impurities from the atmosphere.

This example relates to a manufacturing process of a TFT using a polycrystalline silicon film as a gate electrode in Examples 1 and 2.
A manufacturing process of a thin film transistor (TFT) using the present invention is shown in FIGS.

  First, a glass substrate 501 having an insulating surface is prepared. In this embodiment, Corning 7059 or 1737 substrate is used.

  Next, SiON is formed to a thickness of 200 nm as the base film 502. The conditions for forming the SiON film have been described in detail in the first embodiment, and are omitted here.

  An amorphous silicon film having a thickness of 50 nm (not shown) is formed thereon by a plasma CVD method or a low pressure thermal CVD method, and crystallized by an appropriate crystallization method. This crystallization may be performed by heating or laser light irradiation.

  Next, the crystalline silicon film obtained by crystallizing the amorphous silicon film is patterned to form an island-shaped semiconductor layer 503 constituting the active layer.

  On top of this, a SiON film 504 that functions as a gate insulating film later is formed to a thickness of 150 nm. The formation method of the gate insulating film 504 is the same as the film formation conditions of the base SiON film 502 described above.

Next, a polycrystalline silicon film 505 is formed to a thickness of 400 nm by a thermal CVD method. In this polycrystalline silicon film, P (phosphorus) is added in advance so as to have a conductivity of 1 × 10 ²⁰ to 1 × 10 ²¹ cm ⁻³ so as to have conductivity when formed. FIG.

Next, this polycrystalline silicon film 505 is patterned, and plasma etching is performed with a CF ₄ + O ₂ gas. In this isotropic etching, the selection ratio with respect to the gate insulating film 504 is about 10.

  This isotropic etching is continued until the polycrystalline silicon film 505 is cut by 0.1 to 1.0 μm in the lateral direction. However, it is necessary to consider that the gate insulating film 504 is also gradually etched.

  Thus, a polycrystalline silicon film 507 functioning as a gate electrode as shown in FIG. 5B is formed. At that time, the photoresist 506 used as a mask is left for use in the next step.

  Next, an impurity is implanted into the island-shaped semiconductor layer 503 by ion doping. If an N-channel TFT is manufactured, P (phosphorus) is used as an impurity. If a P-channel TFT is manufactured, B (boron) is used as an impurity.

For example, P (phosphorus) is implanted at an acceleration voltage of 60 to 90 kV and a dose of 0.2 to 5 × 10 ¹⁵ atoms / cm ² .
In this embodiment, P (phosphorus) is implanted at an acceleration voltage of 80 kV and a dose of 1 × 10 ¹⁵ atoms / cm ² .

  Then, the photoresist 506 serves as a mask, and regions 508 and 509 to be source / drain later are formed in a self-aligned manner.

Next, as shown in FIG. 5C, the photoresist 506 is removed and a second doping is performed. The second implantation of P (phosphorus) is performed at an acceleration voltage of 60 to 90 kV and a dose of 0.1 to 5 × 10 ¹⁴ atoms / cm ² .
In this embodiment, the acceleration voltage is 80 kV and the dose is 1 × 10 ¹⁴ atoms / cm ² .

  Then, the gate electrode 507 serves as a mask, and low-concentration impurity regions 510 and 511 having a lower impurity concentration than the source region 508 and the drain region 509 are formed in a self-aligned manner.

  At the same time, since no impurities are implanted immediately below the gate electrode 507, a region 512 functioning as a TFT channel is formed in a self-aligned manner.

  The low concentration impurity region (or LDD region) 511 formed in this manner has an effect of suppressing the formation of a high electric field between the channel region 512 and the drain region 509.

Next, as shown in FIG. 5D, a silicon oxide film is formed as an interlayer insulating film 513 to a thickness of 1 μm by plasma CVD. At this time, it is more effective to use a SiON film as the interlayer insulating film 513.
Of course, other insulating films such as silicon nitride and organic resin may be used.

Next, contact holes are formed, and wiring electrodes 514, 515, and 516 are formed.
Then, annealing is performed at 350 ° C. for 2 hours in a hydrogen atmosphere, and a TFT as shown in FIG. 5D is completed.

The figure which shows the result of BT test The figure which shows the result of BT test The figure which shows the result of BT test Diagram showing TFT fabrication process Diagram showing TFT fabrication process

Explanation of symbols

401 glass substrate 402 base film 403 thin silicon oxide film 404 island-like semiconductor layer 405 thin silicon oxide film 406 gate insulating film 407 aluminum film 408 dense anodic oxide film 409 porous anodic oxide film 410 strong anodic oxide film 411 gate Electrode 412 Source region 413 Drain region 414 Low concentration impurity region 415 Low concentration impurity region 416 Channel region 417 Interlayer insulating film 418 Wiring electrode 419 Wiring electrode 420 Wiring electrode

Claims (25)

Forming a first SiO _x N _y film on a glass substrate;
Forming an island-shaped semiconductor layer on the first SiO _x N _y film;
Forming a second SiO _x N _y film covering the island-shaped semiconductor layer;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Boron is implanted into the island-shaped semiconductor layer through the mask,
After the mask is removed, boron is implanted into the island-shaped semiconductor layer using the gate electrode as a mask. Forming a first SiO _x N _y film on a glass substrate;
Forming an island-shaped semiconductor layer on the first SiO _x N _y film;
Forming a second SiO _x N _y film covering the island-shaped semiconductor layer;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Injecting phosphorus into the island-shaped semiconductor layer through the mask,
After the mask is removed, phosphorus is implanted into the island-shaped semiconductor layer using the gate electrode as a mask. Forming a first SiO _x N _y film on a glass substrate;
Forming an island-shaped semiconductor layer on the first SiO _x N _y film;
Forming a second SiO _x N _y film covering the island-shaped semiconductor layer;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Phosphorus is implanted into the island-like semiconductor layer through the mask at a dose of 0.2 to 5 × 10 ¹⁵ atoms / cm ² ,
After removing the mask, phosphorus is implanted into the island-shaped semiconductor layer at a dose of 0.1 to 5 × 10 ¹⁴ atoms / cm ² using the gate electrode as a mask. Manufacturing method. Forming a first SiO _x N _y film on a glass substrate;
Forming an island-shaped semiconductor layer on the first SiO _x N _y film;
Forming a second SiO _x N _y film covering the island-shaped semiconductor layer;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Boron is implanted into the island-shaped semiconductor layer through the mask,
After removing the mask, boron is implanted into the island-shaped semiconductor layer using the gate electrode as a mask,
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film over the second SiO _x N _y film and the gate electrode. Forming a first SiO _x N _y film on a glass substrate;
Forming an island-shaped semiconductor layer on the first SiO _x N _y film;
Forming a second SiO _x N _y film covering the island-shaped semiconductor layer;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Injecting phosphorus into the island-shaped semiconductor layer through the mask,
After removing the mask, phosphorus is injected into the island-shaped semiconductor layer using the gate electrode as a mask,
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film over the second SiO _x N _y film and the gate electrode. Forming a first SiO _x N _y film on a glass substrate;
Forming an island-shaped semiconductor layer on the first SiO _x N _y film;
Forming a second SiO _x N _y film covering the island-shaped semiconductor layer;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Phosphorus is implanted into the island-like semiconductor layer through the mask at a dose of 0.2 to 5 × 10 ¹⁵ atoms / cm ² ,
After removing the mask, phosphorus is implanted at a dose of 0.1 to 5 × 10 ¹⁴ atoms / cm ² into the island-shaped semiconductor layer using the gate electrode as a mask,
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film over the second SiO _x N _y film and the gate electrode. In any one of Claims 4 thru | or 6,
A method for manufacturing a semiconductor device, wherein the interlayer insulating film is formed of a silicon oxide film. In any one of Claims 4 thru | or 6,
A method of manufacturing a semiconductor device, wherein the interlayer insulating film is formed of a SiO _x N _y film. In any one of Claims 4 thru | or 6,
A method for manufacturing a semiconductor device, wherein the interlayer insulating film is formed of a silicon nitride film. In any one of Claims 4 thru | or 6,
A method for manufacturing a semiconductor device, wherein the interlayer insulating film is formed of an organic resin film. Forming a first SiO _x N _y film on a glass substrate;
Forming a first silicon oxide film on the first SiO _x N _y film;
Forming an island-shaped semiconductor layer on the first silicon oxide film;
Forming a second silicon oxide film on the surface of the island-shaped semiconductor layer;
Forming a second SiO _x N _y film covering the second silicon oxide film;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Boron is implanted into the island-shaped semiconductor layer through the mask,
After the mask is removed, boron is implanted into the island-shaped semiconductor layer using the gate electrode as a mask. Forming a first SiO _x N _y film on a glass substrate;
Forming a first silicon oxide film on the first SiO _x N _y film;
Forming an island-shaped semiconductor layer on the first silicon oxide film;
Forming a second silicon oxide film on the surface of the island-shaped semiconductor layer;
Forming a second SiO _x N _y film covering the second silicon oxide film;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Injecting phosphorus into the island-shaped semiconductor layer through the mask,
After the mask is removed, phosphorus is implanted into the island-shaped semiconductor layer using the gate electrode as a mask. Forming a first SiO _x N _y film on a glass substrate;
Forming a first silicon oxide film on the first SiO _x N _y film;
Forming an island-shaped semiconductor layer on the first silicon oxide film;
Forming a second silicon oxide film on the surface of the island-shaped semiconductor layer;
Forming a second SiO _x N _y film covering the second silicon oxide film;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Phosphorus is implanted into the island-like semiconductor layer through the mask at a dose of 0.2 to 5 × 10 ¹⁵ atoms / cm ² ,
After removing the mask, phosphorus is implanted into the island-shaped semiconductor layer at a dose of 0.1 to 5 × 10 ¹⁴ atoms / cm ² using the gate electrode as a mask. Manufacturing method. Forming a first SiO _x N _y film on a glass substrate;
Forming a first silicon oxide film on the first SiO _x N _y film;
Forming an island-shaped semiconductor layer on the first silicon oxide film;
Forming a second silicon oxide film on the surface of the island-shaped semiconductor layer;
Forming a second SiO _x N _y film covering the second silicon oxide film;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Boron is implanted into the island-shaped semiconductor layer through the mask,
After removing the mask, boron is implanted into the island-shaped semiconductor layer using the gate electrode as a mask,
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film over the second SiO _x N _y film and the gate electrode. Forming a first SiO _x N _y film on a glass substrate;
Forming a first silicon oxide film on the first SiO _x N _y film;
Forming an island-shaped semiconductor layer on the first silicon oxide film;
Forming a second silicon oxide film on the surface of the island-shaped semiconductor layer;
Forming a second SiO _x N _y film covering the second silicon oxide film;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Injecting phosphorus into the island-shaped semiconductor layer through the mask,
After removing the mask, phosphorus is injected into the island-shaped semiconductor layer using the gate electrode as a mask,
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film over the second SiO _x N _y film and the gate electrode. Forming a first SiO _x N _y film on a glass substrate;
Forming a first silicon oxide film on the first SiO _x N _y film;
Forming an island-shaped semiconductor layer on the first silicon oxide film;
Forming a second silicon oxide film on the surface of the island-shaped semiconductor layer;
Forming a second SiO _x N _y film covering the second silicon oxide film;
Forming a gate electrode and a mask on the gate electrode having a width larger than that of the gate electrode on the second SiO _x N _y film;
Phosphorus is implanted into the island-like semiconductor layer through the mask at a dose of 0.2 to 5 × 10 ¹⁵ atoms / cm ² ,
After removing the mask, phosphorus is implanted at a dose of 0.1 to 5 × 10 ¹⁴ atoms / cm ² into the island-shaped semiconductor layer using the gate electrode as a mask,
A method for manufacturing a semiconductor device, comprising forming an interlayer insulating film over the second SiO _x N _y film and the gate electrode. In any one of claims 14 to 16,
A method for manufacturing a semiconductor device, wherein the interlayer insulating film is formed of a silicon oxide film. In any one of claims 14 to 16,
A method of manufacturing a semiconductor device, wherein the interlayer insulating film is formed of a SiO _x N _y film. In any one of claims 14 to 16,
A method for manufacturing a semiconductor device, wherein the interlayer insulating film is formed of a silicon nitride film. In any one of claims 14 to 16,
A method for manufacturing a semiconductor device, wherein the interlayer insulating film is formed of an organic resin film. In any one of Claims 11 thru | or 16,
A method for manufacturing a semiconductor device, wherein the first and second silicon oxide films are formed to a thickness of 1 to 20 nm. In any one of Claims 1 to 21,
The energy band gaps of the first and second SiO _x N _y films are 5.3 to 7.0 eV, the relative dielectric constant is 4 to 6, and x and y are 0 <x <2 and 0, respectively. <Y <4/3 is satisfied. A method for manufacturing a semiconductor device. In any one of claims 1 to 22,
1. The method for manufacturing a semiconductor device, wherein the first and second SiO _x N _y films contain 1 × 10 ¹⁹ to 1 × 10 ²¹ cm ^{−3 of} N (nitrogen). 24. In any one of claims 1 to 23.
A method for manufacturing a semiconductor device, wherein the first and second SiO _x N _y films contain 1 × 10 ²⁰ to 1 × 10 ²² cm ^{−3 of} H (hydrogen). In any one of Claims 1 to 24,
A method of manufacturing a semiconductor device, wherein the gate electrode is formed so that both ends of the gate electrode are 0.1 to 1.0 μm inside from both ends of the mask.

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