JP2005072467A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device where an effective bonding area between an emitter and a base is reduced for reducing a bonding capacity between the emitter and the base, and to provide a method for manufacturing the same. <P>SOLUTION: The semiconductor device is provided with a substrate 10, the first semiconductor area 13 of a first conduction type formed on the substrate 10, the second semiconductor area 14 of a second conduction type which is at least partially bonded with the first semiconductor area 13, and the third semiconductor area 16 of a first conduction type. The third semiconductor area 16 is formed on the surface of the second semiconductor area 14 at a prescribed length from the bonding surface of the first semiconductor area 13 and the second semiconductor area 14 so that a depletion layer 17 extended from the bonding surface with the second semiconductor layer 14 may reduce the bonding area of the first semiconductor area 13 and the second semiconductor area 14. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a junction and a manufacturing method thereof.

  In recent years, semiconductor devices having junctions such as bipolar transistors have been widely used as basic elements such as high-speed digital LSIs and analog ICs. Various elements such as ultrahigh frequency / ultrahigh speed transistors and high power transistors are formed in accordance with the application.

  For example, in a compound hetero bipolar transistor (Hetero Bipolar Transistor, hereinafter also referred to as HBT), a mesa structure (hereinafter referred to as an emitter mesa structure) in an emitter layer is used to reduce the junction capacitance between an emitter and a base when a high frequency signal is input. It is also desired to form a finely-structured layer. At present, the emitter mesa structure is formed by using dry etching, wet etching, or the like. In many cases, side etching specific to wet etching is used for miniaturization of the emitter mesa structure.

  On the other hand, in a method for insulating a semiconductor region and a method for forming a semiconductor region having a different conductivity type in a semiconductor region, an ion implantation method or a diffusion method is generally used.

In the compound heterobipolar transistor formed by using the diffusion method as described above, p-type conductive impurities diffuse from the p-type base layer region outside the mesa-shaped region to the n-type emitter layer region and the n-type collector layer region. It is known to have a base contact region that is p-type to prevent a decrease in current gain (see, for example, Patent Document 1).
JP 2001-35857 A

However, the conventional semiconductor device as described above has various problems.
For example, side etching for miniaturizing the emitter mesa structure is difficult to control, and the mechanical strength of the emitter mesa structure decreases due to the miniaturization.

  In order to reduce the contact resistance, it is desired to increase the width of the emitter electrode formed on the emitter mesa structure. However, an emitter mesa structure that is mechanically miniaturized by etching or the like has an unstable structure because the emitter mesa structure is smaller than the formed emitter electrode. As a result, the yield is reduced.

On the other hand, in the method of forming semiconductor regions of different conductivity types in the semiconductor region by ion implantation, it is difficult to implant ions into the side surface of the emitter layer. In the conventional heterojunction bipolar transistor, the conductive impurity concentration of the emitter cap layer is 1 × 10 ¹⁹ cm ⁻³ or more. For this reason, it is difficult to form semiconductor regions of different conductivity types by ion implantation.

  Further, as in the above-mentioned Patent Document 1, a semiconductor region having the same conductivity type as that of the base layer is formed in the emitter layer region and the collector layer region by using the diffusion method to form the base contact region. The bonding area has not changed significantly. For this reason, it is considered difficult to greatly reduce the junction capacitance.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a junction capacitance between an emitter and a base and reduce an effective emitter-base junction area, and a semiconductor device thereof It is to provide a manufacturing method.

  In order to achieve the above object, a semiconductor device according to the present invention includes a substrate, a first semiconductor region of a first conductivity type formed on the substrate, and at least a part of which is joined to the first semiconductor region. A second semiconductor region having a conductivity type of 2 and formed on the surface of the second semiconductor region at a predetermined distance from a bonding surface between the first semiconductor region and the second semiconductor region, A depletion layer extending from the junction surface with the region has a third semiconductor region of the first conductivity type formed so as to narrow a junction area between the first semiconductor region and the second semiconductor region.

According to the semiconductor device of the present invention, the first conductivity type formed on the surface of the second conductivity type second semiconductor at a predetermined distance from the junction surface between the first semiconductor region and the second semiconductor region. A third semiconductor region.
As a result, the depletion layer extending from the junction surface between the third semiconductor region and the second semiconductor region reduces the junction area between the first semiconductor region and the second semiconductor region.

  To achieve the above object, a semiconductor device according to the present invention is formed on a substrate, a collector layer formed on the upper surface of the substrate, a base layer formed on the upper surface of the collector layer, and an upper surface of the base layer. A depletion layer formed on the emitter layer and the emitter layer surface at a predetermined distance from the junction surface between the base layer and the emitter layer and extending from the junction surface with the emitter layer reduces the junction area between the base layer and the emitter layer. It has an emitter layer formed so as to be narrowed and a semiconductor region having a different conductivity type.

According to the semiconductor device of the present invention, the surface of the emitter layer has a semiconductor region having a conductivity type different from that of the emitter layer formed at a predetermined distance from the junction surface between the base layer and the emitter layer.
As a result, the depletion layer extending from the junction surface between the semiconductor region and the emitter layer narrows the junction area between the base layer and the emitter layer.

  In order to achieve the above object, the above-described method for manufacturing a semiconductor device of the present invention includes a step of forming a first semiconductor region of a first conductivity type on a substrate, and a first step in which at least a part is joined to the first semiconductor region. Forming a second-conductivity-type second semiconductor region; and separating the second semiconductor region from the bonding surface between the first semiconductor region and the second semiconductor region by a predetermined distance on the surface of the second semiconductor region; Forming a third semiconductor region of a first conductivity type in which a depletion layer extending from a junction surface with the semiconductor region narrows a junction area between the first semiconductor region and the second semiconductor region.

According to the method for manufacturing a semiconductor device of the present invention, the first semiconductor region of the first conductivity type is formed on the substrate.
Next, a second semiconductor region of a second conductivity type that is at least partially joined to the first semiconductor region is formed.
Next, on the surface of the second semiconductor region, a depletion layer extending from the junction surface with the second semiconductor region is spaced apart from the junction surface between the first semiconductor region and the second semiconductor region by a predetermined distance. A third semiconductor region of the first conductivity type is formed so as to reduce a junction area between the first semiconductor region and the second semiconductor region.

  In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention includes a step of forming a collector layer on the upper surface of a substrate, a step of forming a base layer on the upper surface of the collector layer, and an upper surface of the base layer. A step of forming the emitter layer, and a depletion layer extending from the junction surface between the base layer and the emitter layer at a predetermined distance from the junction surface between the base layer and the emitter layer on the surface of the emitter layer. Forming a semiconductor region having a conductivity type different from that of the emitter layer so as to narrow the bonding surface.

According to the semiconductor device manufacturing method of the present invention, the collector layer is formed on the upper surface of the substrate, and the base layer is formed on the upper surface of the collector layer.
Next, an emitter layer is formed on the upper surface of the base layer.
Next, a depletion layer extending from the junction surface with the emitter layer narrows the junction surface between the base layer and the emitter layer at a predetermined distance from the junction surface between the base layer and the emitter layer on the surface of the emitter layer. A semiconductor region having a conductivity type different from that of the emitter layer is formed.

According to the semiconductor device of the present invention, the effective emitter-base junction area can be reduced, and the emitter-base junction capacitance can be reduced.
According to the method of manufacturing a semiconductor device of the present invention, the effective emitter-base junction area can be reduced, and the emitter-base junction capacitance can be reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic cross-sectional view schematically showing the semiconductor device according to the present embodiment.
For example, a sub-collector layer 11 made of n-type InGaAs or InP is formed on a substrate 10 made of a semi-insulating Fe-doped InP single crystal, and a part of the upper surface of the sub-collector layer 11 is made of n-type InP. A collector layer 12 is formed. A base layer 13 made of p-type InGaAs is formed on the upper surface of the collector layer 12, and an emitter layer 14 made of n-type InP is formed on a part of the upper surface of the base layer 13. On the upper surface of the emitter layer 14, n ⁺
An emitter cap layer made of type InGaAs is formed to constitute an npn type HTB.
Here, the first semiconductor region is the base layer 13, the second semiconductor region is the emitter layer 14, or the emitter layer 14 and the emitter cap layer 15, and the third semiconductor region is the semiconductor region 16.

Here, the substrate 10 may use GaAs or the like in addition to the above InP.
The subcollector layer 11 is formed with a thickness of about 300 to 500 nm, for example, and the collector layer 12 is formed with a thickness of about 500 nm, for example. The base layer is formed with a thickness of about 50 to 75 nm, for example, and the emitter layer 12 is formed with a thickness of about 100 nm, for example.

  The emitter cap layer 15 and the emitter layer 14 are formed in a mesa structure and form a base contact. The base layer 13 and the collector layer 12 are formed in a mesa structure.

Further, an emitter electrode 18 is formed on the upper surface of the emitter cap layer 15, a base electrode 19 is formed on a part of the upper surface of the base layer 13, and a collector electrode 20 is formed on a part of the upper surface of the subcollector layer 11. Has been.
The emitter electrode 18, the base electrode 19, and the collector electrode 20 are formed by stacking, for example, Ti 50 nm, Pt 20-30 nm, and Au 120 nm.

  A semiconductor region 16 having a conductivity type different from that of the emitter cap layer 15 and the emitter layer 14 is formed on the side walls of the emitter cap layer 15 and the emitter layer 14. A depletion layer 17 extends from the junction surface between the semiconductor region 16 and the emitter cap layer 15 and the emitter layer 14.

FIG. 2 is a schematic enlarged view around the base layer and the emitter layer of the semiconductor device shown in FIG.
An emitter layer 14 is formed on the upper surface of the base layer 13, an emitter cap layer 15 is formed on the upper surface of the emitter layer 14, and the emitter layer 14 and the emitter cap layer 15 are formed in a mesa structure. An emitter electrode is formed on the upper surface of the emitter cap layer 15.
Further, a semiconductor region 16 is formed on the sidewalls of the emitter layer 14 and the emitter cap layer 15, and a depletion layer 17 is formed from the junction surface between the emitter layer 14 and the emitter cap layer 15. Here, a conductive impurity having a conductivity type different from that of the emitter layer 14 and the emitter cap layer 15 is introduced into the semiconductor region 16.

  The semiconductor region 16 is formed at a predetermined distance from the junction surface between the emitter layer 14 and the base layer 13. Further, the depletion layer 17 extending from the junction surface between the semiconductor region 16 and the emitter layer 14 and the emitter cap layer 15 extends to the end portion of the junction surface between the emitter layer 14 and the base layer 13. The bonding area with the base layer 13 is reduced.

When semiconductor regions of different conductivity types are formed in the emitter layer 114, the size of the formed semiconductor region can be controlled by, for example, the diffusion amount and diffusion time of the introduced conductive impurities.
In addition, the size of the region of the depletion layer 17 can be controlled by the semiconductor material into which conductive impurities are diffused, the conductive impurity concentration of the semiconductor material, and the diffusion concentration of the introduced conductive impurities.

  In the semiconductor device according to the present embodiment, the emitter layer 14 is etched from the upper surface using the emitter cap layer 15 as a mask, and the thickness of the emitter layer 14 is smaller than the initial thickness. Here, when the semiconductor region 16 is formed using the insulating film 20 as a mask, if it is assumed that diffusion proceeds isotropically, it cannot be diffused to the side surface of the emitter layer 14 beyond the thickness of the emitter layer 14 after etching. . As a result, when the thickness of the emitter layer 14 is about 100 nm, the formed semiconductor region 16 is about 100 nm on one side at the maximum.

  For example, the width of the emitter electrode 18 is formed to be about 1 μm, and accordingly, the emitter cap layer 15 and the emitter layer 14 are also joined to the base layer 13 with a width of about 1 μm or less than 1 μm. At this time, the semiconductor region is formed so that the side wall portions of the emitter cap layer 15 and the emitter layer 14 are separated by a predetermined distance from the joint surface with the base layer 13 and about 100 nm on each side from the side wall portion of the emitter layer 14. 16 is formed.

  As a result, the depletion layer 17 extends from the junction surface between the semiconductor region 16 and the emitter layer 14 and the emitter cap layer 15. The region where the depletion layer 17 is formed can be obtained by an equation for obtaining the transition region width. Similarly, the depletion layer 17 extends from the junction surface between the emitter layer 14 and the semiconductor region 16 at the junction surface between the emitter layer 14 and the base layer 13 on both side walls, and the junction surface decreases. For example, the depletion layer 17 extending from the junction surface between the emitter layer 14 and the semiconductor region 16 at the junction surface between the emitter layer 14 and the base layer 13 is about 100 nm from the side walls of the emitter layer 14 and the base layer 13. A semiconductor region 16 is formed.

As described above, for example, if the width of the emitter layer 14 is 1 μm, the depletion layer 17 reduces the width of the emitter layer 14 by about 100 nm on one side, that is, about 200 nm on both sides, at the junction surface of the emitter layer 14 and the base layer 13. can do. That is, the junction capacity is simply reduced by 20%.
Here, the current cutoff frequency f _T is approximately expressed by the following equation using the mutual conductance g _m indicating the amount of change in the output current with respect to the input voltage, the emitter-base junction capacitance C _f , and the base-collector junction capacitance C _i. It can be shown by (1).

From the above formula (1), when the junction capacitance is reduced by 20%, the current cutoff frequency f _T can be improved by about 10%.
Thus, the region where the semiconductor region 16 is formed is adjusted by the diffusion amount, and the junction area between the base layer 13 and the emitter layer 14 is reduced by the depletion layer 17 formed accordingly. As a result, the junction capacitance can be reduced and the current cutoff frequency can be improved.

  According to the semiconductor device of the present embodiment, a semiconductor having a conductivity type different from that of the emitter layer 14 at a predetermined distance from the junction surface between the base layer 13 and the emitter layer 14 at the side walls of the emitter layer 14 and the emitter cap layer 15. Region 16 is formed. As a result, the depletion layer 17 extending from the junction surface between the emitter layer 14 and the semiconductor region 16 can reduce the junction area between the base layer 13 and the emitter layer 14.

Therefore, the emitter-base junction capacitance is reduced, and it is conceivable that the high frequency characteristics are greatly improved as described above. Specifically, it gain enhancement expected when used as a device for improving and power amplifier of the current gain cut-off frequency f _T.
Further, since the emitter-base junction interface is not effectively exposed to the outside, the surface recombination current can be suppressed, and an increase in current gain β accompanying improvement in emitter injection efficiency can be expected.

  Next, with reference to FIG. 3 and FIG. 4, the manufacturing method of the semiconductor device according to this embodiment will be described.

First, as shown in FIG. 3A, for example, molecular beam epitaxial (Molecular) is formed on one surface of a substrate 10 made of single crystal InP doped with semi-insulating Fe.
The sub-collector layer 11 made of n-type InGaAs is formed by a Beam Epitaxy (hereinafter also referred to as MBE) growth method or a metal organic chemical vapor deposition (hereinafter also referred to as MOCVD) growth method.

Next, using the same method, the collector layer 12 made of n-type InP is formed on the upper surface of the subcollector layer 11, and the base layer 13 made of p-type InGaAs is formed on the upper surface of the collector layer 12. Next, an emitter layer 13 made of n-type InP is formed on the upper surface of the base layer 13, and an emitter cap layer 14 made of n ⁺ -type InGaAs is formed on the upper surface of the emitter layer 13.

Here, the n-type conductive impurity concentration of the emitter layer 13 is about 1 × 10 ¹⁶ cm ⁻³ , and the n-type conductive impurity concentration of the emitter cap layer 14 is about 1 × 10 ¹⁹ cm ⁻³ .
Further, for example, silicon, phosphorus, arsenic, or the like is used as the n-type conductive impurity, and, for example, carbon, boron, or the like is used as the p-type conductive impurity.

  Next, a mask is formed on the upper surface of the emitter cap layer 15 with a resist film or the like, and Ti, Pt, and Au are sequentially formed by vapor deposition or the like, and then the resist film is removed to form the emitter electrode 18 in a desired region. A metal film is formed. The emitter electrode 18 is formed with a width of about 1 μm and a length of about 5 μm, for example.

  Next, as shown in FIG. 3B, the emitter cap layer 15 is removed by etching or the like using the formed emitter electrode 18 as a mask. Subsequently, the emitter layer 14 is removed by etching with a predetermined thickness using the emitter electrode 18 and the emitter cap layer 15 as a mask. The emitter layer 14 is removed by dry etching or wet etching. At this time, since not all of the emitter layer 14 is removed, but only a predetermined thickness is removed, the etching time is controlled so that the predetermined thickness is removed based on the etching rate of the emitter layer 14.

Next, an insulating film 30 such as a SiN film is formed on the upper surface of the emitter layer 14. Although not shown, the insulating film 30 is formed to prevent introduction of conductive impurities in other adjacent elements. Therefore, there is no need to form the adjacent elements if they do not affect the adjacent elements.
Further, a resist film 31 is formed on the upper surface of the insulating film 30, and the insulating film 30 around the emitter mesa structure including the emitter electrode 18, the emitter cap layer 15 and the emitter layer 14 is removed by a normal photolithography technique or the like. At this time, the insulating film 30 on the side wall portion of the emitter mesa structure is completely removed.

Next, as shown in FIG. 3C, the resist film 31 is removed, and the insulating film 30 is used as a mask on the side wall portions of the emitter cap layer 15 and the emitter layer 14 to have a conductivity type different from that of the emitter layer 14. A semiconductor region 16 is formed by introducing a conductive impurity. Here, a p-type conductive impurity is introduced as a conductivity type different from that of the emitter layer 14. Specifically, during the atmosphere of diethyl Zn at about 600 ° C., Zn diffuses into the exposed emitter layer 14 and emitter cap layer 15. Here, when the semiconductor layer is formed using a material having a growth temperature of 600 ° C. or lower when epitaxially growing the semiconductor layer, the diffusion temperature is lower than 600 ° C. As the p-type conductive impurity, a group 2 element such as Cd can be used in addition to the above Zn. Concentration to be introduced, the conductive impurity concentration of at least n-type emitter layer 14 1 × 10 ¹⁶ cm ^-3, and the n-type conductivity impurity concentration 1 × 10 ¹⁹ cm ^-3 in the emitter cap layer 15 is depleted, respectively Concentration.

  Here, the semiconductor region 16 is formed to a thickness of about 100 nm from the surfaces of the emitter layer 14 and the emitter cap layer 15, for example. At this time, a similar thickness is formed on the upper surface of the emitter layer 14 exposed in the vicinity of the emitter mesa structure. Therefore, the emitter layer 14 must be thicker than the semiconductor region 16 to be formed so that the semiconductor region 16 to be formed is not connected to the underlying base layer 13.

  Next, as shown in FIG. 4D, after the semiconductor region 16 is formed, the insulating film 30 is removed. The emitter layer 14 is removed using the emitter cap layer 15 as a mask. At this time, the semiconductor region 16 formed on the upper surface of the emitter layer 14 is also removed, and the upper surface of the base layer 13 is exposed. As a result, a semiconductor region 16 is formed in part of the side walls of the emitter cap layer 15 and the emitter layer 14 as illustrated.

Next, as shown in FIG. 4E, a base electrode 19 is formed on the exposed upper surface of the base layer 13 by a lift-off method or the like. Thereafter, the base layer 13 and the collector layer 12 are processed to form a base / collector mesa. Further, the subcollector layer 11 is patterned as necessary, and the collector electrode 20 is formed on the upper surface of the subcollector layer 11.
In this way, the semiconductor device according to this embodiment as shown in FIG. 4F is formed.

According to the method for manufacturing a semiconductor device of this embodiment, the surface of the emitter layer 14 and the emitter cap layer 15 has a conductivity type different from that of the emitter layer 14 at a predetermined distance from the junction surface between the base layer 13 and the emitter layer 14. The semiconductor region 16 is formed. The semiconductor region 16 is formed by a diffusion method, and the junction area between the emitter layer 14 and the base layer 13 can be reduced by the depletion layer 17 extending from the junction surface between the semiconductor region 16 and the emitter layer 14.
Further, according to the above method, it is not necessary to finely process the emitter layer 14 and the emitter cap layer 15, and the width of the emitter electrode 18 can be increased. As a result, the emitter contact resistance can be reduced when trying to obtain the same current density.

  Note that a depletion layer 17 extends from a junction surface between the emitter cap layer 15 and the emitter layer 14 and the semiconductor region 16 formed in a part of the side wall portion thereof. Further, since the semiconductor region 16 is formed at a predetermined distance from the base layer 13, even if a voltage is applied to the base electrode 19, the semiconductor region 16 is not affected.

  In the present embodiment, the HBT is formed using the above materials, but the diffusion rate differs depending on the material used. That is, when introducing conductive impurities of different conductivity types, diffusion is performed while compensating, so that the region where the concentration of conductive impurities is low is diffused faster. Therefore, depending on the combination of the emitter cap layer 15 and the emitter layer 14, a more optimal structure can be formed. For example, in the diffusion of Zn, it is known that InGaAs has a faster diffusion rate than AlGaAs. Thus, by forming the emitter layer 14 using a material having a faster diffusion rate than the emitter cap layer 15, the emitter-base junction area can be easily reduced.

The semiconductor device and the manufacturing method thereof according to the present embodiment are not limited to the above method.
For example, although InP is used as the substrate 1, GaAs or the like may be used. When GaAs is used as the substrate, GaAs or the like is used as the base layer 13.

[Second Embodiment]
In the manufacturing method according to the above embodiment, the emitter layer is removed to a predetermined thickness by being controlled by the etching rate. In this embodiment, the emitter layer is formed of a plurality of layers, and an etching stopper layer having the same conductivity type as the emitter layer is formed therebetween. Due to the etching selectivity between the upper emitter layer and the etching stopper layer, the etching layer is accurately removed to a predetermined thickness to form semiconductor regions of different conductivity types.
In addition, the same part as said embodiment uses the same number, abbreviate | omits description, and demonstrates only a different part hereafter.

FIG. 5 is a schematic cross-sectional view schematically showing the semiconductor device according to the present embodiment.
For example, a sub-collector layer 11 made of n-type InGaAs is formed on a substrate 10 made of a semi-insulating Fe-doped InP single crystal, and a collector made of n-type InP is formed on a part of the upper surface of the sub-collector layer 11. Layer 12 is formed. A base layer 13 made of p-type InGaAs is formed on the upper surface of the collector layer 12, and a first emitter layer 14 b made of n-type InP is formed on a part of the upper surface of the base layer 13.
An etching stopper layer 21 made of n-type InGaAs is formed on the upper surface of the first emitter layer 14 b, and a second emitter layer 14 a is formed on the upper surface of the etching stopper layer 21. The second emitter layer 14a is formed of the same material as the first emitter layer 14b.
An emitter cap layer made of n ⁺ -type InGaAs is formed on the upper surface of the second emitter layer 14a to constitute an npn-type HTB.

  In addition, on the side walls of the emitter cap layer 15, the emitter layers 14 a and 14 b, and the etching stopper layer 21, a semiconductor region 16 having a conductivity type different from that of the emitter cap layer 15, the emitter layer 14, and the etching stopper layer 21 is formed. . A depletion layer 17 extends from the junction surface between the semiconductor region 16 and the emitter cap layer 15, the emitter layer 14, and the etching stopper layer 21.

  The semiconductor region 16 is formed at a predetermined distance from the bonding surface between the first emitter layer 14 b and the base layer 13. Further, the depletion layer 17 extending from the junction surface between the semiconductor region 16 and the emitter layer 14, the emitter cap layer 15, and the etching stopper layer 21 extends to the end of the junction surface between the first emitter layer 14 b and the base layer 13. Thus, the effective junction area between the first emitter layer 14b and the base layer 13 is reduced.

  According to the semiconductor device of the present embodiment, a semiconductor having a conductivity type different from that of the emitter layer 14 at a predetermined distance from the junction surface between the base layer 13 and the emitter layer 14 at the side walls of the emitter layer 14 and the emitter cap layer 15. Region 16 is formed. As a result, the depletion layer 17 extending from the junction surface between the emitter layer 14 and the semiconductor region 16 can reduce the junction area between the base layer 13 and the emitter layer 14.

  Next, with reference to FIG. 6, a method for manufacturing the semiconductor device according to this embodiment will be described. The manufacturing method of the semiconductor device according to this embodiment is substantially the same as that of the above embodiment.

First, as shown in FIG. 6A, the subcollector layer 11 is formed on one surface of the substrate 10 by, for example, the MBE growth method or the MOCVD growth method.
Next, using the same method, the collector layer 12 is formed on the upper surface of the subcollector layer 11, and the base layer 13 is formed on the upper surface of the collector layer 12. Next, the first emitter layer 14b is formed on the upper surface of the base layer 13, and the etching stopper layer 21 is formed on the upper surface of the first emitter layer 14b. A second emitter layer 14a is formed on the upper surface of the etching stopper layer 21, and an emitter cap layer 15 is formed on the upper surface of the second emitter layer 14a.
Next, the emitter electrode 18 is formed on a part of the upper surface of the emitter cap layer 15 by using a lift-off method or the like.

Next, the emitter cap layer 15 is removed by etching or the like using the formed emitter electrode 18 as a mask. Subsequently, the second emitter layer 14a is removed using the emitter electrode 18 and the emitter cap layer 15 as a mask.
Here, since the etching stopper layer 21 is formed under the second emitter layer 14a, it is selectively etched. In addition, the etching stopper layer 21 should just have the same conductivity type as an emitter layer other than said material, and a different etching selectivity.

  Next, an insulating film 30 such as a SiN film is formed on the upper surface of the second emitter layer 14a. A resist film 31 is formed on the upper surface of the insulating film 30, and the insulating film 30 around the emitter mesa structure composed of the emitter electrode 18, the emitter cap layer 15 and the emitter layer 14 is removed by a normal photolithography technique or the like. At this time, the insulating film 30 on the side wall portion of the emitter mesa structure is completely removed.

  Thereafter, the resist film 31 is removed, and with the insulating film 30 as a mask, the emitter cap layer 15, the side wall of the second emitter layer 14 a, and the surface of the etching stopper layer 21 have a conductivity type different from that of the emitter layers 14 a and 14 b. Conductive impurities are introduced to form the semiconductor region 16.

  Next, as shown in FIG. 6B, after the semiconductor region 16 is formed, the insulating film is removed. The etching stopper layer 21 and the first emitter layer 14b are removed using the emitter cap layer 15 and the first emitter layer 14a as a mask. At this time, the semiconductor region 16 formed on the upper surface of the etching stopper layer 21 is removed, and the upper surface of the base layer 13 is exposed. As a result, a semiconductor region 16 is formed in part of the side walls of the emitter cap layer 15 and the emitter layer 14 as illustrated.

Thereafter, a base electrode 19 is formed on the exposed upper surface of the base layer 13 by a lift-off method or the like. Thereafter, the base layer 13 and the collector layer 12 are processed to form a base / collector mesa. Further, the subcollector layer 11 is patterned as necessary, and the collector electrode 20 is formed on the upper surface of the subcollector layer 11.
Thus, the semiconductor device according to the present embodiment as shown in FIG. 6C is formed.

According to the method for manufacturing a semiconductor device of this embodiment, the surface of the emitter layer 14 and the emitter cap layer 15 has a conductivity type different from that of the emitter layer 14 at a predetermined distance from the junction surface between the base layer 13 and the emitter layer 14. The semiconductor region 16 is formed. The semiconductor region 16 is formed by a diffusion method, and the junction area between the emitter layer 14 and the base layer 13 can be reduced by the depletion layer 17 extending from the junction surface between the semiconductor region 16 and the emitter layer 14.
Further, according to the above method, the emitter layer 14 is composed of a plurality of layers, and the etching stopper layer 21 having different etching selectivity is formed between them. As a result, when the semiconductor region 16 is formed, a desired thickness can be reliably removed, and the conductive impurities can be prevented from diffusing into the base layer 13.

The semiconductor device and the manufacturing method thereof according to the present invention are not limited to the above embodiments.
For example, InP is used as the semi-insulating substrate, but GaAs or the like may be used. At that time, the base layer is formed using GaAs or the like. The impurity concentration introduced into the collector layer, the base layer, and the emitter layer can be changed so as to obtain desired characteristics. Furthermore, the film thickness of each layer is an example and is not limited.
In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 1 is a schematic cross-sectional view schematically showing a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a schematic enlarged view schematically showing a part of the semiconductor device shown in FIG. FIG. 3 is a schematic cross-sectional view schematically showing the main steps of the manufacturing process of the semiconductor device according to the first embodiment of the present invention in sequence, and FIG. 3A shows the first step, FIG. 3B shows the second step, and FIG. 3C shows the third step. FIG. 4 is a schematic cross-sectional view sequentially showing main processes of the manufacturing process of the semiconductor device according to the first embodiment of the present invention in order, following FIG. 3, and FIG. FIG. 4 (e) shows the fifth step, and FIG. 4 (f) shows the sixth step. FIG. 5 is a schematic cross-sectional view schematically showing a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a schematic cross-sectional view schematically showing the main steps of the manufacturing process of the semiconductor device according to the second embodiment of the present invention in order, FIG. 6 (a) shows the first step, FIG. 6B shows the second step, and FIG. 6C shows the third step.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Substrate, 11 ... Subcollector layer, 12 ... Collector layer, 13 ... Base layer (first semiconductor region), 14, 14a, 14b ... Emitter layer (second semiconductor region), 15 ... Emitter cap layer, 16 3rd semiconductor region (semiconductor region) 17 Depletion layer 18 Emitter electrode 19 Base electrode 20 Collector electrode 21 Etching stopper layer 30 Insulating film 31 Resist film

Claims (14)

A substrate,
A first semiconductor region of a first conductivity type formed on the substrate;
A second semiconductor region of a second conductivity type at least partially joined to the first semiconductor region;
A depletion formed on the surface of the second semiconductor region at a predetermined distance from the junction surface between the first semiconductor region and the second semiconductor region and extending from the junction surface with the second semiconductor region. A semiconductor device comprising: a third semiconductor region of a first conductivity type, wherein a layer is formed so as to reduce a junction area between the first semiconductor region and the second semiconductor region. The semiconductor device according to claim 1, wherein the second semiconductor region is formed using a material having a band gap larger than that of the first semiconductor region. A substrate,
A collector layer formed on the upper surface of the substrate;
A base layer formed on the upper surface of the collector layer;
An emitter layer formed on an upper surface of the base layer;
A depletion layer formed on the surface of the emitter layer at a predetermined distance from the junction surface between the base layer and the emitter layer and extending from the junction surface with the emitter layer is a junction between the base layer and the emitter layer. And a semiconductor region having a different conductivity type from the emitter layer formed to reduce the area. A subcollector layer formed between the substrate and the collector layer;
An emitter cap layer formed on the upper surface of the emitter layer; and
The sub-collector layer contains more conductive impurities than the collector layer,
The semiconductor device according to claim 3, wherein the emitter cap layer contains more conductive impurities than the emitter layer. A depletion layer extending from the junction surface between the base layer and the emitter layer is formed at a predetermined distance from the junction surface between the base layer formed on the collector layer and the emitter layer, and extends from the junction surface with the emitter layer. The semiconductor device according to claim 4, wherein a semiconductor region having a conductivity type different from that of the emitter layer formed so as to reduce a junction area is formed on surfaces of the emitter layer and the emitter cap layer. The semiconductor device according to claim 3, wherein the emitter layer, the base layer, and the collector layer are formed of a compound semiconductor. The semiconductor device according to claim 3, wherein the semiconductor region is formed on a side wall portion of the emitter layer formed in a mesa structure. The semiconductor device according to claim 3, wherein the emitter layer is formed of a plurality of layers, and an etching stopper layer having the same conductivity type as the emitter layer is formed between predetermined layers. Forming a first semiconductor region of a first conductivity type on a substrate;
Forming a second semiconductor region of a second conductivity type, at least a part of which is joined to the first semiconductor region;
On the surface of the second semiconductor region, a depletion layer extending from the junction surface with the second semiconductor region is spaced a predetermined distance from the junction surface between the first semiconductor region and the second semiconductor region. Forming a third semiconductor region of a first conductivity type that reduces a junction area between the first semiconductor region and the second semiconductor region. The method for manufacturing a semiconductor device according to claim 9, wherein in the step of forming the third semiconductor region, the third semiconductor region is formed by diffusing a first conductivity type conductive impurity. Forming a collector layer on the upper surface of the substrate;
Forming a base layer on the upper surface of the collector layer;
Forming an emitter layer on the upper surface of the base layer;
A depletion layer extending from the junction surface with the emitter layer at a predetermined distance from the junction surface between the base layer and the emitter layer on the surface of the emitter layer forms a junction surface between the base layer and the emitter layer. Forming a semiconductor region having a conductivity type different from that of the emitter layer, such that the emitter layer is narrowed. Before the step of forming the collector layer, forming a subcollector layer between the substrate and the collector layer;
The method for manufacturing a semiconductor device according to claim 11, further comprising: forming an emitter cap layer on an upper surface of the emitter layer between the step of forming the emitter layer and the step of forming the semiconductor region. The method of manufacturing a semiconductor device according to claim 12, wherein in the step of forming the semiconductor region, the semiconductor region is formed on surfaces of the emitter layer and the emitter cap layer. The method for manufacturing a semiconductor device according to claim 11, wherein in the step of forming the semiconductor region, the semiconductor region is formed by diffusing a conductive impurity.

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