JP2005070227A - Electro-optical device, method for driving the electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ameliorate writing deficiency of data in a current program system. <P>SOLUTION: A pixel 2 has a capacitor C, an organic EL element OLED with luminance set by flow of a drive current according to the data held in the capacitor C, and precharge transistors Tp 1 and Tp 2 disposed in parallel with a transistor T 3. In a precharge period, a precharge current Ipcg greater than a data current Idata is supplied to a data line X, and the writing of the data according to the precharge current Ipcg is performed by using the transistor T 3, Tp 1 and Tp 2. In a data writing period following the precharge period, the data current Idata is supplied to the data line X, and the writing of the data meeting the data current Idata is performed by using the transistor T 3. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an electro-optical device, a driving method of the electro-optical device, and an electronic apparatus, and more particularly, to current precharge performed prior to supply of data current.

  In recent years, a display using an organic EL (Electronic Luminescence) element has attracted attention. The organic EL element is a current-driven element that emits light with a luminance corresponding to a driving current flowing through the organic EL element. As one of the driving methods for such an organic EL element, for example, as disclosed in Patent Document 1 and Patent Document 2, there is a current programming method in which data is supplied to a data line on a current basis. The current programming method has an advantage that it can compensate for variations in characteristics of TFTs (thin film transistors) to some extent, but at the time of low gradation where the data current is very small, insufficient data writing is likely to occur due to the wiring capacity of the data lines. There is an inconvenience.

  In order to eliminate such inconvenience, Patent Document 3 discloses subframe driving in which one frame is divided into a plurality of subframes, and the gradation of pixels is set based on the average luminance of the organic EL elements in each subframe. ing. This sub-frame driving has an advantage that it is not necessary to use a minute current at a low gradation because data is written with a current value comparable to that of a high gradation.

As prior applications of the present applicant related to improvement of insufficient data writing, there are Japanese Patent Application Nos. 2003-3331, 2003-368399, and 2001-379714.
Japanese Patent Laid-Open No. 2003-22049 JP 2003-22050 A JP 2003-15605 A

  An object of the present invention is to provide a novel configuration for improving deficiency of data writing in a current programming method.

  In order to solve such a problem, the first invention provides an electro-optical device in which a signal is supplied to a data line on a current basis. The electro-optical device includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to these intersections. Each of the pixels corresponds to a capacitor that holds data, an electro-optical element in which luminance is set by a drive current corresponding to the data held in the capacitor, and a current supplied via the data line A program unit that writes data to the capacitor according to the generated voltage and in which a resistance value in a path through which a current flows is variably set. In a precharge period preceding a data write period in which a data current defining the gray level of a pixel is supplied to the data line, a precharge current larger than the data current is supplied to the data line. Further, the first resistance value of the program unit set in the precharge period is smaller than the second resistance value of the program unit set in the data writing period.

  Here, in the first invention, the first resistance value is preferably set according to the magnitude of the precharge current with respect to the data current, and is inversely proportional to the ratio of increasing the precharge current with respect to the data current. It is desirable to set as follows.

  In the first invention, a data line driver circuit including a latch circuit having a shift register function may be further provided. In this case, the precharge current is set to a power of 2 times the data current by shifting the data held in the latch circuit. At the same time, the first resistance value is set to a power of 1/2 of the second resistance value.

  In the first invention, the precharge current decreases from the current value larger than the data current toward the current value of the data current, and the first resistance value decreases from the resistance value smaller than the second resistance value to the second current value. It is preferable to increase toward the resistance value. In this case, it is desirable that the precharge current decreases stepwise so that the amount of change decreases with time, and the first resistance value increases stepwise so that the amount of change increases with time.

  A second invention provides an electro-optical device in which a signal is supplied to a data line on a current basis. The electro-optical device includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to these intersections. Each of the pixels includes a capacitor that holds data, an electro-optical element in which luminance is set by a drive current corresponding to the data held in the capacitor, and a first transistor that writes data to the capacitor And at least one second transistor that is provided in parallel with the first transistor and writes data to the capacitor. In the precharge period, a precharge current larger than the data current that defines the gray level of the pixel is supplied to the data line, and data writing according to the precharge current flows between the first transistor and the second transistor. Done with. In the data writing period following the precharge period, a data current is supplied to the data line, and data writing according to the data current is performed using the first transistor.

  Here, in the second invention, a data line driving circuit including a latch circuit having a shift register function may be further provided. In this case, the precharge current is set to a power of 2 times the data current by shifting the data held in the latch circuit. At the same time, in the precharge period, the resistance value set by the parallel connection of the first transistor and the second transistor is set to a power of 1/2 of the resistance value of the first transistor.

  In the second invention, it is preferable that the number of second transistors connected in parallel to the first transistor is reduced with time during the precharge period. In this case, it is desirable that the precharge current is variably set according to the number of second transistors connected in parallel to the first transistor. For example, it is preferable that the precharge current gradually decreases from a current value larger than the data current toward the current value of the data current according to the number of second transistors connected in parallel to the first transistor. .

  A third invention provides an electronic apparatus in which the electro-optical device according to the first or second invention described above is mounted.

  According to a fourth aspect of the invention, there is provided a driving method of an electro-optical device having a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and supplying a signal to the data lines on a current basis. I will provide a. In this driving method, in the first step, a precharge current larger than the data current defining the gradation of the pixel is supplied to the data line, and the resistance value in the path through which the precharge current flows is set to the first resistance value. Then, data is written to the capacitor with a voltage generated according to the precharge current. In the second step, the data current is supplied to the data line, the resistance value in the path through which the data current flows is set to a second resistance value larger than the first resistance value, and the data current is Data is written to the capacitor by the generated voltage. In the third step, the gradation of the pixel is set by supplying a drive current corresponding to the data held in the capacitor to the electro-optic element.

  Here, in the first step according to the fourth invention, it is preferable to set the first resistance value according to the magnitude of the precharge current with respect to the data current, and to increase the precharge current with respect to the data current. It is desirable to set the first resistance value in inverse proportion to the ratio. For example, in the first step, the precharge current may be set to a power of 2 of the data current, and the first resistance value may be set to a power of 1/2 of the second resistance value.

  In the first step according to the fourth aspect of the invention, the precharge current is decreased from the current value larger than the data current toward the current value of the data current, and the first resistance value is smaller than the second resistance value. The first resistance value may be increased toward a resistance value of 2. In this case, in the first step, the precharge current is decreased stepwise so that the amount of change decreases with time, and the first resistance value is increased stepwise so that the amount of change increases with time. It is preferable to make it.

  According to a fifth aspect of the present invention, there is provided a driving method of an electro-optical device having a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and supplying a signal to the data lines on a current basis. I will provide a. In this driving method, in the first step, a precharge current larger than the data current defining the gradation of the pixel is supplied to the data line, and data writing to the capacitor according to the precharge current is connected in parallel. This is performed using the first transistor and at least one second transistor. In the second step, a data current is supplied to the data line, and data is written to the capacitor in accordance with the data current using the first transistor. In the third step, the gradation of the pixel is set by supplying a drive current corresponding to the data held in the capacitor to the electro-optic element.

  Here, in the first step according to the fifth invention, the precharge current is set to a power of 2 times the data current, and the resistance value set by the parallel connection of the first transistor and the second transistor Is preferably set to a power of 1/2 of the resistance value of the first transistor.

  In the first step according to the fifth aspect of the invention, it is preferable that the number of second transistors connected in parallel to the first transistor is reduced over time. In this case, it is desirable to variably set the precharge current according to the number of second transistors connected in parallel to the first transistor. Furthermore, it is desirable to reduce the precharge current stepwise from a current value larger than the data current toward the current value of the data current according to the number of second transistors connected in parallel to the first transistor. .

  In the present invention, in the precharge period preceding the data write period, a precharge current larger than the data current is supplied to the data line, and the resistance value of the program unit is set smaller in the precharge period than in the data write period. To do. This makes it possible to effectively improve the lack of data writing in the current programming method.

  FIG. 1 is a block diagram of an electro-optical device according to this embodiment. The display unit 1 is an active matrix display panel that drives an electro-optical element by a switching element such as a TFT. In the display unit 1, pixels 2 for m dots × n lines are arranged in a matrix (in a two-dimensional plane). The display unit 1 is provided with scanning line groups Y1 to Yn each extending in the horizontal direction and data line groups X1 to Xm each extending in the vertical direction. Pixels 2 are arranged corresponding to the intersections. In the present embodiment, one pixel 2 is the minimum display unit of an image, but one pixel 2 may be composed of three RGB sub-pixels as in a color panel. In FIG. 1, power supply lines for supplying predetermined voltages Vdd and Vss to each pixel 2 are omitted.

  FIG. 2 is a circuit diagram of the pixel 2 as an example. One pixel 2 includes an organic EL element OLED, eight transistors T1 to T4, Tp1, Tp2, SW1, SW2, and a capacitor C for holding data. The organic EL element OLED represented as a diode is a typical current-driven element in which the luminance is set by the drive current Ioled flowing through itself. In this pixel circuit, n-channel type transistors T1, T2, and T4 and p-channel type transistors T3, Tp1, Tp2, SW1, and SW2 are used. It is not limited to this.

  The gate of the transistor T1 is connected to one scanning line Y supplied with the scanning signal SEL, and the source thereof is connected to one data line X supplied with the data current Idata. The drain of the transistor T1 is commonly connected to the source of the transistor T2, the drain of the transistor T3, and the drain of the transistor T4. Similarly to the transistor T1, the gate of the transistor T2 is connected to the scanning line Y to which the scanning signal SEL is supplied. The drain of the transistor T2 is commonly connected to one electrode of the capacitor C and the gate of the transistor T3. A power supply voltage Vdd is applied to the other electrode of the capacitor C and the source of the transistor T3. The transistor T4 to which the drive signal GEL is supplied to the gate is provided between the drain of the transistor T3 and the anode (anode) of the organic EL element OLED. A reference voltage Vss lower than the power supply voltage Vdd is applied to the cathode (cathode) of the organic EL element OLED.

  Two precharge transistors Tp1 and Tp2 are provided in parallel with the transistor T3. A power supply voltage Vdd is applied to the source of the first precharge transistor Tp1, and its drain is connected to the drain of the transistor T3 via the first switching transistor SW1. The power supply voltage Vdd is applied to the source of the second precharge transistor Tp2, and its drain is connected to the drain of the transistor T3 via the second switching transistor SW2. The gates of these precharge transistors Tp1, Tp2 are commonly connected to the gate of the transistor T3.

  The program unit 20 is mainly composed of three transistors T3, Tp1, and Tp2, and two switching transistors SW1 and SW are added thereto. The program unit 20 writes data to the capacitor C using a voltage generated according to the current supplied via the data line X.

  Here, the resistance ratio of the transistors T3, Tp1, and Tp2 is set to 1: 1: 1/2 in relation to the current precharge described later. The setting of the resistance ratio can be easily realized, for example, by changing the channel width Wp. The channel width of the transistor T3 is Wp × 1, the first precharge transistor Tp1 is Wp × 1, and the second precharge is performed. The transistor Tp2 may be set to Wp × 2 (the channel length is the same). The conduction of the switching transistors SW1 and SW2 is controlled by control signals GPCG1 and GPCG2, thereby setting the connection form of the transistors T3, Tp1, and Tp2. By changing this connection form, the resistance value Rtft of the program unit 20 as a whole, in other words, the resistance value in the path through which the current supplied from the data line X flows is variably set. When both the switching transistors SW1 and SW2 are off (non-conducting), the resistance of the transistor T3 itself becomes the resistance value Rtft. Assuming that the resistance value Rtft in this case is 1, when only the first switching transistor SW1 is on (conductive), the two transistors T3 and Tp1 are connected in parallel, and the resistance value Rtft becomes 1/2. . When both the first and second switching transistors SW1 and SW2 are on, the three transistors T3, Tp1, and Tp2 are connected in parallel, and the resistance value Rtft becomes 1/4.

  The timing signal generation circuit 5 generates various internal signals based on external signals such as a vertical synchronization signal Vs, a horizontal synchronization signal Hs, and a dot clock signal DCLK input from a host device (not shown). Under the synchronous control by these internal signals, the scanning line driving circuit 3 and the data line driving circuit 4 perform display control of the display unit 1 in cooperation with each other. The internal signals include scanning line drive system signals CLY and DY, data line drive system signals CLX and DX, LP, CLK, RST1, and RST2, and precharge control system signals BPCG1 and BPCG2.

  Here, among the signals of the scanning line driving system, the start pulse DY is a signal that defines a period for selecting all the scanning lines Y1 to Yn1, that is, one vertical scanning period (1F), and is a pulse at the start of 1F. Stand up in shape. The clock signal CLY is a signal that defines a selection period of one scanning line Y, that is, one horizontal scanning period (1H), and is set to a clock period of 1H. Among the signals of the data line driving system, the latch pulse LP is a pulse signal output at the beginning of 1H, and rises in a pulse shape at the time of level transition of the clock signal CLY, that is, at the rise and fall. The clock signal CLX is a dot clock signal for data writing to the pixel 2. The start pulse DX defines the timing for starting to take in data for a pixel group (that is, one pixel row) for one horizontal line. The clock CLK and the reset signals RST1 and RST2 are signals used when generating a precharge control signal PCG described later. Further, BPCG1 and BPCG2 which are signals of the precharge control system are base signals for defining a change timing when a precharge current Ipcg described later is changed stepwise.

  The scanning line driving circuit 3 is mainly composed of a shift register, an output circuit, etc., and performs scanning of the scanning lines Y1 to Yn by outputting a scanning signal SEL to the scanning lines Y1 to Yn. The scanning signal SEL takes a binary signal level of high level (hereinafter referred to as “H level”) or low level (hereinafter referred to as “L level”), and is a scanning line corresponding to a pixel row to which data is to be written. Y is set to the H level, and the other scanning lines Y are set to the L level. In 1F, each pixel row is selected in order (line-sequential scanning) in a predetermined selection order (generally from the top to the bottom). In addition to the scanning signal SEL, the scanning line driving circuit 3 outputs a driving signal GEL for controlling conduction of the transistor T4 in the pixel circuit of FIG. 2 in units of pixel rows. The drive period during which the organic EL element OLED emits light is set by the drive signal GEL.

  The data line driving circuit 4 cooperates with the scanning line driving circuit 3 to supply signals to the data lines X1 to Xm on a current basis. FIG. 3 is a configuration diagram of the data line driving circuit 4. The data line driving circuit 4 includes an m-bit X shift register 40, m circuit units 41 provided in units of data lines, a storage circuit 42, and a determination circuit 43. The X shift register 40 transfers the start pulse DX supplied first at 1H according to the clock signal CLX, and sequentially sets the levels of the latch signals S1, S2, S3,. .

  The storage circuit 42 stores the minimum value Dmin of the upper 2 bits D5 and D4 using the data DATA for one pixel row as a comparison target, and outputs the minimum value Dmin to the determination circuit 43 in the subsequent stage. Specifically, when supply of 6-bit serial data DATA defining 64 gradations is started in a certain 1H, the upper 2 bits (D5D4) inputted in time series are stored in the memory circuit 42. It is compared with the stored value at any time. If the current input value (D5D4) is smaller than the current stored value, the stored value is updated to this input value. Therefore, the stored value at the time when the data supply for one pixel row is completed is the minimum value Dmin of the upper 2 bits (D5D4) for this pixel row. A stored value at a certain 1H is reset by a reset signal RST1 prior to data supply at the next 1H in order to prepare for storing a new minimum value Dmin at the next 1H.

  Based on the minimum value Dmin output from the storage circuit 42 for each pixel row, the determination circuit 43 determines whether or not data writing is performed with precharge in units of pixel rows, and indicates whether or not precharge is performed. A precharge control signal PCG is output. In the present embodiment, when the minimum value Dmin is D5D4 = “00”, in other words, even one gradation (gradation 0 to 11) belonging to the low gradation side ¼ region exists in the pixel row. In this case, precharge for this pixel row is instructed. As shown in FIG. 8, for the pixel row to be precharged, the precharge control signal PCG is set to H level in the first half precharge period t0 to t2, and in the second half period t2 to t3. Set to L level. For the pixel rows that are not precharged, the precharge control signal PCG is maintained at the L level in 1H including the precharge periods t0 to t2. The precharge control signal PCG is output in common to all of the circuit units 41 provided in units of data lines, and as shown in FIG. 1, all of the precharge control circuits 6 provided in units of scan lines. Are also output in common.

  Various methods are conceivable for determining the presence or absence of precharge based on the data DATA, and the above method is merely an example. For example, when a predetermined number or more of pixels in which the value of the upper 2 bits (D5D4) is “00” are included in one pixel, this pixel row may be precharged. In addition, the low gradation region to be precharged is appropriately selected, for example, a low gradation side 1/8 region or a low gradation side 1/16 region in consideration of data writing characteristics. You only have to set it. Further, in addition to determining whether or not precharge is performed in units of pixel rows, it is also possible to determine in units of pixels.

  The m circuit units 41 simultaneously perform simultaneous output of current-based signals for a pixel row in which data is written at a certain 1H and dot-sequential latching of data relating to a pixel row to be written at the next 1H. Each circuit unit 41 includes four switch groups 41a, 41c, 41d, and 41e, a first latch circuit 41b, and a second latch circuit having a shift register function, which is a set of switches provided in bit units of data DATA. 41f and current DAC 41g. The operations of the individual circuit units 41 corresponding to the data lines X1 to Xm are the same except that the timing of taking in the data DATA by the latch signals S1, S2, S3,.

  Specifically, first, the frontmost switch group 41a is turned on when the corresponding latch signal S becomes H level. As a result, the 6-bit data D5 to D0 are captured by the first latch circuit 41b at the capture timing defined by the latch signal S. The data D5 to D0 latched in the first latch circuit 41b are transferred to the second latch circuit 41f when the latch pulse LP becomes H level and the switch group 41c is turned on. At the same time, data D5 to D0 in the next 1H are newly latched in the first latch circuit 41b via the switch group 41a.

  The data D5 to D0 output from the first latch circuit 41b are latched by the second latch circuit 41f having a shift register function composed of 8 bits, and the latch position is in accordance with the precharge control signal PCG. Are set in two ways. The current DAC 41g generates the data current Idata based on the lower 6 bits of data latched by the second latch circuit 41f and supplies it to the corresponding data line X.

  FIG. 4 is a schematic characteristic diagram showing the relationship between gradation and data current Idata. According to this characteristic, the current DAC 41g sets the data current Idata based on the lower 6 bits of the 8 bits constituting the second latch circuit 41f. In the figure, the relationship between the gradation and the data current Idata is shown linearly. However, this is merely an example, and the relationship may be set to a non-linear relationship considering the characteristics of the organic EL element OLED. In addition, the data current Idata of the minimum gradation does not need to be 0.

  FIG. 5 is an explanatory diagram of the holding state of the second latch circuit 41f during programming with precharge. In this case, since the precharge control signal PCG becomes H level in the first half, the switch group 41d is turned on and the switch group 41e is turned off. Therefore, the data D5 to D0 output from the first latch circuit 41b are initially latched via the switch groups 41c and 41d to the upper 6 bits of the second latch circuit 41f composed of 8 bits. The Then, the lower two (LSB) 2 bits are reset to Dummy2 and Dummy1 (Dummy2, Dummy1 = 0) according to an instruction by the reset signal RST2. That is, the 6-bit data D5 to D0 are transferred to the second latch circuit 41f in a state in which the data is shifted by 2 bits to the upper (MSB) side, in other words, in a holding state where four times the data current Idata is output. Is latched. Then, the second latch circuit 41f sequentially shifts the latched data bit by bit to the lower side every time the clock CLK rises by the shift register function provided therein. At the first rising edge of the clock CLK (CLK = 1), the holding state outputs two times the data current Idata, and at the second rising edge (CLK = 2), the holding state outputs the original data current Idata. Become.

  As an example, a case where D5D4D3D2D1D0 = “000101” (gradation 5) is latched in the first latch circuit 41b will be described. In this case, the holding state of the second latch circuit 41f at CLK = 0 (initial state) is “00010100” (gradation 20) shifted to the upper side by 2 bits. Therefore, at CLK = 0, the precharge current Ipcg corresponding to the gradation 20 is supplied to the data line X. In the characteristic diagram of FIG. 4, the precharge current Ipcg corresponds to four times the data current Idata in the gradation 5 to be originally displayed. Therefore, the precharge at CLK = 0 is hereinafter referred to as “four times precharge”. At subsequent CLK = 1, the holding state of the second latch circuit 41f changes from “00010100” to “−0001010” (gradation 10). Therefore, at CLK = 1, the precharge current Ipcg corresponding to the gradation 10 is supplied to the data line X. Since the precharge current Ipcg corresponds to twice the data current Idata, the precharge at CLK = 1 is hereinafter referred to as “double precharge”. When CLK = 2, the holding state of the second latch circuit 41f changes from “−0001010” to “−000101” (gradation 5). Therefore, at CLK = 2, the data current Idata corresponding to the original gradation 5 is supplied to the data line X.

  It should be noted that due to the precharge being performed in units of pixel rows, even for the pixels 2 that do not inherently have insufficient data writing, there are pixels 2 that belong to the low gradation side 1/4 region in this pixel row. As long as precharge is performed. In this case, regarding the pixel 2 whose upper 2 bits (D5D4) are not “00”, the relationship of 4 times precharge and 2 times precharge is broken. For example, regarding the pixel 2 that should display “110001” (gradation 49), the precharge current Ipcg of “000100” (gradation 4) when CLK = 0 and “100010” (gradation 34) when CLK = 1. Will be output. However, in the subsequent data writing (CLK = 2), data writing is performed in a short time with a large current (equivalent to the original gradation 49), so how to set the set value of the precharge current Ipcg. Does not cause any problems.

  FIG. 6 is an explanatory diagram of the holding state of the second latch circuit 41f during programming without precharge. In this case, since the precharge control signal PCG remains at the L level, the switch group 41d is turned off and the switch group 41e is turned on. Therefore, the data D5 to D0 output from the first latch circuit 41b are latched on the lower 6 bits side of the second latch circuit 41f via the switch groups 41c and 41e. In this case, the second latch circuit 41f functions as a general latch circuit that does not involve a shift operation by the clock CLK. For example, in a case where D5D4D3D2D1D0 = “100101” (gradation 37) is latched in the first latch circuit 41b, “−-100101” (gradation 37) is latched as it is in the second latch circuit 41f. As a result, the original data current Idata corresponding to the gradation 37 is supplied to the data line X as it is without being precharged.

  The precharge control circuit 6 outputs control signals GPCG1 and GPCG2 based on the scanning signal SEL, the precharge control signal PCG, and the base signals BPCG1 and BPCG2. As shown in FIG. 7, the precharge control circuit 6 can be configured by one AND circuit 6a and two NAND circuits 6b and 6c as an example. FIG. 8 is a timing chart of the precharge control circuit 6. The period t0 to t3 during which the scanning signal SEL is at the H level is 1H. Of the base signals BPCG1 and BPCG2 supplied from the timing signal generation circuit 5, the former has a period equivalent to 1H and the latter has a period equivalent to 0.5H.

  In the case of precharge, the precharge control signal PCG becomes H level during the precharge period t0 to t2 in the first half of 1H. Accordingly, the output of the AND circuit 61 becomes H level, and the NAND circuits 61 and 62 output the inverted levels of the base signals BPCG1 and BPCG2 as the control signals GPCG1 and GPCG2. As a result, the first control signal GPCG1 is set to the L level over the period t0 to t2, and the second control signal GPCG2 is set to the L level during the period t0 to t1 and the H level during the period t1 to t2. Is set. In the data write period t2 to t3 following the precharge period t0 to t2, the precharge control signal PCG is at the L level. Accordingly, the output of the AND circuit 61 becomes L level, and the NAND circuits 61 and 62 set both the control signals GPCG1 and GPCG2 to the H level regardless of the levels of the base signals BPCG1 and BPCG2.

  On the other hand, when there is no precharge, the precharge control signal PCG is maintained at the L level throughout the period t0 to t3. Therefore, the output of the AND circuit 61 becomes the L level, and the NAND circuits 61 and 62 maintain the control signals GPCG1 and GPCG2 at the H level regardless of the levels of the base signals BPCG1 and BPCG2.

  FIG. 9 is a drive timing chart of the pixel 2 at the time of programming with precharge. The timing when the selection of the pixel 2 is started is t0, and the timing when the selection of the pixel 2 is started next is t4. The periods t0 to t4 are roughly divided into program periods t0 to t3 and drive periods t3 to t4. The program period t0 to t3 is divided into a first half precharge period t0 to t2 and a second half data write period t2 to t3. Further, the precharge period t0 to t2 is divided into a quadruple precharge period t0 to t1 and a double precharge period t1 to t2.

  First, in the 4-times precharge period t0 to t1, CLK = 0 and a precharge current Ipcg that is 4 times the data current Idata is supplied to the data line X. At the same time, data is written to the capacitor C shown in FIG. 2 using three transistors T3, Tp1, and Tp2 connected in parallel. FIG. 10 is a diagram for explaining the operation during the 4-times precharge period t0 to t1. At timing t0, the scanning signal SEL rises to H level, and both the transistors T1 and T2 are turned on. Further, since the two control signals GPCG1 and GPCG2 become L level and the switching transistors SW1 and SW2 are both turned on, the three transistors T3, Tp1, and Tp2 are connected in parallel. Thus, the data line X is commonly connected to the drains of the three transistors T3, Tp1, and Tp2, and each of the transistors T3, Tp1, and Tp2 is a diode in which its own gate and its own drain are electrically connected. Connect.

  As described above, since the resistance ratio of the three transistors T3, Tp1, and Tp2 is set to 1: 1: 1/2, the resistance value Rtft of the entire program unit 20 is reduced to 1/4 at the time of data writing. Become. The precharge current Ipcg (Idata × 4) supplied from the data line X is shunted according to this resistance ratio. A current of Idata × 1 flows through the channel of the transistor T3, and a gate voltage corresponding to this current is generated at its own gate. In addition, a current of Idata × 1 flows through the channel of the first precharge transistor Tp1, and a gate voltage corresponding to this current is generated at its own gate. Furthermore, a current of Idata × 2 flows through the channel of the second precharge transistor Tp2, and a gate voltage corresponding to this current is generated at its own gate. The gate voltages of the three transistors T3, Tp1, and Tp2 are the same, and charges corresponding to the generated gate voltage are accumulated as data in the capacitor C commonly connected to these gates.

  Next, in the double precharge period t1 to t2, CLK = 1, and the precharge current Ipcg that is twice the data current Idata is supplied to the data line X. At the same time, data writing to the capacitor C is performed using two transistors T3 and Tp1 connected in parallel. FIG. 11 is an operation explanatory diagram of the double precharge period t1 to t2. During this period t1 to t2, the second control signal GPCG2 rises from the L level to the H level, so that the second switching transistor SW2 is turned off and the two transistors T3 and Tp1 are connected in parallel. As a result, the data line X is commonly connected to the drains of the two transistors T3 and Tp1, and each of the transistors T3 and Tp1 is diode-connected.

  In the double precharge period t1 to t2, the resistance value Rtft of the program unit 20 is ½ of that at the time of data writing, and the precharge current Ipcg (Idata × 2) supplied from the data line X is the transistor T3, The current is divided according to the resistance ratio (1: 1) of Tp1. A current of Idata × 1 flows through the channel of the transistor T3, and a gate voltage corresponding to this current is generated at its own gate. In addition, a current of Idata × 1 flows through the channel of the first precharge transistor Tp1, and a gate voltage corresponding to this current is generated at its own gate. The gate voltages of the two transistors T3 and Tp1 are the same, and the gate voltages of the previous four times precharge period t0 to t1 are also the same. Charges corresponding to the generated gate voltage are accumulated as data in the capacitors C commonly connected to these gates.

  In the data write period t2 to t3 following the precharge period t0 to t2, CLK = 2 and the original data current Idata is supplied to the data line X. At the same time, data is written to the capacitor C using the single transistor T3. FIG. 12 is a diagram for explaining the operation during the data writing period t2 to t3. During this period t2 to t3, the first control signal GPCG1 also rises from the L level to the H level, so the first switching transistor SW1 is also turned off. As a result, the data line X is connected only to the drain of the transistor T3, and only the transistor T3 is diode-connected. The data current Idata supplied from the data line X flows through the channel of the transistor T3, and a gate voltage corresponding to this flows in its own gate. The gate voltage of the transistor T3 is the same as the gate voltage in the previous precharge period t0 to t2, and charges corresponding to the generated gate voltage are stored as data in the capacitor C commonly connected to the gate.

  In the program period t0 to t3, since the drive signal GEL is maintained at the L level, the transistor T4 remains off. Therefore, since the current path of the drive current Ioled with respect to the organic EL element OLED is interrupted, the organic EL element OLED does not emit light.

  In the drive period t3 to t4 following the program period t0 to t3, the drive current Ioled corresponding to the charge amount (data) accumulated in the capacitor C flows through the organic EL element OLED, and the luminance of the organic EL element OLED is set. FIG. 13 is an explanatory diagram of the operation during the driving period t3 to t4. First, at timing t3, the scanning signal SEL falls to the L level, and both the transistors T1 and T2 are turned off. As a result, the data line X to which the data current Idata is supplied is electrically isolated from the drain of the transistor T3, and the gate and drain of the transistor T3 are also electrically isolated. A gate voltage corresponding to the charge stored in the capacitor C is continuously applied to the gate of the transistor T3. In synchronization with the falling edge of the scanning signal SEL at the timing t3, the driving signal GEL, which was previously at the L level, rises to the H level. As a result, a current path of the drive current Ioled through the transistors T3 and T4 and the organic EL element OLED is formed from the power supply voltage Vdd to the reference voltage Vss. The drive current Ioled flowing through the organic EL element OLED corresponds to the channel current of the transistor T3, and the current level is controlled by the gate voltage resulting from the amount of charge in the capacitor C. The organic EL element OLED emits light with a luminance corresponding to the drive current Ioled, and thereby the gradation of the pixel 2 is set.

  The transistor T3 functions as a programming transistor that writes data to the capacitor C in the programming period t0 to t3, but functions as a driving transistor that generates the driving current Ioled in the driving period t3 to t4.

  On the other hand, at the time of programming without precharge, the above-described precharge period t0 to t2 does not exist, and the entire program period t0 to t3 is a data writing period. In this case, the data current Idata defining the gradation of the pixel 2 is supplied to the data line X during the entire programming period t0 to t3, and data writing to the capacitor C is performed only by the transistor T3 functioning as a programming transistor. .

  Thus, according to the present embodiment, in the precharge period t0 to t2 prior to the data write period t2 to t3, the precharge current Ipcg larger than the data current Idata defining the gradation of the pixel 2 is applied to the data line X. To supply. In the subsequent data writing period t2 to t3, the data current Idata corresponding to the gradation to be displayed is supplied to the data line without increasing the current. Thus, by limiting the period during which the current precharge is performed to a part of the program period t0 to t3, the power consumption can be reduced as compared with the case where the current is increased in the entire program period t0 to t3. Is possible.

  Further, in the present embodiment, in response to the precharge current Ipcg being increased from the data current Idata, the resistance value Rtft of the program unit 20 in the precharge period t0 to t2 is set to that in the data write period t2 to t3. Is set smaller. Thereby, compared with the case where only a current value is increased, the precharge effect can be improved. This point will be described in detail with reference to the equivalent model of the pixel 2 at the time of programming shown in FIG. In the figure, Cstg is the capacitance of the capacitor C in the pixel 2, Cclm is the wiring capacitance of the data line X, and Rtft is the overall resistance of the program unit 20.

First, when the gate application voltage of the program unit 20 is set from Vpcg to Vdata by data writing following precharge, the writing time Δt required for this is expressed by Equation 1.
(Equation 1)
Δt = (Cstg + Cclm) (Vpcg−Vdata) / Idata

Here, when the resistance value Rtft of the program unit 20 is constant and the precharge current Ipcg is set to α times the data current Idata, Equation 1 can be expressed as Equation 2.
(Equation 2)
Δt = (Cstg + Cclm) (Ipcg · Rtft−Idata · Rtft) / Idata
= (Cstg + Cclm) (α-1) Idata · Rtft / Idata
= (Cstg + Cclm) (α-1) Rtft

  As can be seen from Equation 1, when the gate applied voltage difference (Vpcg−Vdata) increases between precharge and data write, the write time Δt required for charging and discharging the capacitor C and the wiring capacitance becomes longer. . Further, as can be seen from Equation 2, when only the precharge current Ipcg is increased without changing the resistance value Rtft of the program unit 20, the write time Δ increases as α increases. Therefore, even if only the precharge current Ipcg is simply increased, the write time Δt takes a long time, and as a result, it becomes difficult to obtain a sufficient precharge effect.

Therefore, in this embodiment, in addition to increasing the precharge current Ipcg with respect to the data current Idata, the resistance value Rtft of the program unit 20 is variably set according to the magnitude of the precharge current Ipcg. In the present embodiment, by reducing the number of precharge transistors Tp1 and Tp2 connected in parallel to the transistor T3, the resistance value Rtft as a combined resistance thereof is changed. Then, the resistance value Rtft is set to be smaller at the time of precharging than at the time of data writing, in inverse proportion to the ratio of increasing the precharge current Ipcg to the data current Idata. Specifically, the resistance value Rtft ′ at the time of precharging is set to 1 / α times the resistance value Rtft at the time of data writing. In this case, Formula 1 can be expressed as Formula 3.
(Equation 3)
Δt = (Cstg + Cclm) (Ipcg · Rtft'−Idata · Rtft) / Idata
= (Cstg + Cclm) (Idata.alpha.Rtft / .alpha.-Idata.Rtft) / Idata
= 0

  Thus, when the precharge current Ipcg is set to α times the data current Idata, the precharge resistance is set to 1 / α times that at the time of data writing in inverse proportion to this. This eliminates the difference between the gate applied voltage Vpcg at the time of precharging and the gate applied voltage Vdata at the time of data writing, so that the writing time Δt can be theoretically reduced to zero. Actually, the writing time Δt cannot be completely reduced to zero because of variations in characteristics of transistors and wirings, but the writing time Δt can be sufficiently shortened. Note that the original data is not written after the precharge, and the data to be written in the precharge may be rough to some extent because the written data is finely adjusted at that time.

  For the reasons described above, according to the present embodiment, in the current program method, it is possible to effectively improve the lack of data writing that is likely to occur particularly at a low gradation. In addition, data writing can be completed in a short time even when the gradation is low. As a result, it becomes easy to cope with high definition of the display unit 1 and it is possible to speed up display control.

  In the present embodiment, the precharge current Ipcg is decreased from the current value larger than the data current Idata toward the current value of the data current Idata. Correspondingly, the resistance value Rtft of the program unit 20 is increased from a smaller resistance value at the time of data writing to a resistance value at the time of data writing. As a result, the transition from the current precharge to the data writing becomes smooth and the above-described fluctuation of the gate applied voltage is suppressed, so that the data writing can be performed in a shorter time.

In this embodiment, the precharge current Ipcg is set stepwise by a power of 2 of the data current Idata, for example, Idata × 4, Idata × 2. Correspondingly, the resistance value Rtft of the program unit 20 is a power of 1/2 of R1 (R1 is Rtft at the time of data writing), for example, R1 × 1/4, R1 × 1/2. Set in stages. Setting of Ipcg = Idata × 2 ⁿ (n = 0, 1, 2,...) Can be easily realized by data shift in the second latch circuit 41f having a shift register function. Therefore, the precharge current Ipcg can be set stepwise without greatly changing the existing circuit configuration of the data line driving circuit 4, which is advantageous in terms of circuit design.

  In the above-described embodiment, the setting of the precharge current Ipcg is realized by the data shift operation by the second latch circuit 41f, but the present invention is not limited to this. For example, it is also possible to set the precharge current Ipcg by holding the data DATA in a normal latch circuit having no shift register function and referring to a conversion table prepared in advance. In this case, the precharge current Ipcg can be set with a higher degree of freedom. For example, the precharge current Ipcg can be set to a current value other than 2 times the gradation, such as Idata × 15, Idata × 7, and Idata × 2. Is possible.

  In the above-described embodiment, the program unit 20 is configured by the plurality of transistors T3, Tp1, and Tp2. However, the number and resistance value of the program unit 20 are arbitrary, or the program unit 20 has a different circuit configuration. May be configured.

  FIG. 15 is a circuit diagram of the pixel 2 as another example. The same elements as those shown in FIG. 2 are denoted by the same reference numerals, and description thereof is omitted here. In the configuration of FIG. 15, the third precharge transistor Tp3 is added to the configuration of FIG. 2, and the connection relationship is set by the third switching transistor SW3 controlled by the control signal GPCG3. The resistance ratio of the transistors T3, Tp1, Tp2, and Tp3 is set to 1: 2: 4: 8 (channel length is the same) by setting the ratio of these channel widths to 1: 2: 4: 8. 8 is set.

  In such a configuration, the current precharge can be performed in the order of Idata × 15, Idata × 7, and Idata × 3, for example. That is, when the precharge current Ipcg of Idata × 15 is supplied at 15 times precharge, all the three switching transistors SW1 to SW3 are turned on and the four transistors T3 and Tp1 to Tp3 are connected in parallel. Thereby, the resistance value Rtft of the program unit 20 becomes 1/15 at the time of data writing. When the precharge current Ipcg of Idata × 7 is supplied at 7 times precharge, the switching transistor SW3 is switched from on to off, and the three transistors T3, Tp1, and Tp2 are connected in parallel. As a result, the resistance value Rtft becomes 1/7 that during data writing. When the precharge current Ipcg of Idata × 3 is supplied three times, the switching transistor SW2 is also switched from on to off, and the two transistors T3 and Tp1 are connected in parallel. As a result, the resistance value Rtft becomes 1/3 of that at the time of data writing.

  When reducing the precharge current Ipcg, it is preferable to reduce the amount of change over time from the viewpoint of suppressing the fluctuation of the gate applied voltage described above. For example, when current precharge of Idata × 15, Idata × 7, and Idata × 3 is performed, the amount of change between the steps decreases with time by decreasing in this order. This is because the amount of change ΔI1 between 15 times precharge and 7 times precharge is Idata × 8, and the amount of change ΔI2 between 7 times precharge and 3 times precharge is Idata × 4, 3 times precharge and data This is because the amount of change ΔI3 during the writing of I is Idata × 2, and the relationship ΔI1> ΔI2> ΔI3 is satisfied. In this case, it is preferable to increase the resistance value Rtft of the program unit 20 so as to increase with time in correspondence with the decrease of the precharge current Ipcg.

  In addition, the pixel circuit to which the present invention is applicable is not limited to the configuration of FIG. 2 or FIG. 15. For example, the pixel circuit has a configuration in which a programming transistor and a driving transistor are formed of separate transistors. However, it is widely applicable.

  In the above-described embodiment, the example in which the organic EL element OLED is used as the electro-optical element has been described. However, the present invention is not limited to this, and an electro-optical element (inorganic LED display device, field emission display device, etc.) whose luminance is set according to the drive current, or transmittance according to the drive current. -Widely applicable to electro-optical devices (electrochromic display devices, electrophoretic display devices, etc.) exhibiting reflectivity.

  Furthermore, the electro-optical device according to the above-described embodiment can be mounted on various electronic devices including, for example, a television, a projector, a mobile phone, a mobile terminal, a mobile computer, a personal computer, and the like. When the above-described electro-optical device is mounted on these electronic devices, the commercial value of the electronic devices can be further increased, and the product appeal of electronic devices in the market can be improved.

Block diagram of electro-optical device Pixel circuit diagram as an example Data line drive circuit configuration diagram Schematic characteristic diagram showing the relationship between gradation and data current Explanatory drawing of the holding state of the second latch circuit during programming with precharge Explanatory diagram of the holding state of the second latch circuit during programming without precharge Configuration diagram of precharge control circuit Timing chart of precharge control circuit Pixel drive timing chart during programming with precharge Operation explanatory diagram of 4 times precharge period Operation explanatory diagram of double precharge period Operation explanatory diagram of data writing period Operation explanatory diagram of drive period Equivalent model of pixels during programming Circuit diagram of pixel as another example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Display part 2 Pixel 3 Scan line drive circuit 4 Data line drive circuit 5 Timing signal generation circuit 6 Precharge control circuit 6a AND circuit 6b, 6c NAND circuit 20 Program part 40 X shift register 41 Circuit unit 41a, 41c, 41d, 41e Switch group 41b First latch circuit 41f Second latch circuit 41g Current DAC
42 memory circuit 43 discriminating circuit 61 AND circuit 62, 63 NAND circuit T1-T4 transistor Tp1, Tp2 precharge transistor SW1, SW2 switching transistor
OLED organic EL element C capacitor

Claims (23)

In an electro-optical device in which a signal is supplied to a data line on a current basis,
A plurality of scan lines;
Multiple data lines,
A plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
Each of the plurality of pixels is
A capacitor for holding data;
An electro-optic element whose luminance is set by a drive current corresponding to data held in the capacitor flowing;
A program unit for writing data to the capacitor by a voltage generated in accordance with a current supplied through the data line and variably setting a resistance value in a path through which the current flows. ,
A precharge current larger than the data current is supplied to the data line in a precharge period preceding a data writing period in which a data current defining the gray level of the pixel is supplied to the data line,
The electro-optical device, wherein a first resistance value of the program unit set in the precharge period is smaller than a second resistance value of the program unit set in the data writing period.   The electro-optical device according to claim 1, wherein the first resistance value is set according to a magnitude of the precharge current with respect to the data current.   3. The electro-optical device according to claim 2, wherein the first resistance value is set in inverse proportion to a ratio of increasing the precharge current with respect to the data current. A data line driving circuit including a latch circuit having a shift register function;
The precharge current is set to a power of 2 of the data current by shifting the data held in the latch circuit,
The electro-optical device according to claim 3, wherein the first resistance value is set to a power of 1/2 of the second resistance value. The precharge current decreases from a current value larger than the data current toward a current value of the data current,
5. The electro-optic according to claim 1, wherein the first resistance value increases from a resistance value smaller than the second resistance value toward the second resistance value. 6. apparatus. The precharge current decreases so that the amount of change decreases with time,
6. The electro-optical device according to claim 5, wherein the first resistance value increases so that the amount of change increases with time. In an electro-optical device in which a signal is supplied to a data line on a current basis,
A plurality of scan lines;
Multiple data lines,
A plurality of pixels provided corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
Each of the plurality of pixels is
A capacitor for holding data;
An electro-optic element in which brightness is set by a drive current flowing according to data held in the capacitor;
A first transistor for writing data to the capacitor;
At least one second transistor provided in parallel with the first transistor for writing data to the capacitor;
In the precharge period, a precharge current larger than a data current defining the gray level of the pixel is supplied to the data line, and data writing according to the precharge current is performed in the first transistor and the second transistor. With the transistor of
In the data writing period following the precharge period, the data current is supplied to the data line, and data writing according to the data current is performed using the first transistor. Electro-optic device. A data line driving circuit including a latch circuit having a shift register function;
The precharge current is set to a power of 2 of the data current by shifting the data held in the latch circuit,
In the precharge period, the resistance value set by the parallel connection of the first transistor and the second transistor is set to a power of 1/2 of the resistance value of the first transistor. The electro-optical device according to claim 7.   9. The electro-optical device according to claim 7, wherein, in the precharge period, the number of the second transistors connected in parallel to the first transistor is reduced over time.   The electro-optical device according to claim 9, wherein the precharge current is variably set according to the number of the second transistors connected in parallel to the first transistor.   The precharge current gradually decreases from a current value larger than the data current toward the current value of the data current according to the number of the second transistors connected in parallel to the first transistor. The electro-optical device according to claim 10.   An electronic apparatus comprising the electro-optical device according to claim 1 mounted thereon. In a driving method of an electro-optical device having a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and supplying a signal to the data lines on a current basis,
A precharge current larger than a data current defining the gradation of the pixel is supplied to the data line, and a resistance value in a path through which the precharge current flows is set to a first resistance value, and then the precharge current is set. A first step of writing data to the capacitor by a voltage generated according to the charge current;
The data current is supplied to the data line, and a resistance value in a path through which the data current flows is set to a second resistance value larger than the first resistance value, and is generated according to the data current. A second step of writing data to the capacitor according to the voltage to be applied;
And a third step of setting a gradation of the pixel by supplying a driving current corresponding to data held in the capacitor to the electro-optical element.   14. The method of driving the electro-optical device according to claim 13, wherein, in the first step, the first resistance value is set according to a magnitude of the precharge current with respect to the data current.   15. The electro-optical device according to claim 14, wherein, in the first step, the first resistance value is set in inverse proportion to a ratio of increasing the precharge current with respect to the data current. Device driving method.   In the first step, the precharge current is set to a power of 2 of the data current, and the first resistance value is set to a power of 1/2 of the second resistance value. 16. The driving method of an electro-optical device according to claim 15,   In the first step, the precharge current is decreased from a current value larger than the data current toward a current value of the data current, and the second current value is decreased from a resistance value smaller than the second resistance value. The method of driving an electro-optical device according to claim 13, wherein the first resistance value is increased toward a resistance value.   In the first step, the precharge current is decreased so that the amount of change decreases with time, and the first resistance value is increased so that the amount of change increases with time. The driving method of the electro-optical device according to claim 17. In a driving method of an electro-optical device having a plurality of pixels provided corresponding to intersections of a plurality of scanning lines and a plurality of data lines, and supplying a signal to the data lines on a current basis,
Supplying a precharge current larger than a data current defining a gray level of the pixel to the data line, and writing data to a capacitor in accordance with the precharge current; a first transistor connected in parallel; A first step performed using at least one second transistor;
A second step of supplying the data current to the data line and writing data to the capacitor in accordance with the data current using the first transistor;
And a third step of setting a gradation of the pixel by supplying a driving current corresponding to data held in the capacitor to the electro-optical element.   In the first step, the precharge current is set to a power of 2 times the data current, and a resistance value set by a parallel connection of the first transistor and the second transistor is set to the first value. 20. The method of driving an electro-optical device according to claim 19, wherein the resistance is set to a power of 1/2 of the resistance value of the transistor.   21. The method of driving an electro-optical device according to claim 19, wherein, in the first step, the number of the second transistors connected in parallel to the first transistor is reduced over time. .   The electric charge according to claim 21, wherein, in the first step, the precharge current is variably set according to the number of the second transistors connected in parallel to the first transistor. Driving method of optical device.   In the first step, according to the number of the second transistors connected in parallel to the first transistor, the precharge from the current value larger than the data current toward the current value of the data current. 23. The method of driving an electro-optical device according to claim 22, wherein the current is decreased stepwise.

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