JP2005064413A - Parallel flat plate capacitor - Google Patents

Parallel flat plate capacitor Download PDF

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JP2005064413A
JP2005064413A JP2003296037A JP2003296037A JP2005064413A JP 2005064413 A JP2005064413 A JP 2005064413A JP 2003296037 A JP2003296037 A JP 2003296037A JP 2003296037 A JP2003296037 A JP 2003296037A JP 2005064413 A JP2005064413 A JP 2005064413A
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thin film
plate capacitor
sto
dielectric constant
parallel plate
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JP4362581B2 (en
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Hiroshi Takashima
浩 高島
Akira Shoji
彰 東海林
Ruiping Wang
瑞平 王
Junji Ito
順司 伊藤
Mitsuru Ito
満 伊藤
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National Institute of Advanced Industrial Science and Technology AIST
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a parallel flat plate capacitor that uses a strontium titanate laminate as a dielectric, which has solved the problem wherein a bulk single crystal STO's dielectric constant drops when used as a thin film although it is a very useful dielectric in practically using a superconducting or low temperature device because of its high dielectric constant at a low temperature. <P>SOLUTION: As a dielectric of a parallel flat plate capacitor, a first strontium titanate thin film is formed on a substrate, and the surface of the thin film is polished through chemical-mechanical polishing, and then, a second strontium titanate thin film is formed on the polished surface, thus using a strontium titanate thin film laminate having a high dielectric constant. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、YBaCu7−δ薄膜を中心とする酸化物超伝導デバイスや低温で使用される半導体デバイス等に使用されるチタン酸ストロンチウム積層体を誘電体として用いたコンデンサに関する。 The present invention relates to a capacitor using a strontium titanate laminate used as a dielectric for an oxide superconducting device centering on a YBa 2 Cu 3 O 7-δ thin film, a semiconductor device used at a low temperature, and the like.

バルク単結晶のチタン酸ストロンチウム(以下「STO」という。)は、量子常誘電体として知られ、その比誘電率は、4.2Kで20,000以上の値を示す。また、その比誘電率は、バイアス依存性、ストレス依存性を持ち、それらによって低下する特長を持っている。   Bulk single crystal strontium titanate (hereinafter referred to as “STO”) is known as a quantum paraelectric, and has a relative dielectric constant of 20,000 or more at 4.2K. In addition, the relative dielectric constant has a bias dependency and a stress dependency, and has a feature of decreasing by them.

STOの格子定数は、酸化物超伝導体に非常に近い値を持つことから、該超伝導体のエピタキシャル成長下地基板として用いられ、超伝導デバイスの開発には重要な材料である。   Since the lattice constant of STO has a value very close to that of an oxide superconductor, it is used as an underlying substrate for epitaxial growth of the superconductor and is an important material for the development of superconducting devices.

実際に、STO薄膜は、デバイスに使用されているが、その比誘電率は10,000以下(4.2K)であり、バルク単結晶で得られている 20,000には達していない。   Actually, although the STO thin film is used for a device, its relative dielectric constant is 10,000 or less (4.2K), and does not reach 20,000 obtained by a bulk single crystal.

図1に、例として、M. Lippmaa, M. Kawasakiらの報告によるものを示す。この場合の比誘電率は、8,200にしか達していない。   FIG. 1 shows an example reported by M. Lippmaa, M. Kawasaki et al. In this case, the relative dielectric constant reaches only 8,200.

Appl. Phys. Lett. 74, 3543(1999)Appl. Phys. Lett. 74, 3543 (1999) Appl. Phys. Lett. 73, 464(1998)Appl. Phys. Lett. 73, 464 (1998)

上述したように、バルク単結晶STOは、低温で高い誘電率を示すため、超伝導デバイスや低温で使用される半導体デバイスで使用した場合は、極めて有用な誘電体であるにも関わらず、薄膜化すると誘電率が低下してしまうという欠点があった。そのため、低温で高い誘電率を有する薄膜STOを平行平板コンデンサの誘電体として利用することができなかった。
本発明の目的は、上記の問題点に鑑み、薄膜STOを誘電体として用い、低温で高い誘電率を有し、かつ電場依存性の小さい平行平板コンデンサを提供することにある。
As described above, the bulk single crystal STO exhibits a high dielectric constant at a low temperature. Therefore, when used in a superconducting device or a semiconductor device used at a low temperature, the bulk single crystal STO is a very useful dielectric. However, there is a drawback that the dielectric constant is lowered. Therefore, a thin film STO having a high dielectric constant at a low temperature cannot be used as a dielectric for a parallel plate capacitor.
In view of the above problems, an object of the present invention is to provide a parallel plate capacitor that uses a thin film STO as a dielectric, has a high dielectric constant at a low temperature, and has a small electric field dependency.

本発明は、STO膜を第1と第2の2層構造とし、その2つの層の界面を化学的機械研磨(以下「CMP」という。)することによって、高誘電率チタン酸ストロンチウム薄膜積層体を構成し、該高誘電率チタン酸ストロンチウム薄膜積層体を誘電体とする平行平板コンデンサを構成した。   In the present invention, a high-dielectric-constant strontium titanate thin film laminate is obtained by making the STO film a first and second two-layer structure and chemically and mechanically polishing (hereinafter referred to as “CMP”) the interface between the two layers. And a parallel plate capacitor using the high dielectric constant strontium titanate thin film laminate as a dielectric.

本発明によれば、100kHzで温度4.2Kにおいて20,000以上の比誘電率を有し、かつ電場依存性の小さいキャパシタンス(比誘電率)を有する平行平板コンデンサが得られる。   According to the present invention, it is possible to obtain a parallel plate capacitor having a relative dielectric constant of 20,000 or more at 100 kHz and a temperature of 4.2 K, and having a capacitance (relative dielectric constant) having a small electric field dependency.

図2に、本願発明に係る平行平板コンデンサの概念図を示す。
同図において、基板上に平行平板コンデンの下部電極となる下部イットリウム系酸化物超伝導(以下「YBCO」という。)層を積層し、該下部YBCO層の上に、第1のSTO層を堆積する。該第1層のSTO層の表面をCMPする。この後、該表面に第2のSTO層を形成し、該第2のSTO層の上に平行平板コンデンサの上部電極となるYBCO層を形成し、平行平板コンデンサの誘電体となる高誘電率チタン酸ストロンチウム薄膜積層を構成する。
FIG. 2 shows a conceptual diagram of a parallel plate capacitor according to the present invention.
In the figure, a lower yttrium-based oxide superconducting (hereinafter referred to as “YBCO”) layer, which becomes a lower electrode of a parallel plate capacitor, is laminated on a substrate, and a first STO layer is deposited on the lower YBCO layer. To do. The surface of the first STO layer is subjected to CMP. Thereafter, a second STO layer is formed on the surface, and a YBCO layer serving as an upper electrode of a parallel plate capacitor is formed on the second STO layer, and a high dielectric constant titanium serving as a dielectric of the parallel plate capacitor is formed. A strontium acid thin film stack is constructed.

次に、本発明に係るCMPを用いた3層構造の平行平板コンデンサの作製プロセスを図5を用いて説明する。
なお、該作製プロセスにおけるYBCO薄膜の成膜条件およびSTO薄膜の成膜条件をそれぞれ図3および図4に示す。
まず、工程(a)において、パルスレーザ成長法(以下「PLD法」という。)を用いて、STO(100)基板上に下部YBCO膜としてc軸配向YBCO(00n)薄膜を厚さ300nm成膜後、真空を破ることなく連続してSTO(001)薄膜を厚さ10nm成膜して、STO/YBCO構造を作製する。
Next, a manufacturing process of a parallel plate capacitor having a three-layer structure using CMP according to the present invention will be described with reference to FIGS.
The film forming conditions for the YBCO thin film and the film forming conditions for the STO thin film in the manufacturing process are shown in FIGS. 3 and 4, respectively.
First, in step (a), a c-axis oriented YBCO (00n) thin film having a thickness of 300 nm is formed as a lower YBCO film on an STO (100) substrate by using a pulse laser growth method (hereinafter referred to as “PLD method”). Thereafter, an STO (001) thin film having a thickness of 10 nm is continuously formed without breaking the vacuum to produce an STO / YBCO structure.

この厚さ10nmのSTO薄膜は、カバーSTO薄膜とよばれ、作製プロセスでYBCOが直接、大気や純水にさらされることを防ぎ、YBCO本来の超伝導特性を低下させないために成膜される。   This STO thin film having a thickness of 10 nm is called a cover STO thin film, and is formed in order to prevent YBCO from being directly exposed to the atmosphere and pure water in the manufacturing process, and not to deteriorate YBCO's original superconducting characteristics.

次に半導体技術で利用されているフォトリソグラフィー法を用いて、レジストにより下部パターンを作製し、低エネルギーイオンミリングを用いてエッチングを行い、平行平板コンデンサの下部電極となる下部YBCOのパターンを形成する。   Next, using a photolithography method used in semiconductor technology, a lower pattern is formed with a resist, and etching is performed using low energy ion milling to form a pattern of a lower YBCO that becomes a lower electrode of a parallel plate capacitor. .

次に、工程(b)において、PLD法により、STO(100)薄膜厚さ1μm成膜を行う。この成膜は、まず、基板を200℃に保持し、真空度が10−4Paに到達した後、酸素ガス雰囲気中(酸素圧100Pa)において温度上昇を行い、810℃に到達した後、STO薄膜を成長させる。 Next, in step (b), a STO (100) thin film having a thickness of 1 μm is formed by the PLD method. In this film formation, first, the substrate is held at 200 ° C., the degree of vacuum reaches 10 −4 Pa, the temperature is increased in an oxygen gas atmosphere (oxygen pressure 100 Pa), and after reaching 810 ° C., STO Grow a thin film.

次に、工程(c)において、このSTO薄膜表面上に存在する突起物を除去し、下部YBCO薄膜の作るパターンの段差を平坦化するためにCMPにより研磨する。   Next, in step (c), the protrusions present on the surface of the STO thin film are removed, and polishing is performed by CMP in order to flatten the step of the pattern formed by the lower YBCO thin film.

下部YBCO薄膜を直接研磨すると超伝導特性を劣化させる原因になるため、STO薄膜の研磨を行う。その後、CMPプロセスによって表面に付着したSi粒子等の不純物を、アセトン中でサンプルを超音波洗浄による表面クリーニングによって取り除く。   Polishing the lower YBCO thin film directly causes deterioration of superconducting properties, so the STO thin film is polished. Thereafter, impurities such as Si particles attached to the surface by the CMP process are removed by surface cleaning by ultrasonic cleaning of the sample in acetone.

CMPプロセス後、RHEED観測で観測した結果、試料表面は、アモルファス的であることが分かった。アモルファス結晶上にはエピタキシャル成長は、期待できない。このため、酸素圧100Pa雰囲気中、温度600℃、2時間の熱処理を行った。
原子間力顕微鏡(AFM)を用いて表面構造の観察を行った結果を図6に示す。この写真に見られるように、CMP前においては、かなり大きな突起が観察されるが、CMP後においては、上記突起に比べるとはるかに小さな突起が見られる程度に表面が滑らかになっている。
As a result of observation by RHEED observation after the CMP process, it was found that the sample surface was amorphous. Epitaxial growth cannot be expected on amorphous crystals. For this reason, a heat treatment was performed at a temperature of 600 ° C. for 2 hours in an atmosphere having an oxygen pressure of 100 Pa.
FIG. 6 shows the results of observation of the surface structure using an atomic force microscope (AFM). As can be seen in this photograph, fairly large protrusions are observed before CMP, but after CMP, the surface is smooth enough to have much smaller protrusions than the above protrusions.

典型的に、200nm程度の高さの円錐状形状の突起物は、CMPにより、高さが1/10以下の20nm以下に減少し、底面の面積が0.04μm以下と1/10以下になっていることが確認された。CMPによって突起物の形状が小さくなっていることから、超伝導マイクロショートが解消されるであろうことが期待される。 Typically, a conical protrusion having a height of about 200 nm is reduced by CMP to 20 nm or less, which is 1/10 or less, and the area of the bottom surface is 0.04 μm 2 or less and 1/10 or less. It was confirmed that Since the shape of the protrusion is reduced by CMP, it is expected that the superconducting micro-short will be eliminated.

次に、工程(d)において、熱処理後、PLDを用いて絶縁層STO薄膜を200nm成膜し、真空を破ることなく連続して上部YBCO薄膜を250nm成膜する。このSTO薄膜は、CMPによって下部YBCO薄膜から成長している突起物の上部を切断した後、上部平面がSTO研磨表面に出現していることで生じるマイクロショートによる絶縁性の低下を防ぐためである。
図7に絶縁層STO薄膜と上部YBCOの境界面の観察結果を示す。この写真に示すように、この境界面において格子配列がエピタキシャル成長していることが分かる。
Next, in step (d), after heat treatment, an insulating layer STO thin film is formed to 200 nm using PLD, and an upper YBCO thin film is continuously formed to 250 nm without breaking the vacuum. This STO thin film is for preventing the deterioration of the insulation due to the micro-short caused by the upper plane appearing on the STO polished surface after cutting the upper part of the protrusion growing from the lower YBCO thin film by CMP. .
FIG. 7 shows an observation result of the boundary surface between the insulating layer STO thin film and the upper YBCO. As shown in this photograph, it can be seen that the lattice arrangement is epitaxially grown at this boundary surface.

成膜した平行平板コンデンサの上部電極となる上部YBCOのパターンをフォトリソグラフィー法及び低エネルギーイオンミリングを用いて行い、平行平板コンデンサを作製した。HF5%を用いて、下部YBCOに作製した電極部分のSTO膜をエッチングにより取り除いた。   A pattern of the upper YBCO that becomes the upper electrode of the formed parallel plate capacitor was formed by using a photolithography method and low energy ion milling to produce a parallel plate capacitor. The STO film of the electrode portion formed on the lower YBCO was removed by etching using HF 5%.

上部YBCOと下部YBCO薄膜のパターンは、クロスオーバーした構造であり、クロスした部分は、上部YBCO/絶縁層STO/CMP-STO/capped−STO/下部YBCOの積層構造である。   The pattern of the upper YBCO and the lower YBCO thin film has a crossover structure, and the crossed portion has a stacked structure of an upper YBCO / insulating layer STO / CMP-STO / capped-STO / lower YBCO.

図8に作製した平行平板コンデンサの絶縁抵抗率の温度特性を示す。
同図に示すように、該絶縁抵抗率は、CMP研磨することによって半導体的挙動が確認され、従来のCMP研磨をせずに作製した3層構造のものでは、低温域で急激に絶縁抵抗率が減少したのに対して、低温域での絶縁抵抗率が大幅に改善されていることが分かる。
FIG. 8 shows the temperature characteristics of the insulation resistivity of the manufactured parallel plate capacitor.
As shown in the figure, the insulation resistivity is confirmed by semiconducting behavior by CMP polishing, and in the case of a three-layer structure manufactured without conventional CMP polishing, the insulation resistivity suddenly decreases in a low temperature range. It can be seen that the insulation resistivity in the low temperature region is greatly improved.

図9に作製した平行平板コンデンサの誘電率の温度特性を示す。
同図に示すように、100kHzで温度4.2Kにおいて20,000以上の比誘電率が確認された。この比誘電率の温度依存性は単結晶で得られた特性と一致していることから、優れた誘電特性を持つSTO薄膜がYBCO薄膜上に作製されていることが分かる。
FIG. 9 shows the temperature characteristics of the dielectric constant of the manufactured parallel plate capacitor.
As shown in the figure, a relative dielectric constant of 20,000 or more was confirmed at 100 kHz and at a temperature of 4.2 K. Since the temperature dependence of the relative dielectric constant is consistent with the characteristics obtained with the single crystal, it can be seen that an STO thin film having excellent dielectric characteristics is produced on the YBCO thin film.

図10に2.2Kで測定した平行平板コンデンサのキャパシタンス(比誘電率)の電場特性を示す。
同図に示すように、電場強度の変化に対してほぼ一定のキャパシタンス(比誘電率)を有する平行平板コンデンサが得られることが分かる。
FIG. 10 shows the electric field characteristics of the capacitance (relative permittivity) of the parallel plate capacitor measured at 2.2K.
As shown in the figure, it can be seen that a parallel plate capacitor having a substantially constant capacitance (dielectric constant) with respect to a change in electric field strength can be obtained.

M. LippmaaらによるSTO薄膜の比誘電率を示す。The dielectric constant of the STO thin film by M. Lippmaa et al. 本願発明に係る平行平板コンデンサの概念図を示す。The conceptual diagram of the parallel plate capacitor | condenser which concerns on this invention is shown. YBCO薄膜の成膜条件を示す。The film forming conditions of the YBCO thin film are shown. STO薄膜の成膜条件を示す。The film forming conditions of the STO thin film are shown. CMPを用いた3層構造の平行平板コンデンサの作製プロセスを示す。A manufacturing process of a parallel plate capacitor having a three-layer structure using CMP will be described. 原子間力顕微鏡を用いて観察したSTO表面構造を示す。The STO surface structure observed using an atomic force microscope is shown. 絶縁層STO薄膜と上部YBCOの境界面の観察結果を示す。The observation result of the interface between the insulating layer STO thin film and the upper YBCO is shown. 本願発明を利用した平行平板コンデンサの絶縁抵抗率の温度特性を示す。The temperature characteristic of the insulation resistivity of the parallel plate capacitor using this invention is shown. 本願発明を利用した平行平板コンデンサの比誘電率の温度特性を示す。The temperature characteristic of the dielectric constant of the parallel plate capacitor using the present invention is shown. 本願発明の平行平板コンデンサのキャパシタンス(比誘電率)の電場特性を示す。The electric field characteristic of the capacitance (relative permittivity) of the parallel plate capacitor of the present invention is shown.

Claims (2)

基板上に第1のチタン酸ストロンチウム薄膜を形成し、該薄膜表面を化学的機械研磨により研磨した後、該研磨された表面上に第2のチタン酸ストロンチウム薄膜が形成されてなる高誘電率チタン酸ストロンチウム薄膜積層体を誘電体として用いたことを特長とする平行平板コンデンサ。   A high dielectric constant titanium formed by forming a first strontium titanate thin film on a substrate, polishing the surface of the thin film by chemical mechanical polishing, and then forming a second strontium titanate thin film on the polished surface A parallel plate capacitor using a strontium oxide thin film laminate as a dielectric. 上記基板は、YBaCu7−δ(A=Y,Nd,Sm,Eu,Gd,Dy,Ho,Yb;δは1以下の正数)、MgO、LaAlO又は半導体ウェーハ基板に前記物質が形成されたものであることを特長とする請求項1に記載の平行平板コンデンサ。 The substrate is YBa 2 Cu 3 O 7-δ (A = Y, Nd, Sm, Eu, Gd, Dy, Ho, Yb; δ is a positive number of 1 or less), MgO, LaAlO 3 or the semiconductor wafer substrate. The parallel plate capacitor according to claim 1, wherein a substance is formed.
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JPH11307735A (en) * 1998-04-22 1999-11-05 Sharp Corp Manufacture of semiconductor memory element
JP4022620B2 (en) * 2003-05-22 2007-12-19 独立行政法人産業技術総合研究所 Strontium titanate thin film laminate and method for producing the same

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