JP3735604B2 - Superconducting element manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a superconducting element.
[0002]
[Prior art]
Digital information processing devices using superconductors have excellent characteristics such as ultra-high-speed operation and ultra-low power consumption. The single flux quantum device is the only device other than a semiconductor that has been proved to be capable of realizing an integrated circuit capable of performing complicated processing. In view of the expected increase in power demand in the future, there are a wide range of devices that are required to replace superconductivity, such as servers, mainframes, routers, and filters for communication base stations. In particular, the high temperature superconductor is superior from the low temperature superconductor in terms of cooling cost. However, high-temperature superconductors have a poor variation in bonding characteristics, and it is extremely important to suppress this variation. From recent research results, it has been found that the surface properties of samples expressed by the amount of heterogeneous precipitates deposited due to deviations in the roughness and composition of the sample surface have a significant effect on the dispersion of bonding characteristics. (For example, see Non-Patent Document 1).
[0003]
As a solution to this problem, the following method has been implemented. For example, as a surface treatment method, a method of scraping the surface of a sample by mechanical polishing using alumina having a particle size of 0.03 μm (for example, refer to Non-Patent Document 2), or by stacking a sample thicker than a desired film thickness by ion milling A method of shaving the sample surface has been implemented. In addition, a method of reducing the density of precipitates by using a solid solution material capable of suppressing the precipitation of foreign phases has begun to be widely adopted.
[0004]
Currently, the mainstream bonding of high-temperature superconductors is an interface-modified bonding that uses an amorphous layer mainly composed of rare earth elements produced as a barrier layer when the lamp edge shape is processed by ion milling. Yes (see Non-Patent Document 3, for example). An ion milling process is performed on a sample in which a superconducting thin film (lower electrode layer) and an insulating oxide thin film are laminated on a substrate, and then a superconducting thin film (upper electrode layer) is laminated thereon. The design value of the characteristics of the element and each superconducting thin film is determined from constraints such as the formula Φ ₀ = LI _{c to} be satisfied by the magnetic flux quantum, the lower limit of the inductance of the superconducting wiring, and thermal noise at the circuit operating temperature (30K to 40K). Since it is necessary to reduce the inductance L of each electrode layer in order to obtain high-speed operation and circuit operation margin, each superconducting thin film is grown in c-axis orientation. The c-axis alignment film can be obtained in a temperature region where the deposition substrate temperature is high, but the junction characteristics suitable for circuit operation can be obtained only in the low temperature region. For this reason, the suppression of the a-axis mixing rate in the low temperature region is an important factor for circuit fabrication, and the suppression of the a-axis mixing rate has been demanded.
[0005]
[Non-Patent Document 1]
H. Katsuno, S. Inoue, T. Nagano, and J. Yoshida, "Characteristics of interface-engineered Josephson junctions using a YbBa ₂ Cu ₃ O _y counterelectrode layer," Appl. Phys. Lett., Vol. 79, pp. 4189-4191, December 2001.
[0006]
[Non-Patent Document 2]
T. Hato, Y. Ishimaru, H. Aso, A. Yoshida, and N. Yokoyama, "Leveling Technique for High Tc Superconducting Films and Circuits," Advances in Superconductivity, pp. 1008-1010, 1999. [Proceedings of the 12th International Symposium on Superconductivity 1999]
[0007]
[Non-Patent Document 3]
BH Moeckly, and K. Char, "Properties of interface-engineered high Tc Josephson junctions," Appl. Phys. Lett. Vol. 71, pp. 2526-2528, October 1997.
[0008]
[Problems to be solved by the invention]
An object of the present invention is to provide a method capable of manufacturing a superconducting element having good characteristics by suppressing the mixing of the a-axis in a low temperature region.
[0009]
[Means for Solving the Problems]
A method of manufacturing a superconducting element according to an aspect of the present invention includes a step of laminating a lower electrode layer formed of an oxide superconducting thin film and an insulating oxide thin film, and the lower electrode layer and the insulating oxide thin film. The laminated film is processed by ion milling using a rare gas, an amorphous layer is formed on the processed end face of the lower electrode layer, and the processed laminated film is exposed to an atmosphere of an active species of a halogen-based gas or a reducing gas. The step of cleaning the surface of the insulating oxide thin film, and the step of crystallizing the amorphous layer on the processed end face of the lower electrode layer by heating the laminated film in an oxygen atmosphere to form a barrier layer And a step of laminating an upper electrode layer formed of an oxide superconducting thin film on the laminated film.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below.
A superconducting element manufactured by a method according to an embodiment of the present invention has an interface-modified junction, and a laminated film of an oxide superconducting thin film (lower electrode layer) and an insulating oxide thin film is ionized using a rare gas. Processing by milling and forming an amorphous layer on the processed end face of the lower electrode layer, crystallizing the amorphous layer on the processed end face of the lower electrode layer to form a barrier layer, and an oxide superconducting thin film on the laminated film It is manufactured by a method including a step of forming (upper electrode layer).
[0011]
Therefore, this superconducting element includes a three-layer structure of lower electrode layer / barrier layer and insulating oxide thin film / upper electrode layer. The junction structure may be a lamp edge type or a laminated junction type. After the oxide superconducting thin film and the insulating oxide thin film to be the ground plane are laminated on the substrate, the above-described three-layer structure of the lower electrode layer / barrier layer and the insulating oxide thin film / upper electrode layer may be formed. . An insulating oxide thin film or an oxide superconducting thin film may be laminated on the upper electrode layer. Further, a buffer layer may be provided between the above layers.
[0012]
The inventors of the present invention have found that the upper electrode layer laminated on the sample that has been subjected to the ion milling treatment has an a-axis mixing ratio increased by one to two digits compared to the upper electrode layer on the sample that has not been subjected to the ion milling treatment. I found out. In order to investigate this cause, surface analysis was performed by XPS and RHEED on the surface of the CaSnO ₃ insulating oxide thin film subjected to ion milling. Then, it was found that CaO-based amorphous oxide was generated on the surface. This amorphous oxide cannot be removed by ion milling or mechanical polishing. This is because the barrier layer is extremely sensitive to ion milling conditions and water.
[0013]
In response to this problem, the present inventors are exposed to an atmosphere of an active species of a halogen-based gas or a reducing gas, thereby forming an amorphous layer (mainly composed of rare earth elements) formed on the processed end face of the lower electrode layer ( The present invention has been completed by finding that the amorphous oxide can be selectively removed and the surface of the insulating oxide thin film can be cleaned without affecting the barrier layer.
[0014]
Next, materials and conditions used in the method according to the embodiment of the present invention will be described.
[0015]
As a material of the oxide superconducting thin film, the following general formula (L1 _(1-x) L2 _x ) AE ₂ M ₃ O _y
(Here, L1 and L2 represent at least one metal selected from the group consisting of Y and lanthanoid metals, AE represents at least one metal selected from the group consisting of Ca, Ba and Sr, and M represents 80 % Represents a metal containing Cu at a molar ratio of at least%, and y satisfies the relationship shown in 6.0 ≦ y ≦ 7.5)
Is used. Typical oxide superconductors are YBa ₂ Cu ₃ O _y , YbBa ₂ Cu ₃ O _y and the like.
[0016]
As a material of the insulating oxide thin film, the following general formula AESnO _y or AETiO _y
(AE is at least one metal selected from the group consisting of alkaline earths)
A perovskite oxide represented by the following formula is used. A typical insulating oxide is CaSnO ₃ or the like.
[0017]
When processing a laminated film of the lower electrode layer formed of the oxide superconducting thin film and the insulating oxide thin film by ion milling, a rare gas such as Ar is used. This process forms an amorphous layer (used as a barrier layer for bonding) containing rare earth elements, which are constituent elements of the oxide superconducting thin film, on the processed end face of the lower electrode layer, and at the same time on the surface of the insulating oxide thin film. An amorphous oxide containing the constituent elements of the insulating oxide thin film is formed. Further, when the surface of the substrate is processed, an amorphous oxide containing the constituent components of the substrate is formed on the substrate surface.
[0018]
In the method according to the embodiment of the present invention, a surface treatment is performed on a stacked body of a lower electrode layer and an insulating oxide thin film processed by ion milling using an active species of a halogen-based gas or a reducing gas.
[0019]
Examples of the halogen-based gas include CF ₄ , F ₂ , CH _x F _y , SF ₆ , NF ₃ , BF ₃ , CBrF ₃ , XeF ₂ , SiF ₄ , C _x F _y (F / C <4), and CCl _x F. _{y, C 2 Cl x F y} , CH x Cl y, SiCl 4, PCl 3, BCl 3, Cl 2, although HCl or the like is used, without limitation. Since halogen has a high electronegativity, a Coulomb force acts during the reaction, and the reactant can be peeled off from the thin film surface. For this reason, an amorphous oxide can be removed efficiently. The oxide superconducting thin film and the amorphous film on the processed end face are hardly affected by the halogen-based gas.
[0020]
As the reducing _{gas, B x C 2 H x +} 2, B x H x + 4, B x H x + 6, C x H 2x-2, C x H 2x, C x H 2x + 2, N x H _{x + 2, Si x H 2x} + 2, PH 3, AsH 3, Ge x H 2x + 2, H 2 S, HCN, CsH, but HI, NHR1R2 (R1, R2 = C x H y) and the like can be used However, it is not limited to these. Since these reducing gases generate hydrogen efficiently, they show high reduction efficiency. Note that oxygen released by the use of the reducing gas can be recovered by long-term annealing in the final process.
[0021]
In order to activate reactive gas (halogen-based gas or reducing gas) to generate active species, plasma with high frequency of 2.45 GHz, inductively coupled plasma using 13.56 MHz, helicon plasma, normal RF, etc. The plasma energy can be used. Further, the reactive gas may be activated using photon energy, thermal energy, or the like. The temperature of the sample can be set in the range of room temperature to 800 ° C.
[0022]
Annealing in an oxygen atmosphere for forming the barrier layer by crystallizing the amorphous layer on the processed end face of the lower electrode layer is performed in the range of 600 to 900 ° C.
[0023]
【Example】
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a cross-sectional view showing a schematic configuration of an ECR type ion etching apparatus used in the following examples. This apparatus has an activation chamber 11 and a sample chamber 12. The activation chamber 11 contains an ECR plasma source 13 for activating the reactive gas. In the sample chamber 12, a sample table 14 on which a sample (object to be processed) 20 is fixed and a heater 15 for heating the sample 20 are housed. The sample 20 can be heated from room temperature to 900 ° C. by the heater 15. A gas introduction port 16 is installed in the activation chamber 11 and a gas exhaust port 17 is installed in the sample chamber 12, respectively, and the inside of the sample chamber 12 can be evacuated to the 10 ⁻⁸ Torr level. For example, by adjusting the degree of vacuum of the activation chamber 11 to 10 ⁻³ Torr and the degree of vacuum of the sample chamber 12 to 10 ⁻⁴ Torr, the activated reactive gas is relatively discharged from the activation chamber 11 having a relatively high pressure. The sample can be supplied to the low-pressure sample chamber 12.
[0024]
Example 1
With reference to FIGS. 2A to 2D, an example of a method of manufacturing a superconducting element having a lamp edge type junction will be described.
First, a YBa ₂ Cu ₃ O _y lower electrode layer 22 having a thickness of 200 nm and a CaSnO ₃ insulating layer 23 having a thickness of 500 nm are stacked on the SrTiO ₃ substrate 21. A pattern of a photoresist 24 is formed on the CaSnO ₃ insulating layer 23. Using the photoresist 24 as a mask, Ar ions are incident obliquely and ion milling is performed to process the CaSnO ₃ insulating layer 23 (FIG. 2A).
[0025]
Next, after removing the photoresist 24, Ar ions are vertically incident to perform ion milling, and the CaSnO ₃ insulating layer 23 and the YBa ₂ Cu ₃ O _y lower electrode layer 22 are processed. By this step, an amorphous layer 25 containing a rare earth element which is a constituent element of the oxide superconducting thin film is mainly formed on the processed end face of the lower electrode layer 22. Further, a CaO-based or SrO-based amorphous oxide 26 is formed on the surfaces of the CaSnO ₃ insulating layer 23 and the substrate 21 (FIG. 2B).
[0026]
This sample is placed on the sample stage 14 of the apparatus shown in FIG. When CF ₄ is introduced from the gas inlet 16 and a high frequency of 2.45 GHz is applied to the ECR plasma source 13, plasma is generated in the activation chamber 11 and CF ₄ is activated. The generated CF ₄ active species are introduced into the sample chamber 12 and reactive etching is performed to remove the amorphous oxide 26 (FIG. 2C).
[0027]
Next, the surface-treated sample is annealed at 680 ° C. in an oxygen atmosphere, and the amorphous layer 25 formed on the surface of the lower electrode layer 22 is crystallized to form a barrier layer 25 ′. Finally, the YbBa ₂ Cu ₃ O _y upper electrode layer 27 is stacked and then patterned (FIG. 2D).
[0028]
In the above method, the substrate temperature was variously changed when the upper electrode layer 27 was formed, and the a-axis mixing rate of the upper electrode layer 27 was examined. As a result, a c-axis alignment film having an a-axis mixing ratio of 1% or less was obtained in a relatively low temperature region (about 650 ° C.) in which bonding characteristics suitable for circuit operation were obtained. This was the same result as when the laminated body of the lower electrode layer 22 and the insulating oxide layer 23 was not subjected to Ar ion milling.
[0029]
In addition, the electrical characteristics of 100 junctions manufactured at a substrate temperature of 650 ° C. were examined at 4.2K. FIG. 3 shows typical electrical characteristics. As shown in FIG. 3, Ic = 0.9 mA, the modulation rate was 90% or more, and the variation of the Ic value was 10%, indicating good bonding characteristics. Tc and Jc were 80K for the lower electrode layer, 1 × 10 ⁷ A / cm ² , 85K for the upper electrode layer, and 2 × 10 ⁷ A / cm ² , and both showed good values.
[0030]
Next, the surface of the CaSnO ₃ insulating layer was observed by XPS by changing some of the process conditions of FIGS. 2B and 2C. Specifically, when film formation (as-depo) is performed and Ar ions are vertically incident at 400 W after film formation, and ion milling is performed at 800 W after film formation and Ar ions are vertically incident. and normal incidence the Ar ions in 800W and ion milling after film, further the case of surface treatment with CF4, was examined Ca / Sn ratio of CaSnO ₃ insulating layer surface. The result is shown in FIG.
[0031]
The following can be seen from FIG. When the film is formed (as-depo), the Ca / Sn ratio is 1, and CaSnO ₃ is observed. However, it can be seen that the Ca / Sn ratio is greater than 1 (Ca rich) and CaO is generated only by performing Ar ion milling. In contrast, when the surface treatment with CF ₄ is performed after Ar ion milling, the Ca / Sn ratio returns to 1, and CaO is removed and CaSnO ₃ is observed again.
[0032]
(Example 2)
5A to 5D show a method of manufacturing a superconducting element having a lamp edge type junction in which a ground plane and an insulating layer are formed under the lower electrode layer.
First, a YBa ₂ Cu ₃ O _y ground plane 31 and a CaSnO ₃ insulating layer 32 are stacked on the SrTiO ₃ substrate 21. Thereafter, the same process as in Example 1 is performed. That is, the lower electrode layer 22, the insulating layer 23, and the photoresist 24 are formed, and the insulating layer 23 is processed by Ar ion milling (FIG. 5A). After the photoresist 24 is removed, Ar ion milling is performed to process the insulating layer 23 and the lower electrode layer 22. At this time, an amorphous layer 25 is formed on the processed end face of the lower electrode layer 22, and an amorphous oxide 26 is formed on the surface of the insulating layer (CaSnO ₃ ) (FIG. 5B). Reactive etching with activated CF ₄ species is performed to remove the amorphous oxide 26 on the surface of the insulating layer 23 (FIG. 5C). Annealing treatment is performed in an oxygen atmosphere, the amorphous layer 25 is crystallized to form a barrier layer 25 ′, an upper electrode layer 27 is laminated, and then patterned (FIG. 5D). In this case, the same effect as in the first embodiment can be obtained.
[0033]
Example 3
6A to 6D show a method for manufacturing a superconducting element having a laminated junction.
First, the lower electrode layer 22, the insulating layer 23, and the photoresist 24 are formed on the SrTiO ₃ substrate 21, and the insulating layer 23 in the region surrounded by the photoresist 24 is processed by Ar ion milling (FIG. 6A). ). After removing the photoresist 24, Ar ion milling is performed to process the insulating layer 23 until the lower electrode layer 22 is exposed. At this time, an amorphous layer 25 is formed on the exposed surface of the lower electrode layer 22, and an amorphous oxide 26 is formed on the surface of the insulating layer 23 (FIG. 6B). Reactive etching with activated CF ₄ species is performed to remove the amorphous oxide 26 on the surface of the insulating layer 23 (FIG. 6C). Annealing treatment is performed in an oxygen atmosphere, the amorphous layer 25 is crystallized to form a barrier layer 25 ′, an upper electrode layer 27 is laminated, and then patterned to form a laminated junction (FIG. 6D). . In this case, the same effect as in the first embodiment can be obtained.
[0034]
【The invention's effect】
As described above in detail, according to the present invention, it is processed by ion milling using a rare gas without affecting the amorphous layer mainly composed of rare earth elements which becomes the barrier layer of the interface-modified bonding. Amorphous oxide generated on the surface of the insulating oxide thin film can be selectively removed, and a superconducting element having good characteristics can be manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a schematic configuration of an ECR type ion etching apparatus.
2 is a cross-sectional view showing a method for manufacturing a superconducting element having a lamp edge type junction in Example 1. FIG.
3 is a graph showing electrical characteristics of the superconducting element manufactured in Example 1. FIG.
FIG. 4 is a diagram showing the process condition dependency of the Ca / Sn composition ratio on the surface of the CaSnO ₃ insulating layer.
5 is a cross-sectional view showing a method of manufacturing a superconducting element having a lamp edge type junction in Example 2. FIG.
6 is a cross-sectional view showing a method for manufacturing a superconducting element having a laminated junction in Example 3. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Activation chamber, 12 ... Sample chamber, 13 ... ECR plasma source, 14 ... Sample stand,
15 ... heater, 16 ... gas inlet, 17 ... gas exhaust, 20 ... sample,
21 ... SrTiO ₃ substrate, 22 ... Lower electrode layer, 23 ... Insulating layer,
24 ... Photoresist, 25 ... Amorphous layer, 25 '... Barrier layer,
26 ... amorphous oxide, 27 ... upper electrode layer,
31 ... Ground plane, 32 ... Insulating layer.

Claims (2)

A step of laminating a lower electrode layer formed of an oxide superconducting thin film and an insulating oxide thin film;
Processing the laminated film of the lower electrode layer and the insulating oxide thin film by ion milling using a rare gas, and forming an amorphous layer on the processed end face of the lower electrode layer;
Exposing the processed laminated film to an atmosphere of an active species of a halogen-based gas or a reducing gas, and cleaning the surface of the insulating oxide thin film;
Heating the laminated film in an oxygen atmosphere to crystallize the amorphous layer on the processed end face of the lower electrode layer to form a barrier layer;
And a step of laminating an upper electrode layer formed of an oxide superconducting thin film on the laminated film. 2. The method of manufacturing a superconducting element according to claim 1, wherein each of the steps is carried out after a ground plane formed of an oxide superconducting thin film and an insulating oxide thin film are laminated on a substrate.

Images