JP2005057249A - Circuit board and manufacturing method thereof, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board capable of preventing multilayering of thin films and suppressing an increase of the number of manufacturing processes of the circuit board and a cost increase thereof, and to provide the manufacturing method thereof and an electronic device. <P>SOLUTION: Gate wiring 13 is formed with a silver alloy having silver as a main material and containing indium in a TFT array substrate 11. The content of indium against silver is adjusted so that plasma resistance of the terminal portions of the gate wiring 13 is higher than the plasma resistance of the other portions. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a circuit board in which wiring is formed on an insulating substrate, a manufacturing method thereof, and an electronic device such as a display device and an image input device using the circuit board.

  A liquid crystal display device, which is one of electronic devices, includes a TFT array substrate having a number of TFTs (thin film transistors), wirings, and the like as a circuit substrate.

  Conventionally, a TFT array substrate has been manufactured by a series of processes as shown in Non-Patent Document 1 (Flat Panel Display 1999 (page 129 of Nikkei Microdevices, Nikkei BP)). About 5 times of photolithography were required.

  In such a conventional TFT array substrate manufacturing method using photolithography, many vacuum apparatuses such as a film forming apparatus used in each film forming process and a processing apparatus such as a dry etching apparatus are used. Therefore, enormous equipment costs are required to manufacture a TFT array substrate that has been demanded for further enlargement in recent years.

  In order to solve such a problem, a technique for forming a wiring or the like by an inkjet method has been proposed. In this technique, for example, as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 11-204529), an affinity region and a non-affinity region for a wiring forming material are formed on a substrate on which a wiring is formed, and the affinity region is formed. Wiring is formed by dropping droplets of wiring material on the ink jet method.

  Similarly, in Patent Document 2 (Japanese Patent Application Laid-Open No. 2000-353594), in the wiring formation technique using the inkjet method, in order to suppress the protrusion of the wiring material from the wiring formation region, banks are provided on both sides of the wiring formation region. It is disclosed that the upper part of the bank is made non-lyophilic and the wiring formation region is made lyophilic.

  As shown in Non-Patent Document 2 (Nikkei Electronics, June 17, 2002 (Nikkei BP Co., Ltd.), 2002) as a material for forming wiring by the above-described inkjet method, silver or gold nanomaterials are used. A fluid wiring material in which particles are dispersed in a solvent is used. These are dropped on a predetermined location on the substrate and then subjected to a treatment such as firing, and the contained metal appears and becomes a wiring or the like. Examples of metals that can be processed into a fluid wiring material include palladium, platinum, and the like in addition to silver and gold. However, considering the price of raw materials, only silver is realistic in this. Regarding wiring formation using silver, Japanese Patent Application Laid-Open No. 2003-80694 discloses a method of forming wiring without using a bank.

For this reason, it is considered to use silver that can be used in the ink jet method as a material constituting the wiring on the TFT array substrate.
Japanese Patent Laid-Open No. 11-204529 (published July 30, 1999) JP 2000-353594 A (published on December 19, 2000) JP 2003-80694 A (published March 19, 2003) Flat Panel Display 1999 (Nikkei Microdevices, Nikkei Business Publications, Inc.), page 129, 1998 Nikkei Electronics June 17, 2002 issue (Nikkei BP), 2002

  By the way, when forming a thin film laminated substrate, for example, in the case of a TFT array substrate used passively for liquid crystal, the performance required for wiring is low resistance, smooth surface property, process gas such as etching, and this. Therefore, it is required to have resistance in a plasma using a material, adhesion to a base material, contact property with a different material, that is, low contact resistance, no unnecessary diffusion, and corrosion resistance.

  However, it is difficult to cover all of these performances with one kind of material, and in sputter, vapor deposition, and CVD film formation, a single material or alloy material having these performances is formed as much as possible, and photolithography is performed. After patterning in the process, another material is separately formed thereon as appropriate according to the required performance.

  In addition, in the wiring forming method using the ink jet method that simplifies the wiring forming process, the silver material as the material used in the ink jet is used as a fine particle colloidal material in which fine particles are dispersed in a dispersion medium. Although it is a material attracting attention as an upper wiring material, its range of use is limited due to its properties.

  For example, when silver is deposited on a glass substrate by vapor deposition, sputtering, etc., depending on the temperature, the grain growth becomes remarkable from firing at about 250 ° C., and therefore the smooth surface becomes rough and the surface becomes clouded. There is a problem of extremely lacking heat resistance.

  In addition, in order to use silver as a thin film, it is essential to have an adhesive force on glass. However, in the case of silver, which is a coating material, it is not possible to expect an effect on the substrate during film formation. Adhesive strength to weakens, causing problems in processability and stability. Further, when the adhesion force is improved by firing, there arises a problem that the surface smoothness deteriorates due to the grain growth characteristics of silver as described above.

  Furthermore, there is a problem even when the wiring on the TFT array substrate is configured. For example, in the manufacture of a TFT array substrate, dry etching is frequently used for etching an insulating film or the like. When exposed to plasma in an atmosphere of this dry etching gas, film deterioration and peeling occur due to oxidation and the like. For this reason, there is a problem in using silver as a wiring material as it is.

  Therefore, when silver is used as a wiring material, in order to solve the various problems as described above, a treatment for improving the adhesion force on the insulating substrate is performed, or the surface smoothness is deteriorated by heat. In order to prevent film deterioration and peeling due to the etching gas, it is necessary to form a thin film serving as a protective film on the silver wiring. That is, there arises a problem that the thin film is multilayered on the insulating substrate. As a result, the number of circuit board manufacturing steps increases and the cost also increases.

  The present invention has been made in view of the above-mentioned problems, and its object is to prevent a thin film from being multilayered, and to suppress an increase in the number of manufacturing steps of a circuit board and an increase in cost, and the circuit board. A manufacturing method and an electronic device are provided.

  In order to solve the above problems, the inventors of the present application have made extensive studies, and as a result, by adjusting the necessary characteristics for each part of the wiring on the same wiring, it is possible to reduce the number of circuit board manufacturing processes and cost. I found what I could do.

  That is, the circuit board of the present invention is characterized in that the characteristics of at least two portions on the same wiring are different in a circuit board having wiring formed on the board.

  Here, the same wiring is a wiring that is continuous in shape, and a circuit on a substrate is a unit of a plurality of such wirings, and a circuit board is formed.

  In order to make the characteristics of a certain part on the same wiring different from the characteristics of other parts, for example, it can be realized by making the composition ratio of the material of each part different. Moreover, it is realizable also by making the constituent material of each site | part differ, respectively.

  For example, in a TFT array substrate used in a liquid crystal display device as a circuit substrate, necessary characteristics are different between a wiring portion and a terminal portion on the same wiring. The wiring portion needs to have low resistance, but since a protective film is formed, plasma resistance is not so necessary. On the other hand, the terminal portion needs to have a low resistance, but is not protected by a protective film for connection with a driver or the like, so process resistance (particularly plasma resistance) is required.

  Therefore, change the composition ratio of the wiring material or change the composition material of the wiring so that the wiring of the wiring part has characteristics that emphasize low resistance, and the wiring of the terminal part has characteristics that emphasize plasma resistance. Just do it.

  The same wiring is preferably formed of a single layer.

  In this case, it is possible to reduce the thickness of the circuit board and reduce the level difference with other wirings formed on the wiring, so that disconnection of the other wiring due to the level difference can be prevented, and as a result, the circuit The yield of the substrate can be improved.

  The same wiring may be formed in multiple layers.

  For example, when the adhesion between the wiring material and the substrate is poor, a layer having good adhesion to the substrate is formed between the substrate and the wiring material, and the wiring material is applied thereon to form two layers. It is good also as wiring.

  The wiring is preferably formed of a fluid material containing a conductor material.

  Further, since wiring can be easily formed without stacking other films, it is possible to easily reduce the number of manufacturing steps and the manufacturing cost.

  Each of the liquid materials including the conductor material used in the parts having different characteristics may include the same type of solvent or organic matter.

  In this case, even if the wiring materials have different characteristics, if the solvent is the same, the liquids are well-adapted, hardly aggregate, and difficult to separate, so that the wiring can be formed efficiently.

  The wiring may be made of a metal whose main material is silver, aluminum, or copper.

  In this case, since the wiring is formed of a metal having a relatively low resistance value and mainly made of silver, aluminum, or copper, the resistance of the entire wiring can be reduced. Here, surface smoothness, plasma resistance, and adhesion can be adjusted by components other than silver, aluminum, and copper, which are the main materials of wiring.

  Such components include at least aluminum, indium, tin, bismuth, gallium, lead, copper, gold, silver, cobalt, nickel, palladium, platinum, rhodium, vanadium, titanium, zirconium, niobium, tantalum, tungsten, hafnium, One or more metals selected from osmium and iridium are preferred.

  In addition, the inventors of the present application, when a wiring or electrode is formed on an insulating substrate using an alloy in which silver is a main component and indium is added as a material as a wiring material, the insulating substrate is made of silver alone. It has been found that the adhesion of the wiring and the electrode to the insulating substrate is improved and the heat resistance and plasma resistance of the wiring and the electrode are improved as compared with the case where the wiring or the electrode is formed thereon. Moreover, it discovered that the same effect was acquired even if it was an alloy which added not only said indium but tin, zinc, lead, bismuth, and gallium to silver.

  Therefore, it is preferable to use such a silver alloy material as the wiring material.

  In particular, it is preferable to use a silver indium alloy as a wiring material.

  In this case, the silver indium alloy material can cover a wide range in terms of surface smoothness, adhesion, plasma resistance, etc., by adjusting the content of indium with respect to silver.

  The indium content (indium / silver (wt%)) is preferably 0.5 wt% to 28 wt%. If the indium content is lowered, the plasma resistance is lowered, but the resistance can be reduced. However, if the indium content is less than 0.5% by weight, there arises a problem that the plasma resistance is lowered. Further, if the indium content is increased, the resistance value is increased, but the plasma resistance is increased. However, if the indium content is more than 28% by weight, there arises a problem that solid solution formation with silver cannot be performed. In this way, by simply adjusting the content of indium with respect to silver, it is possible to easily change the characteristics even if the required characteristics are different, such as the wiring part and terminal part on the wiring. It becomes.

  Further, if the wiring material is applied by the ink jet method, wiring materials having different indium contents can be easily used properly, so that wiring having different characteristics can be easily formed depending on the part.

  Further, if the circuit substrate having the above configuration is applied to a TFT array substrate in which plasma resistance is required at the time of channel portion processing and terminal portion processing, low resistance is required for the wiring portion, and surface smoothness is required for the gate electrode portion, It is possible to improve the yield of the TFT array substrate and reduce the manufacturing cost.

  In addition, if the circuit substrate of the present invention is applied to the TFT array substrate as described above, there is a merit such as an improvement in yield as described above. Therefore, display devices such as other electronic devices, liquid crystal display devices, plasma display devices, etc. Also, it can be suitably used.

  As described above, the circuit board of the present invention has a configuration in which the characteristics of at least two portions on the same wiring are different in the circuit board having the wiring formed on the board. There is an effect that necessary multi-layering can be prevented, and an increase in the number of circuit board manufacturing steps and an increase in cost can be suppressed.

  The embodiment of the present invention will be described as follows.

  In this embodiment, first, a silver alloy material used as a wiring material for wiring (including electrodes) of a TFT array substrate, which is a kind of circuit board, will be described, and subsequently, wiring formed by this silver alloy material will be described. A TFT array substrate and a liquid crystal display device will be described.

  The silver alloy material used in the present invention is a material constituting a wiring or an electrode formed on an insulating substrate such as a glass substrate, and is mainly composed of silver, at least tin, zinc, lead, bismuth, indium, It contains one or more elements selected from gallium.

  If the silver alloy material having the above structure is used, a wiring or an electrode having low electrical resistance and high process resistance such as heat resistance, adhesion to a glass substrate, and plasma resistance can be formed.

  Hereinafter, the above-described advantages of the silver alloy material used in the present invention will be demonstrated with reference to Examples 1 to 9 and Comparative Examples 1 and 2.

  The silver alloy material was prepared by the following procedure, and formed on an insulating substrate to evaluate process resistance.

  Preparation of the silver alloy material and film formation of the silver alloy material on the insulating substrate were performed by an evaporation method using an electron beam evaporation machine (Japan Vacuum Technology Co., Ltd., high vacuum evaporation apparatus EBX-10D).

  First, silver, tin, zinc, lead, bismuth, indium, gallium lump or granular raw materials having a purity of 99.9% or more were mixed at a predetermined weight ratio as an evaporation source.

Next, the mixed raw materials were put into a crucible made of molybdenum, and melted in a vacuum better than 1 × 10 ⁻⁵ Torr to be alloyed.

  Finally, after confirming complete dissolution, a film was formed on an alkali-free glass substrate. In addition, the glass substrate temperature at the time of film-forming was set to 100 degreeC. The alloy films formed on the glass substrate all had a thickness of about 0.2 μm.

  In the present embodiment, such a method is used for forming an alloy and forming a film, but the present invention is not necessarily limited thereto. A sputtering method using a solid solution or a sintered body or other target may be used, or a flowable wiring material coating method containing a metal element at an appropriate concentration, or any other method may be used.

  The composition of the silver alloy film thus prepared was confirmed using an Auger electron spectrometer (Parking Elmer, SAM670). The composition distribution in the film thickness direction was uniform and uniform, but the overall composition ratio of the prepared silver alloy film was somewhat different from the mixing ratio of the raw materials. However, the deviation is such that it does not affect the object, means, effect, etc. of the present invention at all. The prepared silver alloy film is merely a representative example of the present invention.

  The alloy film made of silver and indium was quantitatively analyzed by ICP emission analysis in order to know a more accurate composition. The method is as follows.

  First, as a sample, a silver alloy film formed on an alkali-free glass substrate was peeled off with a metal spoon. Before peeling, the thickness of the silver alloy film on the glass substrate was about 0.2 μm, and the amount of the obtained sample was about 10 mg for each example. Subsequently, a solution obtained by dissolving this sample in 50 mL of 3N nitric acid was used as a measurement solution for ICP emission analysis. As a measuring device, SPS-1700HVR manufactured by SII Nano Technology was used, and argon was used as a plasma gas.

  In the present embodiment, adhesion, heat resistance, electrical resistivity, and plasma resistance were evaluated as process resistance of the silver alloy film. These items are the most basic items for wiring on the circuit board. Each item is described in detail below.

  The adhesion was examined by directly forming a film on an alkali-free glass substrate.

  When it is intended to be used for a circuit board as in the present invention, the adhesion to the glass substrate is a useful index.

  Here, the adhesion test was performed after firing at 200 ° C. for 1 hour in a nitrogen atmosphere. After firing, a method was used in which an adhesive tape was applied to the cut film surface, and the adhesive tape was peeled off so as to peel off the film surface. Judgment was good only when a part of the film surface was peeled off, and only when there was no peeling at all.

  Evaluation of heat resistance was performed by observing the film surface after baking at 300 ° C. for 1 hour in a nitrogen atmosphere with an electron microscope (Hitachi, S-4100). Judgment is good when there is no unevenness on the film surface, it is judged as good when a protrusion with a height less than the film thickness is partially formed on the film surface, and other cases are judged as defective. .

  The electrical resistivity was evaluated on the substrate after baking at 200 ° C. for 1 hour in a nitrogen atmosphere. The electrical resistivity was obtained from the sheet resistance value obtained by the four-probe method with a measuring instrument (Mitsubishi Chemical Corporation, Loresta-GP) and the film thickness measured separately.

  Evaluation of plasma resistance was performed using a dry etching apparatus (RIE, reactive ion etching method). Specifically, after carrying the substrate into the process chamber, discharge was performed while introducing various etching gases.

The evaluation conditions were three conditions for introducing chlorine (Cl ² ) gas, carbon tetrafluoride (CF ⁴ ) gas and oxygen (O ² ) gas mixed gas, and oxygen (O ² ) gas.

Hereinafter, these three conditions are referred to as Cl ² condition, CF ⁴ + O ² condition, and O ² condition, respectively. The discharge times were 180 seconds, 60 seconds, and 60 seconds, respectively. It should be noted that this discharge time is intentionally set to a strict condition in consideration of the five-mask process described later.

  In order to determine the plasma resistance, the surface resistance of the film was examined. The sheet resistance value was measured in the same manner as the electrical resistivity. As judgment criteria, the case where the sheet resistance value was 2.5 times or less, more than 2.5 times and 7 times or less than that before the treatment was judged as good and slightly good, and the others were judged as bad.

  These evaluation items are examples set only to show the properties of the silver alloy material of the present invention. In order to make the difference clear, each condition is intentionally set to be stricter than the assumed use condition. In carrying out the present invention, it is not always necessary to evaluate these items, and details of observation means, determination criteria, conditions, and the like are merely examples. The scope of application of the present invention is not limited by these evaluation items and individual conditions.

  Examples of evaluation results for the silver alloy material of the present invention are shown in Tables 1 and 2.

  In each table, Comparative Example 1 is an example of a metal film made of simple silver, and Comparative Example 2 is an example of a silver alloy film in which 2% by weight of aluminum is mixed in an evaporation source. In Examples 1 to 9, 10% by weight of tin, 10% by weight of zinc, 1% by weight of indium, 3% by weight of indium, 5% by weight of indium and 10% by weight of silver as an evaporation source Indium, 0.1% by weight of indium, 0.3% by weight of indium, and 20% by weight of indium are examples of silver alloy films, which are examples of the present invention. Each raw material should contain a very small amount of impurities, but since the amount does not affect the results, the description of the impurities is omitted.

  First, ICP emission analysis values, adhesion strength and heat resistance evaluation results are shown in Table 1 below.

  As a result of the quantitative analysis by the ICP emission analysis method described above, in each of Examples 3 to 8, the content of indium with respect to silver is 0.5 wt%, 1.6 wt%, and 3.4 wt%. %, 9.3 wt%, 0.05 wt%, and 0.2 wt%.

  As shown in Table 1, the film made of silver alone as Comparative Example 1 has poor adhesion and heat resistance. Silver also has a remarkable lack of heat resistance, such as clear surface turbidity, even in a baking test at 250 ° C. for 1 hour, which is gentler than this. Here are some of the reasons why it has traditionally been difficult to use silver as wiring.

  On the other hand, as shown in Examples 1 to 9 of the present invention, the silver alloy film in which tin, zinc, and indium are added to silver shows an improvement in adhesion to the glass substrate as a whole. Regarding the addition of indium, as in Example 3 and the like, when the content of indium with respect to silver is about 0.5% by weight or more, a clear improvement in adhesion is observed.

  Regarding heat resistance, Examples 1 to 9 of the present invention show an overall improvement in heat resistance. In particular, in Examples 7 and 8, although the indium content with respect to silver is an analytical value of 0.05% by weight and 0.2% by weight, respectively, the heat resistance is improved. . From this, it can be said that the addition of indium is very effective in improving heat resistance.

  The reason why the adhesion is improved is that the elements such as tin, zinc, and indium constituting the silver alloy of the present invention are diffused in a very small amount to the glass substrate and the interface disappears, so that the adhesion energy is close to the bulk cohesive energy. It is thought that it became value. This idea is supported by the fact that, in the silver alloy film of the present invention, the adhesive strength was greater in the state of firing at 200 ° C. for 1 hour than in the state of being deposited at a substrate temperature of 100 ° C. That is, the present invention is based on the principle that adhesion is obtained by diffusion of tin, zinc, indium and the like in the silver alloy film.

  Note that the scope of the present invention is not limited to obtaining adhesion by a method of baking after film formation as in this embodiment, and the adhesion can be obtained by sufficiently raising the substrate temperature during film formation. Including cases.

  On the other hand, the reason why the heat resistance has improved is that the silver crystal contained tin, zinc, and indium in the film, which caused changes in the crystal lattice constant and crystal grain size, and the movement of silver atoms in the film. It is thought that the grain growth was suppressed and it became difficult to cause grain growth.

  Here, in the silver alloy material of this example, it is also important that the composition of the obtained film is set so as to enter a region where a mixed solid element dissolves in a silver crystal to form a primary solid solution (solid solution). . If it is set in the region where such a primary solid solution is made, even if the film is baked, an intermediate solid solution having a crystal structure different from that of silver crystals and intermetallic compounds are difficult to precipitate, and a new crystal on the film surface can be obtained. Grain growth is difficult to occur. For this reason, the surface property does not change even when baked, resulting in an increase in heat resistance.

  The composition range for producing such a primary solid solution depends on the environmental temperature, but in the case of tin, zinc and indium, the respective contents are less than 11 to 14% by weight and 25 to 39% by weight with respect to silver. Less than 27 to 28% by weight.

  Thus, from the evaluation results of Table 1, the silver alloy material of the present invention has improved heat resistance compared to silver, and particularly in the case of containing 0.5% by weight or more of indium in the case of an alloy with indium. Adhesion was improved.

  Further, the silver alloy material may be an alloy of gallium, which is the same group as indium in the periodic table of elements, lead of the same group as tin, and bismuth which is similar in nature to lead, and also has excellent adhesion and heat resistance. Showing gender.

  Next, the evaluation results obtained by examining the electrical resistivity and the plasma resistance are shown in Table 2 below.

  From the evaluation results of Table 2, it was found that the electrical resistivity was approximately 7 μΩcm or less, except for Examples 6 and 9, which was equivalent to or lower than that of conventional aluminum alloys. Thereby, it turns out that this silver alloy material is suitable as materials, such as wiring with low electrical resistance. If the electrical resistivity is approximately 10 μΩcm or less, it can be practically used as a material for the circuit board for the surface device.

  Particularly in Examples 7, 8, and 3, the content ratio of indium with respect to silver is 0.5% by weight or less, but the respective electric resistances are very low values of 2.2 μΩcm, 2.3 μΩcm, and 2.7 μΩcm. is there. Since aluminum has an electric resistivity of 2.7 μΩcm even in a bulk state, it does not become 2.7 μΩcm or less in a thin film, and these are low electric resistances that cannot be achieved with aluminum.

  Therefore, among the silver alloy materials of the present invention, particularly when the content ratio of indium with respect to silver is 0.5% by weight or less, it is possible to form a low electrical resistance wiring that cannot be achieved by a conventional aluminum wiring. When it is particularly desired to reduce the electrical resistance of the wiring, for example, in a liquid crystal display device used for a liquid crystal TV or the like, a circuit board may be formed using the silver alloy material of the present invention.

  However, since the indium content is low, the plasma resistance is not sufficient, and it is generally necessary to stack another metal film. The adhesion to the substrate is not sufficient because the content of indium is low, so that a base treatment or the like may be necessary.

  The plasma resistance is improved in Examples 1 to 6 and 9 of the present invention. In particular, in the case of indium, an improvement in plasma resistance was observed when it contained approximately 0.5% by weight or more. Strictly speaking, however, some alloy materials may be defective depending on the plasma conditions.

For silver single Comparative Example 1, but if made of silver and aluminum of Comparative Example 2 are all bad, Example somewhat good 1, with O ² conditions, good in Cl ² conditions in Example 2, O ² Slightly better under conditions. Particularly useful as the silver alloy is the case of Examples 3 to 6, and 9 characterized by containing indium. Under Cl ² conditions, the effect of improving the plasma resistance is great, such as being all good. Example 5 with a relatively high indium content is very useful because it has both low process resistance and low electrical resistance because it has a low electrical resistivity of 6.1 μΩcm, despite being good under all plasma resistance conditions. I found out. On the other hand, in Examples 6 and 9, the electrical resistivity was relatively high in the table, but the plasma resistance was further improved as compared with Example 5.

  Thus, the plasma resistance is improved because the vapor pressure of a compound of tin, zinc, indium, etc. in the silver alloy and chlorine, fluorine, oxygen, etc., supplied from the gas introduced into the chamber is silver. This is probably because these compounds served as a protective layer that delayed the erosion of the film surface.

  On the other hand, in the case of containing indium at a ratio of 0.5 wt% or less with respect to silver as in Examples 7 and 8, all the plasma resistance was poor.

  As described above, the present silver alloy material is a material having both low electrical resistance and plasma resistance, particularly when indium is contained at a ratio of 0.5 wt% or more. In many cases, plasma resistance is required, and the present invention is a particularly useful material. However, the constituent elements and ratios of tin, zinc, indium, etc. of this silver alloy material do not necessarily have to satisfy all the characteristics in the table, and so as to satisfy the required resistance depending on the case. You can choose.

  Further, the silver alloy material of the present invention has an electrical resistivity of 2.7 μΩcm or less and a very low electrical resistance, particularly when indium is contained at a ratio of 0.5 wt% or less. Therefore, it is suitable for use as a circuit board for a liquid crystal display device used for a liquid crystal TV.

  Further, the present silver alloy material may be an alloy of gallium, which is the same group of indium in the periodic table of elements, lead of the same group as tin, and bismuth which has similar properties to lead, and similarly exhibits excellent properties.

  In summary, the present silver alloy material was found to be a very useful material having process resistance such as adhesion, heat resistance, low electrical resistance, and plasma resistance.

  In addition, these evaluation results are the results on the conditions set in order to show the property of this silver alloy material to the last. In order to clarify the difference between the materials, the individual conditions are set to stricter conditions intentionally than the assumed use conditions. The scope of application of the present invention is not limited by the results shown in Tables 1 and 2.

  This silver alloy material is further made of aluminum, copper, nickel, gold, platinum, palladium, cobalt, rhodium, iridium, ruthenium, osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, neodymium. It may be characterized by containing an element selected from the inside. By adding these elements, the heat resistance, plasma resistance, and adhesion can be further improved, and an optimal alloy material can be obtained.

  When this silver alloy material is used as a constituent material for the wiring of the TFT array substrate, a desirable material is a silver alloy material mainly composed of silver and containing zinc. Thus, when zinc is added to silver, the effects of improving heat resistance, adhesion and plasma resistance are obtained, and the material is suitable for the manufacturing process of the TFT array substrate.

  The silver alloy material may contain other elements intentionally added in addition to silver and zinc. The present invention is based on the fact that adding zinc to silver is effective in improving heat resistance, adhesion and plasma resistance. Therefore, even when other elements other than these are included, a silver alloy material having a configuration capable of obtaining the effect of addition of zinc is included in the scope of the present invention.

  When this silver alloy material is used as a constituent material for the wiring of the TFT array substrate, the most desirable material is a silver alloy material mainly composed of silver and containing indium. Thus, when indium is added to silver, when the ratio of indium to silver is 0.5% by weight or more, the effect of significantly improving plasma resistance can be obtained characteristically. The material is suitable for the process.

  When the above-mentioned silver alloy material is used as a constituent material for the wiring of the TFT array substrate, the most desirable material for low electrical resistance is a material containing indium at a ratio of 0.5% by weight or less with respect to silver. At this time, the electrical resistivity is 2.7 μΩcm or less, and it is possible to form a low electrical resistance wiring that cannot be achieved by a conventional aluminum wiring. When it is particularly desired to reduce the electrical resistance of the wiring, for example, in a liquid crystal display device used for a liquid crystal TV or the like, a circuit board may be formed using the present silver alloy material.

  As a further excellent characteristic of the present silver alloy material, when it contains indium moderately, it has a high visible light reflectance, and maintains this even after firing at 200 ° C. or 300 ° C. This will be described below.

  As a measurement sample, a comparative example shown in Tables 1 and 2, a silver or silver alloy film equivalent to that in Example, and an aluminum film prepared in the same procedure as Comparative Example 3 for reference were used. All of these were formed on an alkali-free glass substrate, the glass substrate temperature at the time of film formation was set to 100 ° C., and the film thickness was set to about 0.2 μm. The visible light reflectance was measured using a spectrophotometer (Hitachi Instrument Service, U-4100) over the entire visible light region from 380 nm to 780 nm.

  The visible light reflectance of the silver alloy film of the present invention will be described with reference to FIGS. In these figures, the horizontal axis represents the wavelength of light applied to the metal film sample, and the vertical axis represents visible light reflectance as the reflectance of the light. Each figure shows the reflectivity after film formation is complete, after baking at 200 ° C. and after baking at 300 ° C., and the change in reflectivity due to baking can also be seen. Note that these firing treatment conditions were such that a clean oven was used for firing for 1 hour in a nitrogen atmosphere.

  The results will be described in detail. First, in the case of Comparative Example 1 (silver) as shown in FIG. 28, the heat resistance is extremely poor as described above. Despite the high reflectivity when the film is formed at 100 ° C., the reflectivity is remarkably lowered after baking at 200 ° C. and 300 ° C. For this reason, it cannot withstand a manufacturing process involving a baking process at about 200 ° C., and it has been difficult to use it as a light reflection film for a reflective liquid crystal display device, for example.

  Next, in Comparative Example 3 (aluminum) as shown in FIG. 29, the light reflectance hardly changes after film formation is completed, after baking at 200 ° C., and after baking at 300 ° C. Aluminum is a material often used in the past as a light reflection film application for a reflective liquid crystal display device.

  FIG. 30 shows an example of a silver alloy film of the present invention, which is an example of a silver alloy film containing 0.05% by weight of indium with respect to silver. In this case, the result of silver is greatly different from that of FIG. Further, compared with the case of the aluminum film in FIG. 29, the reflectivity is high in almost all wavelength regions after baking at 200 ° C., and even after baking at 300 ° C., it is totally reflected except for a very narrow region on the short wavelength side. The rate is high. Thereby, it turns out that the silver alloy film of a present Example has a high visible light reflectance, and is excellent as a light reflection film.

  FIG. 31 also shows an example of a silver alloy film of the present invention, which is an example of a silver alloy film containing 0.2% by weight of indium with respect to silver. In this case, the result is almost the same as in the case of Example 7 in FIG. Even when the baking is performed at 200 ° C. and 300 ° C., the decrease in reflectance is small, and the visible light reflectance is higher than the aluminum film as a whole, so that it is excellent as a light reflecting film.

  FIG. 32 shows a case where indium is contained at a ratio of 0.5% by weight with respect to silver. By baking at 200 ° C., the reflectance is superior to the aluminum film as a whole except for a small part on the short wavelength side. However, after baking at 300 ° C., the reflectance decreases particularly on the short wavelength side, which is not superior to the aluminum film. As in this example, it is preferable to add an appropriate amount of indium to silver, and if the amount of indium is increased excessively, the reflectivity is lowered.

  FIG. 33 shows a case where indium is contained at a ratio of 1.6% by weight with respect to silver. In this case, since the content of indium is increased, the reflectance is lowered as a whole. Therefore, it cannot be said that it is superior to aluminum.

  In summary, in the present invention, when indium is contained at a ratio of 0.5% by weight or less, the reflectivity is slightly changed even after baking at 200.degree. Reflectance is high over almost the entire visible light region. For this reason, it is suitable for a light reflecting film application.

  In the present invention, when indium is contained at a ratio of 0.2% by weight or less, a decrease in reflectance is suppressed even by baking at 300 ° C., and the reflectance is high over the entire visible light region compared to aluminum. . For this reason, it is suitable for a light reflecting film application particularly when heat resistance is required.

  The silver alloy material may contain other elements intentionally added in addition to silver and indium. The present invention is based on the fact that adding indium to silver is most effective in improving plasma resistance. Therefore, even when other elements other than these are included, a silver alloy material having a configuration capable of obtaining the effect of indium addition is included in the scope of the present invention.

  The above-described silver alloy material of the present invention is suitably used as a material constituting wirings on the TFT array substrate. The TFT array substrate is suitably used for a liquid crystal display device which is one of electronic devices.

  The TFT array substrate and the liquid crystal display device according to the present embodiment will be described below with reference to FIGS.

  The liquid crystal display device according to the present embodiment has the pixel shown in FIG. This figure is a plan view showing a schematic configuration of one pixel in the TFT array substrate 11 of the liquid crystal display device. Further, FIG. 2 shows a cross-sectional view taken along line AA in FIG.

  As shown in FIGS. 1 and 2, in the TFT array substrate 11, gate wirings 13 and source wirings 14 are provided in a matrix on a glass substrate (insulating substrate) 12, and a switching element is located near the intersection between them. A TFT 15 is provided. Further, an auxiliary capacitance line 16 is provided between the adjacent gate lines 13.

  As shown in FIG. 2, on the glass substrate 12, the gate electrode 17 branched from the gate wiring 13 and the auxiliary capacity wiring 16 are formed, and the gate insulating layer 18 is formed thereon.

  On the gate electrode 17, an amorphous silicon layer 19, an n + -type silicon layer 20, a source electrode 21, and a drain electrode wiring 22 are formed via the gate insulating layer 18 to form a TFT 15. Here, the source electrode 21 is branched from the source line 14.

  The drain electrode wiring 22 extends from the TFT 15 to the contact hole 23, serves as a drain electrode of the TFT 15, serves to electrically connect the TFT 15 and the pixel electrode 24, and is electrically connected between the auxiliary capacitor wiring 16 through the contact hole 23. A role of forming a capacitor. Further, a protective layer 25 covering the TFT 15, an interlayer insulating layer 26 for flattening, and the like, and a pixel electrode 24 for applying a voltage to the liquid crystal and the like are formed on the upper layer.

  Hereinafter, an area on the glass substrate 12 in which such pixels are provided is referred to as a pixel formation area 61 and is shown in FIG. 4 later.

  Further, the liquid crystal display device according to the present embodiment has a terminal portion 28 shown in FIG. The terminal portion 28 is a connection portion for electrically connecting an external circuit substrate, a driving driver IC, and the like to the TFT array substrate 11. FIG. 2 is a plan view showing a schematic configuration of one terminal portion in the TFT array substrate 11 of the liquid crystal display device. In addition, FIG. 3B shows a cross-sectional view taken along line LL in FIG.

  As illustrated in FIG. 3B, the terminal portion 28 is configured such that the terminal wiring 30, the gate insulating layer 18, and the terminal electrode 29 are arranged from the glass substrate 12 side. The terminal electrode 29 is disposed for the purpose of improving the electrical connection with the external circuit board and the driver IC for driving. The terminal wiring 30 is connected to the gate wiring 13 and the source wiring 14 in the pixel formation region.

  In the present embodiment, the terminal wiring 30 and the terminal electrode 29 are both formed on the glass substrate 12 and both are made of a silver indium alloy that is a silver alloy material having the same composition. . However, the proportion of indium contained in silver differs between the terminal wiring 30 and the terminal electrode 29. Here, the blending ratio is adjusted so that the ratio of indium to silver in the terminal wiring 30 is smaller than the ratio of indium to silver in the terminal electrode 29.

  Hereinafter, the region on the glass substrate 12 where the terminal portion 28 is provided is referred to as a terminal portion forming region 62 and is shown in FIG.

  4 is a plan view of the TFT array substrate 11. The pixel formation region 61 and the terminal portion formation region 62 are arranged on the glass substrate 12 as shown in the figure. Each of the pixel formation region 61 and the terminal portion formation region 62 includes a large number of pixels and terminal portions as shown in FIGS.

  In the present embodiment, the TFT array substrate 11 is manufactured by using a pattern forming apparatus that discharges or drops the material of the layer to be formed, such as an inkjet method. As shown in FIG. 5, the pattern forming apparatus includes a mounting table 32 on which a substrate 31 (corresponding to the glass substrate 12) is mounted, and an X-direction drive that moves the inkjet head 33 and the inkjet head 33 in the X direction. A unit 34 and a Y-direction drive unit 35 that moves in the Y-direction are provided. The inkjet head 33 discharges fluid droplets including, for example, a wiring material onto the substrate 31 on the mounting table 32.

  The pattern forming apparatus includes an ink supply system 36 that supplies a fluid wiring material (ink) to the inkjet head 33, ejection control of the inkjet head 33, and driving of the X-direction drive unit 34 and the Y-direction drive unit 35. A control unit 37 that performs various controls such as control is provided. From the control unit 37, application position information is output to the X and Y direction drive units 34 and 35, and ejection information is output to a head driver (not shown) of the inkjet head 33. As a result, the inkjet head 33 operates in conjunction with the X and Y direction drive units 34 and 35, and a target amount of droplets is supplied to a target position on the substrate 31.

  The inkjet head 33 may be a piezo type using a piezo actuator, a bubble type having a heater in the head, or another type. The amount of ink discharged from the inkjet head 33 can be controlled by controlling the applied voltage. The droplet discharge means may be of any type as long as it can supply droplets, such as a method of simply dropping droplets, instead of the inkjet head 33. Alternatively, a method such as application or immersion in which a predetermined pattern is obtained using a lyophilic region and a non-lyophilic region for a wiring forming material formed in advance on a substrate may be used.

  In the present embodiment, as shown in FIG. 3B, the terminal wiring 30 and the terminal electrode 29 are both formed on the glass substrate 12, and the silver alloy materials each having a different indium content. Therefore, the inkjet head 33 needs to have at least a mechanism capable of discharging a fluid wiring material made of silver alloy materials having different blending ratios.

  For example, as shown in FIGS. 19A and 19B, the first head 33a for discharging the fluid wiring material of the low resistance material for the wiring section along the traveling direction (arrow direction) of the inkjet head 33; And a second head 33b for discharging the fluid wiring material of the plasma resistant material for the terminal portion in order, and switching the first head 33a and the second head 33b as appropriate to discharge the fluid wiring material. It is possible to do so.

  Details of the formation of the terminal portion using the ink jet head 33 configured as described above will be described later.

  Next, a method for manufacturing the TFT array substrate 11 in the liquid crystal display device of the present embodiment will be described.

  In this embodiment, as shown in FIG. 6, the TFT array substrate 11 includes a gate wiring pretreatment process 101, a gate wiring forming process 102, a gate insulating film / semiconductor film forming process 103, and a gate insulating film / semiconductor film processing. From step 104, source / drain wiring pre-processing step 105, source / drain wiring forming step 106, channel portion processing step 107, protective film / interlayer insulating film forming step 108, protective film processing step 109, and pixel electrode forming step 110 Become.

(Gate wiring pretreatment step 101)
In the gate wiring pretreatment step 101, pretreatment for forming the gate wiring 13, the gate electrode 17, the auxiliary capacitance wiring 16, and the like is performed using the pattern forming apparatus described above. This will be described below with reference to FIGS. 7 (a) and 8 (a). FIGS. 7A and 8A are plan views of the glass substrate 12 included in the TFT array substrate 11.

  In the gate wiring pretreatment step 101, the fluidity from the pattern forming apparatus is added to the gate wiring forming region 41, the gate electrode forming region 42, the auxiliary capacitance wiring forming region 43, and the terminal wiring forming region 44 shown in these drawings. A process for properly applying the fluid wiring material is performed by discharging (dropping) the wiring material.

  This processing is roughly as follows.

  First, on the substrate (glass substrate 12), the fluid wiring material is imparted with the property of being easily wetted or repelled. A hydrophilic region (lyophilic region) for forming the gate wiring formation region 41, the gate electrode formation region 42, the auxiliary capacitance wiring formation region 43, and the terminal wiring formation region 44, and a water repellent region (repellent region) as a non-formation region thereof. A liquid repellent treatment (liquid repellent treatment).

  The second is a process of forming a guide for regulating the liquid flow, that is, a guide along the gate wiring formation region 41 and the like.

The former is typically a hydrophilic / water-repellent treatment using a photocatalyst using titanium dioxide. In the latter, a resist material is used and guide formation is performed by photolithography. Further, in order to impart hydrophilicity (liquidity) to the guide or the substrate surface, there are cases in which they are exposed to a plasma atmosphere into which CF ⁴ or O ² gas is introduced. The resist used here is peeled off after the wiring is formed.

Here, the photocatalytic treatment using titanium dioxide was performed as follows. That is, the glass substrate 12 of the TFT array substrate 11 was coated with a mixture of ZONYL FSN (trade name: manufactured by DuPont), which is a fluorine-based nonionic surfactant, in isopropyl alcohol. Further, a titanium dioxide fine particle dispersion and a mixture of ethanol were applied as a photocatalyst layer to a mask such as a gate wiring pattern by spin coating and baked at 150 ° C. Then, using the mask, the glass substrate 12 was exposed to UV light. As the exposure conditions, 365 nm ultraviolet light was used, and irradiation was performed at an intensity of 70 mW / cm ² for 2 minutes.

  Here, the formation of the hydrophilic / hydrophobic (lyophobic) region with titanium dioxide will be described below with reference to FIGS. 9 (a) to 9 (d).

  FIG. 9A shows a first film 2 in which ZONYL FSN (trade name, manufactured by DuPont), which is a fluorine-based nonionic surfactant, is mixed with isopropyl alcohol on a glass substrate 1 by using a spin coating method or the like. It shows a place where is applied.

  FIG. 9B shows that UV exposure is performed with a mask 4 such as a gate wiring pattern provided on the transparent glass substrate 3. The photocatalyst layer 5 is formed on the pattern surface of the mask 4 as the titanium dioxide. A mixture of fine particle dispersion and ethanol is applied and heat treated at 150 ° C.

  After the exposure under the above conditions, as shown in FIGS. 9C and 9D, only the UV-exposed portion 6 was improved in wettability, and a hydrophilic (liquid) pattern was formed.

(Gate wiring formation process 102)
Next, the gate wiring formation step 102 will be described below with reference to FIGS. 7B and 7C and FIGS. 8B and 8C.

  FIGS. 7B and 8C and 8B and 8C are views showing a state where the gate wiring formation step 102 is completed. FIGS. 7B and 8B are plan views of the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. FIGS. 7C and 8C are a cross-sectional view taken along line CC and a cross-sectional view taken along line DD in FIGS. 7B and 8B, respectively.

  Next, a fluid wiring material was applied to a hydrophilic region (lyophilic region) such as the gate wiring formation region 41. For this, a pattern forming apparatus can be used, and the fluid wiring material can be used for wiring such as silver copper alloy, silver palladium alloy, silver gold alloy coated with an organic film. The thing which disperse | distributed the silver indium alloy fine particle shown in ~ 6 in the organic solvent was used. This is because the flatness, plasma resistance, and low resistance can be widely handled by the indium content, and it can be formulated and used according to the place where low resistance is required, the place where plasma resistance is required, and the application. It is. Silver and indium contained in the fluid wiring material at this time were appropriately adjusted so that the ratio of indium to silver was about 10% by weight or less. The wiring width was approximately 50 μm, and the amount of wiring material discharged from the inkjet head 33 was set to 40 pl.

  Alloy fine particles are prepared by mixing an appropriate amount of silver and indium in advance and alloying them by a method such as arc melting or ion beam, and re-depositing them in a rare gas or organic solvent atmosphere as a base material. It may be dispersed.

  Note that the ratio of silver and indium contained in the fluid ink is that dry etching is performed in the subsequent gate insulating film / semiconductor film processing step 104, channel portion processing step 107, and protective film processing step 109. A silver indium alloy was applied to the portion exposed to plasma so that the ratio of indium to silver was about 10% by weight.

  On the other hand, since a temperature of 300 ° C. is applied to the gate wiring in the subsequent gate insulating film / semiconductor film forming step 103, the surface of the gate wiring is also affected by crystal growth due to this temperature. It must not be rough. In addition, since the time for applying a signal to the gate wiring is as short as several tens of microseconds, the response characteristic change due to the signal delay between the TFT near the driver and the TFT at a distant position is as small as possible due to the resistance of the gate wiring. Therefore, the wiring is required to have a low resistance. In consideration of this, a portion covered with a gate insulating layer or a protective film and not directly exposed to plasma was used with a ratio of indium to silver of about 5% by weight. However, the ratio can be appropriately selected according to the manufacturing process and the required performance of the TFT array substrate.

  On the hydrophilic (liquid) treated surface, the fluid wiring material discharged from the ink jet head 33 spreads along the gate wiring forming region 41, so that the discharge interval is appropriately adjusted at intervals of approximately 50 to 500 μm. went. After coating, baking was performed at 300 ° C. for 1 hour to form a gate wiring 13, a gate electrode 17, an auxiliary capacitance wiring 16, and a terminal wiring 30 composed of silver and indium.

  Here, since the gate wiring 13 and the like are made of silver and indium, the gate wiring 13 has sufficient heat resistance with respect to the condition of 300 ° C., and the surface smoothness is not lost. In conventional silver, the surface smoothness is remarkably lost, and therefore leakage with the upper layer occurs, resulting in a failure.

  In addition, the gate wiring 13 and the like are in direct contact with the glass substrate 12, but in this embodiment, the gate wiring 13 and the like are composed of silver and indium. There is no. In conventional silver, since the adhesive force was small, peeling occurred in a later process, which was defective.

  The reason why the baking temperature is set to 300 ° C. is that processing heat of about 300 ° C. is applied in the subsequent gate insulating film / semiconductor film forming step 103. Therefore, the firing temperature is not limited to this temperature.

  Next, the formation of the gate wiring by the ink jet method will be described. FIG. 22 shows a schematic diagram of the gate wiring. The entire gate wiring is shown, and is composed of a gate wiring 13, an auxiliary capacitance wiring 16, and a terminal wiring 30. The gate wiring 13 is connected to a terminal of a driver IC (not shown) at the end of the substrate. Further, the auxiliary capacitance wiring 16 is grouped with the terminal wiring 30 at one end. In addition, each member number of FIG. 22 has shown the location corresponding to FIG. 7 (a)-FIG.7 (c) and FIG. 8 (a)-FIG.8 (c) by the same number.

  As described above, the gate wiring portion is made of a silver alloy material in which the ratio of indium to silver is 5% by weight, and the terminal wiring and the terminal are made of a silver alloy material in which the ratio of indium to silver is 10% by weight. These different types of wiring materials are separately mounted on the droplet supply device of the ink jet apparatus shown in FIG. 5, and ink jet heads 33 are prepared in the same number as the types of fluid wiring materials. Here, two heads (see FIGS. 19A and 19B) were prepared for an indium ratio of 5% by weight and an indium ratio of 10% by weight.

  This situation is shown in FIGS. 19 (a) and 19 (b). In FIG. 19A, a wiring material in which the ratio of indium to silver is 5% by weight is applied to the gate wiring formation region 41 of FIG. 7A by the first head 33a which is a head dedicated to this material. It shows that. Next, as shown in FIG. 19B, a wiring material having an indium ratio of 10% by weight is applied to the terminal wiring forming region 44 of FIG. 8A by the second head 33b which is a head dedicated to this material. Shows you to do.

  At this time, since the two materials are fluid materials, they are mixed on the glass substrate 12 after being discharged, so that they are electrically connected after the subsequent firing step. Further, in the intermingled region, an intermediate state is partially created by both liquids, but for example, all flows into the terminal portion of the terminal wiring formation region 44 in FIG. It is sufficient to switch the wiring material sufficiently before the terminal wiring forming region 44. For example, it is sufficient to switch each material at a position of about several hundred μm before the terminal portion. Of course, you may apply | coat from a terminal part first.

  Furthermore, the gate electrode 17 shown in FIG. 7B may be formed of a silver alloy material having a high indium content. This is because, in particular, the gate electrode 17 is formed with a semiconductor layer on the gate electrode 17 in a later step, and therefore it is desired that the gate electrode 17 is particularly excellent in smoothness. This is because 10% by weight is more stable than 5% by weight for suppressing crystal growth. Further, as another material for obtaining the same surface smoothness, for example, a refractory metal such as cobalt, titanium, niobium, or molybdenum may be mixed in silver.

  To further describe the characteristics of the wiring formed in this way, the characteristics of at least two portions on the same wiring are different from each other. Here, the characteristics of the wiring portion and the electrode portion of the gate wiring 30 are made different. Specifically, as described above, by changing the ratio of indium to silver in the silver indium alloy that is the wiring material, the characteristics of each portion (part) are made different.

  Note that the wiring material may be different in order to make the characteristics of the parts different.

  Here, the same wiring is a wiring that is continuous in shape, and a circuit on a substrate is a unit of a plurality of such wirings, and a circuit board is formed.

  Also, as mentioned above. The wiring is preferably made of a single layer. On the other hand, the wiring has been multilayered for the following reasons.

  Conventionally, there is no change in surface property with respect to applied heat, that is, heat resistance, resistance to etching gas in plasma in dry etching processing, that is, performance such as plasma resistance and adhesion, and resistance value as wiring Conventionally, the wiring material is layered in a layered manner. In other words, for example, a low resistance metal such as aluminum is the main metal, and silicon or copper is applied to a trace amount on or under the wiring material to which heat resistance is applied, and titanium, molybdenum or the like is used as an adhesive material, tantalum, Niobium or the like was formed and used as a plasma-resistant material.

  As described above, conventionally, a two-layer or three-layer structure may be used to achieve the target performance. In particular, a wiring material used for a TFT array substrate often needs to satisfy two or more of the various performances described here at the same time. For this reason, in order to form one wiring-like film, the film forming process requires a plurality of times such as two times and three times, and the apparatus is also required only for that process, so that the capital investment is increased. Further, even when the formed film is processed into a pattern, the selection remains in order to process the layered film with the same etching material.

  Further, in the TFT array substrate, the formed film thickness may be limited due to a later process. This is because a film such as a wiring formed thereon may be cut due to a step formed by the stacked films. Furthermore, in addition to the limitations on the film thickness, many of the materials formed in layers, that is, the tantalum, niobium and the like have high specific resistance.

  Therefore, a low resistance metal portion that mainly contributes to electrical conduction is required to have a lower resistance. For this reason, it is very difficult to search for a low-resistance material or to search for an alternative material when it is already alloyed with other required performance.

  In addition, there is a method to cope with the direction of increasing the wiring width. However, for example, in a liquid crystal panel, it is difficult to increase the wiring width because a bright screen is required by increasing the aperture area of the pixel.

  From this point of view, the formation of the wiring as a single layer as in the present application solves the above-described problems, and is extremely important from the viewpoints of cost and performance. This is the same not only for liquid materials but also for sputtering and vapor deposition.

  In the case of a liquid material, since it is possible to separate the coating material at the time of formation using an ink jet method, the meaning of further monolayering is further increased. Even if it is a liquid material, the formation of the liquid material in layers by inkjet does not change from the viewpoint of manufacturing costs such as equipment investment and tact time.

  Another advantage of using a liquid material is that the same type of material can be used particularly in the case of adjusting the compounding ratio of indium in the silver indium system as in this embodiment. The same type of material means that a solvent in which fine particle material is dispersed or a protective colloid with similar properties to prevent fine particles from being dispersed and agglomerated are used, or if the metal is a metal compound and is contained in the solvent Then, when the solvent mixes, it means that an unnecessary deposit does not precipitate. In the case of fine particles, the same-system solvent has a small shock when mixed, and the fine particles are less likely to aggregate or precipitate by mixing. If liquid materials composed of solvents having too different polarities are mixed, separation and aggregation are likely to occur. In addition, for an inkjet head that discharges such a liquid material, there are a wide range of options for the head constituent material for the fluid wiring material, for example, the adhesive used inside the head, and the tuning of the fluid material for the head is easy. become. Of course, it is possible to select carefully so that there is no different aggregation or precipitation, and to mix them in different solvent systems. However, this selection and tuning often takes an enormous amount of time, and considering this point, it is very useful to be a material of the same system.

  In addition, what is called a single layer here is to form a functional film necessary for satisfying the performance as a wiring by forming a wiring by one layer in film formation and by applying once in a liquid. Say. For example, as in the case of hydrophilic / hydrophobic (hydrophobic) treatment, it is necessary only for coating and is multilayered with a layer that does not work to positively improve adhesion, and film formation is performed in a later process. In addition, it is possible to eliminate the case where a film that improves adhesion is separated first and the above-described configuration is formed by a single coating on it is separated. Is not to be done.

(Gate insulating film / semiconductor film forming step 103)
Subsequently, the gate insulating film / semiconductor film forming step 103 will be described below with reference to FIGS. 10 (a) and 10 (b) and FIGS. 11 (a) and 11 (b).

  FIGS. 10A and 10B and FIGS. 11A and 11B are views showing the glass substrate 12 in a state where the gate insulating film / semiconductor film forming step 103 is completed. 10A and 11A are plan views of the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. FIGS. 10B and 11B are a cross-sectional view taken along line EE and a cross-sectional view taken along line FF in FIGS. 10A and 11A, respectively.

  In the gate insulating film / semiconductor film forming step 103, the gate insulating film 45 to be the gate insulating layer 18 and the amorphous silicon film 46 to be the amorphous silicon layer 19 are formed on the glass substrate 12 after the gate wiring forming step 102. , And an n + type silicon film 47 to be the n + type silicon layer 20 is continuously formed. Here, the gate insulating film 45 is a film made of silicon nitride. All of these films were formed by the CVD method, and the respective film thicknesses were set to 0.3 μm, 0.15 μm, and 0.04 μm in order. The film forming temperature was 300 ° C.

  As described in the previous step, the gate wiring 13 has improved heat resistance due to indium added in addition to silver, and new crystal growth is suppressed. Therefore, the surface of the gate wiring 13 is not roughened even under a high temperature condition of 300 ° C., and the gate wiring 13 having a better surface property than that formed of silver alone can be obtained. For this reason, there is no leakage from the semiconductor layer 27 and the source electrode 21 formed thereon via the gate insulating layer 18, so that the yield is improved and the TFT characteristics are stabilized.

(Gate insulating film / semiconductor film processing step 104)
Next, the gate insulating film / semiconductor film processing step 104 will be described below with reference to FIGS. 12 (a) and 12 (b) and FIGS. 13 (a) and 13 (b).

  FIGS. 12A and 12B and FIGS. 13A and 13B are views showing a state where the gate insulating film / semiconductor film processing step 104 is completed. 12A and 13A are plan views of the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. FIGS. 12B and 13B are a cross-sectional view taken along line GG and a cross-sectional view taken along line HH in FIGS. 12A and 13A, respectively.

  In this gate insulating film / semiconductor film processing step 104, processing was performed using photolithography.

First, the amorphous silicon film 46 and the n + type silicon film 47 were processed by the first photolithography. These are processed so that they are left in the shape of islands above the gate electrode 17 in the pixel formation region 61 and not left in the terminal portion formation region 62. As a result, an amorphous silicon layer 19 and an n + type silicon processed film 48 which later becomes the n + type silicon layer 20 were obtained. Etching was performed by introducing a mixed gas of sulfur hexafluoride (SF ⁶ ) gas and hydrogen chloride (HCl) gas by a dry etching method. Up to this point, since the gate insulating film 45 covers the entire surface of the substrate, the terminal wiring 30 and the like are not exposed to the dry etching atmosphere.

Subsequently, the gate insulating film 45 was processed by second photolithography. In the terminal portion formation region 62, the gate insulating film 45 was partially etched to obtain the gate insulating layer 18 and the opening 49. Etching was performed by introducing a mixed gas of CF ⁴ gas and O ² gas by a dry etching method.

  In the dry etching of the gate insulating film 45, the terminal wiring 30 is exposed to the dry etching atmosphere at the opening 49 formed in the terminal portion forming region 62 and other portions for electrical connection (not shown). This is because the dry etching method is a method with good controllability, but overetching cannot be prevented in actual manufacturing.

  Here, if the terminal wiring 30 is formed of silver, which is a conventional technique, it does not have plasma resistance. For this reason, the terminal wiring is greatly etched in the opening 49, which becomes defective. On the other hand, in the present embodiment, the terminal wiring 30 is made of silver and indium, and the ratio of indium to silver is set to be about 10% by weight. Therefore, it has plasma resistance and can withstand such a dry etching process.

(Source / drain wiring pretreatment step 105)
Next, the source / drain wiring pretreatment step 105 will be described below with reference to FIG. FIG. 14A is a plan view showing a state in which the wiring guide 52 for forming the source wiring 14, the source electrode 21, and the drain electrode wiring 22 is formed on the glass substrate 12 that has undergone the gate insulating film / semiconductor film processing step 104. FIG.

  In this source / drain wiring formation step 106, no wiring or the like is formed in the terminal portion formation region 62, so only the pixel formation region 61 will be described here.

  In this step, the wiring guide 52 is formed so as to exclude the region (source / drain formation region 53) in which the source wiring 14, the source electrode 21, and the drain electrode wiring 22 are formed. The wiring guide 52 was formed using a photoresist material. That is, a photoresist was applied on the glass substrate 12 that had undergone the gate insulating film / semiconductor film processing step 104, pre-baked, then exposed and developed using a photomask, and then post-baked. The wiring guide 52 formed here was formed so that the line width of the region forming the source wiring 14 and the source electrode 21 was 10 μm, and the line width of the region forming the drain electrode wiring 22 was 10 μm to 40 μm. The distance between the source electrode 21 and the drain electrode wiring 22, that is, the length of the channel portion 51 of the TFT was set to 4 μm.

In addition, the upper surface of the gate insulating layer 18 is subjected to hydrophilic (liquid) treatment with oxygen plasma so that the wiring material applied by the pattern forming apparatus is well adapted to the surface to be the base surface. Water repellent (liquid) treatment may be performed by exposure to CF ⁴ plasma.

  Further, in place of the formation of the wiring guide 52, the hydrophilic / hydrophobic treatment according to the wiring electrode pattern may be performed by the hydrophilic / hydrophobic (hydrophobic) method using the photocatalyst used for forming the gate electrode. .

(Source / drain wiring forming step 106)
Next, the source / drain wiring forming step 106 will be described below with reference to FIGS. FIGS. 14B and 14C are views showing a state in which the source / drain wiring forming step 106 is completed. FIG. 14B is a plan view of a pixel formation region on the glass substrate 12. FIG.14 (c) is the II sectional view taken on the line in FIG.14 (b).

  Even in the source / drain wiring formation step 106, since no wiring or the like is formed in the terminal portion formation region, only the pixel formation region will be described.

  This source / drain wiring formation step 106 is a step of forming the source wiring 14, the source electrode 21, and the drain electrode wiring 22 using the wiring guide 52 provided in the previous step. As the coating apparatus, a pattern forming apparatus as shown in FIG. 5 was used.

  At this time, the fluid wiring material used was an organic film-coated silver indium alloy fine particle dispersed in an organic solvent. The silver and indium contained in the fluid wiring material at this time were set so that the ratio of indium to silver was about 10% by weight.

  The ratio of silver and indium contained in the fluid wiring material is selected so as to have plasma resistance in consideration of dry etching performed in the subsequent channel portion processing step 107 and protective film processing step 109. It is out. However, the ratio can be appropriately selected according to the manufacturing process and the required performance of the TFT array substrate.

  Here, the discharge amount of the fluid wiring material from the inkjet head 33 is set to 2 pl. The formed film thickness was 0.3 μm. The firing temperature was set to 200 ° C., which is lower than the amorphous silicon film 46 and the like, which were formed at about 300 ° C. The wiring guide 52 was removed using an organic solvent.

  In this case as well, the fact that the wiring is a single layer has the same advantages as those described in the gate wiring process.

(Channel processing step 107)
Next, the channel portion processing step 107 will be described below with reference to FIG. FIG. 15 is a diagram illustrating a state in which the channel part machining step 107 is completed, and is a cross-sectional view taken along the line corresponding to the position of the line II in FIG.

  In the channel portion processing step 107, the TFT channel portion 51 is processed. This process is performed by dry etching using chlorine gas. At this time, new photolithography is not performed, and processing is performed using the pattern of the source electrode 21 and the drain electrode wiring 22.

  In this embodiment, a pattern forming apparatus such as an ink jet apparatus is used in the previous process. Thus, when the source wiring 14, the source electrode 21, and the drain electrode wiring 22 are formed, it is impossible in the process to leave a resist on these. Therefore, in the channel portion processing step 107, the channel portion 51 is processed using the source wiring 14 and the like as a mask, so that the source wiring 14 and the like are in a dry etching atmosphere for a long time from the start to the end of etching. Exposed to.

  That is, particularly when a pattern forming apparatus such as an ink jet apparatus is used, the source wiring 14 and the like are required to have a high resistance to dry etching (plasma resistance).

  The conventional source wiring 14 composed of silver alone has no plasma resistance, so that most of the wiring is etched and the intended conductivity cannot be obtained. In contrast, in the present embodiment, the source wiring 14 and the like are made of silver and indium, and the ratio of indium to silver is set to be about 10% by weight. Therefore, it has plasma resistance and can withstand such a dry etching process.

  As described above, the wiring material composed of silver and indium according to the present invention has high plasma resistance, and thus facilitates a method of manufacturing a TFT array substrate using a pattern forming apparatus, which has been difficult in the past.

(Protective film / interlayer insulating layer film forming step 108)
Subsequently, the protective film / interlayer insulating layer forming step 108 will be described below with reference to FIGS. 16 (a) and 16 (b) and FIGS. 17 (a) and 17 (b). FIGS. 16A and 16B and FIGS. 17A and 17B are views showing a state where the protective film / interlayer insulating layer forming step 108 is completed. FIGS. 16A and 17A are plan views of the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. FIGS. 16B and 17B are a cross-sectional view taken along line JJ and a cross-sectional view taken along line KK in FIGS. 16A and 17A, respectively.

  In this protective film / interlayer insulating film forming step 108, first, a silicon nitride film 55 was formed on the glass substrate 12 that had undergone the previous step by a CVD method. The substrate temperature at this time is set to 200.degree.

  Next, a photosensitive acrylic resin material was applied on the silicon nitride film 55. Subsequently, an interlayer insulating layer 26 having a predetermined pattern was obtained by performing exposure using a mask, development, and baking. At this time, an opening 56 is provided in a portion where the drain electrode wiring 22 and the auxiliary capacitance wiring 16 overlap. On the other hand, in the terminal portion formation region 62, the interlayer insulating layer 26 is not formed on the entire surface.

(Protective film processing step 109)
Next, the protective film processing step 109 will be described below with reference to FIGS. 18 (a) and 18 (b). 18A and 18B are views showing a state in which the protective film processing step 109 is completed. 18A and 18B are cross-sectional views taken along the lines JJ and KK in FIGS. 16A and 17A, respectively.

In this protective film processing step 109, the silicon nitride film 55 formed in the protective film / interlayer insulating layer forming step 108 is processed with the pattern of the interlayer insulating layer 26. In the pixel formation region 61, the silicon nitride film 55 immediately below the opening 56 is etched to obtain the protective layer 25 and the contact hole 23. On the other hand, in the terminal portion forming region 62, the silicon nitride film 55 is etched and removed on the entire surface. Etching was performed by introducing a mixed gas of CF ⁴ gas and O ² gas by a dry etching method.

  In the dry etching of the silicon nitride film 55, the drain electrode wiring 22 and a part of the terminal wiring 30 are exposed to the dry etching atmosphere in the contact hole 23 and the opening 49 in the terminal portion 28. This is because the dry etching method is a method with good controllability, but overetching cannot be prevented in actual manufacturing.

  Silver, which is a conventional technique, does not have plasma resistance. Therefore, in this case, the drain electrode wiring 22 and a part of the terminal wiring 30 are largely etched, resulting in a defect. In contrast, in the present embodiment, the drain electrode wiring 22 and the terminal wiring 30 are made of silver and indium, and the ratio of indium to silver is set to be about 10% by weight. Therefore, it has plasma resistance and can withstand such a dry etching process.

(Pixel electrode forming step 110)
As the last step, an ITO (indium tin oxide) film that later becomes the pixel electrode 24 and the terminal electrode 29 was formed by sputtering. The substrate temperature at this time was 200 degreeC. Subsequently, this ITO film was patterned using photolithography, and the TFT array substrate 11 shown in FIGS. 1, 2, 3A, 3B and 4 was obtained.

  As described above, since the material of the present invention has an excellent adhesion to a glass substrate that is not found in conventional silver alone, it can withstand a series of manufacturing processes and does not cause defects due to peeling of the gate wiring and the like.

  In addition, since the material of the present invention has excellent heat resistance not found in conventional silver alone, the surface is not roughened even when the substrate is exposed to a high temperature condition of 300 ° C. as in this example, The gate wiring 13, the auxiliary capacitance wiring 16, the gate electrode 17 and the like with good surface smoothness can be obtained. For this reason, there is no leakage from the source wiring 14, the semiconductor layer 27, the source electrode 21, and the like formed thereon via the gate insulating layer 18, yield is improved, and TFT characteristics are stabilized.

  And above all, the material of the present invention has high plasma resistance, which enables such a manufacturing process.

  In the present embodiment, the gate insulating layer 18 is etched in the gate insulating film / semiconductor film processing step 104, the n + type silicon processing film 48 is etched in the channel portion processing step, and the silicon nitride film 55 is etched in the protective film processing step 109. Dry etching is used in a total of three processes. At this time, in the case where wirings, electrodes, and the like were formed by conventional silver alone, they were etched during over-etching or when used as an etching mask for other films, resulting in defects. However, since the wiring material of the present invention containing silver and indium has excellent plasma resistance as in the present embodiment, it does not become defective.

  As described above, in manufacturing a TFT array substrate, dry etching is frequently used, and accordingly, high dry etching resistance (plasma resistance) is required as a material constituting wiring, electrodes, and the like. The material mainly composed of silver and containing indium of the present invention has high plasma resistance, and is particularly excellent as a material constituting wirings, electrodes and the like on the TFT array substrate.

  Further, the material of the present invention is particularly effective when the source wiring 14, the semiconductor layer 27, the source electrode 21 and the like are drawn and formed by a pattern forming apparatus such as an ink jet method as in this embodiment. In such a case, since the source wiring 14 and the like are used as an etching mask for forming the n + -type silicon layer 20, the source wiring 14 is exposed to a dry etching atmosphere for a long time from the start to the end of etching. Therefore, this process was difficult when using conventional silver alone. However, the material of the present invention makes it possible to manufacture a TFT array substrate by such a pattern forming apparatus.

  As described above, the silver alloy material of the present invention is particularly suitable for a manufacturing process using a coating apparatus such as an ink jet apparatus, and is a material that is beneficially used by being included in a fluid wiring material. In addition, as will be described later, the material is also usefully used in a manufacturing method performed without using a pattern forming apparatus.

  In this embodiment, a six-mask process is performed in which a photomask is used a total of six times to perform exposure and development steps. In order to produce a TFT array substrate at a lower cost, a five-mask process in which this is reduced once is also widely used. In this case, the gate insulating layer 18 and the protective layer 25 are formed by etching the gate insulating film 45 and the silicon nitride film 55 successively. However, in this case, in particular, the exposed portion formed in the drain electrode wiring 22 is exposed to a dry etching atmosphere for a long time, and it is necessary to endure severe use conditions.

  To consider this reason, the state of the substrate being etched is considered. First, since there is a film on the entire surface while the silicon nitride film 55 is being etched, there is no problem. However, during the continuous etching of the gate insulating film 45, the exposed portion formed in the contact hole 23 of the drain electrode wiring is always directly exposed to the dry etching atmosphere from the start to the end of the etching. In the case of the six-mask, only over-etching was performed, but this is a very long time and is a severe process condition.

  Therefore, particularly in the case of such a five-mask process, the drain electrode wiring 22 is required to have high plasma resistance, but the silver alloy material of the present invention represented by a silver alloy material containing silver and indium is Since it has high plasma resistance, it can be used even in such a case, and the use range is wide.

  In the present embodiment, the terminal wiring 30 is formed at the same time as the gate wiring and the like by a six-mask process, but the scope of the present invention is not limited to this. In most of the current manufacturing methods in which a silicon nitride film to be the gate insulating layer 18 or the protective layer 25 is formed on the entire surface of the substrate and partially removed by dry etching, the portion to be removed for the electrical connection is necessarily present. In addition, the electrodes, wirings, and the like disposed below the substrate are required to have plasma resistance against over-etching. The present invention provides a material having excellent plasma resistance and exhibits an excellent effect on the manufacturing process of these TFT array substrates.

  In the present embodiment, as the fluid wiring material, a material in which silver indium alloy fine particles coated with an organic film are dispersed in an organic solvent is used. Silver and indium contained in the fluid wiring material at this time were formed by appropriately using a ratio of indium to silver of about 10% by weight or less. However, the ratio of indium to silver can be appropriately selected so as to have an appropriate plasma resistance according to the manufacturing process, or according to the required performance of the TFT array substrate.

  The form of the fluid wiring material is not limited to a form containing silver and indium as fine particles of a silver indium alloy. Silver fine particles and indium fine particles may be prepared separately and dispersed independently in a solvent. Moreover, it is not necessarily limited to fine particles, and silver or indium may be included in the solvent in the form of a metal compound.

  In this embodiment, the wiring, electrodes, and the like of the source wiring 14 and the gate wiring 13 are formed of a silver alloy material containing silver and indium. However, the present invention is not limited to this, and a silver alloy material containing silver and zinc may be used. good. The gate wiring 13 and the like may be formed using silver and a silver alloy material containing at least one element selected from tin, zinc, lead, bismuth, indium, and gallium. In addition to silver, aluminum and copper may be the main metals. In addition to these elements, at least aluminum, copper, nickel, gold, silver, platinum, palladium, cobalt, rhodium, iridium, ruthenium, and osmium. A silver alloy material characterized by containing an element selected from titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

  Here, the details of the wiring formation in the gate wiring forming step 102 and the source / drain wiring forming step 106 described above will be described below.

  First, the gate wiring formation step 102 will be described with reference to FIGS. 19 (a) to 19 (e).

  First, as shown in FIG. 19A, in the gate wiring pretreatment step 101, the first of the inkjet head 33 is formed in the wiring formation region of the glass substrate 12 on which the surface has been subjected to the hydrophilic / repellent treatment. The terminal wiring 30 is formed by discharging the fluid wiring material of the low resistance material for the wiring portion by the head 33a.

  Subsequently, as illustrated in FIG. 19B, the terminal portion plasma-resistant material is formed on the terminal electrode formation region on the glass substrate 12 after the terminal wiring 30 is formed by the second head 33 b of the inkjet head 33. The terminal electrode 39 is formed by discharging a fluid wiring material.

  Next, as shown in FIG. 19C, after the terminal wiring 30 and the terminal electrode 29 formed on the glass substrate 12 are baked, the gate insulating film 45 serving as a protective film is formed on the terminal wiring 30 and the terminal electrode 29. To cover.

  After that, as shown in FIG. 19D, in order to perform terminal processing, a resist material 100 serving as a mask is provided so as to open a portion of the gate insulating film 45 corresponding to the terminal electrode 29, and patterning is performed by mask exposure or the like. Form.

  Finally, as shown in FIG. 19E, after etching the region of the gate insulating film 45 corresponding to the terminal electrode 29, the resist material 100 is peeled off to form the terminal portion.

  As described above, when the ink jet head 33 is provided with two heads according to functions and can handle two kinds of fluid wiring materials, the ink supply system 36, the control unit 37, the ejection position information, and the like are also made to correspond thereto. It is necessary to keep it.

  The terminal portion 28 formed in this way is as shown in FIGS. The terminal wiring 30 is in contact with the terminal electrode 29, and these have electrical continuity.

  Since the terminal wiring 30 is covered with the gate insulating layer 18, it may be selected so as to have heat resistance and adhesion to the glass substrate out of process resistance. Plasma resistance is not necessary because it is not exposed to a dry etching atmosphere.

  For example, if a circuit board used for a large liquid crystal display device is described as an example, the wiring length of the large liquid crystal display device becomes long. Therefore, it is desirable to reduce the electrical resistance of the wiring as much as possible. In such a case, the terminal wiring 30 can be configured such that the content of indium with respect to silver is 3 wt%. At this time, the electrical resistivity of this portion is about 4 μΩcm. In addition, the gate wiring 13, the gate electrode 17, and the auxiliary capacitance wiring 16 in the pixel formation region 61 are also made of indium with respect to silver so as to have a lower electric resistance for the same reason as the terminal wiring 30 because the wiring length is long. It can comprise so that content may be 3 weight%.

  On the other hand, the terminal electrode 29 is exposed to a dry etching atmosphere by overetching in an etching process for electrical connection. Therefore, emphasis is placed on plasma resistance, and the indium content with respect to silver can be configured to be 10% by weight. The terminal electrode 29 may be much shorter than the gate wiring 13, the source wiring 14, and the terminal wiring 30 on the TFT array substrate, and the electric resistivity may be higher than that of other portions.

  Of course, both the terminal wiring 30 and the terminal electrode 29 may have the same configuration, that is, a content of indium with respect to silver of 10% by weight. However, by performing coating according to the performance required for each part as in the present embodiment, it is possible to form wiring, electrodes, etc. with lower electrical resistance as a whole, so a larger circuit board, There is an advantage that a larger display device or the like can be realized.

  Here, the inkjet head 33 uses the first head 33a and the second head 33b to discharge two types of fluid wiring materials having different indium contents relative to silver to form terminal wirings and terminal electrodes. doing. Specifically, a fluid wiring material was discharged into the region for forming the terminal wiring 30 such that when the terminal wiring 30 was formed, the indium content relative to silver was 3 wt%. On the other hand, in the region for forming the terminal electrode 29, a fluid wiring material was discharged so that when the terminal electrode 29 was formed, the indium content relative to silver was 10% by weight.

  On the other hand, the same fluid wiring material as that of the terminal wiring 30 was discharged into the area for forming the gate wiring 13, the gate electrode 17, and the auxiliary capacitance wiring 16 in the pixel formation region 61. After the discharge, firing was performed at 300 ° C. for 1 hour to obtain predetermined terminal wirings 30, terminal electrodes 29, and the like. As described above, by using a fluid wiring material having an indium content of 3 wt% for the wiring portion of the pixel formation region 61, it is possible to further reduce the resistance of the wiring.

  In the present embodiment, a pattern forming apparatus such as an ink jet method can be applied separately within the substrate surface, wiring formed in the same process requires different plasma resistance or conductivity in each part, And it is important that the indium content of the material of the present invention is well combined with the relationship between conductivity and process resistance. As a result, a large TFT array substrate that is easy to manufacture and has good electrical characteristics can be manufactured.

  In the present embodiment, the terminal wiring 30 and the terminal electrode 29 have a boundary where materials having different indium contents come into contact with each other. However, the present invention is not limited to this. The indium content may change gently near the boundary. As a forming method thereof, fluid wiring materials may be naturally mixed with each other, or may be mixed with the intention of alternately discharging two kinds of materials.

  Of course, it is an important point of the present embodiment that a necessary part of the TFT array substrate 11 is provided with a wiring, an electrode and the like having an increased indium content in a part exposed to a dry etching atmosphere during the manufacturing process. is there.

  As described above, the silver alloy material of the present invention can be manufactured in many processes by performing coating even when the indium content relative to silver is relatively low, for example, 1% by weight or 3% by weight. In particular, it can be appropriately used as a material having a particularly low electrical resistance, which constitutes wiring and electrodes such as the gate wiring 13.

  In this embodiment, the gate wiring 13 and the like are formed using a silver alloy material containing silver and indium. However, the present invention is not limited to this, and a silver alloy material containing silver and zinc may be used. The gate wiring 13 and the like may be formed using silver and a silver alloy material containing at least one element selected from tin, zinc, lead, bismuth, indium, and gallium. In addition to silver, aluminum and copper may be the main metals. In addition to these elements, at least aluminum, copper, nickel, gold, silver, platinum, palladium, cobalt, rhodium, iridium, ruthenium. A silver alloy material characterized in that it contains an element selected from osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

  In addition, silver and indium, silver and zinc, and the like may be properly used depending on the location so that the configuration is different on the TFT array substrate 11.

  Next, details of the source / drain wiring formation step 106 will be described below. Here, the content of indium with respect to silver is 3 wt% in the case of the source electrode 21 and the source wiring 14, and 10 wt% in the case of the drain electrode wiring 22.

  Further, in the drain electrode wiring 22, it may be separately coated so that the content of indium with respect to silver is 3 wt% and 10 wt%, and the plasma resistance may be improved near the contact hole 23. In addition, such coating may be performed at an arbitrary place on the TFT array substrate of the present embodiment.

  The wiring material of the source / drain wiring is not limited to a material composed of silver and indium, and may be a silver alloy material containing silver and zinc. The source wiring 14 and the like may be formed using silver and a silver alloy material including at least one element selected from tin, zinc, lead, bismuth, indium, and gallium. In addition to silver, aluminum and copper may be the main metals. In addition to these elements, at least aluminum, copper, nickel, gold, silver, platinum, palladium, cobalt, rhodium, iridium, ruthenium. A silver alloy material characterized in that it contains an element selected from osmium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, molybdenum, tungsten, and neodymium.

  In addition, silver and indium, silver and zinc, and the like may be properly used depending on the location so that the configuration is different on the TFT array substrate.

  When the TFT array substrate 11 is manufactured, as described above, the coating may be performed separately in both the gate wiring forming process 102 and the source / drain wiring forming process 106, or only one process may be applied. Dividing may be performed.

  Here, a description will be given of a portion where each material comes into contact when wiring materials such as a wiring portion and a terminal portion are separately coated according to the application.

  For example, as shown in FIG. 20 (a), after applying the terminal wiring 30 as the wiring portion with the material M, as shown in FIG. 20 (b), the material is formed at a location corresponding to the terminal electrode 29 forming the terminal portion. Apply N. At this time, the material M and the material N are in contact with each other or mixed with each other at the boundary portion P.

  FIG. 21A to FIG. 21C show a state that is expected to occur at the boundary when different materials M and N come into contact with each other by ink jet application.

  FIG. 21A shows a case where the materials M and N are mixed with each other at the boundary. As a result, the materials M and N are different from each other, that is, an intermediate state (intermediate region) is generated. Shows the state.

  This state varies depending on the mixing ratio of the material M and the material N, but the extent to which they are mixed to create an intermediate state is related to how long the solvent contained after coating remains. That is, if the solvent is dried, it will not mix with the fluidity of the liquid. However, although the intermediate state of the materials M and N is born by melting of the fine metal particles at the time of firing, it is considered that the region is very narrow compared to the intermediate state that is created by mixing in the liquid state. Here, attention is paid to mixing in the liquid state, and at this time, the boundary between the materials M and N is extremely unclear.

  FIG. 21B shows a state in which the materials M and N are not mixed in the liquid state in a state where the material N is applied after the solvent content of the material M applied earlier is substantially dried.

  In this state, since the materials M and N are not mixed, the boundary between the two exists relatively clearly. However, an intermediate state is created by melting the fine particles contained in the materials M and N at the time of firing.

  FIG. 21 (c) is an intermediate case of FIGS. 21 (a) and 21 (b), and the material M becomes liquid again by the solvent content of the material N applied later, and the regions of the materials M and N are unclear. Shows the state. At this time, since the mixed area is narrower than that in FIG. 21A, a virtual boundary can be drawn at the intermediate distance.

  In the present embodiment, it is important that the materials M and N are electrically connected after firing. The states of FIGS. 21A to 21C are electrically connected to each other, and there is no problem in any state in the present invention. However, as will be described later, the state of (a) is desirable in the case of resistance production by actively using the intermediate state by mixing materials M and N, and the end of the resistance is (b) or (c) It is desirable that Note that here, only the boundary between the material M and the material N is emphasized, and the flatness of the surface during the coating process is not related to the present description, so the drawings are all described in a flat state. ing.

  By utilizing the present invention, it is possible to adjust resistance formation and wiring resistance by appropriately combining a low-resistance wiring material and a wiring material having a high resistance with an alloy. Examples thereof will be described below.

  In the schematic diagram of the gate wiring in FIG. 22, the terminal wiring connecting the terminal electrode of the driver IC and the gate wiring is connected to a location where the distance between the terminal and the gate wiring is short, that is, to the center of the driver IC in order to make the wiring length uniform. The wiring shape is a zigzag shape at a place where the driver terminal and the gate wiring are long, that is, the part connected to the end of the driver IC is connected as a straight line.

  Here, a zigzag pattern having a length D and one wiring length L is assumed as shown in FIG. In FIG. 23A, since there are four turns, the total wiring length is approximately 8L. Therefore, compared with the case where the distance D is connected by a straight line, the resistance is approximately 8 L / D times.

For example, if D = 600 μm and L = 150 μm, then 8 L / D = 2. Therefore, if the wiring width and film thickness are not changed, the specific resistance of the wiring should be doubled.
To adjust the wiring resistance,
(1) Forming with a material having a desired specific resistance (2) Adjusting by blending materials with different specific resistances (3) Three methods of changing the wiring shape film thickness are conceivable.

  In the method (1), as shown in FIGS. 20A and 20B, a material with a low specific resistance of the contained metal part, a material M, a material with a high specific resistance, and a material N are prepared, and the wiring is made of the material M. By using the material N in the place where the resistor is formed, the resistor can be formed. When this method is applied to the case of D = 600 μm and L = 150 μm in FIG. 23A, the specific resistance when the ratio of indium to silver is 5% by weight is about 6.1 μΩ · cm (Example 5). The specific resistance of indium to silver is 10 wt% and the specific resistance is 12.3 μΩ · cm (Example 6). Here, the material M is an alloy in which the ratio of indium to silver is 5 wt%, and the material N is silver. If the ratio of indium to the alloy is 10% by weight, the resistance can be formed in a straight line without using a zigzag pattern, as shown in FIG. 23B, if the film thickness and line width are not changed.

  In the method (2) of adjusting the intermediate resistance from the material M and the material N, as shown in FIGS. 24A and 24B, for example, the material M is intermittently moved by the first head 33a that precedes the inkjet head 33. After the material is discharged, the material N is discharged into the gap by the next second head 33b, thereby mixing the material M and the material N and having a resistance value made of the material M and the material N (intermediate body) ) Can be obtained.

  At this time, if the discharge interval and discharge ratio between the material M and the material N are changed, the resistance value can adjust the mixing ratio of the material M and the material N.

  Below, the other example which forms the above intermediates is demonstrated.

  25 (a) (b) and 26 (a) (b), the discharge rate of the material M is different. In FIGS. 25 (a) and 25 (b), the material M is discharged at a rate of once per three drops. FIGS. 26 (a) and 26 (b) show examples in which the material M is discharged at a rate of twice for three drops. The same film thickness, the same wiring width, the ejection amount of one drop, and the ejection interval are the same, and as shown in FIG. 21B, the resistance value is higher in FIGS. 25A and 25B. In this way, the resistance value can be adjusted by the ratio of the number of discharged materials M and N. Of course, the film thickness, line width, discharge amount, and discharge interval can also be changed and adjusted as appropriate.

  Further, if the internal state of the cross section is (a) in FIG. 21, the resistance value is not necessarily an intermediate value proportional to the mixing ratio. In the case of a metal alloy, when different materials are mixed, the resistance value of both is often higher. In addition, when the mixing ratio of the metal to form a compound is used, the resistance value may be lowered. These are because the dissimilar materials are mixed together, and the scattering probability of conduction electrons that contribute to electrical conduction is simply increased, and when it becomes a compound, it takes a fixed crystal structure, so the probability This is because it becomes lower. Also in the case of this example, it is considered that a phenomenon similar to that in the case of the metal alloy occurs because the fine particles are fused by firing after mixing. Thus, when the resistance value does not reach the average value, it is necessary to investigate the resistance characteristic in advance.

  On the other hand, when the discharged droplets are stacked after being dried, that is, when the boundaries are as shown in FIGS. 21B and 21C, the material M and the material N are in contact with each other, Since they are not mixed, the resistance value is close to the average value of both. Therefore, in this case, the intermediate resistance value between the material M and the material N can be adjusted by the ratio of the discharge amount. Thus, it is also possible to adjust the resistance value in a state after application.

  However, in FIG. 21A, since the boundary between the material M and the material N is unclear, the wiring length as a resistor is not clear, and the resistance value varies, so the end of the portion that becomes the resistor is clear. As shown in FIG. 21 (b), it is preferable to dry the film so that a clear boundary appears.

  25 (b) and 26 (b) show cross-sectional views of FIG. 25 (a) and FIG. 26 (a), respectively, and in order to clarify the resistor length, at the end, FIG. As shown in FIG. 21 (a), after sufficiently drying so that the boundary is clear, the materials M and N are discharged between them and the resistance portion is mixed in a liquid state as shown in FIG. In this example, the boundary between the materials M and N is unclear.

  The case of changing the wiring width and film thickness in (3) will be described below with reference to FIGS. 27 (a) to 27 (c).

  FIG. 27A shows a case where the discharge interval is narrowed. In this case, the film thickness is increased if the concentration of the coating material and the wiring width do not change.

  On the other hand, FIG. 27B is an example in which the discharge interval is widened, and the broken line ellipse indicates the position where the droplet has landed. This figure shows a case where the material N that has landed at two locations in the region where the resistance forming position is made hydrophilic (liquid) in advance by the hydrophilic / hydrophobic (hydrophobic) process spreads along the hydrophilic (liquid) pattern. Therefore, the film thickness is smaller than that in the case where the discharge interval in FIG. By increasing the discharge interval and reducing the film thickness in this way, it is possible to make a higher resistance.

  Thus, materials having different resistance values can be produced by appropriately combining the methods (1) to (3).

  This is effective when a monolithic IC is formed on glass. In an IC process for processing a Si wafer, a resistor is appropriately formed by ion implantation. For a panel manufactured from a large substrate such as a panel of a liquid crystal display device as in this example, an ion implantation method is used. However, the size of the device is large, and it is not realistic from the viewpoint of the device itself and the device price. Therefore, such a method is very effective for forming a circuit board that requires resistance on the substrate.

  In addition, as described in the present embodiment, a material used as a resistor can be a material in which the ratio of indium to silver is changed. Materials with high resistance, for example, alloys such as cobalt and nickel, and high melting point materials such as tantalum, molybdenum, tungsten, and niobium may be used, or they may be used as a single material rather than an alloy with silver. May be.

  Further, as shown in FIG. 27C, the wiring width can be narrowed when the wiring forming position is made hydrophilic (liquid) by using the hydrophilic / hydrophobic (hydrophobic) process. In this case, if the film thickness is the same, the resistance increases. In this way, it is possible to control the resistance according to the wiring width.

  In FIGS. 25 (a), 26 (a), and 27 (a) used here, the resistor portion is described by clearly writing the droplet shape immediately after landing for the sake of clarity. However, the present embodiment is not limited to these drawings. When landed on the area after lyophilic (liquid repellent) treatment, the droplet shape after landing spreads on the hydrophilic area (lyophilic area), so the shape immediately after landing remains clearly as shown in the figure. It can happen that nothing happens. In particular, if the liquid is in a droplet state after landing, as shown in FIGS. 25B and 26B, the materials M and N may be mixed and integrated.

  In this embodiment, a pattern forming apparatus that discharges fluid droplets such as an ink jet method is used. However, the silver alloy material of the present invention can be used beneficially without using such a pattern forming apparatus. In this case, the TFT array substrate is manufactured by the most general method using a conventional sputtering method or vapor deposition method and photolithography in a corresponding process. However, wiring, electrodes, and the like formed by the silver alloy composition of the present invention are obtained using a sputtering target, a vapor deposition evaporation source, and the like instead of a fluid wiring material. Even in such a case, the silver alloy material of the present invention is beneficially used as a material having excellent process resistance such as heat resistance, adhesion, and plasma resistance and having low electric resistance.

  Note that the silver alloy material of the present invention can be beneficially used as a single layer in a multilayer wiring structure formed by superposing two or more layers of materials. For example, even when heat-fired at 300 ° C., the surface smoothness is not lost as in the case of silver alone, and particularly contains indium, and its content is relatively large, for example, 10% by weight with respect to silver. In some cases, it has sufficient plasma resistance and can be effectively used as a protective metal layer for protecting the underlying wiring. Further, it can be used as all or part of the source electrode 21 and the drain electrode wiring 22 for direct contact with the semiconductor layer 27 in Embodiment 1 to obtain electrical connection. Adhesive force is exerted, and it is beneficially used in the manufacturing process of the TFT array substrate.

  Alternatively, the silver alloy material of the present invention can also be used for a light reflective electrode on a TFT array substrate used in a reflective TFT liquid crystal display device or the like. In this case, due to the excellent heat resistance of the silver alloy material of the present invention, surface smoothness is not lost as in the case of single silver, even when heat-fired at 300 ° C., for example. Therefore, light scattering outside the design does not occur, and the characteristics as a TFT array substrate can be sufficiently exhibited, such as maintaining a sufficient light reflectance as a light reflective electrode.

Furthermore, the silver alloy material, the wiring configuration, and the wiring forming method of the present invention are also used as a bus electrode and a data electrode on a glass substrate constituting a PDP (plasma display panel). These electrodes are disposed on the front glass substrate or the rear glass substrate to drive the PDP, and conventionally have a silver, chrome / copper / chrome, or aluminum / chrome configuration. In order to improve the adhesion of copper and aluminum to the substrate and to take measures against differences in the expansion coefficient, it was impossible to use it unless a structure in which a chromium layer was sandwiched between the glass substrate in this way. On the other hand, conventional silver has a problem in heat resistance, and is a material that is difficult to use due to growth of crystal grains caused by high-temperature firing.
On the other hand, the silver alloy material of the present invention has excellent heat resistance and adhesion to a glass substrate, so that it can be used beneficially as a bus electrode and a data electrode in place of these conventional materials such as silver. It is done.

  The silver alloy material, the wiring configuration, and the wiring forming method of the present invention can also be used for a display device using EL (electroluminescence). In comparison with a liquid crystal display device, an EL display device may control the gradation of light emission luminance depending on the amount of current. In such a case, a low-resistance material is required for the current supply line that supplies current to the light-emitting elements forming the pixel. This is because power is consumed by the wiring resistance, resulting in poor light emission efficiency, heat generation of the display device, and spots on the display surface.

  In addition, a circuit substrate for driving an EL element is often formed using a TFT array, and may be manufactured through a process similar to that shown in this embodiment. Therefore, the contents described in this embodiment can be applied to a display device using an EL. In particular, the wiring used as the current supply line, the wiring material that is selectively low-resistance for the current supply line from the external circuit to the drive driver, that is, the silver alloy material whose indium content is 3% by weight with respect to silver is used. For the wire and terminal electrode, a material having an indium content of 10% by weight with respect to silver can be used.

  Furthermore, the silver alloy material, wiring configuration, and wiring forming method of the present invention can also be used as a wiring material for flexible substrates and glass epoxy substrates. The connection terminals on these boards are designed to increase the content of indium with respect to silver and place emphasis on oxidation resistance, and to reduce the content of indium to silver and use it as a low-resistance wiring in the internal wiring part. I can do it.

  Further, among the above silver alloy materials, in particular, when the content ratio of indium with respect to silver is 0.5% by weight or less, the electrical resistivity is 2.7 μΩcm or less, which is a low electric power that cannot be achieved by conventional aluminum wiring. Resistance wiring can be formed and is beneficial. However, since the indium content is low, the plasma resistance is not sufficient, and it is generally necessary to stack another metal film. The adhesion to the substrate is not sufficient because the content of indium is low, so that a base treatment or the like may be necessary. Therefore, even a silver alloy material having an indium content of 0.5% by weight or less with respect to silver can be used as a main wire of a circuit board by applying a base treatment.

  Below, the manufacturing method of a circuit board in case the content of indium with respect to silver is 0.5 weight% or less as a wiring material is demonstrated.

  In the gate wiring forming step 102 shown in FIG. 6, a pattern forming apparatus represented by an ink jet method is used, and wiring materials having different configurations are separately applied on the TFT array substrate 71. On the other hand, in the third embodiment, in the source / drain wiring forming step 106, different wiring materials having different configurations were applied.

  Here, in the gate wiring forming step 102, wiring and the like are formed by using a sputtering method, and these wirings and the like are laminated with the silver alloy material of the present invention and titanium.

  FIGS. 34A, 34B, and 35A, 35B are views showing a state in which the gate wiring forming step 102 is completed in the present embodiment. 34A and 35A are plan views of the pixel formation region 61 and the terminal portion formation region 62 on the glass substrate 12, respectively. 35 (b) and 36 (b) are a cross-sectional view taken along line MM and a cross-sectional view taken along line NN in FIGS. 34 (a) and 35 (a), respectively.

  In these drawings, the gate wiring 80, the gate electrode 81, the auxiliary capacitance line 82, and the terminal wiring 83 have the same laminated structure and are composed of two layers. Each layer 80a, 81a, 82a, 83a on the side close to the glass substrate 12 is made of the silver alloy of the present invention, and the content of indium with respect to silver is 0.2% by weight. Each of the upper layers 80b, 81b, 82b, and 83b is made of titanium. The film thickness was 0.2 μm for all of 80a, 81a, 82a, 83a, 80b, 81b, 82b, and 83b.

  Here, each of the layers 80a, 81a, 82a, and 83a on the side close to the glass substrate 12 is formed of an alloy made of silver and indium, and thus has heat resistance, and is fired at about 300 ° C. in a later step. However, the gate wiring 80 and the like are not adversely affected. In the case where these are formed with conventional silver alone, there is a lack of heat resistance, resulting in significant surface irregularities and a leak failure with the upper layer.

  If the silver alloy has an indium content of 0.5% by weight or less, the electrical resistivity is 2.7 μΩcm or less as described above, and it is possible to form a low electrical resistance wiring that cannot be realized with aluminum. It is. In this example, the electrical resistivity is as low as about 2.3 μΩcm. Therefore, when it is particularly desired to reduce the electrical resistance of the wiring, the silver alloy material of the present invention is a useful material in a liquid crystal display device such as for a liquid crystal TV.

  In this description, a method for forming the gate wiring 80 and the like will be described. Here, in the gate wiring formation process 102, since a pattern forming apparatus represented by an ink jet method is not used, a process corresponding to the gate wiring pretreatment process 101 is not performed.

  First, a silver alloy film containing 0.2% by weight of indium with respect to silver was formed to a thickness of 0.2 μm on the glass substrate 12 by sputtering. At this time, an alloy target in which indium was dissolved in silver was used as a sputtering target. Next, titanium was continuously formed in vacuum by sputtering. The film thus obtained was processed by photolithography to obtain a gate wiring as shown in FIGS. 34 (a) (b) and 35 (a) (b). A dry etching method was used for the etching at this time.

  The terminal wiring 83 and the like need to have plasma resistance in consideration of a later process, but in the present description, it is obtained by titanium on the upper layer side.

  Thus, the present silver alloy material may be used as a single layer in a multilayer wiring structure, and by reducing the indium content to 0.5% by weight or less with respect to silver, the low electric power that cannot be realized with conventional aluminum Resistive wiring is realized.

  In the above-described forming method, the silver alloy film of the present invention was formed directly on the glass substrate 12. However, when sufficient adhesion to the substrate cannot be obtained, an intermediate made of a metal or the like between the two is used. A layer may be provided, or the glass substrate may be surface-treated with plasma, chemicals, or the like to obtain adhesion.

  In the present invention, the material of each of the upper layers 80b, 81b, 82b, and 83b is not limited to titanium, but is chromium, molybdenum, tantalum, tungsten, a material containing nitrogen or oxygen therein, or ITO (indium tin). It may be a metal oxide such as (oxide). As described above, the gate wiring 80 and the like may be formed by applying a fluid wiring material and laminating it, or by forming and processing by an evaporation method using an evaporation source composed of silver and indium. It may be formed.

  In this description, in the gate wiring formation step 102, the wiring is formed by the film made of the silver alloy and titanium of the present invention. However, as another embodiment of the present invention, in the source / drain wiring formation step 106, similarly. A wiring made of a laminated film may be formed. Even in this case, since the alloy made of silver and indium has heat resistance, there is no adverse effect even if firing is performed in a later step.

  Even in this case, by setting the indium content to 0.5% by weight or less with respect to silver, it is possible to realize a low electrical resistance wiring that cannot be realized by conventional aluminum.

  Moreover, by containing indium with respect to silver, a film having a higher reflectance than aluminum can be formed when baked. In particular, when the wiring also serves as a reflector or a reflective electrode, the wiring may be formed of a silver alloy material containing 0.5% by weight or less of indium with respect to silver.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  The present invention can be applied to a circuit board capable of preventing the thin film from being multi-layered and suppressing an increase in the number of manufacturing steps and cost of the circuit board, particularly an electronic device (display device, liquid crystal display device) using the circuit board. it can.

It is a top view of the circuit board concerning one embodiment of the present invention. It is AA arrow sectional drawing of the circuit board of FIG. The terminal part vicinity of the circuit board shown in FIG. 1 is shown, (a) is a top view, (b) is the LL arrow directional cross-sectional view of (a). It is a top view of the TFT array substrate which shows an example of the circuit board shown in FIG. It is a schematic block diagram of the manufacturing apparatus for manufacturing the circuit board of this invention. It is process drawing which shows the manufacturing process of the circuit board of this invention. (A) is a plan view showing a pixel portion at the completion of the gate wiring pre-processing step, (b) is a plan view showing a pixel portion at the completion of the gate wiring formation step, and (c) is a CC line arrow in (b). FIG. (A) is a plan view showing a terminal part at the completion of the gate wiring pretreatment process, (b) is a plan view showing a terminal part at the completion of the gate wiring formation process, and (c) is a DD line arrow in (b). FIG. (A)-(d) is a figure which shows the formation process of the hydrophilic / water-repellent (lyophobic liquid) area | region in a gate wiring pre-process. It is a figure which shows the pixel part by the gate insulating film and semiconductor film formation process completion, (a) is a top view, (b) is the EE arrow directional cross-sectional view of (a). It is a figure which shows the terminal part in the gate insulating film and semiconductor film formation process completion, (a) is a top view, (b) is a FF arrow directional cross-sectional view of (a). It is a figure which shows the pixel part by the gate insulating film and semiconductor film processing process completion, (a) is a top view, (b) is a GG arrow directional cross-sectional view of (a). It is a figure which shows the terminal part in a gate insulating film and semiconductor film processing process completion, (a) is a top view, (b) is a HH arrow directional cross-sectional view of (a). (A) is a plan view of the pixel portion after completion of the source / drain wiring pre-processing step, (b) is a plan view of the pixel portion after completion of the source / drain wiring formation step, and (c) is a line II of FIG. FIG. FIG. 15 is a cross-sectional view taken along an arrow corresponding to the position of the line I-I in FIG. The pixel part by the channel part process process completion is shown, (a) is a top view, (b) is the JJ arrow directional cross-sectional view of (a). The terminal part by the completion of a channel part process process is shown, (a) is a top view, (b) is (a) KK arrow sectional drawing. The pixel part and the terminal part after the protective film processing step are shown, (a) is a cross-sectional view taken along the line JJ in FIG. 16 (a), and (b) is K-- in FIG. 17 (a). It is arrow sectional drawing equivalent to the position of K line. (A)-(e) is a figure which shows the formation process of the wiring part and terminal part of the circuit board of this invention. (A) is a figure which shows the state which forms the wiring part using the material M, (b) is a figure which shows the state which forms the terminal part using the material N. (A)-(c) is a figure which shows the state of the boundary part which the materials M and N contact. It is the schematic of the gate wiring in the circuit board of this invention. (A) is a figure which shows the conventional wiring pattern, (b) is a figure which shows the wiring pattern of this invention. (A) (b) is a figure which shows the other example of wiring formation in the circuit board of this invention. (A) (b) is a figure which shows the further another example of wiring formation in the circuit board of this invention. (A) (b) is a figure which shows the further another example of wiring formation in the circuit board of this invention. (A)-(c) is a figure which shows the further another example of wiring formation in the circuit board of this invention. It is a graph of the visible light reflectance of the silver film of the comparative example 1 shown in Table 1. It is a graph of the visible light reflectance of the aluminum film of the comparative example 3 shown in Table 1. It is a graph of the visible light reflectance of the silver alloy film (indium 0.05 weight%) of Example 7 shown in Table 1. It is a graph of the visible light reflectance of the silver alloy film (indium 0.2 weight%) of Example 8 shown in Table 1. It is a graph of the visible light reflectance of the silver alloy film (indium 0.5 weight%) of Example 3 shown in Table 1. It is a graph of the visible light reflectance of the silver alloy film (indium 1.6 weight%) of Example 4 shown in Table 1. (A) is a top view which shows the pixel part by the completion of a gate wiring formation process, (b) is the OO arrow directional cross-sectional view of (a). (A) is a top view which shows the terminal part by the completion of a gate wiring formation process, (b) is PP sectional view taken on the line of (a).

Explanation of symbols

1 Glass substrate (insulating substrate)
3 Transparent glass substrate (insulating substrate)
11 TFT array substrate (circuit board)
12 Glass substrate (insulating substrate)
13 Gate wiring (wiring)
14 Source wiring (wiring)
16 Auxiliary capacity wiring (wiring)
17 Gate electrode 18 Gate insulating layer 19 Amorphous silicon layer (semiconductor layer)
21 Source electrode 22 Drain electrode wiring 27 Semiconductor layer 28 Terminal part (terminal part)
29 Terminal electrode 30 Terminal wiring (wiring part)
31 Substrate (insulating substrate)
33 Inkjet head 33a First head 33b Second head 39 Terminal electrode 41 Gate wiring formation region 42 Gate electrode formation region 43 Auxiliary capacitance wiring formation region 44 Terminal wiring formation region 45 Gate insulating film 46 Amorphous silicon film 49 Opening 51 Channel portion 52 Wiring guide 55 Silicon nitride film 56 Opening 61 Pixel formation area 62 Terminal area formation 101 Gate wiring pretreatment process 102 Gate wiring formation process 103 Gate insulating film / semiconductor film forming process 104 Gate insulating film / semiconductor film processing process 105 Source Drain wiring pre-processing process 106 Source / drain wiring forming process 107 Channel portion processing process 108 Protective film / interlayer insulating film forming process 109 Protective film processing process 110 Pixel electrode forming process M material N material P boundary portion

Claims (15)

In a circuit board having wiring formed on a substrate,
A circuit board characterized in that characteristics of at least two portions on the same wiring are different from each other. In a circuit board having wiring formed on a substrate,
A circuit board, wherein the composition ratios of at least two portions on the same wiring are different from each other. In a circuit board having wiring formed on a substrate,
A circuit board characterized in that constituent materials of at least two portions on the same wiring are different from each other.   4. The circuit board according to claim 1, wherein the same wiring is formed as a single layer.   4. The circuit board according to claim 1, wherein the same wiring is formed in multiple layers.   6. The circuit board according to claim 1, wherein the wiring is made of a metal whose main material is silver, aluminum, or copper.   The wiring includes at least aluminum, indium, tin, bismuth, gallium, lead, copper, gold, silver, cobalt, nickel, palladium, platinum, rhodium, vanadium, titanium, zirconium, niobium, tantalum, tungsten, hafnium. The circuit board according to claim 6, wherein the circuit board is made of an alloy containing one or more kinds of metals selected from osmium, osmium, and iridium.   8. The circuit board according to claim 7, wherein the wiring is formed of a silver indium alloy containing indium with silver as a main material.   The circuit board according to claim 8, wherein the content of indium with respect to silver is 0.5 wt% or more and 28 wt% or less.   The circuit board according to claim 1, wherein the wiring is formed of a fluid material including a conductor material.   The circuit board according to claim 10, wherein each of the flowable materials including the conductive material used for the portions having different characteristics includes a solvent and an organic substance of the same system. It is a manufacturing method of the circuit board according to claim 10,
A method of manufacturing a circuit board, wherein the wiring is formed by an inkjet method.   An electronic device comprising the circuit board according to claim 1.   12. A display device using the circuit board according to claim 1 as a circuit board for display.   12. A liquid crystal display device, wherein the circuit board according to claim 1 is used as a circuit board for liquid crystal display.

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