JP2005057138A - Protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protection circuit having a small pattern area for countermeasure of an electrostatic discharge damage capable of passing an electrostatic discharge damage test of a human body model and a machine model. <P>SOLUTION: The protection circuit has an electrode pad 10 to which an input signal is applied, a polysilicon resistor 11 with its one end connected to the pad 10, an N-channel type MOS transistor M3 with its drain connected to the other end of the resistor 11 and with its source and gate grounded, a first NPN-type bipolar transistor B1 with its base and emitter connected to a connecting point of the pad 10 and the resistor 11 and with its collector applied by a power voltage Vcc, and a second NPN-type bipolar transistor B2 with its collector connected to a connecting point of the pad 10 and the resistor 11 and with its base and emitter grounded. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a protection circuit, and more particularly to a protection circuit for measures against electrostatic breakdown of a semiconductor integrated circuit.

  Conventionally, an input circuit of a semiconductor integrated circuit has been provided with a protection circuit for preventing electrostatic breakdown.

  FIG. 4 is a circuit diagram showing an example of such a protection circuit.

  In FIG. 4, 10 is an electrode pad to which an input signal is applied, 11 is a polysilicon resistor, and one end thereof is connected to the electrode pad 10. Reference numeral 12 denotes an inverter, and the input signal is input via the polysilicon resistor 11.

  M1 is a P-channel MOS transistor, its drain is connected to the connection point between the electrode pad 10 and the polysilicon resistor 11, the gate and source are connected in common, and the power supply voltage Vcc is applied. M2 is an N-channel MOS transistor, the drain of which is connected to the connection point between the electrode pad 10 and the polysilicon resistor 11, and the gate and source of which are grounded. The other end of the polysilicon resistor 11 is connected to the inverter 12.

  M3 is an N-channel MOS transistor whose drain is connected to the other end of the polysilicon resistor 11 and whose gate and source are grounded.

  In this protection circuit, the polysilicon resistor 11 limits the surge current applied to the electrode pad 10 and suppresses an excessive voltage from being applied to the drain of the N-channel MOS transistor M3. In general, since the polysilicon resistor 11 is formed on the field oxide film, a protective element is required before the polysilicon resistor 11 in order to prevent the field oxide film from being destroyed.

  Therefore, in this protection circuit, a P-channel MOS transistor M1 and an N-channel MOS transistor M2 are provided as such protection elements.

In addition, there exist the following patent documents 1, 2, and 3 as a prior art document.
Japanese Patent Publication No. 8-21632 Japanese Patent No. 2725359 JP 2001-44374 A

  By the way, the human body model (MIL standard, 100 PF, 1.5 kΩ, strength 2000 V or more) and the machine model (EIAJ standard, 200 PF, 0 Ω, strength 200 V or more) are used for the electrostatic breakdown test to confirm the effect of countermeasures against electrostatic breakdown. There is. However, when the electrostatic breakdown test using the human body model is performed in the protection circuit of FIG. 4, there is a problem that the P-channel MOS transistor M1 and the N-channel MOS transistor M2 are destroyed.

  In order to prevent electrostatic breakdown of the polysilicon resistor 11, the size of the P-channel MOS transistor M1 and the N-channel MOS transistor M2 must be very large, which increases the pattern area of the protection circuit. I was invited.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a protection circuit that passes the electrostatic breakdown test of both the human body model and the machine model and has a small pattern area.

  The protection circuit of the present invention includes an electrode pad, a polysilicon resistor having one end connected to the electrode pad, an N-channel MOS transistor having a drain connected to the other end of the polysilicon resistor, and a source and a gate grounded. And an NPN bipolar transistor connected to a connection point between the electrode pad and the polysilicon resistor.

  According to the present invention, an NPN bipolar transistor for protecting the polysilicon resistance is provided in addition to the polysilicon resistance and the N-channel type MOS transistor, so that both the human body model and the machine model pass the electrostatic breakdown test. In addition, a protection circuit with a small pattern area can be provided.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a protection circuit according to the first embodiment.

  In FIG. 1, 10 is an electrode pad to which an input signal is applied, 11 is a polysilicon resistor, and one end thereof is connected to the electrode pad 10. Reference numeral 12 denotes an inverter, and the input signal is input via the polysilicon resistor 11. The inverter 12 is a CMOS inverter, for example.

  B1 is an NPN-type first bipolar transistor, the collector of which is applied with the power supply voltage Vcc, the base and the emitter are connected in common and connected to the connection point between the electrode pad 10 and the polysilicon resistor 11. B2 is an NPN-type second bipolar transistor, the collector of which is connected to the connection point between the electrode pad 10 and the polysilicon resistor 11, and the base and emitter of which are grounded. The other end of the polysilicon resistor 11 is connected to the input terminal of the inverter 12.

  M3 is an N-channel MOS transistor whose drain is connected to the other end of the polysilicon resistor 11 and whose gate and source are grounded.

  According to this embodiment, since the first NPN type bipolar transistor B1 and the second NPN type bipolar transistor B2 are directly connected to the electrode pad 10, it is possible to ensure the electrostatic breakdown strength by the human body model. This is because the NPN bipolar transistor does not have a gate oxide film, so that the oxide film does not break down.

  In addition, an NPN-type bipolar transistor can pass a large current with a small pattern area as compared with a MOS transistor.

  The operation of the protection circuit according to the present embodiment will be described. When a surge voltage is applied to the electrode pad 10, a current flows through the first NPN type bipolar transistor B1 or the second NPN type bipolar transistor B2. The surge voltage applied to the polysilicon resistor 11 is attenuated, and the field oxide film below the polysilicon resistor 11 described later is prevented from being destroyed.

  Then, the polysilicon resistor 11 further attenuates the surge voltage and limits the current. The resistance value of the polysilicon resistor 11 is suitably 1 kΩ.

  The source-drain breakdown voltage BVDS of the N-channel MOS transistor M3 is preferably set lower than the gate oxide breakdown voltage of the MOS transistor of the inverter 12. As a result, a current flows through the N-channel MOS transistor before the gate oxide film breaks down, so that the gate oxide film can be prevented from being broken.

  Here, when the gate oxide breakdown voltage is 17V, the source-drain breakdown voltage BVDS is preferably about 10V.

Next, a second embodiment of the present invention will be described with reference to FIG. This protection circuit is obtained by adding a P-channel MOS transistor M4 to the protection circuit of FIG. Thereby, the gate oxide breakdown strength of the MOS transistor of the inverter 12 is further improved. FIG. 3 is a cross-sectional view when the protection circuit according to the first and second embodiments is configured as a semiconductor integrated circuit.

  FIG. 3 shows a cross-sectional structure of an NPN-type bipolar transistor B2, an N-channel MOS transistor M3, and a polysilicon resistor 11.

  First, the NPN bipolar transistor B2 will be described.

  Reference numeral 20 denotes a P-type silicon substrate, and an N-type epitaxial layer 23 is formed on the P-type silicon substrate 20. 22-1 is a first P + type lower isolation layer, 22-2 is a second P + type lower isolation layer, and 21 is an N + type buried layer. Between the P type silicon substrate 20 and the N type epitaxial layer 23, Embedded. 24-1 is a first P + type upper separation layer, and is in contact with the first P + type lower separation layer 22-1. Reference numeral 24-2 denotes a second P + type upper separation layer, which is in contact with the second P + type lower separation layer 22-2. A collector layer 25 is formed on the surface of the N type epitaxial layer 23. The collector layer 25 is connected to the electrode pad 10 and applied with an input signal. A base layer 26 is formed on the surface of the N-type epitaxial layer 23. An emitter layer 27 is formed in the base layer 26. The base layer 26 and the emitter layer 27 are grounded.

  Thus, the NPN bipolar transistor B2 has a vertical bipolar transistor configuration and a large current capacity.

  Next, the N channel type MOS transistor M3 will be described.

  Reference numeral 22-3 denotes a P + type lower separation layer, which is formed on the P type silicon substrate 20. 24-3 is a P + type well, which is formed on the P + type lower separation layer 22-3. A drain 29 is formed on the surface of the P + type well 24-3. The drain 29 is connected to the inverter 12. Reference numeral 30 denotes a source, which is formed on the surface of the P + type well 24-3. A gate electrode 28 is formed on the gate oxide film. The source 30 and the gate electrode 28 are grounded.

  A field oxide film 32 separates the transistors. Reference numeral 11 denotes a polysilicon resistor, which is formed on the field oxide film 32. One end of the polysilicon resistor 11 is connected to a connection point between the electrode pad 10 and the collector layer 25. The other end of the polysilicon resistor 11 is connected to a connection point between the inverter 12 and the drain 29.

  31 is a P + layer formed on the surface of the P + type well 24-3, and the P + layer 31 is a diffusion layer for setting the potential of the P + type well 24-3. In the first and second embodiments, instead of the inverter 12, another input circuit that receives an input signal at the gate may be used.

1 is a circuit diagram of a protection circuit according to a first embodiment of the present invention. It is a circuit diagram of the protection circuit which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the protection circuit which concerns on the 1st and 2nd embodiment of this invention. It is a circuit diagram of the protection circuit which concerns on a prior art example.

Claims (6)

An electrode pad; a polysilicon resistor having one end connected to the electrode pad; an N-channel MOS transistor having a drain connected to the other end of the polysilicon resistor and a source and a gate grounded; and the electrode pad and the polysilicon A protection circuit comprising an NPN-type bipolar transistor connected to a connection point with a silicon resistor. 2. The protection circuit according to claim 1, further comprising a P-channel MOS transistor having a drain connected to the other end of the polysilicon resistor and a power supply voltage applied to the source and gate. 2. The protection circuit according to claim 1, wherein the bipolar transistor has a collector connected to the connection point and a base and an emitter grounded. 2. The protection circuit according to claim 1, wherein the bipolar transistor has a collector connected to a power supply voltage and a base and an emitter connected to the connection point. An electrode pad; a polysilicon resistor having one end connected to the electrode pad; an N-channel MOS transistor having a drain connected to the other end of the polysilicon resistor and a source and a gate grounded; and the electrode pad and the polysilicon A base is connected to the connection point between the silicon resistor and a collector is connected to the connection point between the first NPN-type bipolar transistor whose collector is connected to the power supply voltage and the electrode pad and the polysilicon resistor. And a second NPN-type bipolar transistor, which is grounded. 6. The protection circuit according to claim 5, further comprising a P-channel MOS transistor having a drain connected to the other end of the polysilicon resistor and a power supply voltage applied to the source and gate.

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