JP2005044873A - Method for manufacturing semiconductor device, and semiconductor device - Google Patents

Method for manufacturing semiconductor device, and semiconductor device Download PDF

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Publication number
JP2005044873A
JP2005044873A JP2003200870A JP2003200870A JP2005044873A JP 2005044873 A JP2005044873 A JP 2005044873A JP 2003200870 A JP2003200870 A JP 2003200870A JP 2003200870 A JP2003200870 A JP 2003200870A JP 2005044873 A JP2005044873 A JP 2005044873A
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Japan
Prior art keywords
substrate
semiconductor region
forming
insulating film
conductivity type
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Pending
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JP2003200870A
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Japanese (ja)
Inventor
Isao Arai
Yutaka Hoshino
Masatoshi Morikawa
Hiroyuki Nagai
Masao Yamane
正雄 山根
功 新井
裕 星野
正敏 森川
浩之 長井
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Renesas Technology Corp
株式会社ルネサステクノロジ
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can realize a laterally diffused MOS (LDMOS) obtaining a mutual conductance (Gm) which is relatively high and whose Vg dependence is relatively small in a wide range of Vg. <P>SOLUTION: A gate insulated film 6a is formed on a main surface of a semiconductor layer 1b. After a gate electrode 7 is formed on the gate insulated film 6a, impurity ions are introduced in the semiconductor layer 1b, and an n<SP>+</SP>type semiconductor region 9 is formed in the semiconductor layer 1b on the drain side of an LDMOS. After that, an insulation film 12 is formed on the semiconductor layer 1b and, in this state, impurity ions are introduced in the semiconductor layer 1b. A p<SP>+</SP>type semiconductor region 13 is formed in the semiconductor layer 1b of the drain side of the LDMOS, thereby arranging a high concentration layer constituted of an n<SP>+</SP>type semiconductor layer 9 in the semiconductor layer 1b of the drain side under an end portion of the gate electrode 7. A low concentration layer constituted of an n<SP>-</SP>type semiconductor region 9 is arranged in a region where the n<SP>+</SP>type semiconductor region 9 and the p<SP>+</SP>type semiconductor region 13 overlap. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device technology, and more particularly, to a method for manufacturing a semiconductor device having a lateral field effect transistor (Lateral Diffused Metal Oxide Semiconductor Field Effect Transistor: LDMOS-FET) and the semiconductor device. It relates to effective technology.
[0002]
[Prior art]
LDMOS FET (hereinafter simply referred to as LDMOS) brings various advantages such as simplification of the bias circuit and high power gain, and in recent years, instead of bipolar transistors, mobile phone base stations or digital TV broadcast station transmitters. Is used for high frequency power amplification.
[0003]
LDMOS is p + N is formed in the p epitaxial layer grown on the substrate and reaches the gate and the gate end. + N reaching the source region, below the gate edge Drain region, n from gate edge N separated by the drain region + Drain region, n + A p-well surrounding the source region and the channel region is formed. As described above, in the LDMOS, in order to avoid electric field concentration on the drain side as a countermeasure against gate breakdown voltage and hot electrons, an n-type impurity concentration is relatively low on the drain side. A drain region is provided, and the source side and the drain side have an asymmetric structure.
[0004]
For example, the offset region is an arsenic dose of 5 × 10 12 cm -2 Is implanted into the upper surface of the silicon substrate to a length of 0.4 μm in the surface direction from the gate electrode, and the intermediate concentration layer has an arsenic dose of 2 × 10 14 cm -2 A high breakdown voltage MOSFET is disclosed which is formed by ion implantation and is inserted on the upper surface of a silicon substrate with a length of 10 μm between a gate insulating film and an offset region (see, for example, Patent Document 1).
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-186543
[0006]
[Problems to be solved by the invention]
In an LDMOS that constitutes an amplifier of an RF power module, (1) downsizing, (2) relatively high mutual conductance (hereinafter referred to as Gm), and (3) Gm with small gate bias dependency are required. By the way, in recent years, the GSM / EDGE (Enhances Data GSM Environment) system has begun to replace the GSM (Global System for Mobile Communication) system as a wireless communication system for digital mobile phones. Similar to the (Access) method, importance is attached to the linearity of Gm. Here, the linearity means that the harmonic distortion of the signal at the time of amplification is small, and it is desirable for LDMOS that Gm, which is the basis of amplification, is substantially constant regardless of the signal amplitude. That is, in the relationship between the gate bias (hereinafter referred to as Vg) of LDMOS and Gm, it is important to obtain a substantially constant Gm over a wide range of Vg.
[0007]
However, n + Source consisting of source region and n And n + In the LDMOS having a drain composed of a drain region, the present inventors have found the following problems.
[0008]
FIG. 15 shows the relationship between Gm and Vg of the LDMOS having a gate length of 0.3 μm and the LDMOS having a gate length of 0.23 μm investigated by the present inventors. As shown in the figure, when the gate length of the LDMOS is reduced from 0.3 μm to 0.23 μm with the power supply voltage kept constant, the electric field strength in the traveling direction increases and the electron traveling speed improves, and the LDMOS Gm improves. To do. However, in an LDMOS with a gate length of 0.23 μm, Gm decreases as Vg increases in the operating region in the power stage that handles large signals, and Gm varies greatly according to changes in Vg.
[0009]
An object of the present invention is to provide a technique capable of realizing an LDMOS that can obtain a relatively high Gm with a relatively high Vg dependency in a wide range of Vg.
[0010]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0011]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0012]
The present invention includes a step of forming a gate insulating film on a p-type substrate, a step of forming a gate electrode on the gate insulating film, and introducing an n-type impurity into the substrate to thereby form a substrate on the drain side of the LDMOS. n + Forming a first semiconductor region of the mold, forming an insulating film on the substrate, and introducing a p-type impurity into the substrate in a state where the insulating film is formed, thereby forming a p-type impurity on the drain-side substrate of the LDMOS. + Forming a second semiconductor region of the type, and forming n on the drain side substrate under the end of the gate electrode + A high concentration layer composed of a first semiconductor region of the type + Type first semiconductor region and p + N in the region overlapping the second semiconductor region of the mold A step of disposing a low-concentration type layer, and introducing an n-type impurity into the substrate, so that an n-type impurity is applied to the substrate on the drain side of the LDMOS. + Forming a third semiconductor region of the mold at a predetermined distance from the end of the gate electrode on the drain side.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
[0014]
(Embodiment 1)
First, an estimated cause of Gm degradation found by the present inventors will be described. In LDMOS, when Vg is gradually increased to the + side, the electron concentration immediately below the gate gradually increases, and n This is equivalent to the electron concentration in the drain region. At that time, n When the drain voltage drop in the drain region becomes large and seen from the electrons in the channel, it appears as if n A long gate effect appears in which the electric field distribution changes as if the region combined with the drain region is under the gate.
[0015]
By the way, the lateral electric field E applied to the channel by the drain voltage is generally represented by the formula (1).
[0016]
E = Vds / d Formula (1)
Here, Vds is a drain voltage, and d is an effective channel length. When the drain voltage is constant, the lateral electric field decreases as the effective channel length increases. In the long gate effect, when Vg increases, the drain voltage to be applied to both ends of the gate is n It is applied to a wide region including the drain region. This increases the effective channel length and reduces the lateral electric field applied to the channel under the gate.
[0017]
Gm is generally represented by the formula (2).
[0018]
Gm = q · Ns · W · V (E) Equation (2)
Here, Ns is the charge density, and W is the channel width. As shown in FIG. 1, V (E) is an electron drift velocity expressed as a function of the lateral electric field, and V (E) decreases as the lateral electric field decreases. For this reason, when Vg is large, the lateral electric field becomes small due to the long gate effect, the improvement of the average electron traveling speed cannot be obtained, and Gm is considered to deteriorate.
[0019]
Therefore, in the first embodiment, a method for realizing an LDMOS capable of suppressing the long gate effect will be described. Hereinafter, a method for manufacturing the n-channel type LDMOS according to the first embodiment will be described in the order of steps with reference to cross-sectional views of relevant parts of the semiconductor substrate shown in FIGS. Note that n-channel LDMOS is abbreviated as nLDMOS.
[0020]
First, as shown in FIG. 2, a substrate 1 is prepared. The substrate 1 at this stage is made of a substantially circular member called a semiconductor wafer, and includes a substrate body 1a, a semiconductor layer 1b formed on the main surface thereof, and an insulating layer 2 formed on the back surface of the substrate body 1a. have. The substrate body 1a is formed by a crystal pulling method such as the Czochralski method. + It is made of a single type silicon crystal, and its resistivity is, for example, about 3 to 6 mΩcm. The semiconductor layer 1b is made of, for example, a p-type silicon single crystal formed by an epitaxial method, and has a thickness of, for example, about 3 μm and a resistivity of, for example, about 18 Ωcm to 23 Ωcm. The insulating layer 2 on the back surface of the substrate 1 has a function of protecting the back surface of the substrate 1 from contamination and breakage.
[0021]
Next, after a resist pattern is formed on the main surface of the semiconductor layer 1b by photolithography, p-type impurity ions such as boron are selectively introduced into the semiconductor layer 1b using the resist pattern as a mask. P ++ A type semiconductor region 3 is formed. This p ++ The semiconductor region 3 of the mold is formed so as to reach from the main surface of the semiconductor layer 1b to the substrate body 1a, and is electrically connected to the substrate body 1a. Thereafter, after removing the resist pattern, a field insulating film 4 made of, for example, silicon oxide is formed on the main surface of the semiconductor layer 1b by a LOCOS (Local Oxidation of Silicon) method. The region where the field insulating film 4 is formed can be defined as an isolation region, and the other region can be defined as an element formation region (active region).
[0022]
Next, after a resist pattern is formed on the main surface of the semiconductor layer 1b by photolithography, p-type impurity ions such as boron are selectively introduced into the semiconductor layer 1b using the resist pattern as a mask. Thus, the p-well 5 is formed. The p-well 5 is also a part that becomes a channel region of the nLDMOS.
[0023]
Next, as shown in FIG. 3, the substrate 1 is subjected to a cleaning process to expose the main clean surface of the semiconductor layer 1b, for example, by performing a wet oxidation process to activate the semiconductor layer 1b. A gate insulating film 6a made of, for example, silicon oxide having a thickness of about 11 nm is formed on the region main surface. Subsequently, a conductor film such as low-resistance silicon polycrystal, a silicide film such as tungsten silicide, and a cap insulating film such as silicon oxide are sequentially formed on the main surface of the substrate 1 from the lower layer by CVD (Chemical Vapor). After deposition by a deposition method or the like, the gate electrode 7 and the cap insulating film 8 made of a conductor film and a silicide film are formed by patterning the deposited film by a photolithography technique and a dry etching technique. The gate length of the gate electrode 7 is relatively short, for example, about 0.2 μm. By making the gate length relatively short, the traveling speed of electrons under the gate electrode 7 is increased and Gm is improved.
[0024]
Thereafter, a light oxidation process is performed on the substrate 1 to repair the end portion of the gate insulating film 6a slightly etched in the step of forming the gate electrode 7. At this time, the gate insulating film 6 b is formed on the active region main surface of the substrate 1 around the gate electrode 7.
[0025]
Next, as shown in FIG. 4, a resist pattern RP <b> 1 is formed on the main surface of the substrate 1 so that the drain region of the nLDMOS is exposed and the others are covered by a photolithography technique. For example, an n-type impurity such as phosphorus is ion-implanted into the semiconductor layer 1b so that the drain region has n. + A type semiconductor region 9 is formed. n + The type semiconductor region 9 is formed so that its end portion overlaps (substantially matches) the drain side end portion of the gate electrode 7. The impurity ion implantation energy at this time is, for example, about 40 KeV, and the dose amount is, for example, 1 × 10. 14 cm -2 The range and the range are, for example, about 50 nm and n + The depth of the type semiconductor region 9 from the surface of the substrate 1 is, for example, about 70 nm. Subsequently, the resist pattern RP1 is removed.
[0026]
Next, as shown in FIG. 5, a resist pattern RP2 is formed on the main surface of the substrate 1 so that the source region of the nLDMOS is exposed and the others are covered by photolithography, and this is used as a mask. For example, an n-type impurity such as arsenic is ion-implanted into the semiconductor layer 1b so that a shallow n region is formed in the source region. + A type semiconductor region 10 is formed. n + The type semiconductor region 10 is formed so that its end portion overlaps (substantially matches) the source side end portion of the gate electrode 7. Subsequently, by using the resist pattern RP2 as a mask, a p-type impurity such as boron is ion-implanted into the semiconductor layer 1b, whereby n + P at the bottom of the semiconductor region 10 of the type A mold-shaped halo layer 11 is formed. p The type halo layer 11 is a region that suppresses or prevents the short channel effect, and in this impurity introduction step, impurity ions are implanted from a direction oblique to the main surface of the substrate 1. Thereafter, the resist pattern RP2 is removed, and then the substrate 1 is subjected to an annealing treatment such as RTA (Rapid Thermal Anneal).
[0027]
Next, as shown in FIG. 6, a thin insulating film 12 made of, for example, silicon oxide or the like is deposited on the main surface of the substrate 1 by a CVD method or the like. The thickness of the insulating film 12 is, for example, about 10 to 30 nm. Subsequently, a resist pattern RP3 is formed by photolithography so that the drain region of the nLDMOS is exposed and the others are covered, and using this as a mask, a p-type impurity such as boron is ion-implanted into the semiconductor layer 1b. P in the drain region + A mold type semiconductor region 13 is formed. p + The type semiconductor region 13 is formed such that the end thereof is separated from the gate electrode 7 by the insulating film 12. At this time, the implantation energy of impurity ions is, for example, about 15 KeV, and the dose amount is, for example, 0.9 × 10. 14 cm -2 The range and the range are, for example, about 50 nm and p + The depth of the type semiconductor region 13 from the surface of the substrate 1 is, for example, about 75 nm. Subsequently, the resist pattern RP3 is removed.
[0028]
Here, the dose in the impurity introduction step is 1 × 10 14 cm -2 Degree n + The type semiconductor region 9 is formed so that the end thereof overlaps the end of the gate electrode 7 on the drain side, and the dose in the impurity introduction step is 0.9 × 10 14 cm -2 Degree p + The type semiconductor region 13 is formed such that the end thereof is separated from the gate electrode 7 by the insulating film 12. Therefore n + Type semiconductor region 9 and p + In the region where the semiconductor region 13 of the type overlaps, the low concentration layer (n Type semiconductor region) and n + Type semiconductor region 9 and p + N-type semiconductor region 13 that does not overlap, that is, between the low-concentration layer and the channel region under gate electrode 7 with a width of about 10 to 30 nm. + The type semiconductor region 9 remains, and a high concentration layer (indicated by hatching in the drawing) having an impurity concentration about one digit higher than that of the low concentration layer is formed.
[0029]
Therefore, even if Vg is increased during the operation of the nLDMOS, the high concentration layer (n + The long gate effect can be suppressed by the type semiconductor region 9), and the deterioration of Gm can be prevented. That is, the influence of the potential change of Vg is applied to the high concentration layer (n + N can be shielded by the semiconductor region 9) of the mold + Type semiconductor region 9 impurity and p + The low concentration layer formed by the mutual cancellation of the impurities in the semiconductor region 13 of the type can be seen as a constant resistor regardless of Vg. On the other hand, in the drain region, a structure in which the drain breakdown voltage is increased by the low concentration layer can be maintained.
[0030]
Next, as shown in FIG. 7, on the main surface of the substrate 1, a source pattern and a drain region (a part slightly apart from the end of the gate electrode 7) are exposed, and the other resist pattern RP4 is covered. Then, using this as a mask, n-type impurities such as arsenic are ion-implanted into the semiconductor layer 1b. As a result, drain n is formed on the semiconductor layer 1b. + Type semiconductor region 14a and n for source + A type semiconductor region 14b is formed. N for drain + The end of the type semiconductor region 14 a is formed at a position away from the gate electrode 7 by a predetermined distance. N for source + Type semiconductor region 14b has an end n + It is formed at a position separated from the gate electrode 7 by 10 minutes of the type semiconductor region. An nLDMOS is formed as described above. Subsequently, the resist pattern RP4 is removed.
[0031]
Next, as shown in FIG. 8, a resist pattern (not shown) in which a part of the LDMOS formation region is exposed on the main surface of the substrate 1 while the insulating film 12 is left, and the others are covered. Then, using this as a mask, a p-type impurity such as boron is ion-implanted into the semiconductor layer 1b, thereby forming a p-type impurity in the nLDMOS formation region. + A mold type semiconductor region 15 is formed. This p + Type semiconductor region 15 is p + It is connected to the semiconductor region 3 of the mold, and is electrically connected to the substrate body 1a through this.
[0032]
Next, as shown in FIG. 9, after removing the resist pattern, the substrate 1 is subjected to an annealing treatment such as RTA. Subsequently, an insulating film 16 made of, for example, silicon oxide is deposited on the main surface of the substrate 1 while leaving the insulating film 12 by a CVD method or the like, and then the insulating films 16 and 12 and the gate insulating film 6b are formed on the semiconductor layer 1b. The reaching contact hole CNT is formed by a photolithography technique and a dry etching technique. Subsequently, a titanium nitride film, for example, is deposited on the main surface of the substrate 1 by a sputtering method, and a tungsten film is further deposited thereon by a CVD method or the like, and then the tungsten film is etched back, whereby the inside of the contact hole CNT. The plug PL is formed in
[0033]
Next, on the main surface of the substrate 1, for example, a titanium film, an aluminum-silicon-copper alloy film, a titanium film, and a titanium nitride film are sequentially deposited by sputtering from the lower layer. Subsequently, the laminated film is patterned by a photolithography technique and a dry etching technique to form the first layer wiring M1. Thereafter, the amplifier semiconductor chip is manufactured through a normal semiconductor device manufacturing process. Thereafter, the semiconductor chip is mounted on the module substrate together with other semiconductor chips and electronic components to assemble the RF power module.
[0034]
FIG. 10 shows a high concentration layer (n) under the end of the gate electrode 7 on the drain side according to the first embodiment. + The relationship between Gm and Vg of an LDMOS having a gate length of 0.23 μm provided with a type semiconductor region 9) is shown. For comparison, the relationship between Gm and Vg of an LDMOS having a gate length of 0.23 μm without the high concentration layer is shown. In an LDMOS not provided with a high-concentration layer, Gm decreases as Vg increases in the operating region in the power stage that handles large signals, and Gm varies greatly according to changes in Vg. On the other hand, in an LDMOS provided with a high concentration layer, the relationship between Gm and Vg has a flatter characteristic.
[0035]
In the first embodiment, n + In the impurity introduction step for forming the semiconductor region 9 of the type, the impurity ion implantation energy is 40 keV and the dose amount is 1 × 10 14 cm -2 And p + Impurity ion implantation energy is 15 keV and dose is 0.9 × 10 6 in the impurity introduction step for forming the semiconductor region 13 of the type. 14 cm -2 However, the present invention is not limited to this, and the respective conditions of the impurity introduction process are adjusted so that desired impurity concentrations and depths can be obtained in the low concentration layer and the high concentration layer formed on the drain side, respectively. be able to.
[0036]
Thus, according to the first embodiment, the gate length of the gate electrode 7 is relatively shortened, and the high concentration layer (n + Gm having a relatively high and relatively low Vg dependence in a wide range of Vg can be obtained by forming a type semiconductor region 9) and suppressing the long gate effect during the operation of the nLDMOS. .
[0037]
(Embodiment 2)
A manufacturing method of the n-channel type LDMOS which is the second embodiment will be briefly described with reference to cross-sectional views of the main part of the semiconductor substrate shown in FIGS. Here, n ions are separated by utilizing the sidewall formed on the sidewall of the gate electrode of the LDMOS, thereby forming an n layer on the semiconductor layer below the end of the gate electrode on the drain side. + A high concentration layer of the mold is formed.
[0038]
First, as shown in FIG. + A substrate 1 made of a silicon single crystal of a type, for example, a substrate body 1a having a resistivity of about 5 mΩcm, and a semiconductor layer 1b made of a p-type silicon single crystal, for example, having a thickness of about 2 μm is prepared. Subsequently, in the same manner as in the first embodiment, p ++ After sequentially forming the type semiconductor region 3 and the p-well 5, a gate insulating film 6 made of, for example, silicon oxide having a thickness of about 11 nm is formed on the semiconductor layer 1b, and further, for example, a gate length of about 0.2 to 0.25 μm. The gate electrode 7 is formed.
[0039]
Next, n is formed in the drain region of the semiconductor layer 1b. + A type semiconductor region 17 is formed by ion implantation of n-type impurities. n + The type semiconductor region 17 is formed so that its end portion overlaps (substantially coincides) with the drain side end portion of the gate electrode 7. The impurity ion implantation energy at this time is, for example, about 40 KeV, and the dose amount is, for example, 1 × 10. 14 cm -2 Degree. Subsequently, a shallow n is formed in the source region of the semiconductor layer 1b. + Type semiconductor region 10 is formed, and n + P at the bottom of the semiconductor region 10 of the type A mold-shaped halo layer 11 is formed. n + The type semiconductor region 10 is formed so that its end portion overlaps (substantially matches) the drain measurement end portion of the gate electrode 7.
[0040]
Next, as shown in FIG. 12, after an insulating film made of, for example, silicon oxide is deposited on the main surface of the substrate 1 by a CVD method or the like, the insulating film is etched and side walls are formed on the side walls of the gate electrode 7. A wall 18 is formed. The spacer length of the sidewall 18 is, for example, about 10 to 30 nm. Subsequently, a resist pattern RP5 is formed by photolithography so that the drain region of the nLDMOS is exposed and the others are covered, and using this as a mask, a p-type impurity such as boron is ion-implanted into the semiconductor layer 1b. P in the drain region + A type semiconductor region 19 is formed. p + The end of the type semiconductor region 19 is formed at a position separated from the gate electrode 7 by the side wall 18. At this time, the implantation energy of impurity ions is, for example, about 15 KeV, and the dose amount is, for example, 0.9 × 10. 14 cm -2 Degree. Subsequently, the resist pattern RP5 is removed.
[0041]
As a result, n + Type semiconductor region 17 and p + In the region overlapping with the semiconductor region 19 of the type, a low concentration layer (n Type semiconductor region) and n + Type semiconductor region 17 and p + N-type semiconductor region 19 that does not overlap, that is, between the low-concentration layer and the channel region under gate electrode 7, has a width of about 10 to 30 nm. + A high-concentration layer (indicated by hatching in the figure) made of the semiconductor region 17 of the mold is formed.
[0042]
Next, as shown in FIG. 13, in the same manner as in the first embodiment, n for drain is formed in the semiconductor layer 1b. + Type semiconductor region 14a and n for source + A type semiconductor region 14b is formed. An nLDMOS is formed as described above. Then p + P connected to the semiconductor region 3 of the type + A type semiconductor region 15 is formed in the semiconductor layer 1b.
[0043]
Next, as shown in FIG. 14, the first layer wiring M1 is formed, and further the second layer wiring M2 is formed thereon. Thereafter, the second-layer wiring M <b> 2 is covered with the insulating film 20, and then the back surface source electrode 21 is formed on the back surface of the substrate 1.
[0044]
As described above, according to the second embodiment, the sidewall 18 formed on the side wall of the gate electrode 7 is used to form a high concentration layer (n that suppresses the long gate effect under the end of the gate electrode 7 on the drain side. + A type semiconductor region 17) can be formed.
[0045]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0046]
For example, in the above-described embodiment, the case where the present invention is applied to an LDMOS that constitutes an amplifier of an RF power module used in a digital cellular phone has been described. However, the present invention is not limited to this and can be applied to any LDMOS. .
[0047]
【The invention's effect】
Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0048]
By relatively shortening the gate length of the gate electrode and forming a high-concentration layer below the end of the gate electrode on the drain side to suppress the long gate effect, it is relatively high and depends on Vg in a wide range of Vg. It is possible to realize an LDMOS capable of obtaining a Gm having a relatively low property.
[Brief description of the drawings]
FIG. 1 is a graph showing a relationship between an electron drift velocity and a lateral electric field.
FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an nLDMOS according to the first embodiment of the present invention.
3 is a cross-sectional view of the essential part of the semiconductor substrate showing the method of manufacturing nLDMOS which is Embodiment 1 of the present invention. FIG.
4 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the nLDMOS according to the first embodiment of the present invention. FIG.
5 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the nLDMOS according to the first embodiment of the present invention. FIG.
6 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the nLDMOS according to the first embodiment of the present invention. FIG.
7 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the nLDMOS according to the first embodiment of the present invention. FIG.
8 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the nLDMOS according to the first embodiment of the present invention. FIG.
FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate showing the method for manufacturing the nLDMOS according to the first embodiment of the present invention.
FIG. 10 is a graph showing the effect of the invention from the relationship between Gm and Vg of the LDMOS according to the first embodiment of the present invention.
FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an nLDMOS according to a second embodiment of the present invention.
12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an nLDMOS according to a second embodiment of the present invention. FIG.
13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an nLDMOS according to a second embodiment of the present invention. FIG.
FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an nLDMOS according to Embodiment 2 of the present invention.
FIG. 15 is a graph showing the relationship between Gm and Vg of LDMOS examined by the inventors.
[Explanation of symbols]
1 Substrate
1a Board body
1b Semiconductor layer
2 Insulating layer
3 Semiconductor area
4 Field insulation film
5 p-well
6 Gate insulation film
6a Gate insulation film
6b Gate insulation film
7 Gate electrode
8 Cap insulation film
9 Semiconductor area
10 Semiconductor region
11 Hello layer
12 Insulating film
13 Semiconductor region
14a Semiconductor region
14b Semiconductor region
15 Semiconductor region
16 Insulating film
17 Semiconductor region
18 sidewall
19 Semiconductor area
20 Insulating film
21 Backside source electrode
RP1 resist pattern
RP2 resist pattern
RP3 resist pattern
RP4 resist pattern
RP5 resist pattern
CNT contact hole
PL plug
M1 first layer wiring
M2 Second layer wiring

Claims (6)

  1. A method for manufacturing a semiconductor device having a lateral field effect transistor,
    (A) forming a gate insulating film on the first conductivity type substrate;
    (B) forming a gate electrode on the gate insulating film;
    (C) forming a first semiconductor region of a second conductivity type opposite to the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a first impurity into the substrate;
    (D) forming an insulating film on the substrate;
    (E) forming a second semiconductor region of the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a second impurity into the substrate in a state where the insulating film is formed; A high-concentration layer made of the first semiconductor region is disposed on a drain-side substrate below the end of the gate electrode, and the second-conductivity-type low-concentration layer is formed in a region where the first semiconductor region and the second semiconductor region overlap each other. A step of arranging
    (F) By introducing a third impurity into the substrate, the third semiconductor region of the second conductivity type is separated from the end of the gate electrode on the drain side by a predetermined distance on the substrate on the drain side of the field effect transistor. And a step of forming the semiconductor device.
  2. A method for manufacturing a semiconductor device having a lateral field effect transistor,
    (A) forming a gate insulating film on the first conductivity type substrate;
    (B) forming a gate electrode on the gate insulating film;
    (C) forming a first semiconductor region of a second conductivity type opposite to the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a first impurity into the substrate;
    (D) forming an insulating film on the substrate;
    (E) forming a second semiconductor region of the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a second impurity into the substrate in a state where the insulating film is formed; A high-concentration layer made of the first semiconductor region is disposed on a drain-side substrate below the end of the gate electrode, and the second-conductivity-type low-concentration layer is formed in a region where the first semiconductor region and the second semiconductor region overlap each other. A step of arranging
    (F) By introducing a third impurity into the substrate, the third semiconductor region of the second conductivity type is separated from the end of the gate electrode on the drain side by a predetermined distance on the substrate on the drain side of the field effect transistor. And forming a step,
    The method of manufacturing a semiconductor device, wherein the insulating film has a thickness of about 10 to 30 nm.
  3. A method for manufacturing a semiconductor device having a lateral field effect transistor,
    (A) forming a gate insulating film on the first conductivity type substrate;
    (B) forming a gate electrode on the gate insulating film;
    (C) forming a first semiconductor region of a second conductivity type opposite to the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a first impurity into the substrate;
    (D) forming a sidewall on the sidewall of the gate electrode by etching back the insulating film after forming the insulating film on the substrate;
    (E) forming a second semiconductor region of the first conductivity type in a substrate on a drain side of the field effect transistor by introducing a second impurity into the substrate in a state where the sidewall is formed; A high-concentration layer made of the first semiconductor region is disposed on a drain-side substrate below the end of the gate electrode, and the second-conductivity-type low-concentration layer is formed in a region where the first semiconductor region and the second semiconductor region overlap each other. A step of arranging
    (F) By introducing a third impurity into the substrate, the third semiconductor region of the second conductivity type is separated from the end of the gate electrode on the drain side by a predetermined distance on the substrate on the drain side of the field effect transistor. And a step of forming the semiconductor device.
  4. A method for manufacturing a semiconductor device having a lateral field effect transistor,
    (A) forming a gate insulating film on the first conductivity type substrate;
    (B) forming a gate electrode on the gate insulating film;
    (C) forming a first semiconductor region of a second conductivity type opposite to the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a first impurity into the substrate;
    (D) forming a sidewall on the sidewall of the gate electrode by etching back the insulating film after forming the insulating film on the substrate;
    (E) forming a second semiconductor region of the first conductivity type in a substrate on a drain side of the field effect transistor by introducing a second impurity into the substrate in a state where the sidewall is formed; A high-concentration layer made of the first semiconductor region is disposed on a drain-side substrate below the end of the gate electrode, and the second-conductivity-type low-concentration layer is formed in a region where the first semiconductor region and the second semiconductor region overlap each other. A step of arranging
    (F) By introducing a third impurity into the substrate, the third semiconductor region of the second conductivity type is separated from the end of the gate electrode on the drain side by a predetermined distance on the substrate on the drain side of the field effect transistor. And forming a step,
    The method of manufacturing a semiconductor device, wherein a spacer length of the sidewall is about 10 to 30 nm.
  5. A method for manufacturing a semiconductor device having a lateral field effect transistor,
    (A) forming a gate insulating film on the first conductivity type substrate;
    (B) forming a gate electrode on the gate insulating film;
    (C) forming a first semiconductor region of a second conductivity type opposite to the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a first impurity into the substrate;
    (D) forming an insulating film on the substrate;
    (E) forming a second semiconductor region of the first conductivity type on the substrate on the drain side of the field effect transistor by introducing a second impurity into the substrate in a state where the insulating film is formed; A high-concentration layer made of the first semiconductor region is disposed on a drain-side substrate below the end of the gate electrode, and the second-conductivity-type low-concentration layer is formed in a region where the first semiconductor region and the second semiconductor region overlap each other. A step of arranging
    (F) By introducing a third impurity into the substrate, the second conductive type third semiconductor region for the drain is formed on the drain side substrate of the field effect transistor from the end of the gate electrode on the drain side. Forming the second conductive type fourth semiconductor region for the source on the substrate on the source side of the field effect transistor, and forming the semiconductor device, wherein the method further comprises: Method.
  6. A semiconductor device having a lateral field effect transistor, comprising: (a) a gate insulating film formed on a substrate;
    (B) a gate electrode formed on the gate insulating film;
    (C) a fifth semiconductor region of a first conductivity type formed immediately below the gate electrode;
    (D) an insulating film provided on a side surface of the gate electrode;
    (E) A drain region having a first impurity concentration formed on the substrate, the second conductivity type being opposite to the first conductivity type, and the insulation from the end of the gate electrode on the drain region side A low-concentration layer provided at a position separated by the thickness of the film;
    (F) a drain region formed in the substrate, the second impurity concentration being higher than the first impurity concentration, and the thickness of the insulating film from the end of the gate electrode on the drain region side, and A third semiconductor region of the second conductivity type provided at a position separated by a low concentration layer;
    (G) having a third impurity concentration higher than the first impurity concentration, and having the second conductivity type high concentration layer formed on the substrate between the fifth semiconductor region and the low concentration layer. A semiconductor device.
JP2003200870A 2003-07-24 2003-07-24 Method for manufacturing semiconductor device, and semiconductor device Pending JP2005044873A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008514007A (en) * 2004-09-16 2008-05-01 フェアチャイルド・セミコンダクター・コーポレーション Enhanced surface field reduced high voltage P-type MOS device with stacked heterodoping periphery and gradually changing drift region
JP2013509732A (en) * 2009-11-02 2013-03-14 トランスフォーム インコーポレーテッド Package configuration for low EMI circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008514007A (en) * 2004-09-16 2008-05-01 フェアチャイルド・セミコンダクター・コーポレーション Enhanced surface field reduced high voltage P-type MOS device with stacked heterodoping periphery and gradually changing drift region
JP2013509732A (en) * 2009-11-02 2013-03-14 トランスフォーム インコーポレーテッド Package configuration for low EMI circuit

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