JP2005039231A - Interposer substrate with semiconductor element, substrate with interposer substrate, and structure consisting of semiconductor element, interposer substrate and substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a structure consisting of a semiconductor element, an interposer substrate and a substrate which can be produced relatively easily and exhibiting excellent connection reliability. <P>SOLUTION: The inventive structure 11 consists of a semiconductor element 15, an interposer substrate 21 and a substrate 41. The semiconductor element 15 is mounted on the first surface 32 of an interposer substrate body 38 having a second surface 33 being mounted on the surface of the substrate 41. A plurality of first surface side terminals 28 are arranged on the first surface 22 side of the interposer substrate body 38 and a plurality of second surface side terminals 29 are arranged on the second surface 23 side. The first surface side terminals 28 and the second surface side terminals 29 are conducting through conduction structures 30, 31 and 32. At least any one of dummy terminals 91 and 92 and a dummy conductor post 100 not connected with the surface connection terminal 16 of the semiconductor element 15 is formed in the interposer substrate body 38. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a relay substrate with a semiconductor element, a substrate with a relay substrate, and a structure including a semiconductor element, a relay substrate, and a substrate.

  In recent years, instead of directly connecting a wiring board on which an IC chip is mounted (IC chip mounting board or IC package board) and a printed board such as a motherboard, an interposer is provided between the wiring board and the printed board such as a motherboard. Various structures are known in which a so-called relay board is interposed and connected to each other (see, for example, Patent Document 1).

An IC chip used for this type of structure is generally formed using a semiconductor material (for example, silicon) having a thermal expansion coefficient of about 2.0 ppm / ° C. to 5.0 ppm / ° C. On the other hand, the relay substrate and the wiring substrate are often formed using a resin material having a considerably larger thermal expansion coefficient.
However, a structure in which a relay substrate is interposed between the IC chip and the IC chip mounting substrate is not currently known.

  Therefore, in order to realize a structure in which the relay substrate is interposed between the IC chip and the IC chip mounting substrate, the inventor of the present application forms an upper surface side pad for mounting the IC chip on the upper surface of the relay substrate. It is considered that a lower surface side pad connected to the IC chip mounting substrate is formed on the lower surface of the substrate. Further, it is considered that a plurality of conductor pillars extending in the thickness direction of the relay substrate are provided, and the upper surface side pad group and the lower surface side pad group are directly connected to each other through these conductor pillars to be conducted. Furthermore, it is considered to form solder bumps on the upper surface side pad and the lower surface side pad as necessary.

Japanese Unexamined Patent Publication No. 2000-208661 (FIG. 2 (d), etc.)

  Recently, with the increase in the speed of IC chips, there is a trend to increase the size of IC chips to form more arithmetic circuits. However, as the processing capability of the IC chip improves, the amount of heat generation increases, so the influence of thermal stress gradually increases. Moreover, when mounting an IC chip on an IC chip mounting substrate or an IC package substrate, solder is generally used. When the solder is cooled from the melting temperature to room temperature, the IC chip and the IC chip mounting substrate are used. Due to the difference in thermal expansion coefficient from the IC package substrate, thermal stress is generated in the mounting portion.

  Then, a large thermal stress acts on the interface between the IC chip and the relay substrate, etc., so that there is a possibility that a crack or the like occurs in the IC chip mounting portion (joined portion). Therefore, there is a problem that high connection reliability cannot be imparted between the IC chip and the relay substrate. In particular, if one of the sides of the IC chip exceeds 10.0 mm, particularly large thermal stress acts and there is a possibility that a crack or the like is generated. On the other hand, when the thickness of the IC chip is smaller than 1.0 mm, the strength is weakened, and cracks or the like may occur. Therefore, in these cases, the above problem becomes significant.

  In addition, in the structure in which the relay substrate is interposed between the IC chip and the IC chip mounting substrate considered by the inventor of the present application, the IC chip is mounted on the IC chip mounting substrate with the relay substrate or the IC package substrate with the relay substrate. When solder mounting is performed, thermal stress is also generated between the relay substrate and the IC chip mounting substrate or IC package substrate when the solder cools from the melting temperature to room temperature.

  A large thermal stress acts on the interface between the relay substrate and the IC chip mounting substrate or the IC package substrate, so that a crack or the like is generated at the junction between the relay substrate and the IC chip mounting substrate or the IC package substrate. There is a fear. Therefore, there is a problem that high connection reliability cannot be provided between the relay substrate and the IC chip mounting substrate or the IC package substrate.

Further, when the relay board body is deformed, the flatness of the upper or lower surface of the relay board body is impaired or the entire relay board is distorted, so that the IC chip cannot be accurately mounted on the relay board, or the IC chip mounting board Alternatively, the relay board cannot be accurately mounted on the IC package board.
In addition, when the relay substrate body is deformed during each of the above mountings, abnormal thermal stress is applied to the junction between the IC chip and the relay substrate, or between the relay substrate and the IC chip mounting substrate or the IC package substrate. The problem which becomes easy to generate | occur | produce and a crack etc. arises. Therefore, extremely accurate dimensional accuracy is required for the relay substrate body.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a structure including a semiconductor element, a relay substrate, and a substrate that is excellent in connection reliability. Another object of the present invention is to provide a relay substrate with a semiconductor element and a substrate with a relay substrate, which are suitable for realizing the excellent structure described above.

Means, actions and effects for solving the problem

And as a means to solve the above problems,
Comprising a semiconductor element having a surface connection terminal, and
A substantially substrate-shaped relay substrate body having a first surface on which the semiconductor element is mounted and a second surface and made of an inorganic insulating material;
A plurality of first surface side terminals disposed on the first surface side; a plurality of second surface side terminals disposed on the second surface side; and the first surface side terminals provided on the relay board body. And a conduction structure for conducting the second surface side terminals with each other,
In the relay board body, there is provided a relay board with a semiconductor element, wherein at least one of a dummy terminal and a dummy conductor column not connected to the surface connection terminal of the semiconductor element is formed.

In addition, as other means for solving the above problems,
Comprising a substrate having surface connection pads, and
A substantially board-shaped relay substrate body having a first surface on which a semiconductor element is to be mounted and a second surface to be mounted on the surface of the substrate, and made of an inorganic insulating material;
A plurality of first surface side terminals disposed on the first surface side; a plurality of second surface side terminals disposed on the second surface side; and the first surface side terminals provided on the relay board body. And a conduction structure for conducting the second surface side terminals with each other,
In the relay substrate body, there is provided a substrate with a relay substrate in which at least one of a dummy terminal and a dummy conductor column not connected to the surface connection terminal of the semiconductor element is formed.

Furthermore, as other means for solving the above problems,
Comprising a semiconductor element having a surface connection terminal;
Comprising a substrate having surface connection pads, and
A substantially board-shaped relay substrate body made of an inorganic insulating material, having a first surface on which the semiconductor element is mounted and a second surface mounted on the surface of the substrate;
A plurality of first surface side terminals disposed on the first surface side; a plurality of second surface side terminals disposed on the second surface side; and the first surface side terminals provided on the relay board body. And a conduction structure for conducting the second surface side terminals with each other,
The relay substrate main body is formed with at least one of a dummy terminal and a dummy conductor column that are not connected to the surface connection terminal of the semiconductor element, and a structure comprising a semiconductor element, a relay substrate, and a substrate There is a body.

In the above solution, "the relay board body is formed with at least one of a dummy terminal and a dummy conductor post not connected to the surface connection terminal of the semiconductor element" means that the dummy terminal is a semiconductor There is no direct or indirect electrical connection to the surface connection terminal of the element, or the dummy conductor pillar is not directly or indirectly electrically connected to the surface connection terminal of the semiconductor element. Indicates.
The dummy terminal formed on the relay board body is disposed on the first surface side of the relay board body or on the second surface side of the relay board body. Furthermore, the dummy conductor pillar provided on the relay board body is formed in a form penetrating from the first surface side to the second surface side of the relay board body, or exists only inside the relay board body. It is formed in the form to do.
Further, it is sufficient that at least one of the dummy terminals and the dummy conductor columns is formed, and both the dummy terminals and the dummy conductor columns may be formed. Here, in order to more reliably prevent the relay substrate body from being deformed, it is preferable that both the dummy terminal and the dummy conductor post are formed. Further, the dummy terminal and the dummy conductor post may be connected to each other.

  Further, in the structure in which the relay substrate is interposed between the IC chip and the IC chip mounting substrate, the heat with the wiring substrate formed using a resin material having a considerably larger thermal expansion coefficient than the IC chip. In order to reduce the expansion difference, it is preferable to use a material having a thermal expansion coefficient intermediate between the IC chip and the wiring board for the relay board. Therefore, in the relay substrate, for example, a substantially plate-shaped relay substrate body made of a ceramic sintered body can be used.

  In the above solution, at least one of a dummy terminal and a dummy conductor post that is not connected to the surface connection terminal of the semiconductor element is formed on the relay substrate body. According to the above solution, since there are dummy terminals and dummy conductor columns, conductor portions (metal portions) are uniformly arranged in the inorganic insulating material portion of the relay substrate body. Therefore, it is possible to effectively prevent the relay substrate body from being deformed. In addition, the flatness of the upper surface or lower surface of the relay substrate main body is prevented from being damaged, and the entire relay substrate is prevented from being distorted, so that the IC chip cannot be accurately mounted on the relay substrate, or the IC chip mounting substrate or the IC package substrate. Therefore, it is not possible to mount the relay board accurately.

  As a result, abnormal thermal stress is not applied to the junction between the IC chip and the relay substrate, and the junction between the relay substrate and the IC chip mounting substrate or the IC package substrate, and cracks or the like are generated in these junctions. There is no. As described above, it is possible to provide a structure including a semiconductor element, a relay substrate, and a substrate that has excellent connection reliability. In addition, it is possible to provide a relay substrate with a semiconductor element and a substrate with a relay substrate, which are suitable for realizing the above-described excellent structure.

  In particular, when a substantially plate-shaped relay substrate body made of a ceramic sintered body is used as the inorganic insulating material of the relay substrate body, the following problems occur. That is, in the above case, a green body manufacturing process for manufacturing a ceramic green body having a plurality of through holes to be a relay substrate body, and metal filling for filling the plurality of through holes with a conductive metal In the process and the simultaneous firing step of heating and sintering the ceramic green body and the conductive metal, the firing shrinkage ratio of the ceramic green body and the firing shrinkage ratio of the conductive metal However, due to the difference, the relay substrate body is deformed in the firing step. If the ceramic unsintered body and the conductive metal are unevenly arranged in the relay substrate body, the relay substrate body is particularly deformed. In particular, in such a case, according to the above solution, at least one of the dummy terminal and the dummy conductor pillar of the relay board body is formed, thereby preventing the relay board body from being deformed. Is possible.

  Furthermore, as another means for solving the above-mentioned problem, a first surface on which a semiconductor element having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. and having a surface connection terminal is mounted; A relay board body having a substantially plate shape made of a ceramic laminated sintered body having a structure in which one or a plurality of ceramic insulating materials are laminated, and a plurality of first parts arranged on the first surface side. A surface-side terminal, a plurality of second-surface-side terminals arranged on the second-surface side, a first-surface-side solder bump formed on a surface of the plurality of first-surface-side terminals, and the plurality of second-side terminals. A second surface side solder bump formed on the surface of the second surface side terminal, and a plurality of conductor pillars provided in the relay substrate main body and extending in the thickness direction of the relay substrate; Dummy conductor pillars and dummy terminals that are not connected to the surface connection terminals of the semiconductor element Chi, or as a relay substrate, wherein at least one is formed.

  Further, as a manufacturing method of the above-described solution means, a green body manufacturing step of manufacturing a ceramic green body having a plurality of through holes to be a relay substrate body, and a conductive property in the plurality of through holes. A metal filling step of filling a metal, and a co-firing step of heating and sintering the ceramic unsintered body and the conductive metal, and a surface connection terminal of the semiconductor element on the relay substrate body, There is a method for manufacturing a relay board as described above, wherein at least one of a dummy terminal and a dummy conductor pillar which are not connected is formed.

Moreover, in order to prevent a crack etc. from occurring in a joint portion between the IC chip and the relay substrate, it is preferable to fill a resin filler between the IC chip and the relay substrate.
Further, a resin filler is filled between the relay substrate and the wiring substrate in order to prevent a crack or the like from occurring at a joint portion between the relay substrate and the IC chip mounting substrate or the IC package substrate. It is preferable.

As a means suitable for realizing the above solution, it is preferable that the size of the relay substrate body in plan view is larger than the size of the semiconductor element in plan view. That is, it is preferable that the length of the side in the direction perpendicular to the thickness direction of the relay substrate body is larger than the length of the side in the direction perpendicular to the thickness direction of the semiconductor element.
Here, the length of one side corresponding to the length of the side in the direction perpendicular to the thickness direction of the relay substrate body should be larger than the length of at least one side in the direction perpendicular to the thickness direction of the semiconductor element. . For example, the two opposite sides of the relay board body are the same as the two sides of the corresponding semiconductor element, and the length of only the remaining two opposite sides of the relay board body is the two sides of the corresponding semiconductor element. May be larger than the length of each.
When the resin filler is filled between the semiconductor element and the relay substrate body, the relay substrate body is larger in plan view than the semiconductor element in plan view. This is because a plane (free free space) on which the resin filler is applied is secured on the surface (first surface) of the substrate body, so that the resin filler can be easily filled.

  When there is a plane (free free space) on which the resin filler is applied on the surface (first surface) of the relay board body, the free space includes, among the dummy terminals and dummy conductor pillars of the relay board body, At least one is preferably formed. As a result, even when the relay board body has such free space as described above, it is possible to effectively prevent deformation of the relay board body.

More preferably, one side corresponding to one side of the semiconductor element is larger in a range of 1.0 mm or more than one side in a direction perpendicular to the thickness direction of the semiconductor element. preferable.
More preferably, one side corresponding to one side of the semiconductor element is larger than a length of one side in a direction perpendicular to the thickness direction of the semiconductor element in a range of 2.0 mm or more corresponding to one side of the semiconductor element. It is more preferable. This is because, according to these, the free free space is surely secured, so that the resin filler can be more easily filled.

  However, in the above, one side corresponding to one side of the semiconductor element is 5.0 mm or less of the side of the relay substrate body, rather than the length of one side in the direction perpendicular to the thickness direction of the semiconductor element. It is preferable that the range is large. When one side corresponding to one side of the semiconductor element is larger than 5.0 mm, the free free space is more than necessary than the length of one side perpendicular to the thickness direction of the semiconductor element. Since it is too large, the relay board main body itself is enlarged, which is not preferable.

Therefore, according to the above, a resin filler is filled between the semiconductor element and the relay substrate body, or a resin filler is filled between the substrate and the relay substrate body. It is configured to be filled.
For this reason, the thermal stress in the mounting part between a semiconductor element (for example, IC chip) and a substrate (for example, a wiring substrate such as an IC chip mounting substrate or an IC package substrate) is relieved. That is, the thermal stress between the semiconductor element and the relay substrate body (interposer body) or between the substrate (for example, a wiring substrate such as an IC chip mounting substrate or an IC package substrate) and the relay substrate body (interposer body). Alleviated. Therefore, it is possible to provide a structure including a semiconductor element, a relay substrate, and a substrate that has excellent connection reliability.

Furthermore, in the above, of the sides in the direction perpendicular to the thickness direction of the semiconductor element, the length of two sides facing each other is the length of the side in the direction perpendicular to the thickness direction of the relay substrate body. The lengths of two sides corresponding to the two opposite sides of the element are substantially the same, and the lengths of the other two sides that are perpendicular to the thickness direction of the semiconductor element are the relay lengths. It is preferable that each of the sides in the direction perpendicular to the thickness direction of the substrate main body is longer than the lengths of two sides corresponding to the other two opposite sides of the semiconductor element.
Here, when the size of the relay substrate body in plan view is larger than the size of the semiconductor element in plan view, the resin filler is filled between the semiconductor element and the relay substrate body. In doing so, a plane (free space) on which the resin filler can be applied is secured on the surface (first surface) of the relay substrate body, so that the resin filler can be easily filled. .

However, the length of two sides facing each other among the sides perpendicular to the thickness direction of the semiconductor element is equal to the two sides facing the semiconductor element among the sides perpendicular to the thickness direction of the relay substrate body. Are longer than the two sides corresponding to each other, and the other two sides facing each other out of the sides perpendicular to the thickness direction of the semiconductor element are perpendicular to the thickness direction of the relay substrate body. In the case where the lengths of the two sides are longer than the lengths of two sides corresponding to the other two sides facing the semiconductor element, the following problems occur. That is, the following problems may occur when a part of the first surface of the relay substrate body is exposed in plan view in any of the four sides of the semiconductor element.
That is, as described above, when a plane (free space) on which the resin filler can be applied is secured around any of the four sides of the semiconductor element, the resin filler is placed around the four sides of the semiconductor element. When the resin filler is filled in the joint area between the IC chip and the relay substrate after being applied to a free space, the applied resin filler is not completely filled between the IC chip and the relay substrate. In this case, a problem that a cavity is generated occurs.

  This problem is that the applied resin filler flows around the semiconductor element around the free space around the four sides of the semiconductor element. As a result, the resin filler surrounds the four sides of the semiconductor element. It is caused by that. As a result, a cavity of the resin filler is generated between the semiconductor element and the relay substrate. As described above, when a cavity is generated in the resin filler, it is not possible to completely prevent a crack or the like from being generated at a joint portion between the IC chip and the relay substrate.

  In the above solution, among the sides perpendicular to the thickness direction of the semiconductor element, the length of two opposite sides is equal to the length of the semiconductor element out of the sides perpendicular to the thickness direction of the relay substrate body. The lengths of the two opposite sides, which are substantially the same as the lengths of the two sides corresponding to the two opposite sides, and of the sides perpendicular to the thickness direction of the semiconductor element, It is preferable that each of the sides in the direction perpendicular to the thickness direction is longer than the lengths of two sides corresponding to the other two opposite sides of the semiconductor element. That is, it is preferable that a part of the first surface of the relay substrate body is not exposed in plan view in all of the four sides of the semiconductor element.

That is, as described above, a plane (free space) on which the resin filler can be applied is not secured around all four sides of the semiconductor element, and a part of the side of the semiconductor element is not secured. Free space is secured only around. For this reason, the applied resin filler does not flow around the semiconductor element.
Therefore, the resin filler does not surround the four sides of the semiconductor element, and it is possible to reliably prevent the resin filler from being generated between the semiconductor element and the relay substrate. Furthermore, it is possible to prevent cracks and the like from occurring at the joint between the IC chip and the relay substrate.

  In the above solution, it is preferable that a part of the first surface of the relay substrate body is exposed in plan view around only one side of the semiconductor element. This is because it is possible to reliably prevent the resin filler from surrounding the four sides of the semiconductor element and to more reliably prevent the resin filler from being generated between the semiconductor element and the relay substrate. .

In the above solution, more preferably, the length of the other two opposite sides of the sides in the direction perpendicular to the thickness direction of the semiconductor element is perpendicular to the thickness direction of the relay substrate body. Of the sides, the length of each of the two sides corresponding to the other two opposite sides of the semiconductor element is preferably longer than 1.0 mm. That is, around only one side of the semiconductor element, a part of the first surface of the relay substrate body is exposed with a width of 1.0 mm or more in a direction perpendicular to the one side of the semiconductor element in a plan view. It is good to have a configuration.
More preferably, one side corresponding to one side of the semiconductor element is larger than a length of one side in a direction perpendicular to the thickness direction of the semiconductor element in a range of 2.0 mm or more corresponding to one side of the semiconductor element. It is more preferable. That is, around only one side of the semiconductor element, a part of the first surface of the relay substrate body is exposed in a width of 2.0 mm or more in a direction perpendicular to the one side of the semiconductor element in a plan view. It is good to have a configuration.

This is because, according to these, the free free space is surely secured, so that the resin filler can be more easily filled.
However, in the above, one side corresponding to one side of the semiconductor element is 5.0 mm or less of the side of the relay substrate body, rather than the length of one side in the direction perpendicular to the thickness direction of the semiconductor element. It is preferable that the range is large. That is, further, only around one side of the semiconductor element, a part of the first surface of the relay substrate body in a plan view has a width of 5.0 mm or less in a direction perpendicular to the one side of the semiconductor element. It is preferable to have an exposed configuration.
When one side corresponding to one side of the semiconductor element is larger than 5.0 mm, the free free space is more than necessary than the length of one side perpendicular to the thickness direction of the semiconductor element. Since it is too large, the relay board main body itself is enlarged, which is not preferable.

  Furthermore, in these solutions, since a substantially plate-shaped relay substrate body made of an inorganic insulating material is used, the difference in thermal expansion coefficient from the semiconductor element is reduced, and a large thermal stress acts directly on the semiconductor element. No longer. Therefore, even if the semiconductor element is large and generates a large amount of heat, cracks and the like are unlikely to occur. Therefore, high connection reliability can be imparted also between the relay substrate and the semiconductor element.

  In order to realize the above-described solution, in addition to the above-described configuration, the semiconductor device has a first surface on which a semiconductor element having surface connection terminals is mounted and a second surface, and is made of an inorganic insulating material. A substantially plate-shaped relay board body, a plurality of first surface side terminals disposed on the first surface side, a plurality of second surface side terminals disposed on the second surface side, and the relay board body And a conductive structure that conducts the first surface side terminal and the second surface side terminal to each other, and a center-to-center distance between adjacent second surface side terminals is between adjacent first surface side terminals. It is preferable to use a relay board that is set to be larger than the center-to-center distance.

  Furthermore, a semiconductor element having a surface connection terminal, a first surface on which the semiconductor element is mounted, a second surface, a substantially plate-shaped relay substrate body made of an inorganic insulating material; A plurality of first surface side terminals disposed on one surface side; a plurality of second surface side terminals disposed on the second surface side; provided on the relay board body; the first surface side terminals; and A conductive structure for conducting the second surface side terminals to each other, and the center-to-center distance between adjacent second surface side terminals is set to be larger than the center-to-center distance between adjacent first surface side terminals. It is also preferable to use a relay board with a semiconductor element, which is provided with a relay board that is provided.

  In addition, the substrate has a thermal expansion coefficient of 5.0 ppm / ° C. or more and has a surface connection pad, and has a first surface and a second surface mounted on the surface of the substrate, and is inorganic. A substantially plate-shaped relay substrate body made of an insulating material; a plurality of first surface-side terminals disposed on the first surface side; a plurality of second surface-side terminals disposed on the second surface side; A conductive structure that is provided on the relay board main body and that electrically connects the first surface side terminal and the second surface side terminal to each other, and a distance between centers between adjacent second surface side terminals is adjacent to the first surface; It is also preferable to use a board with a relay board provided with a relay board set so as to be larger than the center-to-center distance between the side terminals.

  That is, according to these preferred examples, the center-to-center distance between adjacent second surface side terminals is set to be larger than the center-to-center distance between adjacent first surface side terminals. For example, bumps can be easily formed on the second surface side terminals. Therefore, it is possible to provide a relay board that is relatively easy to manufacture. Further, in this case, since the center-to-center distance between the surface connection pads corresponding to the second surface side terminals can be set larger, the surface connection pads on the substrate (for example, IC chip mounting substrate or IC package substrate) side are also provided. For example, bumps can be easily formed. Therefore, the substrate can be made relatively easily. In addition, the yield of the substrate is improved and the defective product generation rate is reduced, which contributes to cost reduction.

  Further, bumps having a desired size can be formed on the second surface side terminals and the surface connection pads. As a result, high connection reliability can be provided between the relay substrate and the substrate. Further, since this structure uses a substantially plate-shaped relay substrate body made of an inorganic insulating material, the difference in thermal expansion coefficient from the semiconductor element is reduced, and a large thermal stress does not act directly on the semiconductor element. Therefore, even if the semiconductor element is large and generates a large amount of heat, cracks and the like are unlikely to occur. Therefore, high connection reliability can be imparted also between the relay substrate and the semiconductor element.

  In the above solution, it is preferable to use a semiconductor element having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. and having a surface connection terminal. Examples of such semiconductor elements include semiconductor integrated circuit chips (IC chips) made of silicon having a thermal expansion coefficient of about 2.6 ppm / ° C. The surface connection terminal refers to a terminal for electrical connection, which is connected by surface connection. In addition, surface connection refers to the case where pads or terminals are formed in a line shape or a lattice shape (including a staggered shape) on the plane of an object to be connected, and these are connected to each other. The size and shape of the semiconductor element are not particularly limited, but at least one side is preferably 10.0 mm or more. This is because in such a large semiconductor element, the amount of heat generation is likely to increase, and the influence of thermal stress gradually increases, so that the problem of the present invention is likely to occur. The thickness of the semiconductor element is not particularly limited, but is preferably 1.0 mm or less. If the thickness of the semiconductor element is 1.0 mm or less, the strength of the semiconductor element may be weakened to cause cracks and the like, and therefore it is not possible to provide high connection reliability between the semiconductor element and the relay substrate. This is because problems are likely to occur.

  As the substrate, for example, a substrate having a thermal expansion coefficient of 5.0 ppm / ° C. or more and having a surface connection pad is used. Examples of the substrate include a substrate on which a semiconductor element or other electronic component is mounted, and particularly a wiring substrate on which a semiconductor element or other electronic component is mounted and having a conductor circuit that electrically connects them. . As long as the condition that the thermal expansion coefficient is 5.0 ppm / ° C. or higher is satisfied, the material for forming the substrate is not particularly limited, and is appropriately selected in consideration of cost, workability, insulation, mechanical strength, and the like. can do. Examples of the substrate include a resin substrate, a ceramic substrate, and a metal substrate.

  Specific examples of the resin substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide-triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. It is not limited to. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used. Specific examples of the ceramic substrate include, but are not limited to, an alumina substrate, a beryllia substrate, a glass ceramic substrate, and a substrate made of a low-temperature fired material such as crystallized glass. Specific examples of the metal substrate include, but are not limited to, a copper substrate, a copper alloy substrate, a substrate made of a single metal other than copper, and a substrate made of an alloy of a metal other than copper.

  Moreover, the surface connection pad which a board | substrate has is a pad for terminals for electrical connection with a relay board | substrate, and points out what connects by surface connection. Such surface connection pads are formed in, for example, a linear shape or a lattice shape (including a staggered shape).

  The relay substrate has a substantially plate-shaped relay substrate body made of an inorganic insulating material. The thermal expansion coefficient of the relay substrate body is not particularly limited, but is preferably an intermediate value between the semiconductor element and the substrate, and specifically, 2.0 ppm / ° C. or more and less than 8.0 ppm / ° C. The reason is that if the thermal expansion coefficient of the relay substrate body exceeds 8.0 ppm / ° C., the difference in thermal expansion coefficient from the semiconductor element is not sufficiently reduced, and the influence of thermal stress on the semiconductor element cannot be sufficiently reduced. It is. Therefore, for example, when a silicon IC chip having a thermal expansion coefficient of about 2.6 ppm / ° C. is selected, it is preferable to use a relay substrate body having a thermal expansion coefficient of 3.0 ppm / ° C. or more and less than 8.0 ppm / ° C. It can be said that. More preferably, a relay substrate body having a thermal expansion coefficient of 3.0 ppm / ° C. or more and less than 5.0 ppm / ° C. is used.

  Here, an inorganic material typified by ceramic is used as a material constituting the relay substrate body. This is because ceramic generally has a smaller thermal expansion coefficient than a resin material and is suitable as a material for a relay substrate body. This is because ceramic has desirable characteristics in addition to the characteristic of low thermal expansion coefficient. Preferable examples of such ceramics include oxide-based insulating engineering ceramics (for example, alumina and beryllia) and non-oxide-based insulating engineering ceramics (for example, aluminum nitride, silicon nitride, boron nitride). Nitride-based insulating engineering ceramic). In addition, the ceramic used for the relay substrate body is not only those fired at a high temperature of about 1000 ° C. or higher, but also ceramics fired at a relatively low temperature of about 700 ° C. to 800 ° C. (so-called low-temperature fired ceramic). It may be. As the low-temperature fired ceramic, those containing borosilicate glass, alumina, silica, or the like as components are well known, but are not limited thereto.

  Here, “thermal expansion coefficient” means a thermal expansion coefficient in a direction (XY direction) perpendicular to the thickness direction (Z direction), and a TMA (thermomechanical analyzer between 0 ° C. and 100 ° C. ) Means the value measured. “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01. Incidentally, the thermal expansion coefficient of alumina is, for example, 7.6 ppm / ° C., the thermal expansion coefficient of aluminum nitride is 4.4 ppm / ° C., the thermal expansion coefficient of silicon nitride is 3.0 ppm / ° C., and the thermal expansion coefficient of low-temperature fired ceramic is 5. 0.5 ppm / ° C.

  The ceramic selected as the material constituting the relay substrate main body preferably has an insulating property as described above. The reason is that in the relay board body having no insulating property, it is necessary to provide an insulating layer in advance when forming a conductive structure such as a conductor post, but if it is an insulating relay board body, it is not necessary. It is. Therefore, it is possible to avoid complication of the structure of the relay substrate and increase in the number of man-hours, thereby contributing to the cost reduction of the entire structure.

  Although the thickness of the relay substrate body is not particularly limited, it is preferably 0.1 mm or more and 0.7 mm or less, more preferably 0.1 mm or more and 0.3 mm or less. Within such a thickness range, the thermal stress applied to the semiconductor element junction when the structure is configured becomes relatively small, such as warping of the relay substrate body itself and cracks at the junction with the semiconductor element. It is advantageous for prevention.

  The relay substrate body preferably has not only low thermal expansion as described above but also high rigidity (for example, high Young's modulus and flexural modulus). That is, the rigidity of the relay substrate body, specifically the Young's modulus, is preferably higher than at least the semiconductor element, and is preferably 200 GPa or more, particularly 300 GPa or more. The reason is that if the relay board body has high rigidity, even if a large thermal stress is applied to the relay board body, the relay board body can withstand the thermal stress. Therefore, it is possible to prevent warping of the relay substrate body itself and cracking of the joint portion of the semiconductor element. Examples of the ceramic material satisfying such conditions include alumina (Young's modulus = 280 GPa), aluminum nitride (Young's modulus = 350 GPa), silicon nitride (Young's modulus = 300 GPa), but are not limited thereto.

  Also, the flexural modulus, which is another index indicating the rigidity of the relay substrate body, is preferably 200 MPa or more, particularly 300 MPa or more. The reason is that if the relay board body has high rigidity, even if a large thermal stress is applied to the relay board body, the relay board body can withstand the thermal stress. Therefore, it is possible to prevent warping of the relay substrate body itself and cracking of the joint portion of the semiconductor element. In addition, as a ceramic material satisfying such conditions, alumina (flexural modulus = 350 MPa), aluminum nitride (flexural modulus = 350 MPa), silicon nitride (flexural modulus = 690 MPa), low-temperature fired ceramic (flexural modulus = 200 MPa) However, it is not limited to these.

  Furthermore, it is more preferable that the relay substrate body has not only low thermal expansion and high rigidity as described above but also high heat dissipation. Here, “high heat dissipation” means that at least heat dissipation (for example, thermal conductivity) is higher than that of the substrate. The reason is that if a relay substrate body having high heat dissipation is used, the heat generated by the semiconductor element can be quickly transmitted and dissipated, so that thermal stress can be mitigated. Therefore, a large thermal stress does not act, and it is possible to prevent warping of the relay substrate body itself and cracks at the joint portion of the semiconductor element. In addition, examples of the ceramic material satisfying such conditions include aluminum nitride, but are not limited thereto.

  A plurality of first surface side terminals are disposed on the first surface side of the relay substrate body, while a plurality of second surface side terminals are disposed on the second surface side.

  The number of the first surface side terminals is not particularly limited, but is usually set according to the number of surface connection terminals of the semiconductor element. The size of the first surface side terminal is not particularly limited, but specifically, the diameter may be 125 μm or less, particularly 100 μm or less (excluding 0 μm). This is because if the distance between the centers is too large, it may not be possible to sufficiently cope with finer semiconductor elements expected in the future. Further, the center-to-center distance between the adjacent first surface side terminals is preferably 250 μm or less, more preferably 200 μm or less, and particularly preferably 150 μm or less (excluding 0 μm). The reason is that when the distance between the centers is reduced to this extent, the problem of the present invention that the formation of the second surface side terminals becomes difficult is likely to occur.

  Further, the number and size of the plurality of second surface side terminals should not be particularly limited, but usually the number of the second surface side terminals is formed to be substantially the same as the number of the first surface side terminals. The

  The relay board main body is provided with a conduction structure for conducting the first surface side terminal and the second surface side terminal with each other. The conductive structure includes a plurality of conductor columns extending in the thickness direction of the relay substrate and a wiring group including a plurality of wires extending in the relay substrate surface direction and connected to the conductor columns, and the wiring groups are adjacent to each other. It is preferable to have a fan-out portion in which the interval between wirings to be widened is wide. Here, “the interval between adjacent wirings becomes wider” means that when there are a plurality of wirings mainly from the central part of the relay board main body to the outer peripheral part of the relay board main body, the adjacent wirings are separated in the relay board surface direction. This means that the interval between the wirings becomes wide. A structure in which the center-to-center distance between adjacent second surface side terminals is larger than the center-to-center distance between adjacent first surface side terminals can be realized relatively easily by providing a wiring group having a fan-out portion. can do.

  The conductor pillar can be formed, for example, by filling a hole provided in the relay substrate body with a conductive metal. The first surface side connection terminal may be disposed on one end surface of the conductor pillar, and the second surface side connection terminal may be disposed on the other end surface. Although it does not specifically limit as said conductive metal, For example, 1 type, or 2 or more types of metals selected from copper, gold | metal | money, silver, platinum, palladium, nickel, tin, lead, titanium, tungsten, molybdenum, tantalum, niobium etc. However, it is not limited to these. Examples of the conductive metal composed of two or more metals include solder that is an alloy of tin and lead. As a specific method for filling the hole with the conductive metal, for example, there is a method in which a fluid material containing the conductive metal (for example, a conductive metal paste) is prepared and printed and filled. There is a method to apply. The diameter of the conductor pillar should not be particularly limited, but is preferably smaller than the diameters of the first surface side connection terminal and the second surface side connection terminal, specifically 100 μm or less, preferably 80 μm or less. It is particularly preferable (except for 0 μm). This is because if the conductor pillar has a small diameter, the occupation ratio of the conductor pillar in the relay board body is reduced, and the space in which the wiring can be formed in the relay board body is increased accordingly.

  For example, the wiring is preferably formed by forming a layer made of a conductive metal in a predetermined pattern on the relay substrate body. Although it does not specifically limit as said conductive metal, For example, 1 type, or 2 or more types of metals selected from copper, gold | metal | money, silver, platinum, palladium, nickel, tin, lead, titanium, tungsten, molybdenum, tantalum, niobium etc. However, it is not limited to these. Examples of the conductive metal composed of two or more metals include solder that is an alloy of tin and lead. Specific methods for forming the wiring include, for example, a method of producing a fluid material containing a conductive metal (for example, a conductive metal paste) and printing it, a method of performing conductive metal plating, There is a technique of sputtering metal. The conductive metal for forming the wiring may be the same as or different from the conductive metal for forming the conductor columns.

  Here, the wiring group having a fan-out portion in which the interval between adjacent wirings is wide may be arranged on either the surface layer or the inner layer of the relay board body, but is arranged particularly on the inner layer of the relay board body. It is desirable. When the wiring group is arranged on the surface layer of the relay board main body, it is necessary to form a protective structure (for example, a solder resist) for avoiding adhesion of solder and the like, which may lead to complicated structure and high cost. On the other hand, if the wiring group is arranged in the inner layer of the relay board main body, a structure for avoiding the adhesion of solder or the like becomes unnecessary, and the structure can be prevented from becoming complicated and expensive. In addition, when the wiring group is arranged on the surface layer (especially the surface layer on the first surface side) of the relay board body and the first surface side connection terminals are multi-terminal or the distance between the centers is small, the wiring It becomes difficult to route the relay board, and it becomes difficult to manufacture the relay board. On the other hand, if the wiring group is arranged in the inner layer of the relay board main body, the wiring can be routed relatively freely without being greatly influenced by the state of the first surface side connection terminals. Therefore, it is difficult to manufacture the relay board. In addition, as a suitable example of the above structures, a ceramic laminated sintered body having a structure in which a plurality of ceramic insulating materials are laminated can be used as the relay substrate body. That is, if the wiring group is sandwiched between ceramic insulating materials, the ceramic insulating material itself functions as a protective structure for protecting the wiring group.

  When forming conductor columns and wiring groups using a material containing a conductive metal such as a conductive metal paste for a ceramic relay substrate body, either a simultaneous firing method or a post-firing method is adopted. Good. The co-firing method refers to a method of simultaneously sintering a ceramic and a conductive metal. The post-firing method refers to a method in which the ceramic is first sintered and then the conductive metal is filled and the conductive metal is sintered.

  As a manufacturing method of the relay substrate adopting the simultaneous firing method, there are a green body manufacturing step of manufacturing a ceramic green body having a plurality of through holes, and a metal in which a conductive metal is filled in the plurality of through holes. A filling step, a metal layer forming step of forming a layer made of a conductive metal in a predetermined pattern on the surface of the ceramic unsintered body, and heating and sintering the ceramic unsintered body and the conductive metal. A method of manufacturing a relay substrate including a co-firing step is preferable. Further, as a more preferable method for manufacturing a relay substrate, a green body manufacturing process for manufacturing a ceramic green body having a plurality of through holes, and metal filling for filling a conductive metal into the plurality of through holes A step of forming a layer of a conductive metal on the surface of the ceramic unsintered body in a predetermined pattern; and the ceramic unsintered body that has undergone the metal filling step and the metal layer forming step. A lamination step of laminating a plurality of layers made of the conductive metal in an inner layer and integrating them to form an unsintered laminate, and heating the ceramic unsintered body and the conductive metal There is a method for manufacturing a relay substrate, which includes a simultaneous firing step of sintering.

  On the other hand, as a manufacturing method of the relay substrate adopting the post-firing method, a first firing step of firing a ceramic unsintered body having a plurality of through holes to produce a sintered body, and the plurality of the sintered body in the sintered body A metal filling step of filling the through-holes with a conductive metal, a metal layer forming step of forming a layer made of the conductive metal in a predetermined pattern on the surface of the sintered body, and firing the conductive metal A plurality of the sintered bodies that have undergone the second firing step, the metal filling step, the metal layer forming step, and the second firing step are laminated and integrated with a layer made of the conductive metal disposed in an inner layer. And a lamination step of forming a laminated sintered body to form a relay substrate, which is preferable.

  Whether to use the co-firing method or the post-firing method depends on the type of ceramic that constitutes the relay substrate, but if both methods are possible and cost reduction is a priority, It is advantageous to employ a firing method. This is because the co-firing method generally requires less man-hours than the post-firing method, and can be efficiently produced by that much, and contributes to the cost reduction. When the ceramic is a high-temperature fired ceramic and employs a simultaneous firing method, the conductive metal constituting the conductor column is at least one refractory metal selected from tungsten, molybdenum, tantalum and niobium. Preferably it is. That is, even if a high temperature during firing exceeding 1000 ° C. is encountered, it does not oxidize or evaporate and can be converted into a suitable sintered body and remain in the through hole. When the ceramic is a low-temperature fired ceramic and employs a co-fired method, the conductive metal constituting the conductor column need not be a refractory metal. Therefore, in this case, a metal (for example, copper, silver, gold, etc.) having a lower melting point than tungsten or the like but excellent in conductivity can be selected.

  If the ceramic constituting the relay substrate is a ceramic that cannot be fired simultaneously with a metal material (for example, silicon nitride), a post-fired method is inevitably adopted. Some metallized layer may be formed on the inner wall surface of the hole. If there is no metallized layer between the inner wall surface of the through hole (ie, the surface made of a ceramic sintered body) and the conductive metal and both are in direct contact, high adhesion strength can be imparted between them. It can be difficult. On the other hand, when the metallized layer is interposed between the inner wall surface of the through hole and the conductive metal, it becomes easy to impart high adhesion strength between them. Therefore, cracks and the like hardly occur at the interface between the inner wall surface of the through hole and the conductive metal, and the reliability at the interface between the ceramic and the metal can be improved. On the other hand, when a ceramic capable of co-firing with a metal material is employed, the metallized layer is not necessarily required and may or may not be formed.

  Protruding electrodes such as solder bumps are preferably formed on at least one surface of the first surface side connection terminal and the second surface side connection terminal, and in particular, the first surface side connection terminal and the second surface side. It is more preferable that solder bumps are formed on both connection terminals. The reason is that if the solder bumps are provided on the relay substrate side, the connection with the surface connection terminals and the surface connection pads can be easily and reliably performed. The solder bump can be formed, for example, by printing and reflowing a known solder material.

  Hereinafter, an embodiment embodying the present invention will be described in detail with reference to FIG. FIG. 1 shows a semiconductor package structure (structure) 11 of this embodiment, which includes an IC chip (semiconductor element) 15, an interposer (relay substrate) 21, and a wiring substrate (substrate) 41 as an IC package substrate. It is a schematic sectional drawing. FIG. 2 is a schematic cross-sectional view showing the interposer 21, and FIG. 3 is a partially enlarged plan view showing the interposer 21. FIG. 4 is a schematic cross-sectional view showing an interposer 61 with IC chip (a relay substrate with a semiconductor element). FIG. 5 is a schematic cross-sectional view showing a state when the interposer 61 with IC chip is mounted on the wiring board 41. FIG. 7 is a partial plan view of the IC chip (semiconductor element) 15 and the interposer (relay substrate) 21 of FIG.

  As shown in FIG. 1, the semiconductor package structure 11 of this embodiment has an LGA (land grid array) structure including the IC chip 15, the interposer 21, and the wiring board 41 as described above. Note that the form of the semiconductor package structure 11 is not limited to LGA alone, and may be, for example, a BGA (ball grid array) or PGA (pin grid array) structure. The IC chip 15 having a function as an MPU is a 10 mm square rectangular flat plate made of silicon having a thermal expansion coefficient of about 2.6 ppm / ° C. Circuit elements (not shown) are formed on the lower surface layer of the IC chip 15. A plurality of surface connection terminals 16 are provided in a lattice shape on the lower surface side of the IC chip 15. In the present embodiment, the center-to-center distance between the plurality of adjacent surface connection terminals 16 is set to 120 μm.

A resin filler 81 is filled between the IC chip 15 (semiconductor element) and the interposer 21 (relay substrate). Further, a resin filler 82 is filled between the wiring board 41 (substrate) and the interposer 21.
The resin fillers 81 and 82 are each composed of a composite resin material containing an epoxy resin as a main component and silica filler dispersed therein. As such a material, for example, SEMICOAT (product number 5114) manufactured by Shin-Etsu Chemical Co., Ltd. is used. The resin fillers 81 and 82 may be made of the same material or different materials. In addition, it is preferable from the point of stress relaxation that the thermal expansion coefficients of the resin fillers 81 and 82 use materials of 25.0 ppm / ° C. or less, respectively. As such a material, for example, XS8437-23 manufactured by NAMICS is used.

  In the case where different materials are used for the resin fillers 81 and 82, the thermal expansion coefficient of the resin filler 81 between the IC chip 15 (semiconductor element) and the interposer 21 (relay substrate) is determined by wiring. It is preferable to make it smaller than the thermal expansion coefficient of the resin filler 82 between the substrate 41 (substrate) and the interposer 21 in terms of stress relaxation in the entire structure.

  The size of the interposer body 38 (relay substrate body) in plan view is set larger than the size of the IC chip 15 in plan view (10 mm square). That is, the length of the side in the direction perpendicular to the thickness direction of the interposer body 38 (relay substrate body) (the one side of the IC chip is larger than the length in the direction perpendicular to the thickness direction of the IC chip (10 mm square)). The length of one side of the corresponding interposer body: 11 mm) is set large. In this embodiment, a length L (FIG. 10) is obtained by subtracting the length (11 mm) of the side perpendicular to the thickness direction of the interposer body 38 from the length (10 mm) of the side perpendicular to the thickness direction of the IC chip. 1 and L) in FIG. 7 are set to 1 mm.

  When the interposer body 38 (relay substrate body) is larger in plan view than the IC chip 15 in plan view, the resin filler 81 is filled between the IC chip 15 and the interposer 21. Since a plane (free space of length L) for applying the resin filler 81 is secured on the surface (first surface) of the interposer 21, the resin filler 81 can be easily filled. In addition, a free space is secured only around a part of the side of the IC chip 15. For this reason, the applied resin filler 81 does not flow around the IC chip 15.

  Therefore, the resin filler 81 does not surround the four sides of the IC chip 15, and the occurrence of a cavity of the resin filler 81 between the IC chip 15 and the interposer body 38 is reliably prevented. be able to. Furthermore, it is possible to prevent cracks and the like from being generated at the joint portion between the IC chip 15 and the interposer 21.

In the free space of the interposer body 38, dummy terminals (first surface) that are not connected to the surface connection terminals 16 of the IC chip 15 are connected to the respective surfaces (first surface 22 and second surface 23) of the interposer 21. A side dummy terminal 91 and a second surface side dummy terminal 92) are respectively formed. The interposer body 38 is formed with dummy conductor pillars 100 that are not connected to the surface connection terminals 16 of the IC chip 15. The dummy terminal and the dummy conductor post 100 are connected to each other. In addition, the dummy conductor pillar 100 provided in the interposer body 38 is formed in a form penetrating from the first surface side to the second surface side of the interposer body 38.
In addition, according to the present embodiment, both the dummy terminal and the dummy conductor pillar are formed, but the present invention is not limited to this, and dummy terminals (first surface side dummy terminal 91, second surface side dummy terminal 92) and At least one of the dummy conductor pillars 100 may be formed.

  The wiring board 41 is a so-called multi-layer wiring board (resin IC package board), which is made of a rectangular flat plate member having an upper surface 42 and a lower surface 43, and has a plurality of resin insulation layers 44 and a plurality of layers of conductor circuits 45. It is. In the case of this embodiment, specifically, the resin insulating layer 44 is formed of an insulating base material obtained by impregnating a glass cloth with an epoxy resin, and the conductor circuit 45 is formed of a copper foil or a copper plating layer. The thermal expansion coefficient of the wiring board 41 is 13.0 ppm / ° C. or more and less than 16.0 ppm / ° C. On the upper surface 42 of the wiring board 41, a plurality of surface connection pads 46 for electrical connection with the interposer 21 side are formed in a lattice shape. In the present embodiment, the center-to-center distance between the plurality of adjacent surface connection pads 46 is set to 200 μm. On the surface of each surface connection pad 46, substrate-side solder bumps 49, which are protruding electrodes, are formed. On the lower surface 43 of the wiring substrate 41, a plurality of surface connection pads 47 for electrical connection with a mother board (not shown) are formed in a lattice shape. The surface connection pads 47 for connecting the motherboard have a wider area and a wider pitch than the surface connection pads 46 for interposer connection. Via hole conductors 48 are provided in the resin insulating layer 44, and the conductor circuits 45, the surface connection pads 46, and the surface connection pads 47 of different layers are electrically connected to each other via these via hole conductors 48. . In addition to the interposer 61 with an IC chip shown in FIG. 2, a chip capacitor, a semiconductor element, and other electronic components (all not shown) are mounted on the upper surface 42 of the wiring board 41.

  As shown in FIGS. 1 and 2, the interposer 21 has a rectangular flat plate-shaped interposer body 38 (relay substrate body) having an upper surface 22 (first surface) and a lower surface 23 (second surface). . The interposer body 38 is made of an alumina substrate having a multilayer structure. More specifically, the interposer body 38 of the present embodiment is made of an alumina substrate having a thickness of 0.3 mm and having a two-layer structure in which the first alumina insulating layer 24 and the second alumina insulating layer 25 are laminated. Such an alumina substrate has a thermal expansion coefficient of about 7.6 ppm / ° C., a Young's modulus of about 280 GPa, and a flexural modulus of about 350 MPa. Therefore, the thermal expansion coefficient of the interposer body 38 is smaller than the thermal expansion coefficient of the wiring substrate 41 and larger than the thermal expansion coefficient of the IC chip 15. That is, it can be said that the interposer 21 of this embodiment has a lower thermal expansion than the wiring board 41. Further, since the Young's modulus of the alumina substrate is higher than that of the IC chip 15 (that is, 190 GPa or more), the interposer 21 of the present embodiment has high rigidity. The interposer body 38 may be a low-temperature fired ceramic substrate.

  A plurality of vias (through holes) extending in the thickness direction of the interposer 21 are formed in a lattice shape in the first alumina insulating layer 24 constituting the interposer body 38, and these vias are made of tungsten (W). Conductor pillars 30 are provided. The second alumina insulating layer 25 constituting the interposer body 38 is also formed with a plurality of vias (through holes) extending in the thickness direction of the interposer 21, and conductor columns 31 made of tungsten are provided in the vias. ing. In the present embodiment, the diameters of the conductor columns 30 and 31 are both set to about 80 μm.

  On the upper surface 22, an upper surface side pad 28 that is a first surface side terminal is disposed at a position where the upper end surface of each conductor pillar 30 is present. The upper surface side pad 28 has a circular shape and a diameter of 120 μm, and the center-to-center distance 36 (see FIG. 3) between the adjacent upper surface side pads 28 and 28 is set to about 200 μm. On the other hand, a lower surface side pad 29 that is a second surface side terminal is disposed at a position where the lower end surface of each conductor pillar 31 is located on the lower surface 23. The lower surface side pad 29 is circular and has a diameter of 120 μm, and the center-to-center distance 37 (see FIG. 3) between the adjacent lower surface side pads 29 and 29 is set to about 300 μm. That is, in this embodiment, the center-to-center distance 37 between the adjacent lower surface side pads 29 and 29 is set to be about 100 μm larger than the center-to-center distance 36 between the adjacent upper surface side pads 28 and 28.

  On the surface of each upper surface side pad 28, an upper surface side solder bump 26 having a substantially hemispherical shape is provided. These upper surface side solder bumps 26 protrude from the upper surface 22 and are connected to the surface connection terminals 16 on the IC chip 15 side. On the surface of each lower surface side pad 29, lower surface side solder bumps 27 having a substantially hemispherical shape are provided. These lower surface side solder bumps 27 protrude from the lower surface 23 and are connected to the surface connection pads 46 on the wiring substrate 41 side via the substrate side solder bumps 49.

  As shown in FIG. 1, FIG. 2, FIG. 3, etc., the inner layer of the interposer body 38, more specifically, the interface between the first alumina insulating layer 24 and the second alumina insulating layer 25 is formed in a predetermined pattern. A wiring group composed of the plurality of wirings 32 is arranged. These wirings 32 are made of tungsten (W) and extend in the surface direction of the interposer 21. Such a wiring group has fan-out portions 33 where the intervals between adjacent wirings 32 are widened (see FIG. 3).

  As shown in FIGS. 1, 2, and 4, the wiring group includes a plurality of wirings 32 that extend from the central portion of the interposer body 38 toward the outer peripheral portion. One end of the wiring 32 is connected to the inner end of the conductor column 30 belonging to the first alumina insulating layer 24, and the other end of the wiring 32 is connected to the inner end of the conductor column 31 belonging to the second alumina insulating layer 25. As a result, a current flows through a path (or a path opposite thereto) of the upper surface side pad 28, the conductor column 30, the wiring 32, the conductor column 31, and the lower surface side pad 29. Therefore, in the semiconductor package structure 11 having such a structure, the wiring substrate 41 side and the IC chip 15 side are electrically connected via the conductor columns 30 and 31 and the wiring 32 of the interposer 21. Therefore, signals are input / output between the wiring board 41 and the IC chip 15 via the interposer 21, and power for operating the IC chip 15 as an MPU is supplied. When the interposer body 38 is a low-temperature fired ceramic substrate, the conductor columns 30 and 31 and the wiring 32 are preferably formed using silver (Ag) or copper (Cu) having high conductivity. The interposer 21 having the conductor columns 30 and 31 and the wiring 32 is suitable for speeding up.

  In this embodiment, the center-to-center distance 37 between the adjacent lower surface side pads 29, 29 is set to be larger than the center-to-center distance 36 between the adjacent upper surface side pads 28, 28. It is not limited to. For example, the center-to-center distance 37 between the adjacent lower surface side pads 29 and 29 and the center-to-center distance 36 between the adjacent upper surface side pads 28 and 28 may be the same center-to-center distance (about 200 μm). In this case, the wiring group such as the wiring 32 may be omitted.

  Here, a procedure for manufacturing the semiconductor package structure 11 having the above structure will be described.

  The interposer 21 is produced through the following procedure, for example. First, two alumina green sheets having a thickness of about 0.15 mm are manufactured by a known ceramic green sheet forming technique (unsintered body manufacturing process). Vias (through holes) are formed in a lattice shape at predetermined positions in the alumina green sheet. The via (through hole) is formed by, for example, drilling, punching, or laser processing. Vias (through holes) may be formed simultaneously with the formation of each alumina green sheet. In any case, in this embodiment, since drilling is performed at the stage of the green body, it is relatively easy and low-cost compared to the method of drilling at the stage of being a sintered body. Can be drilled.

  Next, a conventionally known tungsten paste (a paste containing a conductive metal) is printed using a screen printing device or the like, and the via paste is filled in the via (metal filling step). Further, after such a metal filling step, a tungsten paste is further printed on the alumina green sheet (metal layer forming step). As a result, a paste print layer that will later become the wiring 32 is formed in a predetermined pattern on the surface of one of the alumina green sheets, and a paste print layer that later becomes the lower surface side pad 29 is formed on the back surface. Further, a paste print layer that will later become the upper surface side pad 28 is formed on the surface of the other alumina green sheet.

  Next, by laminating the two alumina green sheets and applying a pressing pressure in the thickness direction, the alumina green sheets are integrated to form an alumina green sheet laminate (lamination step). At this time, a paste print layer that will later become the wiring 32 is arranged in the inner layer. Next, the alumina green sheet laminate is transferred to a firing furnace and heated to several hundreds of degrees Celsius, thereby simultaneously sintering alumina and tungsten in the paste (simultaneous firing step). Further, after a known solder material (for example, a solder material of Sn / Ag = 96.5 / 3.5) is printed on the upper surface side pad 28 and the lower surface side pad 29, reflow is performed. As a result, the upper surface side solder bump 26 having a predetermined height is formed on the upper surface side pad 28, and the lower surface side solder bump 27 having a height higher than that is formed on the lower surface side pad 29 (bump forming step). As a result, the interposer 21 shown in FIG. 2 is obtained.

Next, the IC chip 15 is placed on the upper surface 22 of the completed interposer 21. At this time, the surface connection terminals 16 on the IC chip 15 side and the upper surface side solder bumps 26 on the interposer 21 side are aligned. And by heating and reflowing each upper surface side solder bump 26, the upper surface side solder bump 26 and the surface connection terminal 16 are joined.
Next, the resin filler 81 is applied to the upper surface 22 of the interposer 21 by a known dispenser (not shown). The space between the interposer 21 and the IC chip 15 is filled with a resin filler 81, and the upper surface side solder bumps 26 are fixed with the resin filler 81.
Thereafter, the resin filler 81 is cured at a temperature of about 120 ° C.
As a result, the interposer 61 with an IC chip shown in FIG. 4 is completed (the resin filler 81 is omitted in FIGS. 4 and 5).

  Next, the wiring board 41 is prepared in advance, and a known solder material is printed on the surface connection pads 46 and reflowed to form the board-side solder bumps 49. Next, the lower surface side solder bumps 27 on the interposer 21 side and the substrate side solder bumps 49 on the surface connection pads 46 are aligned (see FIG. 5), and the interposer 61 with IC chip is mounted on the wiring substrate 41. Put. Then, the lower surface side bump 27 and the surface connection pad 46 are joined.

Thereafter, a resin filler 82 (not shown) is applied to the upper surface 42 of the wiring board 41 by a known dispenser (not shown). The space between the interposer 21 and the wiring substrate 41 is filled with a resin filler 82, and the lower surface side solder bumps 27 and the substrate side solder bumps 49 are fixed by the resin filler 82.
Thereafter, the resin filler 82 is cured at a temperature of about 120 ° C.
As a result, the semiconductor package structure 11 shown in FIG. 1 is completed.

  Therefore, according to the present embodiment, the following effects can be obtained.

(1) The resin filler 81 is filled between the IC chip 15 (semiconductor element) and the interposer body 38 (relay substrate body), or the wiring board 41 (substrate) and the interposer body 38 ( Since it is configured to be filled with the resin filler 82 between the relay substrate body) and the mounting portion between the IC chip 15 and the wiring substrate 41 (substrate) (that is, the IC chip 15 and The thermal stress between the interposer body 38 or between the wiring board 41 and the interposer body 38) is relieved.
Furthermore, since there are dummy terminals (first surface side dummy terminals 91, second surface side dummy terminals 92) and dummy conductor pillars 100, the conductor portion (metal portion) is uniformly formed on the inorganic insulating material portion of the relay substrate body 38. Be placed. Therefore, it is possible to effectively prevent the relay substrate body 38 from being deformed. Further, it is possible to prevent the flatness of the upper surface (first surface 22) or the lower surface (second surface 23) of the relay substrate main body 38 from being damaged, and the entire relay substrate 21 from being distorted. Cannot be accurately mounted, or the relay substrate 21 cannot be accurately mounted on the wiring board 41.
Therefore, it is possible to provide a structure including a semiconductor element, a relay substrate, and a substrate that has excellent connection reliability. In addition, it is possible to provide a relay substrate with a semiconductor element and a substrate with a relay substrate, which are suitable for realizing the above-described excellent structure.

  (2) In the semiconductor package structure 11 (structure), the center-to-center distance 37 between the adjacent lower surface side pads 29 and 29 is larger than the center-to-center distance 36 between the adjacent upper surface side pads 28 and 28. It is set to be. Therefore, it is possible to easily form a large lower surface side solder bump 27 on the lower surface side pad 29 with a large amount of solder. Therefore, the interposer 21 that is relatively easy to manufacture can be obtained. In this case, the center-to-center distance between the surface connection pads 46 corresponding to the lower surface side pads 29 can be set larger. Therefore, it is possible to easily form a large board-side solder bump 49 with a large amount of solder on the surface connection pad 46 on the wiring board 41 side. Therefore, the wiring board 41 that is relatively easy to manufacture can be obtained. In addition, since the yield of the wiring substrate 41 is improved and the defective product generation rate is reduced, the cost of the semiconductor package structure 11 can be reduced.

  (3) Furthermore, solder bumps 27 and 49 having a desired size can be formed on the lower surface side pad 29 and the surface connection pad 46. As a result, the interposer 21 and the wiring board 41 are firmly bonded via solder. Become so. Therefore, high connection reliability can be imparted between the interposer 21 and the wiring board 41.

  (4) The semiconductor package structure 11 (structure) is configured using a substantially plate-shaped interposer body 38 made of alumina. Therefore, the difference in coefficient of thermal expansion between the interposer 21 and the IC chip 15 is small. Therefore, a large thermal stress does not act directly on the IC chip 15. Therefore, even if the IC chip 15 is large and generates a large amount of heat, cracks and the like are unlikely to occur at the interface between the IC chip 15 and the interposer 21. Therefore, high reliability can be imparted to the chip bonding portion and the like, and the semiconductor package structure 11 excellent in connection reliability and durability can be realized. Moreover, alumina is an inexpensive ceramic material compared to silicon nitride and the like, and tungsten is also a commonly used conductive metal material. Therefore, when these are combined, the interposer 21 and the semiconductor package structure are relatively inexpensive. The body 11 can be realized.

  (5) In this embodiment, since the simultaneous firing method is adopted as a method for sintering tungsten contained in the paste, the number of steps is relatively small, and the interposer 21 can be efficiently and low-cost. Can be produced.

  In addition, you may change embodiment of this invention as follows.

For example, the semiconductor package structure 11 (structure) of the above embodiment may be manufactured as follows. As shown in FIG. 6, first, the interposer-attached wiring substrate 71 (substrate with a relay substrate) is prepared in advance by bonding the interposer 21 to the upper surface 42 of the wiring substrate 41 by soldering or the like.
Thereafter, a resin filler 82 (not shown) is applied to the upper surface 42 of the wiring board 41 by a known dispenser (not shown). The space between the interposer 21 and the wiring substrate 41 is filled with a resin filler 82, and the lower surface side solder bumps 27 and the substrate side solder bumps 49 are fixed by the resin filler 82.
Thereafter, the resin filler 82 is cured at a temperature of about 120 ° C.
Thereafter, the IC chip 15 is bonded to the upper surface 22 of the wiring board 71 with an interposer. Next, a resin filler 81 (not shown) is applied to the upper surface 22 of the interposer 21 by a known dispenser (not shown). The space between the interposer 21 and the IC chip 15 is filled with a resin filler 81, and the upper surface side solder bumps 26 are fixed with the resin filler 81.
Thereafter, the resin filler 81 is cured at a temperature of about 120 ° C.
As a result, a desired semiconductor package structure 11 is obtained (see FIG. 1).

  In the semiconductor package structure 11 of the above embodiment, the interposer 21 is configured using the interposer body 38 having a two-layer structure, but the interposer 21 may be configured using an interposer body having a multilayer structure of three or more layers. Good. Conversely, the interposer 21 may be configured using an interposer body having a single layer structure instead of a multilayer structure.

  In the above-described embodiment, the wiring group is formed only on the inner layer of the interposer body 38. However, the present invention is not limited to this. For example, the wiring group is formed on the inner layer and the upper surface 22, and the wiring group is formed on the inner layer and the lower surface 23. A mode in which wiring groups are formed on the inner layer, the upper surface 22 and the lower surface 23 may be used.

  Next, in addition to the technical ideas described in the claims, a part of the technical ideas grasped by the embodiment described above will be listed below.

  (1) First surface side bumps are formed on the surfaces of the plurality of first surface side terminals, and second surface side bumps are formed on the surfaces of the plurality of second surface side terminals. The relay board as described above.

  (2) First surface side solder bumps are formed on the surfaces of the plurality of first surface side terminals, and solder is formed on the surfaces of the plurality of second surface side terminals more than the first surface side solder bumps. The relay substrate as described above, wherein a large amount of the second surface side solder bumps are formed.

  (3) The relay board described above, wherein the wiring group is arranged in an inner layer of the relay board body.

  (4) The relay board described above, wherein the wiring group is arranged only in an inner layer of the relay board body.

  (5) The relay substrate body is formed of a ceramic laminated sintered body having a structure in which a plurality of ceramic insulating materials are laminated, and the wiring group is disposed in an inner layer of the ceramic laminated sintered body. The above relay board.

  (6) The relay board described above, wherein a thickness of the relay board body is 0.1 mm or more and 0.7 mm or less.

  (7) The relay board described above, wherein a thickness of the relay board body is 0.1 mm or more and 0.3 mm or less.

(8) The relay substrate described above, wherein at least one side of the semiconductor element is 10.0 mm or more.
(9) The relay substrate described above, wherein the semiconductor element has a thickness of 1.0 mm or less.

  (10) A plurality of ceramics having a first surface on which a semiconductor element having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. and having a surface connection terminal is mounted; An approximately plate-shaped relay substrate body made of a ceramic laminated sintered body having a structure in which insulating materials are stacked, a plurality of first surface side terminals disposed on the first surface side, and disposed on the second surface side A plurality of second surface side terminals; a first surface side solder bump formed on a surface of the plurality of first surface side terminals; and a surface of the plurality of second surface side terminals; A second surface side solder bump having a larger amount of solder than the surface side solder bump, a plurality of conductor pillars provided in the relay board body and extending in the thickness direction of the relay board, and the relay so as to extend in the direction of the relay board surface A plurality of wires provided in the inner layer of the substrate body and connected to the conductor pillars And a wiring group having a fan-out portion in which the distance between adjacent wirings is widened, and the first surface side terminal and the second surface side terminal via the plurality of conductor pillars and the wiring group Are connected to each other, and the center-to-center distance between adjacent second surface side terminals is set to be larger than the center-to-center distance between adjacent first surface side terminals. The above relay board.

  (11) A green body manufacturing step of manufacturing a ceramic green body having a plurality of through holes, a metal filling step of filling the plurality of through holes with a conductive metal, and the ceramic green body A metal layer forming step of forming a layer made of a conductive metal on the surface in a predetermined pattern; and a co-firing step of heating and sintering the ceramic unsintered body and the conductive metal. A method for manufacturing the relay board.

  (12) A green body manufacturing step of manufacturing a ceramic green body having a plurality of through holes, a metal filling step of filling a conductive metal into the plurality of through holes, and the ceramic green body A metal layer forming step for forming a layer made of a conductive metal on the surface in a predetermined pattern, and the ceramic unsintered body that has undergone the metal filling step and the metal layer forming step, the layer made of the conductive metal as an inner layer A lamination step of laminating a plurality of sheets in a state where they are arranged and integrated to form an unsintered laminate, and a co-firing step of heating and sintering the ceramic unsintered body and the conductive metal. A method for manufacturing the relay board as described above.

1 is a schematic cross-sectional view showing a semiconductor package structure (structure) according to an embodiment including an IC chip (semiconductor element), an interposer (relay substrate), and a wiring substrate (substrate). 1 is a schematic cross-sectional view showing an interposer (relay substrate) that constitutes a semiconductor package structure according to an embodiment. The partial enlarged plan view which shows the interposer (relay board | substrate) of embodiment. 1 is a schematic cross-sectional view showing an interposer with an IC chip (a relay substrate with a semiconductor element) that constitutes the semiconductor package structure of the present embodiment. It is a schematic sectional drawing which shows a state when mounting the interposer with an IC chip of this embodiment on a wiring board. In another embodiment, the schematic sectional drawing which shows a state when mounting an IC chip on a wiring board with an interposer (substrate with a relay board). It is a fragmentary top view which shows the state which planarly viewed the IC chip and interposer of FIG. 1 of this embodiment partially.

Explanation of symbols

11: Semiconductor package structure as a structure composed of a semiconductor element, a relay substrate, and a substrate 15: IC chip as a semiconductor element 16: Surface connection terminal 21: Interposer as a relay substrate 22: First of relay substrate main body Upper surface as a surface 23: Lower surface as a second surface (of the relay board body) 28: Upper surface side pad as a first surface side terminal 29: Lower surface side pad as a second surface side terminal 30, 31: One of conduction structure Conductor pillars 32: Wiring that is part of the conductive structure 33: Fan-out part 36: Center-to-center distance between adjacent first surface side terminals 37: Center-to-center distance between adjacent second surface side terminals 38: Interposer body as a relay board body 41: Wiring board as a board 46: Surface connection pad 61: Interposer with IC chip as a relay board with semiconductor elements 71: Relay the interposer with the wiring of the substrate with the substrate board 81: resin filler 82: resin filler 91: first surface side dummy terminal 92: second face dummy terminal 100: dummy conductor post

Claims (3)

Comprising a semiconductor element having a surface connection terminal, and
A substantially substrate-shaped relay substrate body having a first surface on which the semiconductor element is mounted and a second surface and made of an inorganic insulating material;
A plurality of first surface side terminals disposed on the first surface side; a plurality of second surface side terminals disposed on the second surface side; and the first surface side terminals provided on the relay board body. And a conduction structure for conducting the second surface side terminals with each other,
The relay board with a semiconductor element is characterized in that at least one of a dummy terminal and a dummy conductor pillar not connected to the surface connection terminal of the semiconductor element is formed on the relay board body. Comprising a substrate having surface connection pads, and
A substantially board-shaped relay substrate body having a first surface on which a semiconductor element is to be mounted and a second surface to be mounted on the surface of the substrate, and made of an inorganic insulating material;
A plurality of first surface side terminals disposed on the first surface side; a plurality of second surface side terminals disposed on the second surface side; and the first surface side terminals provided on the relay board body. And a conduction structure for conducting the second surface side terminals with each other,
A substrate with a relay substrate, wherein at least one of a dummy terminal and a dummy conductor column not connected to a surface connection terminal of the semiconductor element is formed on the relay substrate body. Comprising a semiconductor element having a surface connection terminal;
Comprising a substrate having surface connection pads, and
A substantially board-shaped relay substrate body made of an inorganic insulating material, having a first surface on which the semiconductor element is mounted and a second surface mounted on the surface of the substrate;
A plurality of first surface side terminals disposed on the first surface side; a plurality of second surface side terminals disposed on the second surface side; and the first surface side terminals provided on the relay board body. And a conduction structure for conducting the second surface side terminals with each other,
The relay substrate main body is formed with at least one of a dummy terminal and a dummy conductor column that are not connected to the surface connection terminal of the semiconductor element, and a structure comprising a semiconductor element, a relay substrate, and a substrate body.