JP2005217201A - Extension board and substrate having the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a relatively inexpensive extension board although cracks cannot easily be generated and reliability is improved. <P>SOLUTION: The extension board 31 comprises a extension board body 38 and a plurality of conductive sections 35. The extension board body 38 has a first surface 32 in which a semiconductor element 21 having a face connection terminal 22 should be packaged, and a second surface 33. The extension board body 38 has a plurality of through holes 34 for connecting the first and second surfaces 32, 33. The extension board body 38 is made of an organic macromolecular material in which a Young's modulus is 25 GPa or smaller. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a relay board and a board with a relay board that are interposed between a semiconductor element and a board to achieve electrical connection between the two.

In recent years, instead of directly connecting a wiring board (IC mounting board, IC package, etc.) on which an IC chip is mounted and a printed board such as a mother board, a relay board called an interposer is interposed between the wiring board and the mother board. Various structures are known in which they are electrically connected to each other (see, for example, Patent Document 1). An inorganic material such as ceramic is used as a material for such an interposer. Recently, an interposer for connecting at a level different from the above-described interposer, specifically, an interposer for connecting between an IC chip and a wiring board has been proposed. In this specification, for convenience, the former will be referred to as “second level interposer” and the latter will be referred to as “first level interposer”.
Japanese Unexamined Patent Publication No. 2000-208661 (FIG. 2 (d), etc.)

  Incidentally, the IC chip is generally formed using a semiconductor material (for example, silicon) having a thermal expansion coefficient of about 2.0 ppm / ° C. to 5.0 ppm / ° C. On the other hand, the wiring board is formed using a material having a significantly larger thermal expansion coefficient than the semiconductor material, for example, a resin material of 10.0 ppm / ° C. or higher. Therefore, in a structure using a first level interposer, stress is likely to occur due to a difference in thermal expansion coefficient between the IC chip and the wiring board. This stress causes cracks in the joint portion between the interposer and other components and the IC chip itself, and becomes a factor of reducing the reliability of the structure. Therefore, in order to prevent the occurrence of cracks, it is desirable to give the first level interposer, for example, high rigidity so as to withstand stress. Therefore, at present, inorganic materials such as ceramics with a high Young's modulus are considered suitable as materials for first level interposers.

  However, since ceramic materials (especially ceramic materials with high Young's modulus) are expensive, there is a problem that it is difficult to reduce the cost of the interposer.

  The present invention has been made in view of the above problems, and an object thereof is to provide a relatively inexpensive relay board and a relay board with a semiconductor element, although cracks are less likely to occur and the reliability is excellent. It is in.

  Therefore, the inventor of the present application has intensively studied to prevent the occurrence of cracks due to stress.

  As shown in the following formula 1, Young's modulus (longitudinal elastic modulus: E) is a ratio of stress σ and strain ε when the material behaves elastically, and is a measure of the strength of the material.

      E = σ / ε Equation 1

  According to the following equation 2 obtained by modifying the above equation 1, the stress σ is expressed by the product of the Young's modulus E and the strain ε. This equation 2 means that the stress value σ decreases as the Young's modulus E decreases.

      σ = E · ε Equation 2

  Therefore, the present inventor has conceived to adopt a method completely opposite to the conventional idea of using a high-rigidity relay board material, that is, to use a low-rigidity relay board material, and finally the following invention. Completed.

  Means for solving the above problems include a first surface on which a semiconductor element having surface connection terminals is to be mounted and a second surface, and a plurality of through holes that communicate the first surface and the second surface. A relay board body having a substantially plate shape made of an organic polymer material having a Young's modulus of 25 GPa or less, and a plurality of relay terminals disposed in the plurality of through holes and electrically connected to the surface connection terminals There is a relay board including a conductor portion. In addition, as another means for solving the above-described problem, an organic polymer substrate having a thermal expansion coefficient of 10.0 ppm / ° C. or more and 30.0 ppm / ° C. or less and having a surface connection pad is provided. And a second surface mounted on the surface of the organic polymer substrate, a plurality of through-holes communicating the first surface and the second surface, and a high organic modulus having a Young's modulus of 25 GPa or less A relay board having a substantially plate-shaped relay board body made of a molecular material, and a plurality of conductor portions arranged in the plurality of through holes and electrically connected to the surface connection pads, There is a board with a relay board.

  Therefore, according to these inventions, since the relay substrate is configured using the low-rigidity relay substrate body having a Young's modulus of 25 GPa or less, the relay substrate can be used even when the organic polymer substrate is thermally expanded or contracted. Following that, it can be elastically distorted (deformed). Therefore, the influence of the stress generated due to the difference in thermal expansion coefficient is reduced. Therefore, it is difficult for cracks to occur in the junction between the relay substrate and other components (for example, an organic polymer substrate or a semiconductor element) or the semiconductor element itself, and it is possible to realize a relay substrate with excellent reliability and a substrate with a relay substrate. it can. Moreover, since organic polymer materials are generally not as expensive as ceramic materials, if they are used as a material for forming a relay board body, a relatively inexpensive relay board and a board with a relay board can be realized.

  The relay board main body constituting the relay board or the board with the relay board is a substantially plate-shaped member having a first surface and a second surface.

  The first surface of the relay board body is a surface on which a semiconductor element having surface connection terminals is to be mounted, in other words, a surface on which a semiconductor element having surface connection terminals is to be mounted. As the semiconductor element, for example, one having a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C. is used. Examples of such a semiconductor element include a semiconductor integrated circuit chip (IC chip) made of silicon having a thermal expansion coefficient of about 2.6 ppm / ° C. Note that the number of semiconductor elements to be mounted on the first surface of the relay substrate body may be one or two or more.

  Here, “thermal expansion coefficient” means a thermal expansion coefficient in a direction (XY direction) perpendicular to the thickness direction (Z direction), and a TMA (thermomechanical analyzer between 0 ° C. and 100 ° C. ) Means the value measured. “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01.

  The surface connection terminal refers to a terminal for electrical connection, which is connected by surface connection. In addition, surface connection refers to the case where pads or terminals are formed in a line shape or a lattice shape (including a staggered shape) on the plane of an object to be connected, and these are connected to each other. The size and shape of the semiconductor element are not particularly limited, but at least one side is preferably 10.0 mm or more. This is because in such a large-sized semiconductor element, the amount of heat generation is likely to increase, and the influence of stress gradually increases, so that problems unique to the present application such as the occurrence of cracks are likely to occur. Further, the thickness of the semiconductor element is not particularly limited, but is preferably 1.0 mm or less (however, 0 mm is not included). This is because, when the semiconductor element is 1.0 mm or less, the strength of the semiconductor element is weakened, so that problems specific to the present application such as generation of cracks are likely to occur.

  On the other hand, the 2nd surface of the relay substrate main body which comprises a board | substrate with a relay substrate is a surface mounted on the surface of the organic polymer substrate which has a surface connection pad. The second surface of the relay substrate main body constituting the relay substrate is to be mounted on the surface of the organic polymer substrate having the surface connection pads, in other words, mounted on the surface of the organic polymer substrate having the surface connection pads. Is to be planned. The surface connection pad refers to a terminal pad for electrical connection, which is connected by surface connection. Such surface connection pads are formed in, for example, a linear shape or a lattice shape (including a staggered shape).

  The reason for using the organic polymer substrate in the present invention is to reduce the overall cost by making the substrate material an organic polymer. Here, the organic polymer substrate means a substrate (resin substrate) composed mainly of an organic polymer material such as a resin. Specific examples of the resin substrate include an EP resin (epoxy resin) substrate, a PI resin (polyimide resin) substrate, a BT resin (bismaleimide-triazine resin) substrate, and a PPE resin (polyphenylene ether resin) substrate. In addition, a substrate made of a composite material of these resins and organic fibers such as glass fibers (glass woven fabric or glass nonwoven fabric) or polyamide fibers may be used. Alternatively, a substrate made of a resin-resin composite material obtained by impregnating a thermosetting resin such as an epoxy resin with a three-dimensional network fluorine-based resin base material such as continuous porous PTFE may be used.

  In this case, the thermal expansion coefficient of the organic polymer substrate is preferably 10.0 ppm / ° C. or more and 30.0 ppm / ° C. or less. This is because when the thermal expansion coefficient is less than 10.0 ppm / ° C., the cost of the organic polymer substrate is easily increased. In addition, when an organic polymer substrate having a thermal expansion coefficient exceeding 30.0 ppm / ° C. is used, the difference in thermal expansion coefficient from a semiconductor element or the like becomes very large. Therefore, even if a relay substrate is interposed, the influence of stress may not be sufficiently reduced.

  The organic polymer substrate is preferably a wiring substrate provided with a conductor circuit, and a semiconductor element or other electronic component is mounted on the wiring substrate.

  The relay substrate main body constituting the relay substrate or the substrate with the relay substrate is made of an organic polymer material having a Young's modulus of 25 GPa or less (excluding 0 GPa). The reason is that the influence of stress cannot be sufficiently reduced in a relay substrate body made of an organic polymer material having a Young's modulus exceeding 25 GPa. The Young's modulus of the organic polymer material is more preferably 0.01 GPa or more and 10 GPa or less, and particularly preferably 0.01 GPa or more and 5 GPa or less. When the Young's modulus is 10 GPa or less, a sufficient stress reduction effect can be obtained.

  In addition to having a low Young's modulus as described above, the organic polymer material constituting the relay substrate main body preferably has a low thermal expansion property. That is, the thermal expansion coefficient of the organic polymer material is preferably an intermediate value between the semiconductor element and the organic polymer substrate, for example, 5.0 ppm / ° C. or more and 20.0 ppm / ° C. or less, particularly 5.0 ppm. It is good that it is / ppm or more and 10.0 ppm / degrees C or less. The reason is that if the thermal expansion coefficient of the relay substrate body is less than 5.0 ppm / ° C., the difference in thermal expansion coefficient from the semiconductor element is reduced, while the difference in thermal expansion coefficient from the organic polymer substrate is increased. Therefore, a large stress comes to act on the junction between the relay substrate and the organic polymer substrate, which is not preferable. On the contrary, if the thermal expansion coefficient of the relay substrate body exceeds 20.0 ppm / ° C., the difference in thermal expansion coefficient from the organic polymer substrate decreases, while the difference in thermal expansion coefficient from the semiconductor element increases. Therefore, a large stress comes to act on the junction between the relay substrate and the semiconductor element, which is not preferable.

  Moreover, it is preferable that the organic polymer material constituting the relay substrate body has not only low rigidity and low thermal expansion, but also insulation. The reason for this is that in the case of a relay board body using a material that does not have insulating properties, it is necessary to form an insulating layer in order to insulate the conductor portion, and there is a problem that the structure is complicated and the cost is increased accordingly. Because it occurs. On the other hand, in the relay substrate body using an insulating material, an insulating layer is not necessary, so that the structure can be simplified and the cost can be reduced.

  Specific examples of suitable organic polymer materials constituting the relay substrate body include epoxy-based and rubber-based resin materials. Of course, it is desirable that such a resin material has the characteristics such as low rigidity, low thermal expansion, and insulation. Of course, it is possible to select a resin material other than an epoxy-based material or a rubber-based material and having the above properties.

  Further, the content of the organic polymer material in the relay substrate body is 70% or more, preferably 80% or more, and more preferably 95% or more by weight. That is, it is preferable that the relay substrate body contains little or no inorganic fiber and inorganic filler. The reason is that if the content of the inorganic substance in the relay substrate body is increased, it is difficult not only to achieve a low Young's modulus but also to increase the cost.

  The thickness of the relay substrate main body is not particularly limited, but is preferably 0.3 mm or more and 1.0 mm or less. This is because if the thickness is less than 0.3 mm, the effect of interposing the relay substrate body, that is, the stress reduction effect may not be sufficiently obtained. In addition, if the thickness exceeds 1.0 mm, not only the thickness of the entire structure increases, but also the formation of a small-diameter conductor portion becomes difficult and the manufacturing cost may increase. Note that the thickness of the relay substrate body is more preferably 0.3 mm or more and 0.7 mm or less.

  The relay board main body constituting the relay board or the board with the relay board has a plurality of through holes that allow the first surface and the second surface to communicate with each other. The diameter of the through hole is not particularly limited, but is preferably 125 μm or less, for example, and more preferably 100 μm or less (however, 0 μm is not included). The center-to-center distance between the adjacent through holes is not particularly limited, but is preferably, for example, 250 μm or less, and more preferably 200 μm or less (however, 0 μm is not included). This is because, if the diameter and the distance between the centers are too large, there is a possibility that the semiconductor elements that are expected in the future cannot be sufficiently refined. In other words, if the diameter and the distance between the centers are set too large, a large number of conductor portions cannot be formed within a limited area. Furthermore, the diameter of the through hole is preferably 85 μm or less, and the center-to-center distance between the adjacent through holes is preferably 150 μm or less (however, 0 μm is not included).

  Moreover, the relay board | substrate and board | substrate with a relay board | substrate of this invention have several conductor parts arrange | positioned in several through-holes. For example, these conductor portions are formed in a columnar shape having end portions exposed on each of the first surface side and the second surface side. The plurality of conductor portions in the relay substrate should be electrically connected to the surface connection terminals of the semiconductor element and the surface connection pads of the organic polymer substrate. The plurality of conductor portions in the substrate with the relay substrate are electrically connected to the surface connection pads of the organic polymer substrate.

  The conductor portion is formed, for example, by filling a plurality of through holes with a conductive metal. Although it does not specifically limit as said electroconductive metal, For example, 1 type, or 2 or more types of metals selected from copper, gold | metal | money, silver, platinum, palladium, nickel, tin, lead, titanium, tungsten, molybdenum, tantalum, niobium etc. Can be mentioned. Examples of the conductive metal composed of two or more metals include solder that is an alloy of tin and lead. As a specific method for forming a conductor portion by filling a plurality of through holes with a conductive metal, for example, a non-solid material containing a conductive metal (for example, a conductive metal paste) is prepared and printed and filled. In addition, there is a method of conducting conductive metal plating. Moreover, you may employ | adopt the method of embedding solid material, specifically, a metal lump, a metal pillar, etc. in a through-hole. In addition, when forming a conductor part by filling with a conductive metal, it is preferable to fill up a through-hole almost completely so that a cavity may not arise inside. The reason is to reduce the resistance of the conductor part and increase the strength of the conductor part itself.

  When the conductor portion is a conductor column, a solder layer is formed on at least one end surface of the conductor column, particularly on the first surface side end surface on which the semiconductor element is to be mounted, for convenience of connection. Also good. The solder layer is preferably a solder bump formed so as to protrude from the first surface. This is because the presence of such solder bumps makes it possible to mount bumpless semiconductor elements. Of course, the solder layer may be formed on both end faces of the plurality of conductor pillars. The solder used for forming the solder layer is not particularly limited, and can be arbitrarily selected according to the application. In addition, when the conductor column is formed using solder, a part of the conductor column may protrude from the first surface or the second surface to form a solder bump.

  Further, one or more electronic components and elements other than semiconductor elements may be provided on the surface of the relay substrate body, particularly on the first surface and the second surface. Specific examples of the electronic component include a chip transistor, a chip diode, a chip resistor, a chip capacitor, and a chip coil. These electronic components may be active components or passive components. Specific examples of the element include a thin film transistor, a thin film diode, a thin film resistor, a thin film capacitor, and a thin film coil. These elements may be active elements or passive elements. And even if the wiring layer which connects the said electronic components, the said elements, or the said electronic components, the said element, and a conductor pillar is formed on the 1st surface or the 2nd surface of the said relay substrate main body. Good. By providing electronic components and elements in this way, the added value of the relay board or the board with the relay board can be increased.

  For example, in the case of a relay substrate with a thin film capacitor or a substrate with a relay substrate, the thin film capacitor is arranged on the power line (that is, on the wiring connecting the power circuit on the substrate side and the power terminal on the semiconductor element side). Is good. With this configuration, noise (voltage fluctuation) on the power supply line can be absorbed. Therefore, high frequency noise in the GHz band can be reduced, and the semiconductor element can be operated at high speed. Here, the thin film capacitor means a capacitor having a structure in which a ferroelectric thin film is sandwiched between conductors.

[First Embodiment]

  Hereinafter, a first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a semiconductor package 11 of this embodiment including an IC chip (semiconductor element) 21, an interposer (relay substrate) 31, and a wiring substrate (organic polymer substrate) 41. 2 to 9 are schematic cross-sectional views for explaining the manufacturing process of the interposer 31. FIG. 10 is a schematic cross-sectional view showing the completed interposer 31. FIG. 11 is a schematic cross-sectional view showing a state where an interposer with an IC chip (a relay board with a semiconductor element) 61 constituting the semiconductor package 11 is mounted on the wiring board 41.

  As shown in FIG. 1, the semiconductor package 11 of this embodiment is an LGA (land grid array) including the IC chip 21, the interposer 31, and the wiring substrate 41 as described above. Note that the form of the semiconductor package 11 is not limited to LGA alone, and may be, for example, BGA (ball grid array), PGA (pin grid array), or the like. The IC chip 21 having a function as an MPU is a rectangular flat plate having a length of 12.0 mm, a width of 10.0 mm, and a thickness of 0.7 mm, and is made of silicon having a thermal expansion coefficient of about 2.6 ppm / ° C. Circuit elements (not shown) are formed on the lower surface layer of the IC chip 21. A plurality of surface connection terminals 22 are provided in a lattice pattern on the lower surface side of the IC chip 21. Bumps are not particularly provided on the surface of these surface connection terminals 22.

  The wiring board 41 is a rectangular flat plate (45 mm square) resin multilayer wiring board having an upper surface 42 and a lower surface 43. This multilayer wiring board is composed of a resin core board 52 having through-hole conductors 51 and build-up layers formed on both sides thereof. The build-up layer has a structure in which a plurality of resin insulation layers 44 and a plurality of conductor circuits 45 are alternately stacked. In the case of this embodiment, specifically, the resin insulating layer 44 is formed of an insulating base material obtained by impregnating a glass cloth with an epoxy resin, and the conductor circuit 45 is formed of a copper foil or a copper plating layer. The thermal expansion coefficient of the wiring board 41 is 13.0 ppm / ° C. or more and less than 16.0 ppm / ° C. On the upper surface 42 of the wiring substrate 41, a plurality of surface connection pads 46 for electrical connection with the interposer 31 side are formed in a lattice shape. On the lower surface 43 of the wiring substrate 41, a plurality of surface connection pads 47 for electrical connection with a mother board (not shown) are formed in a lattice shape. The surface connection pads 47 for connecting the motherboard have a wider area and a wider pitch than the surface connection pads 46 for interposer connection. Via hole conductors 48 are provided in the resin insulating layer 44, and through-hole conductors 51, conductor circuits 45 of different layers, surface connection pads 46, and surface connection pads 47 are electrically connected to each other via these via hole conductors 48. It is connected to the. In addition to the interposer 61 with an IC chip in FIG. 11, a chip capacitor, a semiconductor element, and other electronic components (all not shown) are mounted on the upper surface 42 of the wiring board 41.

  The interposer 31 of this embodiment is to be called a so-called first level interposer, and includes a rectangular flat plate-shaped interposer body 38 (relay board body) having an upper surface 32 (first surface) and a lower surface 33 (second surface). Have. The interposer body 38 is made of a resin substrate formed of an epoxy resin having a thickness of about 0.3 mm. Such a resin substrate has a thermal expansion coefficient of about 10 ppm / ° C. and a Young's modulus of about 0.06 GPa.

  Therefore, the thermal expansion coefficient of the interposer body 38 is smaller than the thermal expansion coefficient of the wiring substrate 41 and larger than the thermal expansion coefficient of the IC chip 21. That is, the interposer 31 of this embodiment has a lower thermal expansion than the wiring board 41. The Young's modulus of the IC chip 21 is about 190 GPa, whereas the Young's modulus of the interposer body 38 is considerably lower than that. That is, the interposer 31 of this embodiment has extremely low rigidity. Moreover, since the interposer body 38 of this embodiment does not contain any inorganic fibers and inorganic fillers, the content of the organic polymer material in the interposer body 38 is 95% or more by weight.

  In the interposer main body 38 constituting the interposer 31, a plurality of vias 34 (through holes) penetrating the upper surface 32 and the lower surface 33 are formed in a lattice shape. These vias 34 correspond to the positions of the surface connection pads 46 of the wiring board 41. And in this via 34, the conductor pillar 35 which consists of solder (For example, the thing of a composition of Pb90% -Sn10%) is provided. The upper end of each conductor column 35 is an interposer-side solder bump 36 protruding from the upper surface 32 by about 100 μm. The interposer-side solder bumps 36 are electrically connected to the surface connection terminals 22 on the IC chip 21 side. On the other hand, board-side solder bumps 37 are provided on the surface connection pads 46 on the wiring board 41 side. The lower end surface of each conductor column 35 is electrically connected to each surface connection pad 46 via these board-side solder bumps 37. In the present embodiment, the interposer-side solder bumps 36 are not particularly provided on the lower end surface of each conductor pillar 35, but a configuration in which this is provided may be employed.

  In the semiconductor package 11 having such a structure, the wiring substrate 41 side and the IC chip 21 side are electrically connected via the conductor pillar 35 of the interposer 31. Therefore, signals are input / output between the wiring board 41 and the IC chip 21 via the interposer 31, and power for operating the IC chip 21 as an MPU is supplied.

  Here, a procedure for manufacturing the semiconductor package 11 having the above structure will be described.

  First, the wiring board 41 is produced in the following manner. That is, a core substrate 52 having through-hole conductors 51 is prepared, and a buildup layer composed of a resin insulating layer 44 and a conductor circuit 45 is formed on both surfaces thereof by a conventionally known buildup process. Then, after forming a solder resist (not shown) as necessary, the solder paste is printed and reflowed to provide the board-side solder bumps 37 on the respective surface connection pads 46. In the present embodiment, eutectic solder (Pb 36% -Sn 64%) or the like is used for forming the substrate-side solder bumps 37, for example.

  Next, the interposer 31 is produced in the following manner. First, a copper clad laminate 55 as a starting material is prepared. As shown in FIG. 2, the copper clad laminate 55 is obtained by sticking a copper foil 56 on both surfaces of a rectangular epoxy resin plate 54. Next, for example, laser processing using a carbon dioxide laser is performed on the copper clad laminate 55 to form a large number of vias 34 penetrating the front and back of the copper clad laminate 55 (see FIG. 3). . Of course, the via 34 may be formed by a drilling method other than laser processing, such as drilling. Next, panel plating is performed on the entire surface of the copper-clad laminate 55, thereby depositing a copper plating layer 57 on the surface of the copper foil 56 and the inner surface of the via 34 (see FIG. 4). It is not essential to provide the copper plating layer 57 on the inner surface of the via 34, and may be omitted if unnecessary. The merit when the copper plating layer 57 is not provided is that it is easy to achieve a narrow pitch of the conductor pillars 35. On the other hand, the merit when the copper plating layer 57 is provided is that the solder pillars are improved, so that the conductor pillar 35 having a desired shape can be easily obtained. Next, a plating resist (not shown) is formed on the copper plating layers 57 on both the front and back surfaces, and unnecessary portions in the copper plating layer 57 are removed by etching in this state to complete the interposer body 38 (see FIG. 5). The interposer main body 38 thus obtained is transferred to a paste printing device (not shown), and the solder paste 60 is printed with a predetermined solder resist 58 provided on the upper surface 32 side (see FIG. 6). The solder resist 58 is provided with a large number of through holes 59 corresponding to the positions where the vias 34 are located. The thickness of the solder resist 58 is determined based on the size of the interposer side solder bump 36 to be obtained. In this embodiment, the thickness is set to about 150 μm to 200 μm. When the above solder paste printing is performed, the solder paste 60 is filled into each via 34 through each through hole 59 (see FIG. 7). Next, the solder resist 58 is removed from the upper surface 32 of the interposer body 38 (see FIG. 8). At this time, a part of the solder paste 60 protrudes from the upper surface side opening of the via 34. Then, reflow is performed to form a conductor column 35 having interposer-side solder bumps 36 on the upper end side (see FIG. 9). As a result, the interposer 31 having a desired structure shown in FIG. 10 is completed.

  Next, the IC chip 21 is placed on the upper surface 32 of the completed interposer 31. At this time, the surface connection terminals 22 on the IC chip 21 side and the interposer side solder bumps 36 are aligned. Then, the interposer side solder bumps 36 and the surface connection terminals 22 are flip-chip connected by heating and reflowing the interposer side solder bumps 36. As a result, the interposer 61 with IC chip shown in FIG. 11 is completed.

  Next, the lower end surface of each conductor column 35 on the interposer 31 side and each board-side solder bump 37 on the wiring board 41 side are aligned (see FIG. 11), and the interposer 61 with IC chip is placed on the wiring board 41. Is placed. And the lower end surface of each conductor pillar 35 and each surface connection pad 46 are joined via each board side solder bump 37, respectively. Thereafter, if necessary, the interface is sealed with an underfill (not shown) to complete the semiconductor package 11 shown in FIG.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) The interposer 31 of this embodiment has a Young's modulus of about 0.06 GPa, and is configured using an interposer body 38 with extremely low rigidity. Therefore, even when the resin wiring board 41 is thermally expanded or contracted in the X and Y directions, the interposer 31 can follow and elastically distort (deform). Therefore, the influence of the stress generated due to the difference in thermal expansion coefficient is reduced. Moreover, the interposer body 38 also has a preferable property of low thermal expansion. Therefore, cracks are unlikely to occur in the joint portion IC chip 21 itself between the interposer 31 and other components (that is, the wiring board 41 and the IC chip 21). As a result, the semiconductor package 11 having excellent reliability can be obtained.

  (2) In general, resin materials that are representative examples of organic polymer materials are not as expensive as ceramic materials. Therefore, if this is used as a material for forming the interposer body 38, a relatively inexpensive interposer 31 can be realized, and as a result, the cost reduction of the semiconductor package 11 can be easily achieved. Of course, in the present embodiment, the wiring board 41 is also made of resin, which contributes to the cost reduction of the semiconductor package 11 without fail.

  (3) Moreover, since the interposer body 38 of the present embodiment is made of an epoxy resin having suitable insulating properties, an insulating layer for insulation from the conductor pillar 35 is not particularly required. Therefore, simplification of the structure and cost reduction can be achieved.

(4) The semiconductor package 11 of the present embodiment can be manufactured by the following procedure. As shown in FIG. 12, the interposer 31 is joined to the upper surface 42 of the wiring board 41 by soldering or the like, so that a wiring board with an interposer (substrate with a relay board) 71 is produced in advance. Thereafter, the IC chip 21 is bonded to the upper surface 32 of the wiring board 71 with an interposer to obtain a desired semiconductor package 11.
[Second Embodiment]

  Next, another method for manufacturing the interposer 31 having the above structure will be described as a second embodiment. FIGS. 13 and 14 are schematic cross-sectional views for explaining a method for manufacturing the interposer 31.

  In the present embodiment, the conductor pillar forming jig 81 and the load jig 82 are basically used for forming the conductor pillar 35. In this case, the conductor post forming jig 81 and the load jig 82 are made of a material that has heat resistance and does not wet the molten Pb—Sn eutectic solder. In the present embodiment, these jigs 81 and 82 are both made of carbon. A concave portion 83 having a conical tip is formed at a position corresponding to each via 34 of the interposer body 38 on the upper surface of the conductor post forming jig 81.

  Then, the interposer body 38 is placed on the upper surface of the conductor post forming jig 81 with the surface on which the interposer-side solder bumps 36 are to be formed facing downward. In this state, a Pb—Sn eutectic solder (Pb 36% -Sn 64%) ball 84 having a diameter of about 150 μm to 300 μm is placed in the upper opening of each via 34 of the interposer body 38, and a load jig 82 is further attached. Place (see FIG. 13).

  Subsequently, these are put into a reflow furnace having a maximum temperature of 210 ° C. and 183 ° C. or higher in a nitrogen atmosphere, and the eutectic solder balls 84 are heated and melted. Then, the melted eutectic solder is pressed downward by the weight of the load jig M. As a result, as shown in FIG. 14, the eutectic solder is filled in the via 34 and welded to the copper plating layer 57 on the inner surface of the via 34. Further, a part of the eutectic solder protruding from the lower opening of the via 34 is formed into a substantially hemispherical shape following the shape of the recess 83 to form the interposer-side solder bump 36. And after performing such reflow, if the eutectic solder is solidified by cooling, the interposer 31 shown in FIG. 10 etc. can be obtained.

  The eutectic solder balls 84 may be placed not only in the upper openings of the vias 34 but also in the recesses 83 for reflow. In this case, the heat-melted eutectic solders are integrated in the via 34 by the action of surface tension.

  It goes without saying that the present invention is not limited to the first embodiment and the second embodiment described above, and can be applied with appropriate modifications without departing from the scope of the invention.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A semiconductor element having surface connection terminals has a first surface and a second surface to be mounted, and has a plurality of through-holes communicating the first surface and the second surface, and has a Young's modulus. A substantially plate-shaped relay that is made of an insulating resin material having a thermal expansion coefficient of not less than 0.01 GPa and not more than 10 GPa and having a thermal expansion coefficient of not less than 5.0 ppm / ° C and not more than 20.0 ppm / ° C, and having a thickness of not less than 0.3 mm and not more than 1.0 mm A relay board comprising: a board body; and a plurality of conductor portions that are disposed in the plurality of through holes and are to be electrically connected to the surface connection terminals.

  (2) The relay substrate according to the technical idea (1), wherein at least one side of the semiconductor element is 10 mm or more, and the thickness of the semiconductor element is 1.0 mm or more.

  (3) The relay substrate according to the technical idea (1), wherein the semiconductor element has a thermal expansion coefficient of 2.0 ppm / ° C. or more and less than 5.0 ppm / ° C.

  (4) The relay substrate according to the technical idea (1), wherein a diameter of the through hole is 100 μm or less, and a center-to-center distance between the adjacent through holes is 200 μm or less.

  (5) A plurality of through holes each including a semiconductor element having a surface connection terminal, having a first surface and a second surface on which the semiconductor element is to be mounted, and communicating the first surface and the second surface. A relay board body having a substantially plate shape made of an organic polymer material having a hole and a Young's modulus of 25 GPa or less, and a plurality of relay board bodies disposed in the plurality of through holes and electrically connected to the surface connection terminals A relay substrate with a semiconductor element, comprising a relay substrate having a conductor portion.

  (6) A semiconductor element having surface connection terminals, an organic polymer substrate having a coefficient of thermal expansion of 10.0 ppm / ° C to 30.0 ppm / ° C and having a surface connection pad, and the semiconductor element A first surface to be mounted; a second surface to be mounted on the surface of the organic polymer substrate; a plurality of through-holes communicating the first surface and the second surface; A substantially plate-shaped relay substrate body made of an organic polymer material of 25 GPa or less, and a plurality of conductor portions arranged in the plurality of through holes and electrically connected to the surface connection terminals and the surface connection pads. A structure comprising a semiconductor element, a relay substrate, and a substrate, comprising the relay substrate.

1 is a schematic cross-sectional view showing a semiconductor package of a first embodiment including an IC chip (semiconductor element), an interposer (relay substrate), and a wiring substrate (substrate). The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. The schematic sectional drawing for demonstrating the manufacturing method of the same interposer. FIG. 3 is a schematic cross-sectional view showing the completed interposer according to the first embodiment. The schematic sectional drawing which shows the state when mounting the interposer with an IC chip (intermediate board with a semiconductor element) which comprises the semiconductor package of 1st Embodiment on a wiring board. FIG. 3 is a schematic cross-sectional view showing a state when an IC chip is mounted on a wiring board with an interposer (a board with a relay board) in configuring the semiconductor package of the first embodiment. The schematic sectional drawing for demonstrating 2nd Embodiment which shows another manufacturing method of the said interposer. The schematic sectional drawing for demonstrating 2nd Embodiment which shows another manufacturing method of the said interposer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 ... IC chip as a semiconductor element 22 ... Surface connection terminal 31 ... Interposer as a relay substrate 32 ... Upper surface as a first surface 33 ... Lower surface as a second surface 34 ... Via as a through hole 35 ... Conductor as a conductor portion Pillar 38 ... Interposer body 41 as relay board body 41 ... Organic polymer board 46 ... Surface connection pad 71 ... Board with interposer as board with relay board

Claims (2)

A semiconductor element having surface connection terminals has a first surface and a second surface to be mounted, and has a plurality of through-holes communicating the first surface and the second surface, and a Young's modulus of 25 GPa or less A substantially plate-shaped relay substrate body made of an organic polymer material;
A relay substrate, comprising: a plurality of conductor portions that are disposed in the plurality of through holes and are to be electrically connected to the surface connection terminals. An organic polymer substrate having a coefficient of thermal expansion of 10.0 ppm / ° C. to 30.0 ppm / ° C. and having a surface connection pad; and
Having a first surface and a second surface mounted on the surface of the organic polymer substrate, having a plurality of through-holes communicating the first surface and the second surface, and having a Young's modulus of 25 GPa or less A relay board having a substantially plate-shaped relay board body made of an organic polymer material, and a plurality of conductor portions disposed in the plurality of through holes and electrically connected to the surface connection pads. A board with a relay board.

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