JP2005033838A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a fixed pattern noise caused by the dispersions of the pixel characteristics can be eliminated but a vertical stripe-like fixed pattern noise caused by the dispersion of the circuit characteristics remains. <P>SOLUTION: In an amplifiing solid-state image pickup device which outputs the signal of a pixel 11 in voltage, the input sides of a load capacitor 16 and a dummy capacitor 17 are connected to the output terminal of a sampling switch 15, the output sides of these capacitors 16, 17 are appropriately connected to a reference potential line 18 via reference switches 19 and 20, and the output side of the load capacitor 16 is connected to the input terminal of a vertical output circuit 21. A signal voltage Vsigl in a light state and a signal voltage Vsigd in a dark state are read via the same signal path, thereby eliminating not only the fixed pattern noise caused by the characteristics dispersion of the pixel 11 but also the vertical stripe-like fixed pattern noise caused by the characteristics dispersion of the circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and more particularly to an amplification type solid-state imaging device in which a pixel itself has an amplifying function.

  Known amplification type solid-state imaging devices include CMD (Charge Modulation Device), BASIS (Base Stored Image Sensor), and BCMD (Bulk Charge Modulation Device). In this amplification type solid-state imaging device, since the pixel itself is configured by using an active element such as a MOS structure in order to give the pixel itself an amplification function, the characteristics of the active element (threshold voltage Vth, etc.) The variation comes on the image signal as it is. This variation in characteristics appears as fixed pattern noise (FPN) on the screen because each pixel has a fixed value.

  FIG. 7 shows a conventional example of an amplifying solid-state imaging device that is designed to remove fixed pattern noise caused by pixel characteristic variations (see, for example, Patent Document 1). In the figure, a large number of pixels 101 are arranged in a matrix, the control input terminals of each pixel 101 are connected to each of the vertical selection lines 102 in units of rows, and the output terminals of each of the vertical signal lines 103 in units of columns. It is connected to the. Each end of the vertical selection line 102 is connected to the output end of each row of the vertical scanning circuit 104. The vertical scanning circuit 104 is configured by a shift register or the like, and sequentially outputs vertical scanning pulses φV (..., ΦVm, φVm + 1,...).

  Each vertical signal line 103 is connected to the drains of two sampling switches 105s and 105n made of NchMOS transistors. An operation pulse φOPS for sampling the signal voltage in the bright state before pixel reset output from the pixel 101 is applied to the gate of the sampling switch 105s. In addition, an operation pulse φOPN for sampling the dark signal voltage after pixel reset output from the pixel 101 is applied to the gate of the sampling switch 105n.

  Each source of the sampling switches 105s and 105n is connected to one end of each of the two capacitors 106s and 106n. These capacitors 106s and 106n are provided to hold the signal voltage during light and the signal voltage during dark, and the other ends are both grounded. The sources of the sampling switches 105s and 105n are further connected to the drains of two horizontal selection switches 107s and 107n made of NchMOS transistors, respectively.

  Each source of the horizontal selection switches 107 s and 107 n is connected to the horizontal signal line 108, and each gate is connected to an output terminal of each column of the horizontal scanning circuit 109. The horizontal scanning circuit 109 is configured by a shift register or the like, and outputs horizontal scanning pulses φH (..., ΦHn, φHn + 1,...) For sequentially turning on the horizontal selection switch 107s and the horizontal selection switch 107n for each column. The horizontal signal line 108 is connected to the input terminal of the horizontal output circuit 110. The output terminal of the horizontal output circuit 110 is connected to the input terminal of a CDS (correlated double sampling) circuit 111.

  Next, a circuit operation for removing fixed pattern noise in the conventional apparatus having the above configuration will be described.

  When a certain row is selected by vertical scanning by the vertical scanning circuit 104 in the horizontal blanking period, the signal voltage in the bright state before the pixel reset and the signal voltage in the dark state after the pixel reset of the pixel 101 in the selected row. Are sequentially sampled by the sampling switches 105s and 105n and held in the capacitors 106s and 106n.

  Next, in a horizontal effective period, a certain column is selected by horizontal scanning by the horizontal scanning circuit 109, and the horizontal selection switches 107s and 107n of the selected column are sequentially turned on, so that the light held in the capacitors 106s and 106n. The signal voltage at the time and the signal voltage at the dark time are sequentially read out to the horizontal signal line 108.

  Then, in the CDS circuit 111, correlated double sampling of the signal voltage at the time of light and the signal voltage at the time of dark is performed, and the difference is taken to cancel the noise component. As a result, a signal from which fixed pattern noise due to characteristic variations such as the threshold voltage Vth of the pixel 101 is removed can be obtained.

JP 9-284658 A (Japanese Patent Application No. 8-88492; filing date: April 10, 1996)

  However, in the above-described conventional amplification type solid-state imaging device, the signal voltage at the time of light and the signal voltage at the time of dark are transmitted by the horizontal signal line 108 in succession on the time axis, and the CDS passes through the horizontal output circuit 110. Must be supplied to circuit 111.

  A solid-state imaging device according to the present invention includes a plurality of pixels that output pixel signals, a vertical signal line connected to each output end of the plurality of pixels in units of columns, and a vertical output circuit connected to the vertical signal lines, The pixel signal at the time of light and the pixel signal at the time of darkness from the pixel are differenced in the vertical output circuit and output to the horizontal signal line.

  In the solid-state imaging device having the above-described configuration, the bright pixel signal and the dark pixel signal obtained by the pixels are supplied to the vertical signal circuit via the vertical signal line. Then, the difference between these pixel signals is taken by the vertical signal circuit and output to the horizontal signal line.

  According to the present invention, the difference between the pixel signal at the time of light and the pixel signal at the time of darkness is taken by the vertical output circuit, and the difference signal is output to the horizontal signal line, resulting in variations in pixel characteristics. Since the difference pixel signal in which the fixed pattern noise is suppressed is read out through the horizontal signal line, the signal voltage at the time of light and the signal voltage at the time of dark are not read through the horizontal signal line on the time axis. .

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention. In FIG. 1, a large number of pixels 11 are arranged in a matrix, the control input terminals of each pixel 11 are connected to each of the vertical selection lines 12 in units of rows, and the output terminals of each of the vertical signal lines 13 in units of columns. It is connected to the. A signal is output from the pixel 11 to the vertical signal line 13 as a voltage. Each end of the vertical selection line 12 is connected to the output end of each row of the vertical scanning circuit 14. The vertical scanning circuit 14 is constituted by a shift register or the like, and sequentially outputs vertical scanning pulses φV (..., ΦVm, φVm + 1,...).

  Each vertical signal line 13 is connected to the drain of a sampling switch (first switch means) 15 made of an Nch MOS transistor. The gate of the sampling switch 15 includes a signal voltage at the time of pixel 11 before the pixel reset and a signal voltage at the time of dark obtained by resetting the pixel 11 (hereinafter referred to as a signal voltage at the time of dark after the pixel reset). The sampling pulse φVg-SH for reading each of the above is applied. Each end of a load capacitor (first storage means) 16 and a dummy capacitor (second storage means) 17 is connected to the source of the sampling switch 15.

  A reference switch (second switch means) 19 made of a MOS transistor is connected between the other end of the load capacitor 16 and a reference potential line 18 for supplying a reference potential V-Ref. Similarly, a dummy reference switch (second switch means) 20 made of a MOS transistor is connected between the dummy capacitor 17 and the reference potential line 18. A reference pulse φVg-Ref is applied to the gate of the reference switch 19, and a dummy reference pulse φVg-dumy Ref is applied to the gate of the dummy reference switch 20.

  The other end of the load capacitor 16 is further connected to the input end of the vertical output circuit 21. The output terminal of the vertical output circuit 21 is connected to the horizontal signal line 22. For example, as shown in FIG. 2, the vertical output circuit 21 includes a source follower circuit 23 including a drive MOS transistor Q1 and a load MOS transistor Q2 connected in series between a power supply Vdd and a ground, and a drive MOS transistor Q1. A horizontal selection switch 24 composed of a MOS transistor is connected between the source and the horizontal signal line 22. In the source follower circuit 23, a predetermined bias voltage Vg-load is applied to the gate of the load MOS transistor Q2.

  The gate of the horizontal selection switch 24 is connected to the output terminal of each column of the horizontal scanning circuit 25. The horizontal scanning circuit 25 is composed of a shift register or the like, and outputs horizontal scanning pulses φH (..., ΦHn, φHn + 1,...) For sequentially turning on the horizontal selection switch 24. The horizontal signal line 22 is connected to the input terminal of the horizontal output circuit 26. The output terminal of the horizontal output circuit 26 is connected to the input terminal of a CDS (correlated double sampling) circuit 27.

  Next, in the amplification type solid-state imaging device according to the embodiment of the present invention having the above-described configuration, in order to remove the fixed pattern noise caused by the circuit variation as well as the fixed pattern noise caused by the characteristic variation of the pixel 11. The driving method will be described with reference to the timing chart of FIG.

  First, the operation (t1 to t6) until the signal voltage is sampled and held will be described with reference to the operation explanatory diagram of FIG.

  In the horizontal blanking period, first, the sampling pulse φVg-SH becomes “H” level at the time point t1 and the sampling switch 15 is turned on, whereby the signal voltage Vsigl in the bright state before pixel reset is sampled. At this time, since the reference pulse φVg-Ref is at the “H” level and the reference switch 19 is in the ON state, the output-side potential of the load capacitor 16 is at the reference potential V-Ref.

  Next, at time t2, the sampling pulse φVg-SH changes to the “L” level, and the sampling switch 15 is turned off, so that the signal voltage Vsigl at the time of light is held in the load capacitor 16. At this time, a noise component Vα accompanying switching when the sampling switch (SH Tr) 15 is cut off rides on the load capacitor 16.

  Next, at time point t3, the reference pulse φVg-Ref transitions to the “L” level, and in response thereto, the reference switch 19 is turned off. At this time, since the input side of the load capacitor 16 is in a floating state due to the sampling switch 15 being in the OFF state, the noise component Vβ accompanying switching at the time of the cutoff of the reference switch (Ref Tr) 19 is riding on the load capacitor 16. Not come.

  Next, after the dummy reference pulse φVg-dumy Ref becomes “H” level at time t4 and the dummy reference switch 20 is turned on, the sampling pulse φVg-SH becomes “H” level again at time t5. When the sampling switch 15 is turned on, the dark signal voltage Vsigd after pixel reset is sampled.

  Next, at time t6, the sampling pulse φVg-SH changes to the “L” level, and the sampling switch 15 is turned off, whereby the dark signal voltage Vsigd is held in the dummy capacitor 17. At this time, since the dummy capacitor 17 is connected to the output side of the sampling switch 15, the noise component Vα associated with the switching of the sampling switch 15 is generated in the dummy capacitor 17 in the same manner as when the signal voltage Vsigl at the time of light is held. get on.

  In this way, the input sides of the load capacitor 16 and the dummy capacitor 17 are connected to the output terminal of the sampling switch 15, and the output sides of these capacitors 16 and 17 are connected to the reference potential line 18 as appropriate by the reference switches 19 and 20. At the same time, the output side of the load capacitor 16 is connected to the input terminal of the vertical output circuit 21 and is driven according to the procedure described above, so that the output side of the load capacitor 16 has a correlated double sampling of (Vsigd−Vsigl + V−Ref). The obtained signal voltage is derived.

  That is, a dummy circuit (dummy capacitor 17 and dummy reference switch 20) is provided symmetrically with a circuit responsible for correlated double sampling operation (load capacitor 16 and reference switch 19), and correlated double sampling is performed. By reading out the signal voltage Vsigl and the dark signal voltage Vsigd via the same signal path, not only the fixed pattern noise caused by the characteristic variation of the pixel 11 but also a cause of the vertical streak-like fixed pattern noise. Thus, a signal voltage from which noise components accompanying switching of the sampling switch 15 are removed is obtained.

  Next, an operation (t7 to t8) for outputting a signal voltage to the horizontal signal line 22 will be described.

  In the horizontal effective period, horizontal scanning pulses φH (..., ΦHn, φHn + 1,...) Are sequentially output from the horizontal scanning circuit 25, and the horizontal selection switch 24 (see FIG. 2) in the column vertical output circuit 21 at time t7. By being turned on, the signal voltage (Vsigd−Vsigl + V−Ref) of the column is read out to the horizontal signal line 22 via the vertical output circuit 21.

  Next, at time t8, the reference pulse φVg-Ref becomes “H” level and the reference switch 19 is turned on, so that the reference potential V-Ref is read out to the horizontal signal line 22 via the vertical output circuit 21. . At this time, the dummy reference pulse φVg-dumy Ref transitions to the “L” level. However, the dummy reference pulse φVg-dumy Ref may be maintained at the “H” level as it is, as indicated by a broken line in FIG.

  In this way, the signal voltage (Vsigd−Vsigl + V−Ref) and the reference potential V−Ref sequentially read out to the horizontal signal line 22 are supplied to the source follower circuit 23 (see FIG. 2) when passing through the vertical output circuit 21. If there is a noise component accompanying the offset variation of (see) and the switching of the horizontal selection switch 24, and there is variation between the columns, it becomes fixed pattern noise in the form of vertical stripes.

  However, the signal voltage (Vsigd−Vsigl + V−Ref) sequentially read out to the horizontal signal line 22 and the reference potential V−Ref are transmitted by the horizontal signal line 22 in succession in units of columns on the time axis. After passing through the output circuit 26, the CDS circuit 27 performs correlated double sampling, and the difference is taken. As a result, it is possible to eliminate variations in circuit characteristics between columns in the vertical output circuit 21 that contribute to the vertical streak fixed pattern noise.

  As described above, not only the fixed pattern noise caused by the characteristic variation of the pixel 11, but also the noise component accompanying the switching of the sampling switch 15, the offset variation of the source follower circuit 23 (see FIG. 2), and the switching of the horizontal selection switch 24. Thus, a signal from which vertical streak-like fixed pattern noise caused by circuit characteristic variations such as noise components is removed can be obtained.

  Further, in the conventional amplification type solid-state imaging device, the signal voltage Vsigl at the bright time before the pixel reset and the signal voltage Vsigd at the dark time after the pixel reset are transmitted before and after the column unit on the time axis. Therefore, it is necessary to secure a time margin between the signal voltage Vsigl at the time of light and the signal voltage Vsigd at the time of darkness, and as a result, a sufficient phase margin of the clock in the horizontal scanning circuit and the subsequent CDS circuit is obtained. Could not secure.

  On the other hand, in the amplification type solid-state imaging device according to the present invention, since the signal potential (Vsigd−Vsigl + V−Ref) follows the reference voltage V−Ref in units of columns on the time axis, the signal voltage (Vsigd When reading -Vsigl + V-Ref), the reference potential V-Ref can be continuously read, that is, it is not necessary to have a time margin between the signal voltage (Vsigd-Vsigl + V-Ref) and the reference potential V-Ref. There is also an advantage that a sufficient phase margin of the clock in the horizontal scanning circuit 25 and the subsequent CDS circuit 27 can be ensured as compared with the conventional device.

  FIG. 5 is a schematic configuration diagram showing another embodiment of the present invention, in which the same reference numerals are given to the same parts as in FIG.

  In the previous embodiment, the reference pulse φVg-Ref is commonly applied to the reference switch 19 of each column. In the present embodiment, the reference switch 19 of each column is different for each column. A reference pulse φVg-Ref (..., ΦVg-Ref (n), φVg-Ref (n + 1),...) Is provided. This reference pulse φVg-Ref (..., ΦVg-Ref (n), φVg-Ref (n + 1),...) Is output from the horizontal scanning circuit 25, for example.

  FIG. 6 shows a timing chart for explaining the operation of the other embodiment. In this timing chart, the operation from the time point t1 to the time point t6, that is, the operation until the signal voltage is sampled and held is exactly the same as in the previous embodiment. The operation when a signal voltage is output to the signal line 22 will be described below.

  In the horizontal effective period, horizontal scanning pulses φH (..., ΦHn, φHn + 1,...) Are sequentially output from the horizontal scanning circuit 25, and the horizontal selection switch 24 (see FIG. 2) in the n columns of vertical output circuits 21 at time t7. By being turned on, the signal voltage (Vsigd−Vsigl + V−Ref) in the n columns is read out to the horizontal signal line 22 via the vertical output circuit 21.

  Next, at time point t8, the n-column reference pulse φVg-Ref (n) becomes “H” level and the n-column reference switch 19 is turned on, so that the reference potential V-Ref is output in the n-column vertical output. Read out to the horizontal signal line 22 via the circuit 21. At this time, the dummy reference pulse φVg-dumy Ref may be at the “H” level or the “L” level, but in this example, the “H” level is maintained as it is so as not to be wasted.

  Next, at time t9, when the n-th column horizontal scanning pulse φHn disappears and the n + 1-th column horizontal scanning pulse φHn + 1 is generated, the n + 1-th column horizontal selection switch 24 is turned on, and the n + 1-column signal voltage (Vsigd−Vsigl + V -Ref) is read to the horizontal signal line 22 via the vertical output circuit 21. Subsequently, the reference pulse φVg-Ref (n + 1) of the (n + 1) th column becomes the “H” level and the reference switch 19 of the (n + 1) th column is turned on, so that the reference potential V-Ref is the vertical output circuit 21 of the (n + 1) th column. To the horizontal signal line 22.

  Thereafter, the same operation is sequentially performed over one line. The signal voltage (Vsigd−Vsigl + V−Ref) and the reference potential V−Ref sequentially read out to the horizontal signal line 22 in this way and the reference potential V−Ref are transmitted by the horizontal signal line 22 in succession in units of columns on the time axis. Then, it is supplied to the CDS circuit 27 through the horizontal output circuit 26. Then, in the CDS circuit 27, correlated double sampling is performed and the difference is taken.

  As described above, as in the case of the previous embodiment, not only the fixed pattern noise caused by the characteristic variation of the pixels 11, but also the noise component accompanying the switching of the sampling switch 15, the offset variation of the source follower circuit 23, and the horizontal selection. A signal from which vertical streaky fixed pattern noise caused by circuit characteristic variations such as noise components accompanying switching of the switch 24 is removed is obtained.

  In each of the above embodiments, a signal is output from the pixel 11 as a voltage. As an example, a source follower circuit is formed by using BCMD or CMD as a drive transistor, or the source follower circuit There is a case where a capacitive load read operation is performed by replacing a resistor with a capacitor.

  In the case of the capacitive load reading operation, the load capacitor 16 and the dummy capacitor 17 are used as loads at the time of reading in the light and at the time of reading in the dark. However, in the case of capacitive load operation, it is necessary to add means (such as a transistor) for resetting the vertical signal line 13 to a constant potential immediately before reading out a signal at the time of light or darkness to the circuit of the present invention.

It is a schematic structure figure showing one embodiment of the present invention. It is a circuit diagram which shows an example of a structure of a vertical output circuit. It is a timing chart for explanation of operation of one embodiment of the present invention. It is operation | movement explanatory drawing of one Embodiment of this invention. It is a schematic block diagram which shows other embodiment of this invention. It is a timing chart for explanation of operation of other embodiments of the present invention. It is a schematic block diagram which shows a prior art example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Pixel, 13 ... Vertical signal line, 14 ... Vertical scanning circuit, 15 ... Sampling switch, 16 ... Load capacitor, 17 ... Dummy capacitor, 18 ... Reference potential line, 19 ... Reference switch, 20 ... Dummy reference switch, 21 ... Vertical output circuit, 22 ... Horizontal signal line, 23 ... Source follower circuit, 24 ... Horizontal selection switch, 25 ... Horizontal scanning circuit, 26 ... Horizontal output circuit, 27 ... CDS circuit

Claims (1)

A plurality of pixels that output pixel signals;
Vertical signal lines connected in units of columns to the output ends of the plurality of pixels;
A vertical output circuit connected to the vertical signal line,
The solid-state imaging device, wherein the pixel signal in the bright time and the pixel signal in the dark time from the pixel are differenced in the vertical output circuit and output to a horizontal signal line.

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