JP3855331B2 - Solid-state imaging device and driving method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device and a driving method thereof, and more particularly, to an amplification type solid-state imaging device and a driving method thereof in which a pixel itself has an amplification function and outputs a pixel signal as a voltage.
[0002]
[Prior art]
Known amplification type solid-state imaging devices include BASIS (Base Stored Image Senser), BCMD (Bulk Charge Modulation Device), and CMOS APS (Active Pixel Sensor). In these amplification type solid-state imaging devices, since the pixel is configured by using an active element such as a MOS structure in order to give the pixel itself an amplification function, characteristics of the active element (threshold voltage Vth, etc.) Variation will be on the image signal as it is. This variation in characteristics appears as fixed pattern noise (FPN) on the screen because each pixel has a fixed value.
[0003]
FIG. 8 shows a conventional example of an amplifying solid-state imaging device that is designed to remove fixed pattern noise caused by the characteristic variation of the pixels. In the drawing, a plurality of pixels 101 arranged in a matrix form have their output terminals connected to the vertical signal line 102 in column units. A vertical output circuit 103 for reading out the signal of each pixel 101 is connected to one end of each vertical signal line 102 for each column. FIG. 8 shows only a specific circuit configuration of the vertical output circuit 103 in a certain column.
[0004]
In the vertical output circuit 103, one end of each of the sample hold switches 104s and 104r made of NchMOS transistors is connected to one end of the vertical signal line 102. A switch 105 made of an Nch MOS transistor is connected between one end of the vertical signal line 102 and the reference potential VSS. Between the other ends of the sample hold switches 104s and 104r, switches 105s, 106 and 105r made of NchMOS transistors are connected in series.
[0005]
Capacitors 107s and 107r are connected between the other ends of the sample and hold switches 104s and 104r and the reference potential VSS. The other ends of the sample hold switches 104s and 104r are further connected to the gates of source followers 108s and 108r made of PchMOS transistors. One end of each of these source followers 108s and 108r is connected to a reference potential VSS, and a horizontal selection switch 109s and 109r made of a PchMOS transistor is connected between each other end and two horizontal signal lines 110s and 110r. Yes.
[0006]
Next, a circuit operation for removing fixed pattern noise in the conventional apparatus having the above configuration will be described.
[0007]
In a horizontal blanking period, when a certain row is selected by vertical scanning, a light signal component (hereinafter referred to as a signal level component) before pixel reset of the pixel 101 of the selected row and a dark after pixel reset are selected. The time signal components (hereinafter referred to as reference level components) are sequentially sampled by the sample and hold switches 104s and 104r and held in the capacitors 107s and 107r.
[0008]
Next, in a horizontal effective period, a certain column is selected by horizontal scanning, and the horizontal selection switches 109s and 109r of the selected column are turned on, whereby the signal level component held in the capacitors 107s and 107r and the reference Level components are read out to the horizontal signal lines 110 s and 110 r and further output to an external circuit via the horizontal output circuit 111. Then, in the external circuit, the difference between the two outputs is taken, so that the noise component riding on both the outputs is canceled out. As a result, a signal from which fixed pattern noise due to characteristic variations such as the threshold voltage Vth of the pixel 101 is removed can be obtained.
[0009]
[Problems to be solved by the invention]
However, in the above-described conventional amplification type solid-state imaging device, although it is possible to remove the fixed pattern noise caused by the characteristic variation of the pixel 101, in the vertical output circuit 103 between the vertical signal line 102 and the horizontal signal lines 110s and 110r. Since the signal level component and the reference level component are sampled and held by the separate sample and hold switches 104s and 104r, offset noise is generated along with the switching of the sample and hold switches 104s and 104r. If there is a difference between the columns due to the characteristic variation, it appears as fixed pattern noise in the form of vertical stripes on the screen.
[0010]
The present invention has been made in view of the above problems, and the object of the present invention is not only fixed pattern noise due to pixel characteristic variation but also vertical streak fixed pattern noise due to circuit characteristic variation. Another object of the present invention is to provide a solid-state imaging device and a driving method thereof that can suppress the above-described problem.
[0011]
[Means for Solving the Problems]
A solid-state imaging device according to the present invention includes a plurality of pixels arranged in a matrix, a first switch unit having one end connected to a vertical signal line in which output ends of these pixels are connected in units of columns, Second switch means connected between the other end of the first switch means and the reference potential point, and first and second power storage means each having one end connected in common to the other end of the first switch means And third and fourth switch means respectively connected between the other end of each of the power storage means and the reference potential point, and each of the other end of the first and second power storage means and the first and second The fifth and sixth switch means connected between the horizontal signal lines are provided for each column.
[0012]
In the driving method according to the present invention, in driving the solid-state imaging device having the above-described configuration, first, the first switch means and the third switch means are turned on, and the fourth switch means is turned off in the horizontal blanking period. The component (signal component at the time of light) is sampled and held in the first power storage means, then the first switch means and the fourth switch means are turned on, and the third switch means is turned off to turn on the reference level component (dark Time signal component) is sampled and held in the second power storage means, and then, in the horizontal effective period, the fifth, sixth switch means and second switch means are turned on in turn for each column. The light and dark signal components sampled and held by the two power storage means are read out to the first and second horizontal signal lines.
[0013]
In the solid-state imaging device having the above-described configuration and its driving method, first, in the horizontal blanking period, the first switch means is used to sample the signal level component, the third switch means is turned on, and the fourth switch means is turned off. Then, the output terminal of the first power storage unit is held at the first power storage unit by setting it as a reference potential. At this time, a noise component accompanying the switching of the first switch means comes on the first power storage means. Subsequently, similarly, the first switch means is used to sample the reference level component, the fourth switch means is turned on, the third switch means is turned off, and the output terminal of the second power storage means is connected to the reference potential. As a result, the second power storage means holds. Also at this time, a noise component accompanying the switching of the first switch means comes on the second power storage means.
[0014]
Next, in the horizontal effective period, the fifth and sixth switch means are sequentially turned on for each column to select the horizontal, and at the same time, the second switch means is turned on and each input of the first and second power storage means is made. By using the end as a reference potential, the signal level component and the reference level component sampled and held in the first and second power storage units are read out to the first and second horizontal signal lines. At this time, the signal level component and the reference level component are commonly accompanied by a noise component accompanying switching of the first switch means. Therefore, by taking the difference between the signal level component and the reference level component in the subsequent circuit, the noise component accompanying the switching of the first switch means is canceled. As a result, not only fixed pattern noise caused by pixel characteristic variation but also vertical streak fixed pattern noise caused by circuit characteristic variation can be suppressed.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0016]
FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention. In FIG. 1, a large number of pixels (pixels) 11 are arranged in a matrix, and output ends of these pixels 11 are connected to vertical signal lines 12-1 to 12-n in units of columns. From each of the pixels 11, a signal is output as a voltage to the vertical signal lines 12-1 to 12-n. Connected to one end of each of the vertical signal lines 12-1 to 12-n is a vertical output circuit 13-1 to 13-n that outputs a signal level component and a reference level component for each column.
[0017]
Each of the vertical output circuits 13-1 to 13-n is supplied with column selection signals Col (1) to Col (n) from the horizontal shift register 14, and also has reference signals Ref (1) to Ref (n) and clamps. Signals Clamp S (1) to Clamp S (n) and Clamp R (1) to Clamp R (n) are provided for each column. These timing signals are generated by the horizontal shift register 14 or another timing generation circuit (not shown). The signal level component and the reference level component output from the vertical output circuits 13-1 to 13-n are supplied to the horizontal output circuit 16 via the two horizontal signal lines 15s and 15r.
[0018]
FIG. 2 shows a specific circuit configuration of the vertical output circuit 13-i and the horizontal output circuit 16 in i columns. First, in the vertical output circuit 13-i, one end of a sample hold switch 21 made of an Nch MOS transistor is connected to one end of the vertical signal line 12-i. A sample hold signal SH is applied to the gate of the sample hold switch 21. A reference switch 22 composed of an Nch MOS transistor is connected between the other end of the sample hold switch 21 and the reference potential Vref. A reference signal Ref is applied to the gate of the reference switch 22.
[0019]
The other end of the sample hold switch 21 is further connected to one ends of capacitors 23r and 23s as first and second power storage means. Clamp switches 24r and 24s made of NchMOS transistors are connected between the other ends of the capacitors 23r and 23s and the reference potential Vref. Clamp signals Clamp R and Clamp S are applied to the gates of the clamp switches 24r and 24s, respectively.
[0020]
The other ends of the capacitors 23r and 23s are further connected to the gates of source followers 25r and 25s made of PchMOS transistors. The drains of these source followers 25r and 25s are connected to the negative power source VSS. Each source of the source followers 25r and 25s is connected to each drain of horizontal selection switches 26r and 26s made of PchMOS transistors. A column selection signal Col is applied to the gates of the horizontal selection switches 26r and 26s. The sources of the horizontal selection switches 26r and 26s are connected to the horizontal signal lines 15r and 15s.
[0021]
Subsequently, in the horizontal output circuit 15, one end of each of the capacitors 27r and 27s is connected to one end of each of the horizontal signal lines 15r and 15s. Switches 28r and 28s made of PchMOS transistors are connected between one end of each of the capacitors 27r and 27s and the positive power supply VDD. Also, clamp switches 29r and 29s made of PchMOS transistors are connected between the other ends of the capacitors 27r and 27s and the reference potential Vref.
[0022]
The other ends of the capacitors 27r and 27s are further connected to the input ends of the source follower circuits 30r and 30s, that is, the gates of the drive transistors 31r and 31s formed of NchMOS transistors. The drains of the drive transistors 31r and 31s are connected to the positive power supply VDD, and the sources are connected to the negative power supply VSS via load transistors 32r and 32s made of NchMOS transistors. The sources of the drive transistors 31r and 31s are connected to the output terminals 33r and 33s.
[0023]
Next, circuit operations of the vertical output circuits 13-1 to 13-n and the horizontal output circuit 16 configured as described above will be described with reference to the operation explanatory diagram of FIG. 4 using the timing chart of FIG.
[0024]
In FIG. 4, VsigS is a signal level component of the pixel 11, and VsigR is a reference level component of the pixel 11. vsh is offset noise accompanying switching of the sample hold switch 21, vclampS is offset noise accompanying switching of the clamp switch 24s, and vclampR is offset noise accompanying switching of the clamp switch 24r. g-sfc is the gain of the source followers 25s and 25r of the vertical output circuit 13, and g-sfC is the gain of the source followers 30s and 30r of the horizontal output circuit 16. sf-offset-Sc is the offset of the source follower 25s for the signal level of the vertical output circuit 13, sf-offset-Rc is the offset of the source follower 25r for the reference level of the vertical output circuit 13, and sf-offset-SC is the horizontal output The offset of the source follower 30s for the signal level of the circuit 16 and sf-offset-RC are the offset of the source follower 30r for the reference level of the horizontal output circuit 16.
[0025]
In the horizontal blanking period HBLK, the sample hold signal SH becomes “H” level, and the clamp signals Clamp S (1), Clamp S (2),. When the clamp signals Clamp R (1), Clamp R (2),... Become “L” level (time t1), the sample hold switch 21 and the clamp switch 24s are turned on, and the clamp switch 24r is turned off. The signal level component VsigS is sampled and held in the capacitor 23s.
[0026]
At this time, as apparent from FIG. 5A, the sample hold switch 21 is turned off first, and then the clamp switch 24s is turned off (time t2). With this phase relationship, noise accompanying switching of the sample hold switch 21 (hereinafter referred to as switching noise) rides on the capacitor 23s, but the effect of the switching noise of the clamp switch 24s is the output of the capacitor 23s. If the end parasitic capacitance is Co / capacitor 23s and C is C / C, there is almost no Co / C. The period from time t1 to time t2 is a period during which the signal level component VsigS of the pixel 11 is sampled and held.
[0027]
Similarly, the sample-and-hold signal SH becomes “H” level, and the clamp signals Clamp R (1), Clamp R (2),... When S (1), Clamp S (2),... Becomes “L” level (time t3), the sample hold switch 21 and the clamp switch 24r are turned on, and the clamp switch 24s is turned off. The component VsigR is sampled and held in the capacitor 23r.
[0028]
When sample-holding the reference level component VsigR, as in the case of sample-holding the signal level component VsigS (see FIG. 5A), the sample-hold switch 21 is turned off first, and then the clamp switch 24r is turned on. Turn off (time t4). The period from time t3 to time t4 is a period during which the reference level component VsigR of the pixel 11 is sampled and held.
[0029]
Subsequently, the operation shifts to a signal reading operation from the vertical output circuits 13-1 to 13-n of each column. In the horizontal effective period, first, the column selection signal Col (1) of the first column becomes “L” level, and the vertical output circuit 13-1 of the first column is selected. The horizontal selection switches 26s and 26r are turned on (time t5). At this time, the reference signal Ref (1) in the first column becomes “H” level, and the reference switch 22 is turned on. As a result, the signal level component VsigS and the reference level component VsigR sampled and held in the capacitors 23s and 23r are output to the horizontal signal lines 15s and 15r via the source followers 25s and 25r and the horizontal selection switches 26s and 26r.
[0030]
Then, the clamp signal Clamp that has been in the “H” level state transitions to the “L” level and the clamp switches 29 s and 29 r are turned off, so that the signal level component VsigS and the reference level component VsigR become the capacitors 27 s, Sampled and held at 27r. At this time, the offset variation caused by the Vth variation of the PMOS transistors constituting the source followers 25s and 25r is simultaneously sampled and held in the capacitors 27s and 27r. Subsequently, when the clamp signals Clamp S (1) and Clamp R (1) in the first column transition to the “H” level and the clamp switches 24s and 24r are turned on, the offset variation of the source followers 25s and 25r. Minutes are output (time t6).
[0031]
In order to prevent the data sampled and held in the capacitors 23s and 23r from being destroyed before being read, the reference switch 22 and the clamp switches 24s and 24r connected to both ends of the capacitors 23s and 23r are simultaneously turned on. It is necessary to avoid it. That is, as apparent from FIG. 5B, after the reference signal Ref (i) is set to the “L” level, the clamp signals Clamp S (i) and Clamp R (i) are changed to the “H” level. You can do it.
[0032]
As described above, the signal level component VsigS and the reference level component VsigR sampled and held first are output to the capacitors 23s and 23r, and then the offset variation components of the source followers 25s and 25r are output, whereby the horizontal output circuit 16 The voltage between the output terminals 33s and 33r is
g-sfC ・ g-sfc (VsigS−VsigR) + (sf-offset-SC) + (sf-offset-RC) (1)
It becomes.
[0033]
That is, the offset noise vsh accompanying the switching of the sample hold switch 21 is canceled between the signal level system and the reference level system, and the difference between the signal level component VsigS and the reference level component VsigR causes the source follower 25s, The output is obtained by multiplying the gain g-sfc of 25r and the gain g-sfC of the source followers 30s and 30r of the horizontal CCD 5 power output circuit 16 and is caused by the variation in offset characteristics caused by the switching of the sample hold switch 21. Fixed pattern noise can be suppressed. In the equation (1), (sf-offset-SC) + (sf-offset-RC) is an offset amount of the horizontal output circuit 16 riding on the signals of all pixels, and thus does not become fixed pattern noise. .
[0034]
FIG. 6 is a schematic configuration diagram showing another embodiment of the present invention. In FIG. 6, a large number of pixels (pixels) 51 are arranged in a matrix, and the output ends of these pixels 51 are connected to vertical signal lines 52-1 to 52-n in units of columns. From each of the pixels 51, a signal is output as a voltage to the vertical signal lines 52-1 to 52-n. Connected to one end of each of the vertical signal lines 52-1 to 52-n is a vertical output circuit 53-1 to 53-n for outputting a signal level component and a reference level component for each column.
[0035]
Each of the vertical output circuits 53-1 to 53-n receives column selection signals Col (1) to Col (n) from the horizontal shift register 54 and is generated by, for example, a pulse generation circuit (not shown). A reference signal Ref and clamp signals Clamp S and Clamp R are commonly applied to each column. The signal level component and the reference level component output from the vertical output circuits 53-1 to 53-n are supplied to the horizontal output circuit 56 via the two horizontal signal lines 55s and 55r.
[0036]
The difference between the present embodiment having the above configuration and the previous embodiment is that, in the previous embodiment, the reference signals Ref (1) to Ref (n) and the clamp signals Clamp S (1) to Clamp S (n), Clamp R While (1) to Clamp R (n) are independently given to each column, in this embodiment, the reference signal Ref and the clamp signals Clamp S and Clamp R are commonly given to each column. There is in point. As the vertical output circuits 53-1 to 53-n and the horizontal output circuit 56, those having the same circuit configuration as those of the previous embodiment shown in FIG. 2 are used.
[0037]
FIG. 7 shows a timing chart according to the present embodiment. The basic circuit operations of the vertical output circuits 53-1 to 53-n and the horizontal output circuit 56 are the same as those in the previous embodiment. However, as described above, because the reference signal Ref and the clamp signals Clamp S and R are common to each column, the data sampled and held in the capacitors 23s and 23r (see FIG. 2) in the read unselected column is destroyed. In order to avoid this, the reference signal Ref and the clamp signals Clamp S and R need to have the phase relationship shown in FIG.
[0038]
That is, at time t7, after the clamp signals Clamp S and R first transit to the “L” level, the reference signal Ref transits to the “H” level, whereby the reference connected to both ends of the capacitors 23s and 23r. Since the switch 22 and the clamp switches 24s and 24r are not turned on at the same time, it is possible to reliably prevent the contents held in the capacitors 23s and 23r in the read non-selected column from being destroyed.
[0039]
In the case of the previous embodiment, the reference signals Ref (1) to Ref (n), the clamp signals Clamp S (1) to Clamp S (n), and Clamp R (1) to Clamp R (n) Since it is column independent and data may be destroyed after reading (time t7), the reference signals Ref (1) to Ref (n) and the clamp signals Clamp S (1) to Clamp S (n), Clamp The phase relationship between R (1) to Clamp R (n) is not strict. As shown in FIG. 5B, the transition of the i-th row clamp signals Clamp S and R (i) to the “L” level and i + 1 The transition to the “H” level of the column reference signal Ref (i + 1) may be at the same timing.
[0040]
Also in this embodiment, fixed pattern noise caused by variation in offset characteristics caused by switching of the sample and hold switch 21 can be suppressed as in the case of the previous embodiment. Further, since the reference signal Ref and the clamp signals Clamp S and R are made common to the respective columns, the wiring system for each of the vertical output circuits 53-1 to 53-n is compared with the previous embodiment in which each column is independent. There is an advantage that the configuration can be simplified.
[0041]
【The invention's effect】
As described above, according to the present invention, in the amplification type solid-state imaging device, the sample hold switch in the vertical output circuit provided for each column is shared by the signal level component in the light and the reference level component in the dark. The difference between the signal level component and the reference level component is obtained in the subsequent circuit by causing the offset noise accompanying the switching of the sample hold switch to ride on both the signal level component and the reference level component in the same way. At this time, since this noise component can be canceled, not only fixed pattern noise caused by pixel characteristic variation but also vertical streak-like fixed pattern noise caused by circuit characteristic variation can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing specific circuit configurations of a vertical output circuit and a horizontal output circuit.
FIG. 3 is a timing chart according to one embodiment.
FIG. 4 is an operation explanatory diagram according to one embodiment.
FIG. 5 is a timing chart for supplementary explanation.
FIG. 6 is a schematic configuration diagram showing another embodiment of the present invention.
FIG. 7 is a timing chart according to another embodiment.
FIG. 8 is a circuit diagram showing a conventional example.
[Explanation of symbols]
11, 51 Pixels 12-1 to 12-n, 52-1 to 52-n Vertical signal lines 13-1 to 13-n, 53-1 to 53-n Vertical output circuits 14, 54 Horizontal shift registers 15r, 15s, 55r, 55s Horizontal signal lines 16, 56 Horizontal output circuit

Claims (6)

A plurality of pixels arranged in a matrix;
First switch means having one end connected to a vertical signal line in which the output ends of the plurality of pixels are connected in columns;
Second switch means connected between the other end of the first switch means and a reference potential point;
First and second power storage means each having one end connected in common to the other end of the first switch means;
Third and fourth switch means respectively connected between the other ends of the first and second power storage means and a reference potential point;
A fifth and sixth switch means connected between each other end of the first and second power storage means and the first and second horizontal signal lines is provided for each column. Solid-state imaging device. A plurality of pixels arranged in a matrix, a first switch means having one end connected to a vertical signal line in which output ends of the plurality of pixels are connected in units of columns, and the first switch means A second switch means connected between one end and a reference potential point; first and second power storage means each having one end connected in common to the other end of the first switch means; and the first , Third and fourth switch means connected between the other end of the second power storage means and the reference potential point, respectively, and the other end of the first and second power storage means and the first and first A solid-state imaging device driving method comprising, for each column, fifth and sixth switch means connected between two horizontal signal lines,
In the horizontal blanking period, first, the first switch means and the third switch means are turned on, the fourth switch means is turned off, and the signal component at the time of light is sampled and held in the first power storage means. Subsequently, the first switch means and the fourth switch means are turned on, the third switch means is turned off, and the dark signal component is sampled and held in the second power storage means,
Next, in the horizontal effective period, the fifth and sixth switch means and the second switch means are sequentially turned on for each column, and the light is sampled and held in the first and second power storage means. A driving method of a solid-state imaging device, wherein each signal component in the dark is read out to the first and second horizontal signal lines. When turning off the first switch means and the third and fourth switch means, the third switch means is turned off after turning off the first switch means. Item 3. A driving method of a solid-state imaging device according to Item 2. 3. The method for driving a solid-state imaging device according to claim 2, wherein after the second switch means is turned off, the third and fourth switch means are turned on. 3. The method of driving a solid-state imaging device according to claim 2, wherein each timing signal for driving the second switch means and the third and fourth switch means is applied to each column independently. 3. A method for driving a solid-state imaging device according to claim 2, wherein the timing signals for driving the second switch means and the third and fourth switch means are applied in common to each column.

Images