JP2005026631A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

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Publication number
JP2005026631A
JP2005026631A JP2003270881A JP2003270881A JP2005026631A JP 2005026631 A JP2005026631 A JP 2005026631A JP 2003270881 A JP2003270881 A JP 2003270881A JP 2003270881 A JP2003270881 A JP 2003270881A JP 2005026631 A JP2005026631 A JP 2005026631A
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conductor pattern
semiconductor chip
semiconductor device
peeling
conductor
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JP4341328B2 (en
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Hidetoshi Kusano
英俊 草野
Atsushi Nakajo
敦士 中条
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Sony Corp
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is thin and excellent in the dimensional stability of a conductor pattern, and to provide a method for manufacturing the same. <P>SOLUTION: The method for manufacturing the semiconductor device includes a step of forming the conductor patterns 4 by a pattern plating method on one surface of a conductive release material; a step of connecting the conductor pattern 4 to a semiconductor chip 6, a step of burying between the conductor patterns 4, and forming an insulating resin material 8 on one surface of the release material so as to cover at least a connecting part of the conductor pattern 4 to the semiconductor chip 6; and a step of releasing the release material from the conductor pattern 4, and exposing the opposite surface of the connecting surface of the conductor pattern 4 to the semiconductor chip 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、剥離体から転写された導体パターンを有する半導体装置及びその製造方法に関し、更に詳しくは、導体パターン間を埋め且つ少なくとも導体パターンと半導体チップとの接合部を覆う絶縁樹脂材によって、剥離体から剥離後の導体パターンを支えるようにした半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device having a conductor pattern transferred from a peeled body and a method for manufacturing the same, and more specifically, peeling by an insulating resin material that fills between conductor patterns and covers at least a joint portion between the conductor pattern and a semiconductor chip. The present invention relates to a semiconductor device that supports a conductor pattern after peeling from a body, and a method for manufacturing the same.

近年、携帯電話機やＰＤＡ（Personal Digital Assistant）、ノート型コンピュータ等の電子機器の小型化、高機能化に伴い、これらを構成する電子部品の高密度実装化が不可欠となっている。従来より、電子部品の高密度実装化は、電子部品の小型化による部品端子のファインピッチ化や、電子部品が実装される配線基板上の導体パターンの微細化等によって進められてきた。   In recent years, as electronic devices such as mobile phones, PDAs (Personal Digital Assistants), and notebook computers have become smaller and more sophisticated, it has become essential to mount high-density electronic components. Conventionally, high-density mounting of electronic components has been promoted by making finer pitches of component terminals by miniaturization of electronic components, miniaturization of conductor patterns on a wiring board on which electronic components are mounted, and the like.

また、導体パターンを形成する方法として、従来より、剥離体を用いた転写法が知られている。この転写法による配線基板の製造プロセスは、主として、剥離体の一表面に導体パターンを形成するパターン形成工程と、形成した導体パターンを剥離体から剥離して半導体チップと接合させる転写工程とを有している。この種の従来技術として、例えば特許文献１が知られている。
特開平１０−１０７４４５号公報 As a method for forming a conductor pattern, a transfer method using a peeled body has been conventionally known. The manufacturing process of a wiring board by this transfer method mainly includes a pattern forming process for forming a conductor pattern on one surface of a peeling body, and a transfer process for peeling the formed conductor pattern from the peeling body and bonding it to a semiconductor chip. is doing. As this type of conventional technology, for example, Patent Document 1 is known.
Japanese Patent Laid-Open No. 10-107445

しかし、従来の転写法を用いた工法では、導体パターンに半導体チップを実装し、なおかつその半導体チップの電極パッドを再配置して引き出すための外部端子を形成しようとする場合には、ビア（層間接続層）を介して接続された２つの導体パターンを必要とし、半導体装置全体としての薄型化に限界がある。   However, in the conventional transfer method, when a semiconductor chip is mounted on a conductor pattern and an external terminal for rearranging the electrode pad of the semiconductor chip is to be formed, a via (interlayer) is used. Two conductor patterns connected via a connection layer) are required, and there is a limit to reducing the thickness of the entire semiconductor device.

本発明は上述の問題に鑑みてなされ、その目的とするところは、薄く且つ導体パターンの寸法安定性にも優れた半導体装置及びその製造方法を提供することにある。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device that is thin and excellent in dimensional stability of a conductor pattern and a method for manufacturing the same.

本発明の半導体装置は、剥離体から転写された導体パターンの、剥離体との剥離面の反対面に半導体チップが接合され、導体パターン間及び少なくとも導体パターンと半導体チップとの接合部が絶縁樹脂材で覆われていることを特徴としている。   In the semiconductor device of the present invention, a semiconductor chip is bonded to the surface of the conductor pattern transferred from the peeled body opposite to the peeled surface from the peeled body, and at least the joint between the conductor pattern and the conductor pattern and the semiconductor chip is an insulating resin. It is characterized by being covered with wood.

また、本発明の半導体装置の製造方法は、剥離体の一表面に導体パターンを形成する工程と、その導体パターンに半導体チップを接合する工程と、導体パターン間を埋め、且つ少なくとも導体パターンと半導体チップとの接合部を覆うように剥離体の一表面の上に絶縁樹脂材を形成する工程と、剥離体を導体パターンから剥離して、導体パターンの半導体チップとの接合面の反対面を露出させる工程とを有することを特徴としている。   The method for manufacturing a semiconductor device of the present invention includes a step of forming a conductor pattern on one surface of a peeled body, a step of bonding a semiconductor chip to the conductor pattern, a gap between the conductor patterns, and at least the conductor pattern and the semiconductor. A process of forming an insulating resin material on one surface of the peeling body so as to cover the bonding portion with the chip, and peeling the peeling body from the conductor pattern to expose the opposite surface of the conductor pattern to the semiconductor chip. It has the process to make it have.

本発明では、導体パターンは剥離体上に形成され、その状態で導体パターンに対する半導体チップの接合及び導体パターン間を埋め、且つ少なくとも導体パターンと半導体チップとの接合部を覆う絶縁樹脂材の形成が行われる。   In the present invention, the conductive pattern is formed on the peeled body, and in this state, the bonding of the semiconductor chip to the conductive pattern and the formation of the insulating resin material covering the gap between the conductive pattern and covering at least the bonding portion of the conductive pattern and the semiconductor chip are formed. Done.

この後、導体パターンを剥離体から剥離すると、導体パターンは上記絶縁樹脂材によって支えられることになる。更に、導体パターンにおいて剥離体と貼り合わされていた面が露出し、この面をマザーボードや他の半導体装置との外部接続端子として機能させることができる。このようにして、１層の導体パターンの一方の面に半導体チップが接合され、他方の面を外部接続端子として機能させることのできる半導体装置が得られ、２層の導体パターンがビアを介して接続された構造に比べ半導体装置を薄くできる。   Thereafter, when the conductor pattern is peeled from the peeled body, the conductor pattern is supported by the insulating resin material. Furthermore, the surface of the conductor pattern that is bonded to the peeled body is exposed, and this surface can function as an external connection terminal for a mother board or another semiconductor device. In this way, a semiconductor device is obtained in which the semiconductor chip is bonded to one surface of the one-layer conductor pattern and the other surface can function as an external connection terminal, and the two-layer conductor pattern is connected via the via. The semiconductor device can be made thinner than the connected structure.

絶縁樹脂材によって導体パターンを安定して支持し、また半導体チップと導体パターンとの接合信頼を確保するためには、導体パターン間及び少なくとも導体パターンと半導体チップとの接合部が絶縁樹脂材で覆われるようにする。もちろん、半導体チップの全てが絶縁樹脂材によって覆われるようにして半導体チップの完全な保護を図ってもよい。   In order to stably support the conductor pattern by the insulating resin material and to ensure the bonding reliability between the semiconductor chip and the conductor pattern, the insulating resin material is covered between the conductor patterns and at least the bonding portion between the conductor pattern and the semiconductor chip. To be Of course, complete protection of the semiconductor chip may be achieved by covering all of the semiconductor chip with the insulating resin material.

剥離体は、導体パターンの平面度を維持するため及びハンドリング性を向上させるための支持体として機能する。したがって、この要求に応えるべき強度等の機械的性質及び耐熱温度等の材料学的性質を具備するように構成される。   The peeled body functions as a support for maintaining the flatness of the conductor pattern and for improving handling properties. Therefore, it is configured to have mechanical properties such as strength and material properties such as heat-resistant temperature to meet this requirement.

剥離体は、最終的には導体パターンから分離されて残らない。その分離を容易とするための剥離層を有していることが好ましい。剥離層としては、例えば複数の金属層を積層させた構成が挙げられる。この構成の場合には、加熱工程を経ても寸法変化や変質などが生じないという利点がある。   The peeled body is not finally separated from the conductor pattern. It is preferable to have a release layer for facilitating the separation. As a peeling layer, the structure which laminated | stacked the several metal layer is mentioned, for example. In the case of this configuration, there is an advantage that no dimensional change or alteration occurs even after the heating process.

また、他の剥離層の構成として、剥離されるべき表面の所定部位に離型剤が塗布された樹脂層が挙げられる。更に、他の剥離層として熱発泡層を用いてもよく、この場合、所定温度への加熱処理により熱発泡層を発泡させて転写用支持体の剥離が可能である。   Moreover, as a structure of another peeling layer, the resin layer by which the mold release agent was apply | coated to the predetermined site | part of the surface which should be peeled is mentioned. Furthermore, a thermal foam layer may be used as another release layer. In this case, the transfer support can be peeled by foaming the thermal foam layer by heat treatment to a predetermined temperature.

あるいは、剥離層は設けずに、剥離体を溶解させて、導体パターンから分離させてもよい。   Alternatively, the peeling body may be dissolved and separated from the conductor pattern without providing the peeling layer.

また、剥離体に導電性をもたせれば、アディティブ法によるパターンめっき技術を用いてファインピッチな導体パターンを形成できる。   Further, if the peeled body is made conductive, a fine pitch conductor pattern can be formed using a pattern plating technique based on an additive method.

また、上記半導体装置を複数積層させてもよい。この場合における各半導体装置間の電気的接続の方法として、例えば剥離体を導電材料から構成しその剥離体を全部剥離せずに一部を残せば、この残した部分を他の半導体装置の導体パターンとの接続を担う層間接続材として用いることができる。これにより、無駄のない効率的な工程が行える。もちろん、その一部を残した剥離体を、マザーボードなどの他の配線基板との接続材として用いてもよい。その他に、別途設けたはんだバンプ、めっきバンプ、スタッドバンプなどで層間接続、あるいはマザーボードとの接続を行ってもよい。   A plurality of the semiconductor devices may be stacked. In this case, as a method of electrical connection between the semiconductor devices, for example, if the peeled body is made of a conductive material and a part of the peeled body is left without being peeled, the remaining part is used as a conductor of another semiconductor device. It can be used as an interlayer connection material for connection with the pattern. Thereby, an efficient process without waste can be performed. Of course, the peeled body leaving a part thereof may be used as a connection material with another wiring board such as a mother board. In addition, an interlayer connection or a connection with a mother board may be performed using a solder bump, a plating bump, a stud bump, or the like provided separately.

本発明によれば、剥離体の一表面に導体パターンを形成し、その導体パターンに半導体チップを接合し、更に導体パターン間を埋め、且つ少なくとも導体パターンと半導体チップとの接合部を覆うように剥離体の一表面の上に絶縁樹脂材を形成してから、剥離体を導体パターンから剥離して、導体パターンの半導体チップとの接合面の反対面を露出させて半導体装置を得るので、既存の設備を用いた簡単な工程にて薄く且つ導体パターンの寸法安定性に優れた半導体装置が得られる。この結果、低コストで信頼性に優れた薄型の半導体装置が得られる。   According to the present invention, a conductor pattern is formed on one surface of the peelable body, a semiconductor chip is bonded to the conductor pattern, and further, the gap between the conductor patterns is filled, and at least the junction between the conductor pattern and the semiconductor chip is covered. Since an insulating resin material is formed on one surface of the peeled body, the peeled body is peeled from the conductor pattern, and the surface opposite to the bonding surface of the conductor pattern with the semiconductor chip is exposed to obtain a semiconductor device. A semiconductor device that is thin and excellent in dimensional stability of the conductor pattern can be obtained by a simple process using the above-described equipment. As a result, a thin semiconductor device with low cost and excellent reliability can be obtained.

［第１の実施形態］
本実施形態では半導体チップの実装形態の一例としてフリップチップ方式で半導体チップが導体パターンに接合された半導体装置及びその製造方法について説明する。 [First Embodiment]
In the present embodiment, a semiconductor device in which a semiconductor chip is bonded to a conductor pattern by a flip chip method and an example of a manufacturing method thereof will be described as an example of a semiconductor chip mounting form.

（図１Ａの工程）
支持体１の一表面の全面に剥離層２が形成されてなる剥離体を作製する。支持体１は例えば銅材料からなり、以下の工程中におけるハンドリングに必要とされる機械的性質または材料学的性質を具備するように構成される。厚さは、例えば１４０μｍである。 (Step of FIG. 1A)
A release body in which the release layer 2 is formed on the entire surface of one surface of the support 1 is produced. The support 1 is made of, for example, a copper material, and is configured to have mechanical properties or material properties required for handling in the following steps. The thickness is 140 μm, for example.

剥離層２は、例えば支持体１上に積層されるＣｒ層とこのＣｒ層の上に積層される（Ｎｉ−Ｃｏ）層から構成される。剥離層２は支持体１を給電体とした電気めっき法で形成される。あるいは、支持体１と剥離層２とを圧延ローラなどを用いて貼り合わせてもよい。   The release layer 2 includes, for example, a Cr layer stacked on the support 1 and a (Ni—Co) layer stacked on the Cr layer. The release layer 2 is formed by an electroplating method using the support 1 as a power feeding body. Alternatively, the support 1 and the release layer 2 may be bonded using a rolling roller or the like.

剥離層２を構成するＣｒ層と（Ｎｉ−Ｃｏ）層は、例えば３２０℃ほどの温度でも金属接合しない特性を有し、したがって、途中に熱プレスを受ける工程（半導体チップの接合工程など）があっても、後述するようにＣｒ層と（Ｎｉ−Ｃｏ）層との境界で簡単に剥離することができる。   The Cr layer and the (Ni—Co) layer constituting the release layer 2 have a characteristic that metal bonding does not occur even at a temperature of, for example, about 320 ° C. Therefore, there is a process (such as a semiconductor chip bonding process) that undergoes hot pressing in the middle. Even if it exists, it can peel easily at the boundary of a Cr layer and a (Ni-Co) layer so that it may mention later.

（図１Ｂの工程）
剥離層２上にめっきレジスト３を形成する。具体的には、先ず、剥離層２の表面である（Ｎｉ−Ｃｏ）層の表面にレジスト膜を全面的に形成した後、そのレジスト膜に露光及び現像を施して所望の形状にパターニングしてめっきレジスト３を形成する。 (Step of FIG. 1B)
A plating resist 3 is formed on the release layer 2. Specifically, first, a resist film is formed on the entire surface of the (Ni—Co) layer, which is the surface of the release layer 2, and then the resist film is exposed and developed to be patterned into a desired shape. A plating resist 3 is formed.

（図１Ｃの工程）
剥離体を給電体に、めっきレジスト３をマスクとしたパターンめっきを行い、剥離層２上に例えば銅材料からなる導体パターン４を形成する。 (Step of FIG. 1C)
Pattern plating is performed using the peeling body as a power feeding body and the plating resist 3 as a mask, and a conductive pattern 4 made of, for example, a copper material is formed on the peeling layer 2.

（図１Ｄの工程）
上記めっきレジスト３をそのままマスクとして用い、導体パターン４の表面に金属膜５を例えばめっき法で形成する。金属膜５は、例えばNi,Au,Ag,Sn,Sn-Pb,Sn-Agなどからなり、後述する半導体チップとの接合性を向上させる役割を担う。 (Process of FIG. 1D)
Using the plating resist 3 as a mask as it is, a metal film 5 is formed on the surface of the conductor pattern 4 by, for example, a plating method. The metal film 5 is made of, for example, Ni, Au, Ag, Sn, Sn-Pb, Sn-Ag, and the like, and plays a role of improving the bonding property with a semiconductor chip to be described later.

（図１Ｅの工程）
以上の導体パターン４及び金属膜５が形成された後、不要となっためっきレジスト３を剥離層２上から除去する。 (Step of FIG. 1E)
After the conductor pattern 4 and the metal film 5 are formed, the unnecessary plating resist 3 is removed from the release layer 2.

一般に、ウェットエッチング法によって導体膜の不要部分を除去し導体パターンを形成する方法（サブトラクティブ法）に比べて、電気めっき法によって必要な部分のみ導体膜を析出させて導体パターンを形成する方法（アディティブ法）の方が微細なパターンを形成することができるので、本実施形態によれば、ラインアンドスペース（line／space）が例えば１０μｍ／１０μｍといったファインピッチな導体パターン４を高精度に形成することができる。   In general, compared to a method (subtractive method) in which unnecessary portions of a conductive film are removed by wet etching and a conductive pattern is formed (subtractive method), a conductive pattern is formed by depositing a conductive film only in necessary portions by electroplating ( Since the additive method can form a finer pattern, according to this embodiment, the fine pitch conductor pattern 4 having a line / space of, for example, 10 μm / 10 μm is formed with high accuracy. be able to.

また、剥離体の全厚のほとんどを占める銅材料からなる支持体１は寸法変化が小さく、以下に続く工程中における導体パターンの寸法変化を抑制して微細な導体パターンの寸法精度を安定して保つことができる。   Further, the support 1 made of a copper material that occupies most of the total thickness of the peeled body has a small dimensional change, and suppresses the dimensional change of the conductor pattern during the following process, thereby stabilizing the dimensional accuracy of the fine conductor pattern. Can keep.

（図２Ｆの工程）
導体パターン４上に半導体チップ６をマウントする。具体的には、半導体チップ６の主面に形成された複数の電極パッドの各々に例えばNi,Au,Ag,Sn,Sn-Pb,Sn-Agなどからなる導電性バンプ７を形成し、これら導電性バンプ７を導体パターン４の上に形成された金属膜５に押し付けた状態で加熱を行うことで、導電性バンプ７は金属膜５を介して導体パターン４と金属接合される。これにより、半導体チップ６は、導電性バンプ７を介して導体パターン４と電気的に接続される。 (Process of FIG. 2F)
A semiconductor chip 6 is mounted on the conductor pattern 4. Specifically, conductive bumps 7 made of, for example, Ni, Au, Ag, Sn, Sn-Pb, Sn-Ag or the like are formed on each of the plurality of electrode pads formed on the main surface of the semiconductor chip 6. Heating is performed in a state where the conductive bump 7 is pressed against the metal film 5 formed on the conductor pattern 4, so that the conductive bump 7 is metal-bonded to the conductor pattern 4 through the metal film 5. As a result, the semiconductor chip 6 is electrically connected to the conductor pattern 4 via the conductive bumps 7.

このとき、金属膜５は導電性バンプ７と導体パターン４との間のぬれ性や接合性を高めて、より低荷重、低温での接合が行え、半導体チップ６へのダメージの軽減化が図れる。   At this time, the metal film 5 enhances the wettability and bondability between the conductive bumps 7 and the conductor pattern 4 so that bonding can be performed at a lower load and lower temperature, and damage to the semiconductor chip 6 can be reduced. .

（図２Ｇの工程）
半導体チップ６との接合が完了した導体パターン４を剥離体ごと金型にセットして、金型のキャビティ内に液状化した例えばエポキシ系の熱硬化樹脂を流し込んでモールド成型を行う。その後、流し込んだ樹脂を硬化させた後、剥離体を金型から離型させることで、導体パターン４間を埋め、且つ半導体チップ６と導体パターン４との接合部（導電バンプ７の周囲）を含む半導体チップ６全体を覆う絶縁樹脂材８が形成される。 (Process of FIG. 2G)
The conductor pattern 4 that has been joined to the semiconductor chip 6 is set together with the peeled body in a mold, and liquefied, for example, an epoxy-based thermosetting resin is poured into the mold cavity to perform molding. Thereafter, the poured resin is cured, and then the peeled body is released from the mold so that the space between the conductor patterns 4 is filled and the junction between the semiconductor chip 6 and the conductor pattern 4 (around the conductive bumps 7) is formed. An insulating resin material 8 covering the entire semiconductor chip 6 is formed.

（図３Ｈの工程）
剥離層２を構成するＣｒ層と（Ｎｉ−Ｃｏ）層との境界面に切れ込みを入れて剥離する。これにより、支持体１はＣｒ層と共に導体パターン４から分離され、導体パターン４において半導体チップ６の接合面の反対面の表面には、剥離層２の（Ｎｉ−Ｃｏ）層が残る。 (Process of FIG. 3H)
Peeling is made at the boundary surface between the Cr layer and the (Ni—Co) layer constituting the peeling layer 2. Thus, the support 1 is separated from the conductor pattern 4 together with the Cr layer, and the (Ni—Co) layer of the release layer 2 remains on the surface of the conductor pattern 4 opposite to the bonding surface of the semiconductor chip 6.

（図３Ｉの工程）
その残った（Ｎｉ−Ｃｏ）層を例えば過酸化水素系のエッチング液を用いてウェットエッチングして除去する。これにより、導体パターン４において半導体チップ６の接合面の反対面（剥離体との剥離面）が外部に露出される。 (Step of FIG. 3I)
The remaining (Ni—Co) layer is removed by wet etching using, for example, a hydrogen peroxide-based etchant. Thereby, in the conductor pattern 4, the opposite surface (peeling surface with a peeling body) of the joining surface of the semiconductor chip 6 is exposed outside.

（図３Ｊの工程）
その露出した導体パターン４の表面に、例えばNi,Au,Ag,Sn,Sn-Pb,Sn-Agなどからなる金属膜９を形成する。この金属膜９は、マザーボードや他の半導体装置との接合性を向上させる役割を担う。そして、個片化を行うことによって、単層の導体パターン４の一方の面に半導体チップ６が接合され、反対側の他方をマザーボードや他の半導体装置との接続端子として機能させることのできる半導体装置１１が得られる。 (Process of FIG. 3J)
A metal film 9 made of, for example, Ni, Au, Ag, Sn, Sn—Pb, Sn—Ag or the like is formed on the exposed surface of the conductor pattern 4. The metal film 9 plays a role of improving the bonding property with the mother board and other semiconductor devices. The semiconductor chip 6 is bonded to one surface of the single-layer conductor pattern 4 by dividing into pieces, and the other side can function as a connection terminal for a mother board or another semiconductor device. Device 11 is obtained.

なお、個片化処理は、絶縁樹脂材８を形成した後であれば、どの段階で行っても構わない。   The singulation process may be performed at any stage as long as the insulating resin material 8 is formed.

半導体チップ６に形成された多数の電極パッドは、導体パターン４を介して、より拡大されたピッチでもって導体パターン４における半導体チップ６との接合面の反対面へと引き出されて再配置される。このような構造が、単層の導体パターン４の表裏を利用して実現できるので半導体装置１１全体の薄型化が図れる。   A large number of electrode pads formed on the semiconductor chip 6 are drawn through the conductor pattern 4 to a surface opposite to the bonding surface with the semiconductor chip 6 in the conductor pattern 4 with a larger pitch. . Since such a structure can be realized by using the front and back of the single-layer conductor pattern 4, the entire semiconductor device 11 can be thinned.

また、導体パターン４の形成に際しては、厚く平らな剥離体を出発材とし、アディティブ法によるパターンめっきによって、通常の半導体インターポーザ基板やＴＡＢ（tape automated bonding）テープでは不可能な１０μｍ以下の微細な導体パターン４を形成することが可能となる。   Also, when forming the conductor pattern 4, a fine and flat conductor having a thickness of 10 μm or less, which is impossible with a normal semiconductor interposer substrate or TAB (tape automated bonding) tape, is obtained by pattern plating by an additive method using a thick and flat peeled body as a starting material. The pattern 4 can be formed.

また、剥離体（支持体１及び剥離層２）は金属材料からなるので、樹脂フィルムから構成されるものに比べて強度があり、ハンドリング時における伸縮や反りを抑制し、ファインピッチな導体パターン４を高い寸法安定性でもって扱うことができる。   In addition, since the release body (support 1 and release layer 2) is made of a metal material, it has higher strength than that made of a resin film, suppresses expansion and contraction and warping during handling, and has a fine pitch conductor pattern 4. Can be handled with high dimensional stability.

更に、剥離体が金属材料からなることの利点として、熱処理や薬品を用いた処理における制約が有機材料に比べて少なく、材料や、加熱、加圧条件などの選択自由度が高い。   Further, as an advantage that the peeled body is made of a metal material, there are few restrictions on heat treatment and treatment using chemicals compared to organic materials, and there is a high degree of freedom in selecting materials, heating, and pressure conditions.

［第２の実施形態］
次に本発明の第２の実施形態について説明する。なお、上記第１の実施形態と同じ構成部分には同一の符号を付しその詳細な説明は省略する。 [Second Embodiment]
Next, a second embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and the detailed description is abbreviate | omitted.

本実施形態ではワイヤボンディング方式で半導体チップが導体パターンに接合された半導体装置及びその製造方法について説明する。図１Ａ〜図１Ｅまでは上記第１の実施形態と同様にして行われる。そして、本実施形態では図１Ｅの工程の後以下の工程が続けられる。   In the present embodiment, a semiconductor device in which a semiconductor chip is bonded to a conductor pattern by a wire bonding method and a manufacturing method thereof will be described. 1A to 1E are performed in the same manner as in the first embodiment. And in this embodiment, the following processes are continued after the process of FIG. 1E.

（図４Ｆの工程）
半導体チップ６を例えば熱硬化性樹脂などのダイボンディングペーストを用いて導体パターン４上にマウントすると共に、半導体チップ６の主面に形成された複数の電極パッドと導体パターン４とをボンディングワイヤ１０を用いて接合する。これにより、半導体チップ６は、ボンディングワイヤ１０を介して導体パターン４と電気的に接続される。 (Step of FIG. 4F)
The semiconductor chip 6 is mounted on the conductor pattern 4 using a die bonding paste such as a thermosetting resin, for example, and a plurality of electrode pads formed on the main surface of the semiconductor chip 6 and the conductor pattern 4 are bonded to the bonding wire 10. Use to join. Thereby, the semiconductor chip 6 is electrically connected to the conductor pattern 4 via the bonding wire 10.

（図４Ｇの工程）
半導体チップ６との接合が完了した導体パターン４を剥離体ごと金型にセットして、金型のキャビティ内に液状化した例えばエポキシ系の熱硬化樹脂を流し込んでモールド成型を行う。その後、流し込んだ樹脂を硬化させた後、剥離体を金型から離型させることで、導体パターン４間を埋め、且つ半導体チップ６と導体パターン４との接合部（ボンディングワイヤ１０と半導体チップ６の電極パッドとの接合部、ボンディングワイヤ１０と導体パターン４との接合部）を含む半導体チップ６全体を覆う絶縁樹脂材８が形成される。 (Process of FIG. 4G)
The conductor pattern 4 that has been joined to the semiconductor chip 6 is set together with the peeled body in a mold, and liquefied, for example, an epoxy-based thermosetting resin is poured into the mold cavity to perform molding. Thereafter, the poured resin is cured, and then the peeled body is released from the mold, thereby filling the space between the conductor patterns 4 and joining the semiconductor chip 6 and the conductor pattern 4 (bonding wire 10 and semiconductor chip 6). Insulating resin material 8 is formed to cover the entire semiconductor chip 6 including the bonding portion with the electrode pad and the bonding wire 10 and the conductor pattern 4.

（図５Ｈの工程）
剥離層２を構成するＣｒ層と（Ｎｉ−Ｃｏ）層との境界面に切れ込みを入れて剥離する。これにより、支持体１はＣｒ層と共に導体パターン４から分離され、導体パターン４において半導体チップ６の接合面の反対面の表面には、剥離層２の（Ｎｉ−Ｃｏ）層が残る。 (Step of FIG. 5H)
Peeling is made at the boundary surface between the Cr layer and the (Ni—Co) layer constituting the peeling layer 2. Thus, the support 1 is separated from the conductor pattern 4 together with the Cr layer, and the (Ni—Co) layer of the release layer 2 remains on the surface of the conductor pattern 4 opposite to the bonding surface of the semiconductor chip 6.

（図５Ｉの工程）
その残った（Ｎｉ−Ｃｏ）層を例えば過酸化水素系のエッチング液を用いてウェットエッチングして除去する。これにより、導体パターン４において半導体チップ６の接合面の反対面（剥離体との剥離面）が外部に露出される。 (Step of FIG. 5I)
The remaining (Ni—Co) layer is removed by wet etching using, for example, a hydrogen peroxide-based etchant. Thereby, in the conductor pattern 4, the opposite surface (peeling surface with a peeling body) of the joining surface of the semiconductor chip 6 is exposed outside.

（図５Ｊの工程）
その露出した導体パターン４の表面に、例えばNi,Au,Ag,Sn,Sn-Pb,Sn-Agなどからなる金属膜９を形成する。この金属膜９は、マザーボードや他の半導体装置との接合性を向上させる役割を担う。そして、個片化を行うことによって、単層の導体パターン４の一方の面に半導体チップ６が接合され、反対側の他方をマザーボードや他の半導体装置との接続端子として機能させることのできる半導体装置１２が得られる。なお、本実施形態においても、個片化処理は、絶縁樹脂材８を形成した後であれば、どの段階で行っても構わない。 (Step of FIG. 5J)
A metal film 9 made of, for example, Ni, Au, Ag, Sn, Sn—Pb, Sn—Ag or the like is formed on the exposed surface of the conductor pattern 4. The metal film 9 plays a role of improving the bonding property with the mother board and other semiconductor devices. The semiconductor chip 6 is bonded to one surface of the single-layer conductor pattern 4 by dividing into pieces, and the other side can function as a connection terminal for a mother board or another semiconductor device. Device 12 is obtained. Also in this embodiment, the singulation process may be performed at any stage as long as the insulating resin material 8 is formed.

本実施形態においても、半導体チップ６に形成された多数の電極パッドは、より拡大されたピッチでもって導体パターン４における半導体チップ６との接合面の反対面へと引き出されて再配置される。このような構造が、単層の導体パターン４の表裏を利用して実現できるので半導体装置１１全体の薄型化が図れる。その他、上記第１の実施形態で述べたことと同様な効果が得られる。   Also in this embodiment, a large number of electrode pads formed on the semiconductor chip 6 are drawn out and rearranged on the surface opposite to the bonding surface of the conductor pattern 4 with the semiconductor chip 6 with a larger pitch. Since such a structure can be realized by using the front and back of the single-layer conductor pattern 4, the entire semiconductor device 11 can be thinned. In addition, the same effects as described in the first embodiment can be obtained.

［第３の実施形態］
次に本発明の第３の実施形態について説明する。なお、上記第１の実施形態と同じ構成部分には同一の符号を付しその詳細な説明は省略する。 [Third Embodiment]
Next, a third embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and the detailed description is abbreviate | omitted.

（図６Ａの工程）
支持体１の一表面の全面に剥離層２が形成されてなる剥離体を作製し、その剥離層２の上に導体パターン形成膜１３を形成する。支持体１は例えば銅材料からなり、以下の工程中におけるハンドリングに必要とされる機械的性質または材料学的性質を具備するように構成される。厚さは、例えば１４０μｍである。 (Step of FIG. 6A)
A release body in which a release layer 2 is formed on the entire surface of one surface of the support 1 is produced, and a conductor pattern forming film 13 is formed on the release layer 2. The support 1 is made of, for example, a copper material, and is configured to have mechanical properties or material properties required for handling in the following steps. The thickness is 140 μm, for example.

剥離層２は、例えば支持体１上に積層されるＣｒ層とこのＣｒ層の上に積層される（Ｎｉ−Ｃｏ）層から構成される。導体パターン形成膜１３は例えば銅材料から構成される。剥離層２及びこの上に形成される導体パターン形成膜１３は支持体１を給電体とした電気めっき法で形成される。あるいは、支持体１、剥離層２、および導体パターン形成膜１３を圧延ローラなどを用いて貼り合わせてもよい。   The release layer 2 includes, for example, a Cr layer stacked on the support 1 and a (Ni—Co) layer stacked on the Cr layer. The conductor pattern forming film 13 is made of, for example, a copper material. The peeling layer 2 and the conductor pattern forming film 13 formed thereon are formed by electroplating using the support 1 as a power feeding body. Or you may bond together the support body 1, the peeling layer 2, and the conductor pattern formation film 13 using a rolling roller.

剥離層２を構成するＣｒ層と（Ｎｉ−Ｃｏ）層は、例えば３２０℃ほどの温度でも金属接合しない特性を有し、したがって、途中に熱プレスを受ける工程（半導体チップの接合工程など）があっても、Ｃｒ層と（Ｎｉ−Ｃｏ）層との境界で簡単に剥離することができる。   The Cr layer and the (Ni—Co) layer constituting the release layer 2 have a characteristic that metal bonding does not occur even at a temperature of, for example, about 320 ° C. Therefore, there is a process (such as a semiconductor chip bonding process) that undergoes hot pressing in the middle. Even if it exists, it can peel easily in the boundary of a Cr layer and a (Ni-Co) layer.

（図６Ｂの工程）
導体パターン形成膜１３上にエッチングレジスト１４を形成する。具体的には、先ず、導体パターン形成膜１３の表面にレジスト膜を全面的に形成した後、そのレジスト膜に露光及び現像を施して所望の形状にパターニングしてエッチングレジスト１４を形成する。 (Step of FIG. 6B)
An etching resist 14 is formed on the conductor pattern forming film 13. Specifically, first, a resist film is formed on the entire surface of the conductor pattern forming film 13, and then the resist film is exposed and developed to be patterned into a desired shape to form an etching resist 14.

（図６Ｃの工程）
エッチングレジスト１４をマスクとして、例えばアルカリ系のエッチング液を用いて銅材料からなる導体パターン形成膜１３のみをエッチングする。これにより、導体パターン１５が得られる。 (Step of FIG. 6C)
Using the etching resist 14 as a mask, only the conductor pattern forming film 13 made of a copper material is etched using, for example, an alkaline etching solution. Thereby, the conductor pattern 15 is obtained.

（図６Ｄの工程）
導体パターン１５上に残っているエッチングレジスト１４を除去する。 (Step of FIG. 6D)
The etching resist 14 remaining on the conductor pattern 15 is removed.

（図６Ｅの工程）
導体パターン１５間から露出している剥離層２上に図示しないめっきレジストを形成した後、そのめっきレジストをマスクとして、導体パターン１５の表面に金属膜５を例えばめっき法で形成する。金属膜５は、例えばNi,Au,Ag,Sn,Sn-Pb,Sn-Agなどからなり、後述する半導体チップとの接合性を向上させる役割を担う。 (Step of FIG. 6E)
After forming a plating resist (not shown) on the release layer 2 exposed from between the conductor patterns 15, the metal film 5 is formed on the surface of the conductor pattern 15 by, for example, a plating method using the plating resist as a mask. The metal film 5 is made of, for example, Ni, Au, Ag, Sn, Sn-Pb, Sn-Ag, and the like, and plays a role of improving the bonding property with a semiconductor chip to be described later.

以降、上記第１の実施形態と同様な図２〜図３の工程、あるいは第２の実施形態と同様な図４〜図５の工程が行われて、上記第１あるいは第２の実施形態と同様な半導体装置が得られる。   Thereafter, the processes of FIGS. 2 to 3 similar to those of the first embodiment or the processes of FIGS. 4 to 5 similar to those of the second embodiment are performed, and the process of the first or second embodiment is performed. A similar semiconductor device can be obtained.

本実施形態では、ウェットエッチング法によって導体膜の不要部分を除去し導体パターン１５を形成するので、電気めっき法によって必要な部分のみ導体膜を析出させて導体パターンを形成する方法に比べて低コストで行える。   In the present embodiment, unnecessary portions of the conductor film are removed by the wet etching method to form the conductor pattern 15, so that the cost is lower than the method of forming the conductor pattern by depositing the conductor film only at the necessary portion by the electroplating method. You can do it.

［第４の実施の形態］
次に本発明の第４の実施形態について説明する。なお、上記第１の実施形態と同じ構成部分には同一の符号を付しその詳細な説明は省略する。 [Fourth Embodiment]
Next, a fourth embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and the detailed description is abbreviate | omitted.

図１Ａ〜図２Ｇまでは、上記第１の実施形態と同様にして進められ、図１０Ａに示す状態に至る。その後、本実施形態では図１０Ｂ、Ｃに示す工程が行われる。   1A to 2G proceed in the same manner as in the first embodiment, and reach the state shown in FIG. 10A. Thereafter, in the present embodiment, the steps shown in FIGS. 10B and 10C are performed.

（図１０Ｂの工程）
支持体１の剥離に際して、全部を剥離するのではなくその一部を残す。例えばアルカリ系エッチング液を用いたウェットエッチングによって、銅材料からなる支持体１を部分的に除去し、絶縁樹脂材８の形成されていない導体パターン４の両端部に対応する位置にある部分を残し、これを層間接続材１ａとして機能させる。 (Step of FIG. 10B)
When the support 1 is peeled off, the whole is not peeled off but a part thereof is left. For example, the support 1 made of a copper material is partially removed by wet etching using an alkaline etching solution, leaving portions at positions corresponding to both ends of the conductor pattern 4 where the insulating resin material 8 is not formed. This is made to function as the interlayer connection material 1a.

（図１０Ｃの工程）
すなわち、図１０Ｃに示すように、上記図１０Ｂで得られた半導体装置２０ａを、第１の実施形態と同工程で得られる半導体装置２０ｂの上に重ねて、上記層間接続材１ａの下端部を例えばはんだ１９を介して半導体装置２０ｂの金属膜５に接合させる。 (Step of FIG. 10C)
That is, as shown in FIG. 10C, the semiconductor device 20a obtained in FIG. 10B is overlaid on the semiconductor device 20b obtained in the same process as the first embodiment, and the lower end portion of the interlayer connection material 1a is placed. For example, it is bonded to the metal film 5 of the semiconductor device 20b through the solder 19.

これにより、互いの導体パターン４どうしが層間接続材１ａを介して電気的に接続された、すなわち半導体チップ６どうしが層間接続材１ａを介して電気的に接続された半導体装置２０が得られる。層間接続材１ａは別途形成することなく、支持体１の剥離の際に一部を残すことで得られ、工程の簡略化及びコスト低減が図れる。なお、積層させる半導体装置は２個に限らずそれ以上であってもよい。   As a result, the semiconductor device 20 is obtained in which the conductor patterns 4 are electrically connected to each other via the interlayer connection material 1a, that is, the semiconductor chips 6 are electrically connected to each other via the interlayer connection material 1a. The interlayer connecting material 1a is obtained by leaving a part when the support 1 is peeled off without being separately formed, and the process can be simplified and the cost can be reduced. Note that the number of semiconductor devices to be stacked is not limited to two and may be more than that.

［第５の実施の形態］
次に本発明の第５の実施形態について説明する。なお、上記第１の実施形態と同じ構成部分には同一の符号を付しその詳細な説明は省略する。 [Fifth Embodiment]
Next, a fifth embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as said 1st Embodiment, and the detailed description is abbreviate | omitted.

上記第１の実施形態と同様にして、図１１Ａに示す半導体装置２１ａを得た後、本実施形態では図１１Ｂ、Ｃに示す工程が行われる。   In the same manner as in the first embodiment, after obtaining the semiconductor device 21a shown in FIG. 11A, the steps shown in FIGS. 11B and 11C are performed in this embodiment.

（図１１Ｂの工程）
絶縁樹脂材８の形成されていない、金属膜５、導体パターン４、金属膜９からなる積層体の両端部を、半導体チップ６の接合面の反対面側に折り曲げ、この折り曲げられた部分を層間接続材２３として機能させる。 (Step of FIG. 11B)
Both ends of the laminate composed of the metal film 5, the conductor pattern 4, and the metal film 9 on which the insulating resin material 8 is not formed are bent to the opposite side of the bonding surface of the semiconductor chip 6, and the bent portion is the interlayer. It functions as the connecting material 23.

（図１１Ｃの工程）
すなわち、図１１Ｃに示すように、上記図１１Ｂで得られた半導体装置２１ａを、第１の実施形態と同工程で得られる半導体装置２１ｂの上に重ねて、上記層間接続材２３の下端部を例えばはんだ１９を介して半導体装置２１ｂの金属膜５に接合させる。 (Step of FIG. 11C)
That is, as shown in FIG. 11C, the semiconductor device 21a obtained in FIG. 11B is overlaid on the semiconductor device 21b obtained in the same process as the first embodiment, and the lower end portion of the interlayer connecting material 23 is For example, it is bonded to the metal film 5 of the semiconductor device 21b through the solder 19.

これにより、互いの導体パターン４どうしが層間接続材２３を介して電気的に接続された、すなわち半導体チップ６どうしが層間接続材２３を介して電気的に接続された半導体装置２１が得られる。   As a result, the semiconductor device 21 in which the conductor patterns 4 are electrically connected to each other via the interlayer connection material 23, that is, the semiconductor chips 6 are electrically connected to each other via the interlayer connection material 23 is obtained.

層間接続材２３として機能する金属膜５、導体パターン４、金属膜９からなる積層体の厚さは上述した剥離体からの転写法を用いることで非常に薄く（例えば数μｍ〜２０μｍほど）できる。したがって、層間接続材２３に外部から応力が作用した場合に層間接続材２３を撓ませるような動きをさせることができ、層間接続材２３の下端部と、他の半導体装置２１ｂの金属膜５との接合部にかかる負荷を軽減させて接合信頼性の向上が図れる。なお、積層させる半導体装置は２個に限らずそれ以上であってもよい。   The thickness of the laminate composed of the metal film 5, the conductor pattern 4, and the metal film 9 functioning as the interlayer connection material 23 can be very thin (for example, about several μm to 20 μm) by using the transfer method from the peeled body described above. . Therefore, when an external stress is applied to the interlayer connecting material 23, the interlayer connecting material 23 can be moved so as to bend, and the lower end portion of the interlayer connecting material 23 and the metal film 5 of the other semiconductor device 21b It is possible to improve the joint reliability by reducing the load applied to the joint portion. Note that the number of semiconductor devices to be stacked is not limited to two and may be more than that.

［第６の実施の形態］
次に本発明の第６の実施形態について説明する。なお、上記第１の実施形態と同じ構成部分には同一の符号を付しその詳細な説明は省略する。 [Sixth Embodiment]
Next, a sixth embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and the detailed description is abbreviate | omitted.

図１Ａ〜図２Ｇまでは上記第１の実施形態と同様にして進められ、その後、図１２、図１３に示す工程が行われる。   1A to 2G are performed in the same manner as in the first embodiment, and then the steps shown in FIGS. 12 and 13 are performed.

（図１２Ａの工程）
絶縁樹脂材８に部分的に接続孔をあけた後その接続孔内を導電材２２で充填する。接続孔は例えばドリルやレーザなどで、金属膜５に達するように絶縁樹脂材８の厚さ方向にあけられる。導電材２２は例えば剥離体を給電体としためっき法にて形成される。 (Step of FIG. 12A)
After the connection hole is partially formed in the insulating resin material 8, the connection hole is filled with the conductive material 22. The connection hole is opened in the thickness direction of the insulating resin material 8 so as to reach the metal film 5 with, for example, a drill or a laser. The conductive material 22 is formed by, for example, a plating method using a peeled body as a power feeding body.

（図１２Ｂの工程）
上記図１２Ａで得られる積層体に、上記図１Ａ〜図２Ｆと同工程にて得られるまだ絶縁樹脂材でモールドする前の積層体を貼り合わせる。これにより、導電材２２は両積層体の金属膜５どうしを接続し、両積層体の導体パターン４どうしが導電材２２を介して電気的に接続される。また、図１２Ａで得られる積層体に形成された絶縁樹脂材８は半硬化状態であり、よってその絶縁樹脂材８中に他の積層体の半導体チップ６が埋め込まれる。 (Step of FIG. 12B)
The laminated body obtained in the same step as in FIGS. 1A to 2F is bonded to the laminated body obtained in FIG. 12A before being molded with the insulating resin material. Thereby, the conductive material 22 connects the metal films 5 of both stacked bodies, and the conductor patterns 4 of both stacked bodies are electrically connected via the conductive material 22. Further, the insulating resin material 8 formed in the laminated body obtained in FIG. 12A is in a semi-cured state, and therefore the semiconductor chip 6 of another laminated body is embedded in the insulating resin material 8.

（図１２Ｃの工程）
絶縁樹脂材８を本硬化させた後、上記第１の実施形態と同様にして、両面に形成されたそれぞれの支持体１及び剥離層２を剥離する。 (Step of FIG. 12C)
After the insulating resin material 8 is fully cured, the support 1 and the release layer 2 formed on both surfaces are peeled in the same manner as in the first embodiment.

（図１２Ｄの工程）
上記工程で外部に露出された両面それぞれの導体パターン４の表面に、上記第１の実施形態と同様にして、金属膜９を形成する。これにより、絶縁樹脂材８内に２個の半導体チップ６が収められ、且つ絶縁樹脂材８の両面側に、半導体チップ６に形成された電極パッドのピッチを拡大した電極を取り出せる。なお、半導体チップ６は２個に限らずそれ以上であってもよい。 (Step of FIG. 12D)
In the same manner as in the first embodiment, the metal film 9 is formed on the surfaces of the conductive patterns 4 on both sides exposed to the outside in the above process. As a result, two semiconductor chips 6 are accommodated in the insulating resin material 8, and electrodes on which the pitch of electrode pads formed on the semiconductor chip 6 is enlarged can be taken out on both surface sides of the insulating resin material 8. The number of semiconductor chips 6 is not limited to two and may be more than that.

以上、本発明の実施の形態について説明したが、勿論、本発明はこれに限定されることなく、本発明の技術的思想に基づいて種々の変形が可能である。   The embodiment of the present invention has been described above. Of course, the present invention is not limited to this, and various modifications can be made based on the technical idea of the present invention.

フリップチップ方式の実装形態において、半導体チップ６の全てを絶縁樹脂材８で覆うことに限らず、図７に示すように、半導体チップ６の下方の空間に部分的に絶縁樹脂材８を流し込んで、少なくとも半導体チップ６と導体パターン４との接続を担う導電性バンプ７の周囲が絶縁樹脂材８で覆われるようにすればよい。   In the flip chip type mounting form, not only the entire semiconductor chip 6 is covered with the insulating resin material 8, but the insulating resin material 8 is partially poured into the space below the semiconductor chip 6 as shown in FIG. At least the periphery of the conductive bump 7 responsible for the connection between the semiconductor chip 6 and the conductor pattern 4 may be covered with the insulating resin material 8.

また、フリップチップ方式の実装形態において、導体パターン４が半導体チップ６の平面寸法より広がるファンアウト型に限らず、図８に示すように導体パターン４が半導体チップ６の平面寸法内に収まるファンイン型の半導体チップ１７としてもよい。   Further, in the flip chip type mounting form, the fan pattern is not limited to the fan-out type in which the conductor pattern 4 is wider than the planar dimension of the semiconductor chip 6, but the fan pattern in which the conductor pattern 4 is within the planar dimension of the semiconductor chip 6 as shown in FIG. A semiconductor chip 17 of a mold may be used.

また、ワイヤボンディング方式の実装形態において、図９に示すように、半導体チップ６ａの上に他の半導体チップ６ｂが例えばダイボンディングペーストで接合された半導体装置１８としてもよい。もちろん、半導体チップは２個に限らずそれ以上を積層させてもよい。   Further, in the wire bonding type mounting form, as shown in FIG. 9, a semiconductor device 18 in which another semiconductor chip 6b is bonded onto the semiconductor chip 6a by, for example, a die bonding paste may be used. Of course, the number of semiconductor chips is not limited to two, and more semiconductor chips may be stacked.

また、支持体１としては、金属に限らず、ガラスや半導体ウェーハなどであってもよい。この場合、その支持体に無電解めっき法あるいはスパッタリング法にて、例えばＮｉ層、（Ｎｉ−Ｐ）層、Ｃｒ層などを剥離層２として形成する。   Further, the support 1 is not limited to a metal, and may be glass or a semiconductor wafer. In this case, for example, a Ni layer, a (Ni—P) layer, a Cr layer, or the like is formed as the release layer 2 on the support by electroless plating or sputtering.

また、剥離層２としては、上記実施形態に示す構成に限らず、例えば、Ｃｒ層１層で構成したり、あるいはＮｉ層１層で構成したり、あるいはＣｒ層と（Ｎｉ−Ｃｒ）層との２層構造、Ｃｒ層とＮｉ層との２層構造であってもよい。   Further, the release layer 2 is not limited to the configuration shown in the above-described embodiment. For example, the release layer 2 may be composed of one Cr layer, one Ni layer, or a Cr layer and a (Ni—Cr) layer. Or a two-layer structure of a Cr layer and a Ni layer.

本発明の第１の実施形態に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. 図１に続く工程を示す断面図である。FIG. 2 is a cross-sectional view showing a step that follows FIG. 1. 図２に続く工程を示す断面図である。FIG. 3 is a cross-sectional view showing a step that follows FIG. 2. 本発明の第２の実施形態に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. 図４に続く工程を示す断面図である。FIG. 5 is a cross-sectional view showing a step that follows FIG. 4. 本発明の第３の実施形態に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. 変形例による半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device by a modification. 他変形例による半導体装置の断面図である。It is sectional drawing of the semiconductor device by another modification. 更なる他変形例による半導体装置の断面図である。It is sectional drawing of the semiconductor device by another another modification. 本発明の第４の実施形態に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 4th Embodiment of this invention. 本発明の第５の実施形態に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 5th Embodiment of this invention. 本発明の第６の実施形態に係る半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 6th Embodiment of this invention. 図１２に続く工程を示す断面図である。FIG. 13 is a cross-sectional view showing a step that follows FIG. 12.

符号の説明Explanation of symbols

１…支持体、１ａ…層間接続材、２…剥離層、３…めっきレジスト、４…導体パターン、６…半導体チップ、６ａ，６ｂ…半導体チップ、８…絶縁樹脂材、１１…半導体装置、１２…半導体装置、１４…エッチングレジスト、１５…導体パターン、１７…半導体装置、１８…半導体装置、２０，２０ａ，２０ｂ…半導体装置、２１，２１ａ，２１ｂ…半導体装置、   DESCRIPTION OF SYMBOLS 1 ... Support body, 1a ... Interlayer connection material, 2 ... Release layer, 3 ... Plating resist, 4 ... Conductor pattern, 6 ... Semiconductor chip, 6a, 6b ... Semiconductor chip, 8 ... Insulating resin material, 11 ... Semiconductor device, 12 ... Semiconductor device, 14 ... Etching resist, 15 ... Conductor pattern, 17 ... Semiconductor device, 18 ... Semiconductor device, 20, 20a, 20b ... Semiconductor device, 21, 21a, 21b ... Semiconductor device,

Claims (7)

剥離体から転写された導体パターンの、前記剥離体との剥離面の反対面に半導体チップが接合され、前記導体パターン間及び少なくとも前記導体パターンと前記半導体チップとの接合部が絶縁樹脂材で覆われている
ことを特徴とする半導体装置。 A semiconductor chip is bonded to the surface of the conductor pattern transferred from the peeling body opposite to the peeling surface from the peeling body, and an insulating resin material covers between the conductor patterns and at least a bonding portion between the conductor pattern and the semiconductor chip. A semiconductor device characterized by that. 前記導体パターンは、導電性の前記剥離体にパターンめっきされて形成されためっき膜である
ことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein the conductor pattern is a plating film formed by pattern plating on the conductive peeling body. 剥離体から転写された導体パターンの、前記剥離体との剥離面の反対面に半導体チップが接合され、前記導体パターン間及び少なくとも前記導体パターンと前記半導体チップとの接合部が絶縁樹脂材で覆われてなる複数の半導体装置が積層され、互いの前記導体パターンどうしが層間接続材を介して電気的に接続されている
ことを特徴とする半導体装置。 A semiconductor chip is bonded to the surface of the conductor pattern transferred from the peeling body opposite to the peeling surface from the peeling body, and an insulating resin material covers between the conductor patterns and at least a bonding portion between the conductor pattern and the semiconductor chip. A semiconductor device, wherein a plurality of separated semiconductor devices are stacked, and the conductor patterns are electrically connected to each other through an interlayer connecting material. 前記層間接続材は、前記導体パターンから剥離されずに残された前記剥離体の一部である
ことを特徴とする請求項３に記載の半導体装置。 The semiconductor device according to claim 3, wherein the interlayer connection material is a part of the peeled body left without being peeled from the conductor pattern. 剥離体の一表面に導体パターンを形成する工程と、
前記導体パターンに半導体チップを接合する工程と、
前記導体パターン間を埋め、且つ少なくとも前記導体パターンと前記半導体チップとの接合部を覆うように前記剥離体の前記一表面の上に絶縁樹脂材を形成する工程と、
前記剥離体を前記導体パターンから剥離して、前記導体パターンの前記半導体チップとの接合面の反対面を露出させる工程とを有する
ことを特徴とする半導体装置の製造方法。 Forming a conductor pattern on one surface of the peeled body;
Bonding a semiconductor chip to the conductor pattern;
Forming an insulating resin material on the one surface of the peeled body so as to fill between the conductor patterns and cover at least a joint portion between the conductor pattern and the semiconductor chip;
And a step of peeling the peeled body from the conductor pattern to expose a surface opposite to the joint surface of the conductor pattern with the semiconductor chip. 前記導体パターンを導電性の前記剥離体にパターンめっきにて形成する
ことを特徴とする請求項５に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5, wherein the conductive pattern is formed on the conductive peeling body by pattern plating. 前記剥離体をその一部を残して前記導体パターンから剥離し、前記導体パターンに残された前記剥離体の前記一部を外部接続端子として用いる
ことを特徴とする請求項５に記載の半導体装置の製造方法。
6. The semiconductor device according to claim 5, wherein the peeling body is peeled off from the conductor pattern, leaving a part of the peeling body, and the part of the peeling body left on the conductor pattern is used as an external connection terminal. Manufacturing method.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011198977A (en) * 2010-03-19 2011-10-06 Sumitomo Metal Mining Co Ltd Manufacturing method of semiconductor device
JP2014116632A (en) * 2014-02-05 2014-06-26 Sh Materials Co Ltd Semiconductor device manufacturing method
WO2014174925A1 (en) * 2013-04-24 2014-10-30 Ｓｈマテリアル株式会社 Method for producing substrate for mounting semiconductor element
CN108695270A (en) * 2017-03-29 2018-10-23 艾普凌科有限公司 Resin molded semiconductor device and its manufacturing method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011198977A (en) * 2010-03-19 2011-10-06 Sumitomo Metal Mining Co Ltd Manufacturing method of semiconductor device
WO2014174925A1 (en) * 2013-04-24 2014-10-30 Ｓｈマテリアル株式会社 Method for producing substrate for mounting semiconductor element
JP2014216431A (en) * 2013-04-24 2014-11-17 Ｓｈマテリアル株式会社 Method of measuring substrate for mounting semiconductor element
KR20160002682A (en) 2013-04-24 2016-01-08 에스에이치 메테리얼스 코퍼레이션 리미티드 Method for producing substrate for mounting semiconductor element
US9870930B2 (en) 2013-04-24 2018-01-16 Sh Materials Co., Ltd. Method for producing substrate for mounting semiconductor element
JP2014116632A (en) * 2014-02-05 2014-06-26 Sh Materials Co Ltd Semiconductor device manufacturing method
CN108695270A (en) * 2017-03-29 2018-10-23 艾普凌科有限公司 Resin molded semiconductor device and its manufacturing method
JP2018170377A (en) * 2017-03-29 2018-11-01 エイブリック株式会社 Resin-sealed semiconductor device and manufacturing method thereof

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