JP2005026568A - Semiconductor circuit device - Google Patents

Semiconductor circuit device Download PDF

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Publication number
JP2005026568A
JP2005026568A JP2003192178A JP2003192178A JP2005026568A JP 2005026568 A JP2005026568 A JP 2005026568A JP 2003192178 A JP2003192178 A JP 2003192178A JP 2003192178 A JP2003192178 A JP 2003192178A JP 2005026568 A JP2005026568 A JP 2005026568A
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Prior art keywords
input
output
output pad
spare
circuit device
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Yoshinobu Ueda
吉伸 植田
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2003192178A priority Critical patent/JP2005026568A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
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    • H01L2924/11—Device type
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit device which can effectively use a once-developed flash memory by previously arranging preliminary input/output pads and by only adding a metal wiring layer. <P>SOLUTION: In the semiconductor circuit device having the input/output pads, preliminary input/output pads are arranged on a dead space 204 in a position region of input/output pads 102a. Since a mask formation cost is reduced and the number of diffusion steps is reduced by making possible to switch input/output arrangements, a development schedule can be shortened. Switching between the input/output pads 102a and the preliminary input/output pads is enabled by using a single wiring layer or contact layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路に関し、特に、最初に用いられた入出力パッドに代えて用いるための予備の入出力パッドを予め備えた半導体集積回路に関するものである。
【０００２】
【従来の技術】
従来は、半導体集積回路の開発において、予めトランジスタ、抵抗、コンデンサ等の予備素子を機能ブロック内のデッドスペースに配置はするが、配線は接続せず、回路の部分に間違いがあった場合にメタル配線をつなぎ替えることにより、回路の間違いの修復を行っていた（例えば、特許文献１参照）。
【０００３】
【特許文献１】
特開２００２−２０３９０３（第１−６頁、第１図）
【０００４】
【発明が解決しようとする課題】
近年の半導体集積回路の代表であるシステムＬＳＩには、種々の機能ブロックが搭載されており、その中にはマイコンおよびフラッシュメモリが別々のＬＳＩで生成され、図１に示すように、それらを圧着した形で１つのシステムＬＳＩを構成されている。このような技術を以下システム・イン・パッケージと呼ぶ。図１において、１０１はマイコンチップ、１０２はフラッシュチップ、１０３はマイコンとフラッシュメモリ間を接続するワイヤ、１０４はマイコンとリードフレーム間を接続するワイヤ、１０５はリードフレームである。
【０００５】
このシステム・イン・パッケージにおいても例えば先に述べた通り、マイコンおよびフラッシュメモリのそれぞれのＬＳＩには予備素子が配置されており、回路の不具合をメタル配線で修正を行っているがこれらの予備素子は回路の機能修正を目的としている。
【０００６】
このような予備素子では、例えばシステム・イン・パッケージにおいて次に述べる場合等においては役割を果たすことができない。
【０００７】
システム・イン・パッケージでは例えば図１の場合はマイコンからフラッシュメモリのデータを読み出す場合、入出力パッド、ワイヤーを介して行わなければならない。この場合入出力パッドの配置によりワイヤー長が長くなるなど設計規約違反を起こすため、入出力パッドの配置には十分注意を払う必要がある。
【０００８】
しかしながら、通常マイコンは内蔵ＲＯＭ、回路機能削減等の展開品種を開発し、この場合に一度開発したフラッシュメモリを流用してシステム・イン・パッケージを組み上げようとした場合にワイヤー長等の規約違反になってしまう。
【０００９】
上述した従来の予備素子は、回路の機能修正を目的としたもので、このような状態を想定したものではないため、メタル配線層のみで修正を行うことは困難であり、全ての層を修正するなど開発期間・開発コストなど無駄が発生するという問題がある。
【００１０】
本発明は、このような問題を解決するために成されたものであり、予め予備の入出力パッドを配置し、メタル配線層の追加のみで一度開発したフラッシュメモリを有効に使用することができる半導体回路装置を提供することを目的とする。
【００１１】
【課題を解決するための手段】
請求項１記載の半導体集積回路装置は、入出力パッドを有する半導体回路装置であって、入出力パッドの位置領域の空き領域に予備の入出力パッドを配置したことを特徴とするものである。
【００１２】
請求項１記載の半導体集積回路装置によれば、入出力パッドの位置領域の空き領域に予備の入出力パッドを配置したため、入出力配置パッド位置の変更時に予備の入出力パッドを利用することにより、マスク設計完了後に発生する入出力パッド位置の変更に対応することができ、例えばメタル配線層のみで一度開発したフラッシュメモリを有効に使用することができる。したがって、ある入出力パッド位置の変更を行う場合には、予め予備に配置した入出力パッド、予め施した配線を使用することにより、修正時にはメタル配線の工程から作業を開始すればよく、その開発期間とコストを大幅に削減することが可能である。
【００１３】
請求項２記載の半導体集積回路装置は、請求項１において、入出力パッドを接続している配線層に交差して予備の入出力パッドを接続してる予備の配線層を引出したものである。
【００１４】
請求項２記載の半導体集積回路装置によれば、請求項１と同様のほか、入出力パッドと予備の入出力パッドとの切り替えを１つのコンタクト層で行うことができコスト削減になる。
【００１５】
請求項３記載の半導体集積回路装置は、請求項１において、入出力パッドを接続している配線層上であって予備の入出力パッドの近辺にコンタクト層を設けたものである。
【００１６】
請求項３記載の半導体集積回路装置によれば、請求項１と同様な効果のほか、入出力パッドと予備の入出力パッドとの切り替えを、予備の入出力パッドに接続される１つの配線層で行うことができコスト削減になる。
【００１７】
【発明の実施の形態】
この発明の第１の実施の形態を図１から図３により説明する。図１に示したように、別に生成されたマイコンチップ１０１およびフラッシュチップ１０２をシステム・イン・パッケージにより１つのシステムＬＳＩにする場合には、ＬＳＩのサイズが変更されるマイコンチップ１０１が上側にくることが多い。この場合にフラッシュチップ１０２には図２に示すように、空き領域であるデッドスペース２０４が多くできるため、入出力パッド位置領域のデッドスペース２０４に予備の入出力パッドを配置しておく。
【００１８】
このようにすることによって、サイズが異なるマイコンチップ１０１側の入出力パッド１０１ａとワイヤー可能なフラッシュチップ１０２側の入出力パッド１０２ａを選択し、配線することができる。例えば図３の場合に置いては、フラッシュメモリ３０１と接続される入出力セル３０２に位置する入出力パッド１０２ａでも、予備の入出力セル３０３、３０４に位置する入出力パッド１０２ａでも自由に選択し、メタル配線層３０５〜３０９で接続することができ、コスト削減になる。３０５はアルミ配線（第２配線層）、３０６はアルミ配線（第１配線層と第２配線層のコンタクト層）、３０７はアルミ配線（第１配線層）、３０８はアルミ配線（第１配線層と第２配線層のコンタクト層）、３０９はアルミ配線（第２配線層）である。この回路修正対応用の予備の入出力パッドは予めマスクの入出力パッド位置領域の空き領域に配置されることにより実現できる。
【００１９】
このように、入出力配置の切り替えを可能にすることにより、マイコン展開品種の開発におけるマスク生成費用の抑制ないし拡散工程の削減により日程短縮を図ることが可能となる。
【００２０】
この発明の第２の実施の形態を図４により説明する。近年の集積度増大に伴う、メタル配線層数の増加においては第１の実施の形態のような変更を行った場合、全てのメタル配線層を修正すればコストが膨大になってしまう。
【００２１】
したがって、本発明は上述した予備入出力パッドを予め配置しておき、さらに予め配線を施すことにより、修正するメタル配線層の数を削減する。
【００２２】
例えば、図４の場合においては、第１の実施の形態のようにフラッシュメモリ３０１に接続されている入出力パッド３０２を予備の入出力セル３０３あるいは３０４にも接続することができるようにするには、フラッシュメモリ３０１から入出力セル３０２の入出力パッド１０２ａを接続しているアルミ配線（第１メタル配線）３０７上に予備のアルミ配線（第２メタル配線）４１０、４１１を引き出しておく。アルミ配線３０７とアルミ配線４１０、４１１は層が異なるためショートはしない。このようにしておけば、予備の入出力セル３０３、３０４の入出力パッド１０２ａへ配置を変更したい場合にアルミ配線層３０７と予め引き出しておいた予備のアルミ配線４１０、４１１が交差する部分に両者を接続するコンタクト層（図示せず）を配置し、もとに接続されていたコンタクト層３０８を外せば入出力パッド１０２ａの配置を１枚のコンタクト層で切り替えることができる。
【００２３】
この発明の第３の実施の形態を図５により説明する。図５の場合において、第１の実施の形態のようにフラッシュメモリ３０１に接続されている入出力セル３０２の入出力パッド１０２ａを予備の入出力セル３０３あるいは３０４の入出力パッド１０２ａにも接続することができるようにするには、フラッシュメモリ３０１から入出力セル３０２の入出力パッド１０２ａを接続しているメタル配線３０７上の入出力パッド３０３、３０４と同一Ｙ軸上の近辺にコンタクト層５０８、５０９を予め施しておく。このようにしておけば、入出力パッド３０３、３０４への配置を変更したい場合に、それぞれの入出力パッド３０３、３０４からメタル配線を引き出し、もとに接続されていた入出力パッド１０２ａからのメタル配線３０９を削除すれば、１枚のメタル配線層で切り替えることができる。
【００２４】
従来は、このようなマイコンの展開品種の開発に併せて、フラッシュメモリのＬＳＩも再度開発し直しており、この場合多くのマスクを作成する必要があり、マスク生成のコストがかかり、また拡散工程をすべてやり直すという日程遅延の弊害も出てくる。今回の発明のような対策をしておけば、チップサイズの異なる展開品種の開発は、アルミ配線層の１層あるいは、コンタクト層の１層で切り替えが可能となり、マスク生成費用も抑えることができ拡散工程も上位層からの拡散になり、製品出荷の日程が早くなるという効果がある。
【００２５】
【発明の効果】
請求項１記載の半導体集積回路装置によれば、入出力パッドの位置領域の空き領域に予備の入出力パッドを配置したため、入出力配置パッド位置の変更時に予備の入出力パッドを利用することにより、マスク設計完了後に発生する入出力パッド位置の変更に対応することができ、例えばメタル配線層のみで一度開発したフラッシュメモリを有効に使用することができる。したがって、ある入出力パッド位置の変更を行う場合には、予め予備に配置した入出力パッド、予め施した配線を使用することにより、修正時にはメタル配線の工程から作業を開始すればよく、その開発期間とコストを大幅に削減することが可能である。
【００２６】
請求項２記載の半導体集積回路装置によれば、請求項１と同様のほか、入出力パッドと予備の入出力パッドとの切り替えを１つのコンタクト層で行うことができコスト削減になる。
【００２７】
請求項３記載の半導体集積回路装置によれば、請求項１と同様な効果のほか、入出力パッドと予備の入出力パッドとの切り替えを、予備の入出力パッドに接続される１つの配線層で行うことができコスト削減になる。
【図面の簡単な説明】
【図１】この発明の第１の実施の形態のシステム・イン・パッケージの断面図を示している。
【図２】パッケージを外した状態でのＬＳＩの上面図を示している。
【図３】フラッシュメモリのＬＳＩにおける入出力パッドの拡大図を示している。
【図４】第２の実施の形態におけるフラッシュメモリのＬＳＩにおける入出力パッドの拡大図を示している。
【図５】第３の実施の形態におけるフラッシュメモリのＬＳＩにおける入出力パッドの拡大図を示している。
【符号の説明】
１０１ マイコンチップ
１０１ａ 入出力パッド
１０２ フラッシュメモリチップ
１０３ ワイヤ
１０４ ワイヤ
１０５ リードフレーム
２０４ デッドスペース
３０１ フラッシュメモリ
３０２ 入出力セル
３０３ 予備の入出力セル
３０４ 予備の入出力セル
３０５ アルミ配線
３０６ コンタクト層
３０７ アルミ配線
３０８ コンタクト層
３０９ アルミ配線
４１０、４１１ アルミ配線
５０８、５０９ コンタクト層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit provided with a spare input / output pad for use in place of the input / output pad used first.
[0002]
[Prior art]
Conventionally, in the development of semiconductor integrated circuits, spare elements such as transistors, resistors, capacitors, etc. are placed in the dead space in the functional block in advance, but the wiring is not connected, and there is an error in the circuit part. A circuit error is repaired by changing the wiring (see, for example, Patent Document 1).
[0003]
[Patent Document 1]
JP 2002-203903 (page 1-6, FIG. 1)
[0004]
[Problems to be solved by the invention]
A system LSI, which is a representative of recent semiconductor integrated circuits, is equipped with various functional blocks, in which a microcomputer and a flash memory are generated by separate LSIs, and they are crimped as shown in FIG. Thus, one system LSI is configured. Such a technique is hereinafter referred to as system-in-package. In FIG. 1, 101 is a microcomputer chip, 102 is a flash chip, 103 is a wire connecting the microcomputer and the flash memory, 104 is a wire connecting the microcomputer and the lead frame, and 105 is a lead frame.
[0005]
In this system-in-package as well, for example, as described above, spare elements are arranged in the LSIs of the microcomputer and the flash memory, and circuit defects are corrected by metal wiring. Is intended to modify the function of the circuit.
[0006]
Such a spare element cannot play a role in, for example, the following cases in a system-in-package.
[0007]
In the case of the system in package, for example, in the case of FIG. 1, when reading the data of the flash memory from the microcomputer, it must be performed via an input / output pad and a wire. In this case, it is necessary to pay sufficient attention to the arrangement of the input / output pads because the design rule is violated, for example, the wire length becomes longer due to the arrangement of the input / output pads.
[0008]
However, the microcomputer usually develops development types such as built-in ROM, circuit function reduction, etc. In this case, when trying to assemble the system in package by diverting the flash memory developed once, it violates the regulations such as wire length. turn into.
[0009]
The above-mentioned conventional spare elements are intended to correct the function of the circuit and are not intended for such a state. Therefore, it is difficult to correct only with the metal wiring layer, and all layers are corrected. There is a problem that waste such as development period and development cost occurs.
[0010]
The present invention has been made to solve such a problem, and it is possible to effectively use a flash memory that has been developed once only by adding spare input / output pads and adding a metal wiring layer. An object is to provide a semiconductor circuit device.
[0011]
[Means for Solving the Problems]
The semiconductor integrated circuit device according to claim 1 is a semiconductor circuit device having an input / output pad, wherein a spare input / output pad is arranged in an empty area in a position area of the input / output pad.
[0012]
According to the semiconductor integrated circuit device of the first aspect, since the spare input / output pad is arranged in the empty area of the position area of the input / output pad, the spare input / output pad is used when the input / output placement pad position is changed. Therefore, it is possible to cope with a change in the input / output pad position that occurs after the mask design is completed. For example, a flash memory that has been developed once with only a metal wiring layer can be used effectively. Therefore, when changing the position of a certain I / O pad, it is only necessary to start from the metal wiring process at the time of correction by using a pre-arranged I / O pad and a pre-arranged wiring. Time and cost can be greatly reduced.
[0013]
A semiconductor integrated circuit device according to a second aspect is the semiconductor integrated circuit device according to the first aspect, wherein a spare wiring layer connected to the spare input / output pad is drawn across the wiring layer to which the input / output pad is connected.
[0014]
According to the semiconductor integrated circuit device of the second aspect, in addition to the first aspect, the switching between the input / output pad and the spare input / output pad can be performed by one contact layer, thereby reducing the cost.
[0015]
A semiconductor integrated circuit device according to a third aspect is the semiconductor integrated circuit device according to the first aspect, wherein a contact layer is provided in the vicinity of the spare input / output pad on the wiring layer to which the input / output pad is connected.
[0016]
According to the semiconductor integrated circuit device of the third aspect, in addition to the same effect as that of the first aspect, one wiring layer connected to the spare input / output pad can be switched between the input / output pad and the spare input / output pad. Cost reduction.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, when the separately generated microcomputer chip 101 and flash chip 102 are made into one system LSI by the system in package, the microcomputer chip 101 whose LSI size is changed is on the upper side. There are many cases. In this case, as shown in FIG. 2, the flash chip 102 can have a lot of dead space 204 which is an empty area, and therefore spare input / output pads are arranged in the dead space 204 in the input / output pad position area.
[0018]
By doing so, it is possible to select and wire the input / output pads 101a on the microcomputer chip 101 side having different sizes and the input / output pads 102a on the flash chip 102 side that can be wired. For example, in the case of FIG. 3, the input / output pad 102a located in the input / output cell 302 connected to the flash memory 301 or the input / output pad 102a located in the spare input / output cells 303 and 304 can be freely selected. The metal wiring layers 305 to 309 can be connected, which reduces the cost. 305 is an aluminum wiring (second wiring layer), 306 is an aluminum wiring (contact layer between the first wiring layer and the second wiring layer), 307 is an aluminum wiring (first wiring layer), and 308 is an aluminum wiring (first wiring layer). 309 is an aluminum wiring (second wiring layer). This spare input / output pad for circuit correction can be realized by arranging it in advance in an empty area of the mask input / output pad position area.
[0019]
As described above, by enabling switching of the input / output arrangement, it is possible to reduce the schedule by suppressing mask generation costs in the development of the microcomputer development type or reducing the diffusion process.
[0020]
A second embodiment of the present invention will be described with reference to FIG. In the increase in the number of metal wiring layers accompanying the increase in the degree of integration in recent years, if changes are made as in the first embodiment, the cost becomes enormous if all the metal wiring layers are modified.
[0021]
Therefore, the present invention reduces the number of metal wiring layers to be corrected by arranging the preliminary input / output pads described above in advance and further providing wiring.
[0022]
For example, in the case of FIG. 4, the input / output pad 302 connected to the flash memory 301 can be connected to the spare input / output cell 303 or 304 as in the first embodiment. In this case, spare aluminum wirings (second metal wirings) 410 and 411 are drawn from the flash memory 301 onto the aluminum wiring (first metal wiring) 307 connecting the input / output pad 102a of the input / output cell 302. The aluminum wiring 307 and the aluminum wirings 410 and 411 are not short-circuited because of different layers. In this way, when it is desired to change the arrangement of the spare input / output cells 303 and 304 to the input / output pad 102a, the aluminum wiring layer 307 and the spare aluminum wirings 410 and 411 previously drawn out cross each other. By disposing a contact layer (not shown) for connecting, and removing the contact layer 308 that was originally connected, the arrangement of the input / output pad 102a can be switched by a single contact layer.
[0023]
A third embodiment of the present invention will be described with reference to FIG. In the case of FIG. 5, the input / output pad 102a of the input / output cell 302 connected to the flash memory 301 is also connected to the input / output pad 102a of the spare input / output cell 303 or 304 as in the first embodiment. In order to be able to do so, the contact layer 508 is formed in the vicinity of the same Y axis as the input / output pads 303 and 304 on the metal wiring 307 connecting the input / output pad 102a of the input / output cell 302 from the flash memory 301. 509 is applied in advance. In this way, when it is desired to change the arrangement of the input / output pads 303 and 304, the metal wiring is drawn from each of the input / output pads 303 and 304, and the metal from the input / output pad 102a that was originally connected is extracted. If the wiring 309 is deleted, switching can be performed with one metal wiring layer.
[0024]
In the past, along with the development of these types of microcomputers, flash memory LSIs have been re-developed. In this case, it is necessary to create many masks, which incurs the cost of mask generation and the diffusion process. The adverse effect of the schedule delay of redoing all will also come out. If measures such as the present invention are taken, development of development types with different chip sizes can be switched with one aluminum wiring layer or one contact layer, and mask generation costs can be reduced. The diffusion process is also diffusion from the upper layer, and there is an effect that the schedule of product shipment is accelerated.
[0025]
【The invention's effect】
According to the semiconductor integrated circuit device of the first aspect, since the spare input / output pad is arranged in the empty area of the position area of the input / output pad, the spare input / output pad is used when the input / output placement pad position is changed. Therefore, it is possible to cope with a change in the input / output pad position that occurs after the mask design is completed. For example, a flash memory that has been developed once with only a metal wiring layer can be used effectively. Therefore, when changing the position of a certain I / O pad, it is only necessary to start from the metal wiring process at the time of correction by using a pre-arranged I / O pad and a pre-arranged wiring. Time and cost can be greatly reduced.
[0026]
According to the semiconductor integrated circuit device of the second aspect, in addition to the first aspect, the switching between the input / output pad and the spare input / output pad can be performed by one contact layer, thereby reducing the cost.
[0027]
According to the semiconductor integrated circuit device of the third aspect, in addition to the same effect as that of the first aspect, one wiring layer connected to the spare input / output pad can be switched between the input / output pad and the spare input / output pad. Cost reduction.
[Brief description of the drawings]
FIG. 1 is a sectional view of a system in package according to a first embodiment of the present invention.
FIG. 2 shows a top view of the LSI with the package removed.
FIG. 3 shows an enlarged view of input / output pads in a flash memory LSI.
FIG. 4 shows an enlarged view of input / output pads in an LSI of a flash memory according to a second embodiment.
FIG. 5 shows an enlarged view of input / output pads in an LSI of a flash memory according to a third embodiment.
[Explanation of symbols]
101 microcomputer chip 101a input / output pad 102 flash memory chip 103 wire 104 wire 105 lead frame 204 dead space 301 flash memory 302 input / output cell 303 spare input / output cell 304 spare input / output cell 305 aluminum wiring 306 contact layer 307 aluminum wiring 308 Contact layer 309 Aluminum wiring 410, 411 Aluminum wiring 508, 509 Contact layer

Claims (3)

入出力パッドを有する半導体回路装置であって、前記入出力パッドの位置領域の空き領域に予備の入出力パッドを配置したことを特徴とする半導体回路装置。A semiconductor circuit device having an input / output pad, wherein a spare input / output pad is arranged in a vacant region in a position region of the input / output pad. 入出力パッドを接続している配線層に交差して予備の入出力パッドを接続してる予備の配線層を引出した請求項１記載の半導体回路装置。2. The semiconductor circuit device according to claim 1, wherein a spare wiring layer connected to the spare input / output pad is drawn across the wiring layer to which the input / output pad is connected. 入出力パッドを接続している配線層上であって予備の入出力パッドの近辺にコンタクト層を設けた請求項１記載の半導体回路装置。2. The semiconductor circuit device according to claim 1, wherein a contact layer is provided in the vicinity of the spare input / output pad on the wiring layer to which the input / output pad is connected.
JP2003192178A 2003-07-04 2003-07-04 Semiconductor circuit device Pending JP2005026568A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103378125A (en) * 2012-04-16 2013-10-30 乐金显示有限公司 Organic light emitting display device and reworking method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103378125A (en) * 2012-04-16 2013-10-30 乐金显示有限公司 Organic light emitting display device and reworking method thereof
US9112176B2 (en) 2012-04-16 2015-08-18 Lg Display Co., Ltd. Organic light emitting display device and reworking method thereof

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