JP2005025440A - Information processing device and microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processing device and a microcomputer capable of reducing a load of a CPU. <P>SOLUTION: This information processing device is provided with an event count comparing means 1 counting the number of occurrences of events on an input pulse waveform taking a trailing edge as an event and generating a capture signal when the counted number matches a value previously set in a count comparing register 6, a capturing means 2 performing timer counting by a reference clock Pϕ and holding the value of the timer count in the generation of the capture signal in the capture register 8, and a computing means 3 performing shift computing on the value of the capture register 8 under a condition set in a shift condition setting register 9 and the addition computing of a value set in an addition value setting register 10. These means are mounted in the microcomputer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing apparatus and a microcomputer, and more particularly, to a technology effective when applied to an information processing apparatus that performs processing when performing asynchronous communication and a microcomputer equipped with the information processing apparatus.
[0002]
[Prior art]
According to a study by the present inventor, the following technologies can be considered as a microcomputer technology when performing asynchronous communication.
[0003]
For example, there are many microcomputers equipped with serial communication modules such as SCI (serial communication interface), UART (universal asynchronous transmitter transmitter), and USB (universal serial bus).
[0004]
When asynchronous serial communication is performed between these microcomputers, it is necessary to match both communication transfer rates as preprocessing. When matching the communication transfer rates, generally, a fixed value of the communication transfer rate is set for both serial communication modules in accordance with the definition of the communication protocol.
[0005]
However, there is a communication protocol that reads one communication transfer rate from the actual communication rate and corrects the communication transfer rate, such as a LIN (local interconnect network) communication protocol. In such a case, usually, necessary information is processed by software while using a timer module mounted on the microcomputer.
[0006]
[Problems to be solved by the invention]
By the way, as a result of examination by the present inventor regarding the technology of the microcomputer for performing the asynchronous communication as described above, the following has been clarified.
[0007]
In recent years, due to advances in network technology, there are a large number of communication protocols, and processing of these communication protocols is performed by, for example, a microcomputer. Such a microcomputer is required to perform complicated processing at high speed due to an increase in communication functions and communication target devices and an increase in communication transfer speed.
[0008]
Under such circumstances, for example, even in microcomputers for automobiles, with the digitization of automobile control, demands for implementing complex controls are increasing, and the burden on the control unit is increasing. In particular, software processing in a microcomputer or the like increases the load on the CPU due to signal processing from each sensor and increase in communication transfer speed between units. In the in-vehicle control unit, it is necessary to keep the operating frequency of the microcomputer as low as possible for the reason of reducing the influence of noise, and the load on the CPU becomes heavier.
[0009]
In order to perform more precise control, automobile control units share data by communication between units, and improve efficiency by dividing control. In addition, the interface tends to be standardized in order to reduce unit development man-hours and costs, and communication protocols such as CAN (controller area network) and LIN are now mainstream.
[0010]
Normally, the CAN communication processing is performed by mounting a dedicated module in the microcomputer, but the LIN communication processing is performed by combining existing built-in modules in the microcomputer and software processing. In the LIN communication processing, software processing intervention is indispensable, so the CPU load depends on the operating frequency of the microcomputer. However, as described above, since it is necessary to keep the operating frequency of the microcomputer low, in some cases, it may be difficult to realize all the functions defined in the LIN communication protocol.
[0011]
For example, in the LIN communication protocol, a function for measuring the pulse width of Synch-Feild (synchronization signal field that repeats “High” and “Low” inversion every 10 bits for 10 bits) and correcting the communication transfer rate is required. The In particular, this function requires operations such as division by software processing, so the load on the CPU is heavy, and depending on the CPU operating frequency and communication transfer speed value, it is difficult to realize this function. obtain.
[0012]
Therefore, an object of the present invention is to provide an information processing apparatus and a microcomputer that can reduce the load on the CPU.
[0013]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0014]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0015]
An information processing apparatus according to the present invention counts the number of occurrences of the event with respect to an input pulse waveform having a signal switching as an event, generates a start signal and a capture signal from the count value, and the capture signal Means for setting the value of the generated count; means for counting in synchronization with the reference clock, and means for holding the count value synchronized with the reference clock from when the start signal is generated to when the capture signal is generated And means for calculating the held count value.
[0016]
With this configuration, it is possible to measure the time required for inputting the set number of pulse edges to the input pulse waveform, and perform an operation based on the measured value.
[0017]
The information processing apparatus further includes means for generating a pulse waveform having a value obtained by the means for calculating as a pulse width. With this configuration, it is possible to generate a pulse waveform obtained by modifying the input pulse waveform.
[0018]
The calculating means in the information processing apparatus as described above has a function of setting the number of shifts and the shift direction in advance, and performing a shift calculation for the set number of shifts with respect to the held count value, A function of setting an addition value and adding the set addition value to the value after the shift calculation is included. With these functions, it is possible to calculate values to be set in the serial communication module.
[0019]
Further, the means for generating the pulse waveform in the information processing apparatus as described above performs a down-count in synchronization with the reference clock using the value obtained by the means for calculating as an initial value, and when an underflow occurs. Has a function of reloading the initial value and a function of generating a pulse waveform in which a signal is switched by using the underflow as a trigger. With these functions, it is possible to generate a pulse waveform having the pulse width as a value obtained by the means for calculating.
[0020]
In addition, these information processing apparatuses are particularly useful when applied to a microcomputer.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that in all the drawings for explaining the embodiments, the same members are denoted by the same reference numerals, and the repeated explanation thereof is omitted.
[0022]
FIG. 1 is a schematic diagram showing an example of the configuration and operation of an information processing apparatus according to an embodiment of the present invention.
[0023]
First, an example of the configuration of an information processing apparatus according to an embodiment of the present invention will be described with reference to FIG. The information processing apparatus shown in FIG. 1 includes, for example, an event count compare unit 1, a capture unit 2, a calculation unit 3, and the like.
[0024]
The event count compare means 1 includes, for example, an event counter 4, a control / status register 5, an event count compare register 6, and the like. In the control / status register 5, the type of edge used as an event can be set for the edge (signal switching) of the pulse waveform input from the input terminal. The edge type includes a rising edge, a falling edge, or both. The event counter 4 has a function of detecting an event set in the control / status register 5 and counting the number of occurrences of the event.
[0025]
The event count compare means 1 has a function of generating a start signal as an interrupt signal and a function of generating a capture signal as an interrupt signal. The start signal is generated when the value (event counter value) indicated by the event counter 4 becomes “1”. The capture signal is generated when a value is set in the event count compare register 6 in advance and the set value matches the event counter value.
[0026]
The event counter 4 has a function of setting the event counter value to “0” and a function of “1” after the capture signal is generated. The selection of “0” or “1” can be set by the control / status register 5 or the like, for example.
[0027]
The capture means 2 includes a timer counter 7 and a capture register 8. The timer counter 7 clears the value (timer counter value) indicated by the timer counter 7 by the start signal, and then starts a count operation synchronized with the reference clock Pφ, and the capture signal A function of holding the timer counter value in the capture register 8 is provided.
[0028]
The arithmetic means 3 includes a shift condition setting register 9 for setting the number of shifts and the shift direction, an addition value setting register 10, an arithmetic result storage register 11, and the like. The calculation means 3 takes in the value of the capture register 8, performs a right shift operation or a left shift operation for the number of shifts set in the shift condition setting register 9 with respect to the acquired value, and the shift calculation It has a function of adding the value set in the addition value setting register 10 to the subsequent value, a function of storing the value after the addition in the calculation result storage register 11, and the like. The value of the operation result storage register 11 can be transferred to a built-in I / O register or the like of another module by a DMAC (direct memory access) function or the like.
[0029]
Next, an example of the operation of the information processing apparatus illustrated in FIG. 1 will be described.
[0030]
When the information processing apparatus shown in FIG. 1 is used, for example, when reading or correction of the communication transfer speed is required by actual communication in a communication protocol or the like, processing such as reading or correction is performed by hardware. It can be carried out. Here, as an example, it is assumed that the present invention is applied to the LIN communication protocol.
[0031]
The LIN communication protocol is a standard for performing serial communication between a master node and a slave node, and a configuration outline when performing communication according to the standard is as shown in FIG. In FIG. 2, a master node and a plurality of slave nodes (1) to (3) are connected to a LIN bus via respective LIN bus I / F (interface) circuits.
[0032]
For example, a microcomputer is used for each of the slave nodes (1) to (3). The microcomputer includes an information processing apparatus as shown in FIG. 1 and serial communication such as SCI and UART. Assume that modules are installed.
[0033]
An outline of communication waveforms between the master node and the slave nodes (1) to (3) is as shown in FIG. FIG. 3 is a diagram showing a LIN communication waveform for explaining the operation of the information processing apparatus and microcomputer according to the embodiment of the present invention. FIG. 3A is a schematic diagram showing the communication waveform in one frame. FIGS. 4A and 4B are diagrams showing a part of (a) in detail, and FIG. 4C is a diagram showing another part of (a) in detail.
[0034]
The LIN communication waveform in FIG. 3A shows a header frame transmitted from the master node to the slave nodes (1) to (3) and any one of the slave nodes (1) to (3) to the master node. Consists of response frames that respond. As shown in FIG. 3B, the header frame includes a start field, a synchronization signal field, and an ID field. As shown in FIG. 3C, the response frame includes a plurality of data fields and a checksum field.
[0035]
In such a LIN communication waveform, the synchronization signal field in FIG. 3B is a repeated signal of “L” and “H” for 10 times. Then, the slave node microcomputer reads the communication transfer speed from 8 times (8-bit period) of these signals, and makes a setting reflecting the read value to the built-in serial communication module. There must be.
[0036]
Therefore, when reading these communication transfer rates and setting the serial communication module, the processing as shown in FIG. 4 is performed using the information processing apparatus as shown in FIG. 1 and a microcomputer equipped with the information processing apparatus. FIG. 4 is a diagram illustrating an example of a processing flow when the communication transfer rate in the LIN communication is read and reflected in the serial communication module in the information processing apparatus and microcomputer according to the embodiment of the present invention.
[0037]
Here, it is assumed that the process shown in FIG. 4 is performed using a microcomputer equipped with the information processing apparatus as shown in FIG. As a precondition, the operating frequency of the microcomputer is φ (MHz), and the reference clock Pφ of the capture means 2 in the information processing apparatus is operated at Pφ = φ / 8 (MHz). Under such conditions, the processing flow shown in FIG. 4 is as follows, for example.
[0038]
In S1, the user makes initial settings in advance in each register in the information processing apparatus of FIG. Here, the control / status register 5 designates the falling edge as an event, the event count compare register 6 is “4”, the shift condition setting register 9 is right shift designation and the number of shifts is “5”, and the addition value setting register 10 Set to −1. Also, the event counter value is cleared. 1 monitors the input terminal and waits for an event (falling edge of the input pulse waveform) to occur at this input terminal. Then, the process proceeds to S2.
[0039]
In S2, when the first event signal is generated at the input terminal, the event count compare means 1 adds +1 by the event counter 4 and outputs a start signal to the timer counter 7 of the capture means 2. The timer counter 7 receives the start signal, clears the timer counter value, and starts counting the reference clock Pφ. Then, the process proceeds to S3.
[0040]
In S3, the second to fourth event signals are input to the input terminal, and the event counter value is “4”. During this time, the timer counter 7 continues the counting operation. Then, the process proceeds to S4.
[0041]
In S4, when the fifth event is input to the input terminal, the event count compare means 1 generates the capture signal because the value of the event count compare register 6 matches the event counter value. . As a result, the timer counter value at this time is held in the capture register 8. That is, the timer counter value within the 8-bit period is held. Then, the process proceeds to S5.
[0042]
In S5, the serial communication module is set in accordance with the specification, reflecting the value of the capture register 8. That is, the calculation means 3 calculates the value of the capture register 8. One example will be described below.
[0043]
In general, a serial communication module has a specification for storing a value corresponding to a communication transfer speed to be set in a setting register (BRR: bit rate register) of a baud rate generation circuit built in the module. The value stored in the BRR varies depending on the specification of the serial communication module. As an example, assuming that the operating frequency of the microcomputer is φ (MHz) and the communication transfer speed to be set is TR (bits / second), for example, The following formula can be cited.
[0044]
BRR stored value = {φ × 10 ⁶ / (64 × 2 ^2n-1 × TR)}-1 (1)
Taking the case of this equation (1) as an example, the BRR stored value is calculated by the calculation means 3. In the equation (1), the communication transfer rate TR (bits / second) may be obtained by dividing 8 bits of the 8 bit period by the time required for the 8 bit period. That is, TR is expressed as follows using the value of the capture register 8 (CR value) and the reference clock frequency Pφ (= φ / 8) (MHz) in the capture means 2.
[0045]
TR = 8 / {CR value × 1 / (Pφ × 10 ⁶ )} = Φ × 10 ⁶ / CR value (2)
Therefore, substituting equation (2) into equation (1) yields:
[0046]
BRR stored value = {CR value / (64 × 2 ^2n-1 )}-1 (3)
The value of n is an integer value determined by the clock used by the baud rate generation circuit, but here n = 0. Then, the BRR stored value has a CR value of 32 (= 2 ⁵ ) And -1 added to it.
[0047]
That is, the arithmetic means 3 shifts the value (CR value) of the capture register 8 to the right by the setting value of the shift condition setting register 9 in S1 five times, and the addition value setting register 10 in S1. The value to be set in the serial communication module can be directly calculated by adding −1 by “−1”. For serial communication modules of other specifications, it is generally considered that the value set in the serial communication module can be directly calculated by the shift operation and the addition operation as in the case of Expression (1). .
[0048]
By the way, in the conventional technology which is the premise of the present invention, the reading of the communication transfer speed and the calculation of the value set in the serial communication module as described above are performed using software processing everywhere. Was common. For example, in the past, the capture function of the timer module has been used, but the event occurrence count in S2 to S4, the processing for holding in the capture register 8, and the serial communication module in S5 are set. It was necessary to calculate the value by software processing.
[0049]
However, as the communication transfer speed increases, the necessity for shortening the software processing time and the necessity for reducing the CPU load due to the software processing will arise. In particular, in semiconductor products for automobiles, it is common to keep the CPU operating frequency as low as possible by taking measures against noise and low power consumption. Therefore, it is more difficult to reduce the software processing time and the CPU load as described above. Situation.
[0050]
Further, for example, in the case of FIG. 3B as an example, when there is almost no wait time between the synchronization signal field and the ID field that reflects the synchronization signal field, the processing of S4 to S5 is performed on the serial communication module. Processing must be done very fast. When such processing is performed by software, the processing time may not be in time.
[0051]
Therefore, when the present invention is applied, the communication transfer rate can be read and the serial communication module can be set by hardware processing as described above. As a result, software processing is relaxed, the load on the CPU can be reduced, and higher communication transfer rates can be accommodated.
[0052]
Further, when the information processing apparatus as shown in FIG. 1 is applied, for example, it is possible to generate a multiplied waveform of the input waveform with respect to the input waveform whose pulse period varies. An example is shown in FIG.
[0053]
FIG. 5 is a schematic diagram illustrating an example of a configuration and an operation in which a counter waveform generation unit is added to the information processing apparatus in FIG. 1 in the information processing apparatus according to the embodiment of the present invention. As in the information processing apparatus shown in FIG. 1, for example, the information processing apparatus shown in FIG. 12) is added. Although omitted in FIG. 5, the event count compare means 1 includes a control / status register 5 and an event count compare register 6 as in FIG.
[0054]
The counter waveform generation means 12 is, for example, a down counter 13, a down counter initial value register 14, and although not explicitly shown in FIG. 5, output signal setting and resetting are triggered by the down counter underflow as a trigger. A circuit (for example, a circuit such as a T flip-flop) or the like. The other description regarding the configuration is the same as that of the information processing apparatus of FIG.
[0055]
Next, an example of the operation of the information processing apparatus in FIG. 5 will be described.
[0056]
Here, it is assumed that a pulse waveform from a crank angle sensor of an automobile is input and a multiplied waveform of a clock that is four times the input pulse waveform is generated. The pulse waveform from the crank angle sensor assumes that the pulse cycle varies as the input waveform in FIG. 5 as the automobile is accelerated or decelerated. Then, the information processing apparatus in FIG. 5 operates as follows, for example. Note that the basic operation up to the calculation means 3 is the same as that described in the information processing apparatus in FIG.
[0057]
(1) In the initial setting, both edges are designated as events in the control / status register 5, "1" is designated in the event count compare register 6, "2" is designated in the right shift designation and the number of shifts in the shift condition setting register 9, and the added value Set “0” in the setting register 10. Further, the event counter value is set to “1” after the capture signal is generated by setting the control / status register 5 or the like.
[0058]
(2) When a crank angle sensor pulse including fluctuation of the pulse cycle is input to the input terminal, the event count compare means 1 outputs a start signal when the first edge (falling edge in FIG. 5) occurs. The timer counter value is cleared and the count operation is started. Thereafter, according to the settings of the control / status register 5 and the event count compare register 6, the event count compare means 1 generates a capture signal for each rising and falling edge.
[0059]
Note that when the event counter value becomes “1”, a start signal is generated simultaneously with the capture signal. In this case, the capture signal is processed with priority. Then, the timer counter value is taken into the capture register 8 each time by these capture signals, and then the timer counter value is cleared and the count operation is started by the start signal.
[0060]
(3) Each time a value is taken into the capture register 8, the value in the capture register 8 is transferred to the computing means 3. The calculation means 3 stores the result of performing the right shift calculation (1/4 calculation) twice in the calculation result storage register 11 according to the set value of the shift condition setting register 9.
[0061]
(4) The value of the calculation result storage register 11 is transferred to the down counter initial value register 14 of the counter waveform generation means 12. The down counter 13 performs a counting operation using the value of the down counter initial value register 14 as an initial value, and generates an underflow when the value becomes zero. Thereafter, the down counter 13 is reloaded with the initial value. Then, the counter waveform generation means 12 generates a pulse waveform that switches (inverts) the signal with this underflow as a trigger, and outputs it from the output terminal.
[0062]
In this way, as shown in FIG. 5, it is possible to generate a multiplied waveform such that each pulse width having a different pulse period in the input waveform is divided into four equal parts. The multiplied waveform is generated after measuring the width of a certain pulse in the input waveform. For this reason, the relationship between the input waveform and the multiplied waveform shown in FIG. 5 is shifted by adding the time required for hardware processing in FIG. 5 to one pulse of the input waveform when the time axis is shown together. It becomes a relationship.
[0063]
Further, when the operation as shown in FIG. 5 becomes possible, for example, it is possible to easily and accurately control the ignition timing of the fuel injection of the automobile. An example of this is shown in FIG.
[0064]
FIG. 6 is a conceptual diagram showing an example of actual use using the information processing apparatus of FIG. 5 in the information processing apparatus of one embodiment of the present invention. In FIG. 6, for example, there is a disc-shaped crank angle sensor 15, and this crank angle sensor 15 has observation points fixed on the outer periphery and observed points at regular intervals on the inner periphery. .
[0065]
When such a crank angle sensor 15 rotates while accelerating and decelerating, a pulse waveform as shown in FIG. 6 is generated, for example, when the observation point receives a signal from the observed point. Here, the reference position for recognizing the crank angle is assumed to be the position of the pulse A. Under this assumption, for example, a case is assumed in which the fuel injection timing is set to the middle point of the pulse E.
[0066]
In such a case, as a general processing method, for example, a process that uses pulse A as the starting point of processing and counts as an event when pulses A to G, etc. occur, and a process that measures a pulse width such as pulse D A process of calculating a count value from the measured value to the expected midpoint of the pulse E and generating an ignition signal using a compare match function of a timer or the like can be considered. However, software processing is required for any of these processes, and high-speed software processing is indispensable particularly when the number of crank rotations increases.
[0067]
However, when the information processing apparatus shown in FIG. 5 is used, for example, a waveform in which the varying pulse width is always divided into four can be generated, and the midpoint is a position corresponding to the second half. Therefore, assuming that the pulse A is the starting point of processing, the ignition timing can be set with high accuracy simply by counting the number of occurrences of the edge of the multiplied waveform generated from that point. For example, in FIG. 6, the ignition signal may be generated at the 19th edge (falling edge) in the multiplied waveform, starting from the pulse A.
[0068]
As described above, when the information processing apparatus as shown in FIG. 5 is used, the software processing is only the processing for generating the ignition signal by counting the number of occurrences of the edge of the multiplied waveform. Therefore, software processing can be relaxed compared to the general processing method described above, and the load on the CPU can also be reduced. Note that the process of generating the ignition signal by counting the number of occurrences of the edge of the multiplied waveform is the same as the event count compare means 1 in the information processing apparatus of FIG. 5, and can also be performed by hardware processing.
[0069]
In this example, the multiplied waveform is generated for the input waveform whose pulse width varies. However, if the pulse width is constant, the divided waveform is generated as well as the multiplied waveform. Is also possible. Further, in the counter waveform generation means 12 of FIG. 5, the underflow by the down counter 13 is used, but it can also be realized by, for example, a compare match by an up counter.
[0070]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0071]
For example, the operation of the information processing apparatus as shown in FIG. 1 has been described by taking LIN communication as an example, but of course, the present invention is not limited to this. Widely applicable. Further, for example, the information processing apparatus as shown in FIG. 1 can be mounted not only on the microcomputer but also on a communication controller product.
[0072]
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0073]
(1) An information processing apparatus and a microcomputer capable of reading a communication transfer rate and setting a serial communication module by hardware processing can be realized.
[0074]
(2) It is possible to realize an information processing apparatus and a microcomputer capable of generating a multiplied waveform of an input waveform by hardware processing for an input waveform whose pulse period varies.
[0075]
(3) The above (2) makes it possible to easily and accurately control the ignition timing of the fuel injection of the automobile.
[0076]
(4) Due to the above (1) and (2), the software processing is relaxed and the load on the CPU can be reduced. This makes it possible to cope with higher speed operations.
[0077]
【The invention's effect】
An information processing apparatus and a microcomputer that can reduce the CPU load can be realized by hardware processing.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing an example of the configuration and operation of an information processing apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing an outline of a configuration when communication is performed according to a LIN protocol for explaining an application example and an operation example in the information processing apparatus and the microcomputer according to the embodiment of the present invention.
FIG. 3 is a diagram showing a LIN communication waveform for explaining an operation example in the information processing apparatus and the microcomputer according to the embodiment of the present invention, and (a) shows the communication waveform in one frame. Schematic, (b) is a diagram showing in detail a part of (a), (c) is a diagram showing in detail another part of (a).
FIG. 4 is a diagram illustrating an example of a processing flow when a communication transfer rate in LIN communication is read and reflected in a serial communication module in the information processing apparatus and the microcomputer according to the embodiment of this invention.
5 is a schematic diagram illustrating an example of a configuration and an operation in which a counter waveform generation unit is added to the information processing apparatus of FIG. 1 in the information processing apparatus according to the embodiment of the present invention.
6 is a conceptual diagram showing an example of actual use using the information processing apparatus of FIG. 5 in the information processing apparatus of an embodiment of the present invention.
[Explanation of symbols]
1 Event count compare method
2 Capture means
3 Calculation means
4 Event counter
5 Control / status register
6 Event count compare register
7 Timer counter
8 Capture register
9 Shift condition setting register
10 Addition value setting register
11 Operation result storage register
12 Counter waveform generation means
13 Down counter
14 Down counter initial value register
15 Crank angle sensor

Claims (5)

A means for counting the number of occurrences of the event with respect to an input pulse waveform having a signal switching as an event, and generating a start signal and a capture signal from the count value;
Means for setting a count value for generating the capture signal;
Means for counting in synchronization with a reference clock, and holding a count value synchronized with the reference clock from when the start signal is generated to when the capture signal is generated;
An information processing apparatus comprising: means for calculating the held count value. The information processing apparatus according to claim 1,
The information processing apparatus further comprises means for generating a pulse waveform whose pulse width is a value obtained by the means for calculating. The information processing apparatus according to claim 1, wherein
The means for calculating is
A function of setting the number of shifts and the shift direction in advance, and performing a shift operation for the set number of shifts with respect to the held count value;
An information processing apparatus comprising: a function of setting an addition value in advance and adding the set addition value to the value after the shift calculation. An information processing apparatus according to claim 2 or 3,
The means for generating the pulse waveform includes:
A value obtained by the means for calculating is used as an initial value, down-counting synchronized with the reference clock is performed, and when an underflow occurs, a function of reloading the initial value;
And a function of generating a pulse waveform in which a signal is switched by using the underflow as a trigger. A microcomputer comprising the information processing apparatus according to claim 1.

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