JPH083775B2 - Power-on reset device - Google Patents

Description

DETAILED DESCRIPTION [Outline] When a reset signal and a clock input are provided, and the reset signal is enabled, the device is connected to a device having a phase correction function of an internal clock with respect to the clock input. Multiple to initialize the clock phase,
Or, regarding a power-on reset device at the time of power-on to one device, initialization of a clock phase between one or a plurality of devices is performed even when the power is turned on, and an influence of disturbance of an internal clock of the device is exerted. Reset A until the reference clock is stably supplied.
And a second means for releasing the reset A after the reference clock is stably supplied, and a third means for starting a reset C by a reset signal synchronized with the reference clock after a predetermined time. Means and, further, fourth means for releasing the reset C after a fixed time is provided, and after the inside of the device is initialized by the reset A by the first means and the second means, The phase of the internal clock of each device is initialized by the reset B by the means 3 and the fourth means.

[Industrial applications]

The present invention is connected to a device having a reset signal and a clock input, and having a function of correcting the phase of the internal clock with respect to the clock input when the reset signal is enabled, and initializing the phase of the clock inside the device by inputting the reset signal. The present invention relates to a reset device when power is turned on for a plurality of or one device to be converted.

With the recent remarkable progress in semiconductor technology, the internal clock speed of devices such as central processing units (CPU) has improved. In order to perform high-speed data transfer between the devices, the device speed must be increased. It is necessary to match the phases of the clocks between them and perform data transfer by clock synchronization.

Therefore, there is a need for a power-on reset device that can effectively initialize the clock phase between devices, including when the power is turned on.

[Problems to be Solved by Conventional Techniques and Inventions]

FIG. 3 is a diagram for explaining a conventional power-on reset method, in which (a) shows an example of system configuration, (b) shows an example of conventional reset method, and (c) shows an operation time chart. Shows.

Conventionally, as shown in FIG. 1A, it is known that the same clock is supplied from an external oscillator 1 to a plurality of devices 2 so that the plurality of devices 2 communicate in clock synchronization. .

Further, in order to match the phases of the internal clocks of the plurality of devices 2, a method is known in which a reset signal synchronized with the clock is externally supplied and the release timing (T) of the reset signal is used. .
{Refer to the figures (b) and (c)} However, if an attempt is made to initialize the phase of the internal clock of the device 2 by releasing the reset signal, the reset is released as is clear from the operation time chart of (c). At this time, the internal clock may be disturbed (for example, due to the decrease in the clock width shown by the slanted line in FIG. 6C, the clock may be less than the operating specification of the logic circuit in the device 2). There are problems such as malfunctions and the inability to execute self-diagnosis of devices after reset release.

As a measure to solve the above problem, if the phase of the internal clock of the device 2 is initialized at the start of reset (assertion), even if the internal clock is disturbed by the initialization of the clock, the internal clock is disturbed during the reset period. Therefore, the malfunction of the device 2 can be prevented, but at the time of power-on when the clock from the external oscillator 1 cannot be stably supplied, since the power supply is unstable, the internal clock can be initialized accurately. There was a problem that I could not do it.

In view of the above-mentioned conventional drawbacks, the present invention provides a power-on reset device for initializing an internal clock phase by starting (asserting) a reset signal, or a power-on reset device at the time of power-on of one device. Initialize (phase matching) the clock phase and secure the clock width to eliminate the malfunction in one device, even when the power is turned on, without the influence of the disturbance of the internal clock of the device. It is an object of the present invention to provide a power-on reset device capable of performing the above.

[Means for solving the problem]

FIG. 1 is a diagram for explaining the principle of the power-on reset method of the present invention.

The above problem is solved by the power-on reset device configured as follows.

A plurality of devices that have a reset signal and a clock input, and are connected to a device that has a function of correcting the internal clock phase with respect to the clock input when the reset signal is enabled, and initialize the internal clock phase by starting the reset signal, or A power-on reset device at the time of power-on for one device, which comprises a first means for continuing reset A until the reference clock is stably supplied, and the reset A after stable supply of the reference clock. Means for releasing (B), third means for starting (C) the reset C synchronized with the reference clock after a fixed time, and further releasing (D) the reset C after a fixed time. A fourth means is provided to initialize the inside of the device by the reset A by the first means and the second means, and then the third means and the fourth means.
When the reset C is started (C) by the above means, the phase of the internal clock of each device is initialized.

[Action]

That is, according to the present invention, in a power-on reset device at the time of power-on for a plurality of or one device which initializes an internal clock phase by starting a reset signal, for example, a power-on detection is performed by an external oscillator. A circuit and a reset signal generation circuit are provided. However, each circuit is for obtaining a reset signal in synchronization with the reference clock, and does not necessarily have to be the same element and may be different elements.

Then, a plurality of devices, for example, devices A and B (see FIG. 3A), detect the reset start time from the reset signal generating circuit and initialize the phase of the internal clock.

Therefore, the reset signal generating circuit (A) keeps resetting each device by the reset A until the reference clock supplied from the clock oscillator is stably supplied, and performs internal initialization (for example, register Class reset, control flip-flops (FF) set initial values, etc.).

(B) When the reference clock becomes stable, the reset A is released once.

(C) After a certain period of time, the reset C is started again by the reset C synchronized with the reference clock. Each device detects the reset C and initializes the phase of the internal clock in the stable state. At this time, the internal clock may be disturbed, but since the device is being reset, it does not lead to a malfunction of the device.

(D) Further, after a certain period of time, the reset C is released.

Initialization of the phase of the internal clock will be described with reference to FIG. That is, "Initialization of internal clock phase"
Is to correct (initialize) the internal clock so that the phase relationship between the reference clock and the internal clock in each device is a fixed combination.

The above details will be described with reference to FIG. In FIG.
Indicates a reference clock, is an internal clock, and is a reset signal from the outside.

Then, based on the reference clock from the power-on reset device of the present invention and the reset signal, the logical condition for generating and correcting the internal clock is, as shown in the figure, the “0” condition of the reset signal and the It is assumed that it is generated with the “0” condition of the internal clock.

FIG. 4 (a) shows a case where no correction is made, and as shown in the figure, the internal clock has no disturbance and the reset signal from the outside, the reference clock,
The relationship with the internal clock is maintained under the predetermined combination condition shown.

However, in the case of FIG. 4 (b), the phase relationship between the reference clock and the internal clock is shifted by one cycle compared with the case of FIG. 4 (a). Therefore, in the internal clock correction circuit in each device, the above logical condition is not satisfied at the start of the second reset, so that the generation of the internal clock shown by the dotted line is suppressed and the internal clock is generated at the timing shown in the figure. And the phase relationship between the reference clock, the internal clock, and the reset signal when the reset signal from the outside is released is adjusted to the same condition as in the case without correction in FIG. 4 (a). You can

At this time, since the clock phase is corrected in synchronization with the reference clock, the internal clock width does not decrease as described in the prior art of FIG. 3, and even in the case of a single device, With the decrease of the internal clock width,
A malfunction of the device can be suppressed.

It goes without saying that the above correction circuit is only an example and is not limited to this method. The internal clock initialization means does not indicate the essence of the power-on reset device of the present invention, and the power-on reset device of the present invention exceeds the range of the circuit shown in FIG. 2 (a). Absent.

Since the operation is performed in this way, the clock phase between a plurality of devices can be initialized by a relatively simple circuit, and malfunctions due to the reduction of the clock width in the case of one device can be avoided, There is an effect that a system capable of high-speed communication between them can be constructed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings. The above-mentioned FIG. 1 is a diagram for explaining the principle of the power-on reset system of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention, in which (a) shows the clock for each device. FIG. 6B shows an example of the configuration of an external oscillator for supplying and resetting, and FIG. 9B is an operation time chart when the present invention is implemented. Each device is reset twice (specifically, the first time is the reference clock). Reset A asynchronously to the second, reset C synchronized to the reference clock the second time to reset C the second time
Means for enabling each device to detect the start signal of and to initialize the phase of the internal clock are necessary means for implementing the present invention. Note that the same reference numerals indicate the same object throughout the drawings.

Hereinafter, the power-on reset device of the present invention will be described with reference to FIG. 2 while referring to FIG.

First, in the external oscillator 1 shown in FIG. 3 (a), the time from the power-on to the stabilization of the reference clock output from the oscillator 11 is determined by the resistor (R) and the capacitor (C). Generate a signal to be compensated with a constant,
The signal is generated in the waveform shaping circuit 14 for a period of "on" until it becomes stable, and the signal is ORed.
A reset signal is output to each device 2 via 16 to reset the internal state of each device 2 and prevent the device 2 from outputting an erroneous signal to the outside.

Is the above reference clock, flip-flop (FF)
The clock divided by 1/2 is input to the next 4-bit binary counter 13, which is cleared by the output of the NOT circuit 15 until the above point reaches a certain level. Therefore, after the clear is released, the clock divided by 1/2 is counted for 8 cycles (clock '↑'
Signal) so that the counting is stopped at that point.

Then, the counter 13 outputs a signal that is'on 'from the time when the 1/2 frequency-divided clock is counted for 4 cycles to the time when it is counted for 8 cycles, and outputs this signal via the OR circuit 16 to each The device 2 is caused to function as a second reset signal.

If each device 2 detects the start point (c) of the reset C by the second reset signal and initializes the phase of the internal clock (see FIG. 4), the internal clock is disturbed. However, since it is in the reset period, the device 2 will not malfunction. Further, at this time, the clock supplied from the outside is also stable, so that the initialization of the clock does not become incorrect.

Thus, the present invention allows the initiation of the reset signal to
In a reset method at the time of power-on for a plurality of devices or one device for initializing the clock phase inside the device, a reference clock from an external oscillator and each device while the reference clock is unstable at the time of power-on etc. The first reset signal A for forcibly resetting and the second reset signal C for resetting each device again by the reset signal synchronized with the reference clock when the reference clock becomes stable. The feature is that each device detects the start point (C) of the reset C so that the phase of the internal clock in the stable state can be initialized.

〔The invention's effect〕

As described in detail above, the power-on reset device according to the present invention is a reset device at the time of power-on for a plurality of devices or one device that initializes an internal clock phase by starting a reset signal. Is maintained until a stable supply is obtained, first means for continuing the reset A, second means for releasing the reset A after the stable supply of the reference clock, and after a certain time, synchronized with the reference clock. A third means for restarting the reset C by a reset signal and a fourth means for canceling the reset C after a predetermined time are provided, and the reset A is performed by the first means and the second means. After the inside of the device is initialized, the phase of the internal clock of each device is initialized by the reset C by the third means and the fourth means. Therefore, the phase of the clock between one or a plurality of devices can be initialized with a relatively simple circuit even when the power is turned on without being affected by the disturbance of the internal clock of the device. There is an effect that a system capable of malfunction and high-speed communication between devices can be constructed.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the power-on reset system of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a diagram illustrating a conventional power-on reset system, and FIG. The figure is a diagram for explaining the initialization of the internal clock. In the drawing, 1 is an external oscillator, 11 is an oscillator, and 12 is a flip-flop (F
F), 13 is a 4-bit counter, 14 is a waveform shaping circuit, 15 is a negation circuit, 16 is a logical sum circuit, ~ are various signals, A to D are reset signals, and reset parts are respectively shown.

Claims (1)

[Claims] 1. A device having a reset signal and a clock input, which is connected to a device having a function of correcting a phase of an internal clock with respect to the clock input when the reset signal is enabled, and initializes an internal clock phase by starting the reset signal. A power-on reset device at the time of turning on the power to a plurality of or one device, which is the first means for continuing the reset A until the reference clock is stably supplied, and the reference clock is stably supplied. After that, a second means for releasing the reset A, a third means for starting a reset C by a reset signal synchronized with the reference clock after a fixed time, and a third means for releasing the reset C after a fixed time. 4 means are provided, and the reference A is provided by the reset A by the first means and the second means, and the third means and the fourth means. Power-on reset and wherein the initializing each device by a reset C by the reset signal synchronized with the lock.