JP2005020513A - Differential amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a high gain with respect to an ac input signal while suppressing the influence of a dc offset in a differential amplifier circuit. <P>SOLUTION: A first transistor M1 and a second transistor M2 constitute a differential pair being the input stage of this differential amplifier circuit, and both respective source terminals are connected to one end of a constant current source Ib. A third transistor M3 and a fourth transistor M4 constitute a current mirror circuit, and their drain terminals are respectively connected to the drain terminal of the first transistor and the drain terminal of the second transistor. An impedance circuit Z, wherein impedance becomes low with respect to a dc signal and impedance becomes high with respect to an ac signal, is connected between the drain terminal of the first transistor M1 and the drain terminals of the second transistor M2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a differential amplifier circuit.
[0002]
[Prior art]
Generally, a differential amplifier circuit includes a differential pair composed of two transistors, a constant current source for keeping a current flowing through the differential pair constant, and each transistor constituting the differential pair (hereinafter referred to as “differential pair”). A load resistance for converting a current fluctuation flowing through the transistor ") into a voltage signal.
[0003]
The operation of such a conventional differential amplifier circuit will be described. First, the first and second input signals constituting the differential input signal are respectively input to the control terminals of the two differential pair transistors. Since the current flowing through the differential pair (ie, the sum of the currents flowing through the two differential pair transistors) is kept constant by the constant current source, as a result, the current flowing through each of the differential pair transistors is the first input. It increases or decreases according to the voltage difference between the signal and the second input signal. The current fluctuation is converted into a voltage signal by a load resistance and output. That is, the differential amplifier circuit operates to amplify the voltage difference between the first input signal and the second input signal input to the differential pair.
[0004]
Here, when the mutual conductance of the differential pair transistor is gm and the resistance value of the load resistance is Rc, the gain A of the differential amplifier circuit is
A = gm · Rc
It becomes.
[0005]
Therefore, in order to obtain a high gain in the differential amplifier circuit, a high impedance load may be used. For example, a current mirror circuit is used as such a load. The current mirror circuit can be handled as a kind of constant current circuit having a very large internal impedance. Therefore, a very large gain can be obtained by using the current mirror circuit as a load of the differential amplifier circuit.
[0006]
Further, there is a configuration in which a differential amplifier circuit using a current mirror circuit as a load further includes a load resistor connected between collectors of two differential pair transistors (Patent Document 1). In this case, only the AC component theoretically flows through the load resistance, and the DC component is absorbed by the current mirror circuit. Therefore, only the AC component appears in the output signal without the DC component superimposed.
[0007]
[Patent Document 1]
JP-A-6-224657 (page 3-4, FIG. 1-5)
[0008]
[Problems to be solved by the invention]
In a differential amplifier circuit using a current mirror circuit as a load, a DC offset may occur due to a characteristic mismatch between two differential pair transistors or between two transistors constituting the current mirror circuit. In this case, since the gain of the differential amplifier circuit is very large, the DC offset is amplified with a high gain, causing a problem that the output voltage (output signal) does not become a desired bias point.
[0009]
For example, in the differential amplifier circuit of Patent Document 1, it is considered that if the resistance value of the load resistor connected between the collectors of the two differential pair transistors is reduced, the influence of the DC offset can be reduced. . However, since the load resistance is connected in parallel to the output impedance of the differential amplifier circuit, the circuit gain decreases when the resistance value is reduced.
[0010]
The present invention has been made to solve the above problems, and provides a differential amplifier circuit capable of obtaining a high gain for an AC input signal while suppressing the influence of a DC offset. For the purpose.
[0011]
[Means for Solving the Problems]
In the differential amplifier circuit according to the present invention, the differential pair including the first transistor and the second transistor, the first connection terminal of the first transistor, and the first connection terminal of the second transistor are connected to the same end. A current mirror circuit comprising a constant current source, a third transistor connected to the second connection terminal of the first transistor, and a fourth transistor connected to the second connection terminal of the second transistor; An impedance circuit is connected between the connection terminal and the second connection terminal of the second transistor, and has an impedance circuit having a low impedance for a DC signal and a high impedance for an AC signal.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
<Embodiment 1>
FIG. 1 is a circuit diagram showing a differential amplifier circuit according to Embodiment 1 of the present invention, and shows a differential input, single output type differential amplifier circuit. The first transistor M1 and the second transistor M2 which are nMOS transistors constitute a differential pair which is an input stage of the differential amplifier circuit. The gate terminals (control terminals) of the first transistor M1 and the second transistor M2 function as signal input terminals of the differential amplifier circuit. The source terminals (first connection terminals) of the first transistor M1 and the second transistor M2 are both connected to one end of the constant current source Ib. The other end of the constant current source Ib is grounded.
[0013]
The third transistor M3 and the fourth transistor M4 which are pMOS transistors have their gate terminals connected to each other to form a current mirror circuit. The drain terminal of the third transistor M3 is connected to the drain terminal (second connection terminal) of the first transistor, and the drain terminal of the fourth transistor M4 is connected to the drain terminal (second connection terminal) of the second transistor. The source terminals of the third transistor M3 and the fourth transistor M4 are both connected to the power supply Vdd. Thus, the differential amplifier circuit has a current mirror circuit composed of the third transistor M3 and the fourth transistor M4 as an active load.
[0014]
In the present invention, a predetermined impedance circuit Z is connected between the drain terminal of the first transistor M1 and the drain terminal of the second transistor M2. In the present embodiment, the impedance circuit Z operates so that the impedance is low for a DC signal and the impedance is high for an AC signal.
[0015]
The operation of the differential amplifier circuit according to this embodiment will be described. Differential input signals are respectively input to signal input terminals (gate terminals of the first transistor M1 and the second transistor M2) of the differential amplifier circuit. Here, among the differential input signals, the input to the gate terminal of the first transistor M1 is the first input signal Vin1, and the input to the gate terminal of the second transistor M2 is the second input signal Vin2.
[0016]
Since the constant current source Ib is connected to the differential pair, the current flowing through the differential pair, that is, the sum of the currents flowing through the first transistor M1 and the second transistor M2 is constant. Therefore, for example, when the current flowing through the first transistor M1 increases by ΔI, the current flowing through the second transistor M2 operates so as to decrease by ΔI. As a result, the current flowing through each of the first transistor M1 and the second transistor M2 increases or decreases according to a change in the voltage difference between the first input signal Vin1 and the second input signal Vin2. This increase / decrease in current changes the voltage at the drain terminal of each of the first transistor M1 and the second input signal Vin2, and an output signal Vout is obtained. That is, the differential amplifier circuit outputs the output signal Vout obtained by amplifying the fluctuation of the voltage difference between the first input signal Vin1 and the second input signal Vin2.
[0017]
In the present embodiment, the impedance circuit Z is connected in parallel to the output impedance of the differential amplifier circuit. As described above, the impedance circuit Z operates so as to have a low impedance with respect to a DC signal and a high impedance with respect to an AC signal. Therefore, the differential amplifier circuit has a gain with respect to a DC component. Is small and the gain is large for the AC component. That is, since the gain is small with respect to the DC offset, the output signal Vout is less susceptible to the DC offset. Further, a high gain can be obtained for the first input signal Vin1 and the second input signal Vin2 that change in an alternating manner. Therefore, it becomes easy to set the output signal Vout having a large gain to a desired bias point.
[0018]
An example of the impedance circuit Z according to the present embodiment is an inductor element. FIG. 2 is a diagram showing a specific example of the differential amplifier circuit according to the first embodiment, in which the impedance circuit Z in FIG. The operation of this circuit is the same as described above. When the impedance circuit Z is composed of the inductor element L, the DC gain is theoretically 0, so that it is not affected by the DC offset. As the frequency of the input signal increases, the impedance of the inductor element L increases and the gain of the differential amplifier circuit increases. Since an actual inductor element has a self-resonant frequency, it is conceivable that when the frequency of the input signal increases to some extent, the impedance value decreases and the gain of the differential amplifier circuit decreases. If it does not decrease, it does not depart from the gist of the present invention.
[0019]
In the above description, an example in which the differential pair and the current mirror circuit are configured by MOS transistors has been described. However, a bipolar transistor may be used instead. It is obvious that the differential pair can be composed of a pMOS transistor and the current mirror circuit can be composed of an nMOS transistor as opposed to the structure of FIGS. 1 and 2 (the same applies when using a bipolar transistor). In addition, each of the differential pair and the current mirror circuit may be composed of either an npn type transistor or a pnp type transistor). Further, as the current mirror circuit serving as a load, for example, a cascode current mirror circuit or the like other than those shown in FIGS. 1 and 2 may be used.
[0020]
<Embodiment 2>
The circuit configuration of the differential amplifier circuit according to the second embodiment is the same as that shown in FIG. However, the impedance circuit Z according to the present embodiment is a resonance circuit that has a low impedance for a DC signal and a high impedance for an AC signal in a predetermined frequency band. That is, the differential amplifier circuit has a small gain with respect to the DC component and a particularly large gain with respect to the AC component in a predetermined frequency band.
[0021]
Therefore, according to the present embodiment, the output signal Vout is not easily affected by the DC offset, and a high gain can be obtained for the first input signal Vin1 and the second input signal Vin2 in a predetermined frequency band. it can. Since the signal amplification operation in the differential amplifier circuit is the same as that of the first embodiment, description thereof is omitted here.
[0022]
Examples of the resonant circuit that is the impedance circuit Z according to the present embodiment include an inductor element and a capacitive element connected in parallel to each other. FIG. 3 is a diagram showing a specific example of the differential amplifier circuit according to the second embodiment, in which the impedance circuit Z in FIG. 1 is configured by an inductor element L1 and a capacitive element C1. The inductor element L1 and the capacitive element C1 are connected in parallel to each other to constitute a resonance circuit in which the impedance is increased at a specific resonance frequency.
[0023]
According to this configuration, the direct current gain is 0, so that it is not affected by the direct current offset. When the frequency of the input signal is the resonance frequency of the resonance circuit, the impedance of the resonance circuit increases and the gain of the differential amplifier circuit increases. Therefore, by adjusting the reactance of the inductor element L1 and the capacitance of the capacitive element C1, and setting the resonance frequency of the resonance circuit to the operating frequency band of the first input signal Vin1 and the second input signal Vin2, the influence of the DC offset is suppressed. On the other hand, a high gain can be obtained for the first input signal Vin1 and the second input signal Vin2. Therefore, it becomes easy to set the output signal Vout having a large gain as a desired bias point with respect to an input signal having a specific operating frequency.
[0024]
<Embodiment 3>
In order to increase the gain of the differential amplifier circuit, it is conceivable to cascade a plurality of differential amplifier circuits. When the conventional differential amplifier circuits are cascade-connected, the DC gain is further increased, and the influence of the DC offset appears more remarkably. Further, for example, when the differential amplification circuit of the inductor load is cascade-connected, the output node of each cascaded differential amplification circuit works as a power supply node, and the differential pair transistor of the input stage of the next-stage differential amplification circuit In some cases, a high voltage is applied to the differential pair transistor, and it is necessary to use a differential transistor having a high breakdown voltage.
[0025]
In the third embodiment, a differential amplifier circuit having a configuration in which a plurality of differential amplifier circuits of the first embodiment or the second embodiment are cascade-connected is proposed. That is, the differential amplifier circuit according to the present embodiment has a configuration as shown in FIG. In the figure, reference numerals A1 to A3 denote the differential amplifier circuits of the first embodiment or the second embodiment, respectively. 1 to 3, the output of the differential amplifier circuit has been described as a single output. However, when differential output is performed as in the differential amplifier circuits A1 and A2 of FIG. 4, the first transistor M1 and the second transistor An output signal is obtained from both drain terminals of the transistor M2 (that is, both ends of the impedance circuit Z become output nodes).
[0026]
According to the present embodiment, it is possible to obtain a differential amplifier circuit having higher gain than those of the first and second embodiments. Further, since each of the differential amplifiers A1, A2, and A3 has a small DC gain, the problem of increase in DC gain can be suppressed even if cascade connection is made. Further, since the loads of the differential amplifier circuits A1, A2 and A3 are current mirror circuits having high internal impedance, for example, the output nodes of the differential amplifier circuits A1 and A2 are input stage transistors (first stage differential amplifier circuits). It is appropriately biased by the gate-source voltage of one transistor M1 or second transistor M2). Therefore, the withstand voltage characteristic of the transistor in the input stage does not matter.
[0027]
Although FIG. 4 shows an example in which three differential amplifier circuits are cascade-connected, it goes without saying that the number of differential amplifier circuits cascade-connected in the present invention is not limited to three.
[0028]
【The invention's effect】
As described above, the differential amplifier circuit according to the present invention has a small gain for a DC signal and a large gain only for an AC signal. That is, since the gain is small with respect to the DC offset, the output is not easily affected by the DC offset. Further, a high gain can be obtained for an input signal that changes in an alternating manner. Therefore, it becomes easy to set an output signal having a large gain as a desired bias point. In addition, the differential amplifier circuit can be used in cascade connection, whereby a higher gain can be obtained.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a differential amplifier circuit according to a first embodiment.
FIG. 2 is a circuit diagram showing a specific example of a differential amplifier circuit according to the first embodiment;
FIG. 3 is a circuit diagram showing a specific example of a differential amplifier circuit according to a second embodiment.
FIG. 4 is a diagram illustrating a configuration of a differential amplifier circuit according to a third embodiment.
[Explanation of symbols]
M1 first transistor, M2 second transistor, M3 third transistor, M4 fourth transistor, Z impedance circuit, L, L1 inductor element, C1 capacitor element, Ib constant current source, Vdd power supply.

Claims (5)

A differential pair having a first transistor and a second transistor;
A constant current source in which the first connection terminal of the first transistor and the first connection terminal of the second transistor are connected to the same end;
A current mirror circuit having a third transistor connected to the second connection terminal of the first transistor and a fourth transistor connected to the second connection terminal of the second transistor;
An impedance circuit is connected between the second connection terminal of the first transistor and the second connection terminal of the second transistor, and has an impedance circuit having a higher impedance with respect to an AC signal than that with respect to a DC signal. Differential amplifier circuit. The differential amplifier circuit according to claim 1,
The differential amplifier circuit, wherein the impedance circuit includes an inductor element. The differential amplifier circuit according to claim 1,
The impedance circuit is:
A differential amplifier circuit characterized by being a resonant circuit that resonates with an AC signal in a predetermined frequency band. The differential amplifier circuit according to claim 3,
The resonant circuit includes an inductor element and a capacitor element connected in parallel to each other. 5. A differential amplifier circuit in which a plurality of differential amplifier circuits according to claim 1 are cascade-connected.

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