TWI623193B - Power amplifier circuit - Google Patents

Abstract

The power amplifier circuit includes: a power transistor receiving an input signal and outputting an output signal; and a variable impedance circuit coupled to the power transistor, wherein the equivalent impedance value of the variable impedance circuit is based on the input signal The variable impedance circuit includes an impedance control transistor and a first filter capacitor. The first end of the impedance control transistor is coupled to the power transistor, and the second end of the impedance control transistor is coupled. Connected to the first filter capacitor, the third end of the impedance control transistor receives a first control voltage, the first filter capacitor is coupled between the second end of the impedance control transistor and a ground terminal; a first wave packet detecting circuit coupled to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit; and a second wave packet detecting circuit coupled Connected to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit, the second wave packet detecting circuit comprising a protection resistor and an input a signal amplifying transistor, wherein a first end of the input signal amplifying transistor is coupled to the ground, and a second end of the input signal amplifying transistor is coupled to the protective resistor, and the input signal amplifying the transistor The three ends are coupled to the first filter capacitor and the second end of the impedance control transistor, and the protection resistor is coupled to the input signal and the input The second wave packet detecting circuit amplifies the input signal between the second end of the signal-amplifying transistor and inputs the second signal to the second end of the impedance control transistor.

Description

Power amplifier circuit

This case is about a power amplifier circuit.

In the wireless communication system, the power amplifier of the wireless transmitting end can amplify the RF signal (or high frequency signal or microwave signal) to be transmitted to a high power level, and transmit it to the wireless receiving end through the antenna and the transmission medium (for example, air). .

Power amplifiers are used in a wide range of applications, such as entertainment (remote control, remote control, remote control, etc.) or mobile communications (Global System for Mobile Communications (GSM), broadband code division) Wideband Code Division Multiple Access (W-CDMA), Long Term Evolution (LTE), Wireless Local Area Network (Wireless LAN, WLAN), military applications and space applications. In terms of power consumption, the power amplifier's power consumption in the system is one of the best. In terms of linearity, in wireless communication systems, power amplifiers are usually components with poor linearity, which are prone to distortion and even degrade transmission quality and correctness.

In the process of amplifying the signal by the power amplifier, the third-order distortion signal adjacent to the main signal may deteriorate the communication signal quality. Figure 1 shows a schematic diagram of signal distortion. As shown in the left sub-picture of Figure 1, if the main frequency phase used by the two users If they are far apart, they will not affect each other. However, as shown in the right sub-picture of Figure 1, if the two users use similar frequencies to transmit communication signals, their third-order distortion signals will affect each other and deteriorate the original communication quality.

Therefore, in order to maintain the quality of the communication signal, the receiving end can smoothly demodulate the signal, and avoid the process of transmitting the communication signal affecting other users, the specification of the transmission signal of the transmitting end is formulated in the communication standard. ACLR (Adjacent Channel Leakage Ratio) measures the degree of spectral interference to users outside the channel when the communication signal is distorted. At a certain frequency from the center frequency, the spectrum of the transmitting end is lower than the Spectral Mask. This requires the power amplifier of the transmitting end to have high linearity and reduce the phenomenon of spectral regrowth to avoid interference with signals of adjacent channels.

According to an embodiment of the present invention, a power amplifier circuit includes: a power transistor that receives an input signal and outputs an output signal; a variable impedance circuit coupled to the power transistor; the variable impedance circuit includes a An impedance control transistor, a first filter capacitor and a compensation resistor, wherein the first end of the compensation resistor is coupled to the power transistor, and the second end of the compensation resistor is coupled to one of the impedance control transistors One end of the impedance control transistor is coupled to the first filter capacitor, and the third terminal of the impedance control transistor receives a first control voltage, and the first filter capacitor is coupled to the impedance control a first wave packet detecting circuit coupled to the input signal and the variable impedance circuit, the first wave packet detecting circuit comprising a second filter capacitor and a Filter inductor, The second filter capacitor is coupled to the input signal, the filter inductor is coupled between the second end of the impedance control transistor and the second filter capacitor; and a second wave packet detection circuit is coupled to the The input signal and the variable impedance circuit, the second wave packet detecting circuit includes a protection resistor and an input signal amplifying transistor, and the first end of the input signal amplifying transistor is coupled to the ground, and the input signal is amplified. a second end of the transistor is coupled to the protection resistor, and a third end of the input signal amplifying transistor is coupled to the second end of the impedance control transistor, the protection resistor is coupled to the input signal and the The input signal amplifies between the second ends of the transistors.

According to an embodiment of the present invention, a power amplifier circuit includes: a power transistor receiving an input signal and outputting an output signal; and a variable impedance circuit coupled to the power transistor, the variable impedance circuit The equivalent impedance value is changed according to the input signal, the variable impedance circuit includes an impedance control transistor and a first filter capacitor, and the first end of the impedance control transistor is coupled to the power transistor, and the impedance control a second end of the transistor is coupled to the first filter capacitor, and a third end of the impedance control transistor receives a first control voltage, and the first filter capacitor is coupled to the second of the impedance control transistor Between the end and a ground; a first wave packet detecting circuit coupled to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit; and a second wave packet detecting circuit coupled to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit, the second wave packet inspection Protection circuit comprising a resistor and a transistor input signal amplifier, the signal amplifier one input transistor first terminal is coupled to the ground terminal, the input signal amplifying crystal a second end of the body is coupled to the protection resistor, and a third end of the input signal amplifying transistor is coupled to the first filter capacitor and the second end of the impedance control transistor, and the protection resistor is coupled to The input signal is coupled to the second end of the input signal amplifying transistor, and the second wave packet detecting circuit amplifies the input signal and inputs the second end of the impedance control transistor.

According to another embodiment of the present invention, a power amplifier circuit includes: a power transistor receiving an input signal and outputting an output signal; and a variable impedance circuit coupled to the power transistor, the variable impedance circuit An equivalent impedance value is changed according to the input signal, the variable impedance circuit includes an impedance control transistor and a first filter capacitor, and the first end of the impedance control transistor is coupled to the power transistor, the impedance The second end of the control transistor is coupled to the first filter capacitor, and the third end of the impedance control transistor receives a first control voltage, and the first filter capacitor is coupled to the first of the impedance control transistors a first wave packet detecting circuit coupled to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit, The first wave packet detecting circuit includes a filtering unit for extracting the input signal and providing the second end of the impedance control transistor of the variable impedance circuit; a second wave packet detecting circuit, Connected to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit, the second wave packet detecting circuit amplifying the input signal and inputting to the impedance control transistor The second end; and a control circuit coupled to the variable impedance circuit to control a current supplied to the power transistor by the variable impedance circuit.

In order to better understand the above and other aspects of the present invention, the following specific embodiments, together with the drawings, are described in detail below:

200‧‧‧Power amplifier circuit

210‧‧‧Variable impedance circuit

220‧‧‧First wave packet detection circuit

230‧‧‧ second wave packet detection circuit

240‧‧‧Control circuit

Q1‧‧‧Power transistor

260‧‧‧Input matching circuit

270‧‧‧Output matching circuit

V1-V3‧‧‧ control voltage

200A‧‧‧Power Amplifier Circuit

210A‧‧‧Variable Impedance Circuit

220A, 230A‧‧‧ wave packet detection circuit

240A‧‧‧Control circuit

R1-R3‧‧‧ resistance

M1-M3‧‧‧O crystal

CF1-CF2‧‧‧Filter Capacitor

CB1-CB3‧‧‧ bypass capacitor

L1-L2‧‧‧Inductance

410‧‧‧Power detection circuit

200B‧‧‧Power Amplifier Circuit

240B‧‧‧Control circuit

200C1, 200C2‧‧‧ power amplifier circuit

210C‧‧‧Variable Impedance Circuit

240C1, 240C2‧‧‧ control circuit

200D1, 200D2‧‧‧ power amplifier circuit

240D1, 240D2‧‧‧ control circuit

200E‧‧‧Power Amplifier Circuit

240E‧‧‧Control circuit

1010‧‧‧Inverter

1020‧‧‧ comparator

1030‧‧‧Voltage Converter

200F‧‧‧Power Amplifier Circuit

240F‧‧‧Control circuit

1110‧‧‧ Comparator

1120‧‧‧ finite state machine

200G, 200H, 200I‧‧‧ power amplifier circuit

210H, 210I‧‧‧Variable Impedance Circuit

Figure 1 shows a schematic diagram of signal distortion.

Fig. 2 is a functional block diagram showing a power amplifier circuit according to an embodiment of the present invention.

FIG. 3A and FIG. 3B respectively show schematic diagrams of the power amplifier circuit of the embodiment of the present invention under the small signal and the large signal.

Fig. 4 is a circuit block diagram showing a power amplifier circuit according to an embodiment of the present invention.

Fig. 5 is a circuit block diagram showing a power amplifier circuit according to an embodiment of the present invention.

Figure 6 shows a comparison of the performance of the second embodiment (Figs. 4 and 5) of the present case and the technique without the use of the present invention.

Figure 7 is a graph showing voltage, current and current of a transistor according to an embodiment of the present invention.

8A and 8B are circuit block diagrams showing a power amplifier circuit according to two embodiments of the present invention.

Figures 9A and 9B show circuit block diagrams of power amplifier circuits in accordance with two embodiments of the present invention.

Figure 10 is a circuit block diagram showing a power amplifier circuit in accordance with an embodiment of the present invention.

Figure 11 is a circuit block diagram showing a power amplifier circuit in accordance with an embodiment of the present invention.

Figure 12 is a circuit block diagram showing a power amplifier circuit in accordance with an embodiment of the present invention.

Figure 13 is a circuit block diagram showing a power amplifier circuit in accordance with an embodiment of the present invention.

Figure 14 is a circuit block diagram showing a power amplifier circuit in accordance with an embodiment of the present invention.

The technical terms of the present specification refer to the idioms in the technical field, and some of the terms are explained or defined in the specification, and the explanation of the terms is based on the description or definition of the specification. Various embodiments of the present disclosure each have one or more of the technical features. Those skilled in the art can selectively implement some or all of the technical features of any embodiment, or selectively combine some or all of the technical features of these embodiments, where possible.

Referring now to Figure 2, there is shown a functional block diagram of a power amplifier circuit in accordance with an embodiment of the present invention. As shown in FIG. 2, the power amplifier circuit 200 according to the embodiment of the present invention includes: a variable impedance circuit 210, a first wave packet detection circuit 220, a second wave packet detection circuit 230, a control circuit 240, and a power supply. Crystal Q1. Moreover, power amplifier circuit 200 in accordance with embodiments of the present invention may more selectively include input matching circuit 260 and output matching circuit 270. Variable impedance circuit 210, first and second wave packet detecting circuits 220 and 230, and control circuit 240 A dynamic bias circuit can be formed.

The variable impedance circuit 210 can increase its equivalent impedance value according to the power increase of the input signal IN. When the power of the input signal IN is small, the impedance value of the variable impedance circuit 210 is low. When the power of the input signal IN is large, the impedance value of the variable impedance circuit 210 is high. The details of the variable impedance circuit 210 will be additionally described below. The variable impedance circuit 210 allows the dynamic bias circuit of the embodiment of the present invention to have gain expansion and phase compression characteristics to compensate for gain compression and phase amplification of the power transistor. Expansion) and increase the linearity of the power amplifier circuit.

The first and second wave packet detecting circuits 220 and 230 can detect the phase and amplitude of the input signal IN to dynamically control the impedance value of the variable impedance circuit 210. When the input signal IN is a small signal, the second wave packet detecting circuit 230 can amplify the input signal IN and provide it to the variable impedance circuit 210 to allow the variable impedance circuit 210 to supply sufficient current to the power transistor Q1. When the input signal IN is a large signal, the operation of the second wave packet detecting circuit 230 alone may make it difficult for the variable impedance circuit 210 to supply sufficient current to the power transistor Q1. Therefore, when the input signal IN is a large signal, the first wave packet detecting circuit 220 captures the input signal IN and supplies it to the variable impedance circuit 210 to allow the variable impedance circuit 210 to supply sufficient current to the power transistor Q1. Details of the first and second wave packet detecting circuits 220 and 230 will be further described below. Through the first and second wave packet detecting circuits 220 and 230, the power amplifier circuit 200 of the embodiment of the present invention can make the power level of the input signal IN more sensitive.

Control circuit 240 can control variable impedance circuit 210 to provide power Current of transistor Q1. When the power amplifier circuit 200 of the embodiment of the present invention is in the high power mode, the control circuit 240 can control the variable impedance circuit 210 to supply a higher current to the power transistor Q1. When the power amplifier circuit 200 of the embodiment of the present invention is in the low power mode, the control circuit 240 can control the variable impedance circuit 210 to provide a lower current to the power transistor Q1. Therefore, the quiescent current and power consumption of the power amplifier circuit 200 of the embodiment of the present invention can be reduced.

The power transistor Q1 is, for example, a BJT (bipolar junction transistor) transistor. Power transistor Q1 has three terminals. One end (eg, a base) is coupled to the input signal IN, and the variable impedance circuit 210, and the other end (eg, an emitter) is coupled to the ground, and the other end (eg, A collector is coupled to the output signal OUT (eg, directly or through the output matching circuit 270). If the power amplifier circuit 200 of the embodiment of the present invention operates in a low power mode, the control circuit 240 can control the variable impedance circuit 210 to provide a low but sufficient current to the base of the power transistor Q1 to provide sufficient power transistor Q1. The linearity thus reduces the power consumption of the power amplifier circuit 200. In another embodiment, the power transistor Q1 may also be a field-effect transistor (FET), such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).

The input matching circuit 260 is used to match the input signal IN. The output matching circuit 270 is used to match the output signal OUT. The architecture of input matching circuit 260 and output matching circuit 270 and its operational details may be omitted herein.

In addition, in another possible embodiment of the present application, the control circuit 240 is also It can be a selective element. The power amplifier circuit with less control circuitry can still achieve high linearity and sensitivity to the power level of the input signal IN.

Referring now to FIG. 3A and FIG. 3B, a schematic diagram of the power amplifier circuit 200 of the embodiment of the present invention under the small signal and the large signal is respectively shown. As shown in FIG. 3A, when the input signal IN is a small signal, most of the input signal IN is fed to the variable impedance circuit 210, and a small portion of the input signal IN is fed to the power transistor Q1, so power The gain of the amplifier circuit 200 is small. As shown in FIG. 3B, when the input signal IN is a large signal, a small portion of the input signal IN is fed to the variable impedance circuit 210, and most of the input signal IN is fed to the power transistor Q1, so the power The gain of the amplifier circuit 200 is large.

Referring now to Figure 4, there is shown a block diagram of a power amplifier circuit 200A in accordance with an embodiment of the present invention. As shown in FIG. 4, the variable impedance circuit 210A includes a resistor R1 (also referred to as a compensation resistor), a transistor M1 (also referred to as an impedance control transistor), a first filter capacitor CF1, and a first bypass capacitor CB1. . The first wave packet detecting circuit 220A includes an inductor L1 (also referred to as a filter inductor) and a second filter capacitor CF2. The second wave packet detecting circuit 230A includes a transistor M3 (also referred to as an input signal amplifying transistor) and a resistor R2 (also referred to as a protective resistor). The control circuit 240A includes a transistor M2 (also referred to as a feedback control transistor), a second bypass capacitor CB2 and a third bypass capacitor CB3, a resistor R3 (also referred to as a feedback resistor), and a power detector. Circuit 410. Inductor L1 and capacitors CB1-CB3 are optional components. The transistors M1-M3 are, for example, BJT or FETs.

The resistor R1 is coupled between the power transistor Q1 and the transistor M1. The resistor R1 can thermally compensate the power transistor Q1 (so, the resistor R1 can also be referred to as a compensation resistor).

The base of the transistor M1 is coupled to the wave packet detecting circuits 220A and 230A, and the control circuit 240A. The emitter is coupled to the resistor R1, and the collector is coupled to the first bypass capacitor CB1 and the control voltage V1. The first filter capacitor CF1 is coupled between the base of the transistor M1 and the ground. The first filter capacitor CF1 can be used to filter the base current of the transistor M1. The first bypass capacitor CB1 is coupled between the collector of the transistor M1 and the ground.

The inductor L1 is coupled between the base of the transistor M1 and the second filter capacitor CF2. The second filter capacitor CF2 is coupled between the input terminal (eg, directly connected or through the input matching circuit 260) and the inductor L1. The inductor L1 and the second filter capacitor CF2 can form a filter unit, and the second filter capacitor CF2 can filter the input signal IN. For example, but not limited to, the inductor L1 and the second filter capacitor CF2 are designed to appropriately capture the amplitude information and phase information of the input signal IN, and feed the amplitude information and phase information of the input signal IN that is captured. Variable impedance circuit 210A.

The base of the transistor M3 is coupled to the input terminal (for example, directly connected or through the resistor R2 and/or the input matching circuit 260), the emitter is coupled to the ground, and the collector is coupled to the base of the transistor M1.

The resistor R2 is coupled between the input terminal (eg, directly connected or through the input matching circuit 260) and the base of the transistor M3. Resistor R2 protects transistor M3 (so resistor R2 can also be referred to as a protection resistor), avoiding large currents from burning transistor M3.

When the input signal IN is a small signal, a part of the input signal IN flows to the transistor M3 of the second wave packet detecting circuit 230A and the resistor R2, and conducts the crystal M3. That is, the transistor M3 of the second wave packet detecting circuit 230A amplifies the input signal IN (so, the transistor M3 can also be referred to as an input signal amplifying transistor), and feeds it to the base of the transistor M1 to allow the transistor M1 can supply enough current to power transistor Q1. The transistor M1 operates in a non-linear region.

When the input signal IN is a large signal, in addition to the transistor M3 providing the amplified input signal IN to the transistor M1, the input signal IN having a predetermined frequency can pass the inductance L1 of the first wave packet detecting circuit 220A and the second filter capacitor CF2. The feed is applied to the base of the transistor M1 to further increase the base voltage of the transistor M1 to provide more current to the power transistor Q1.

The base of the transistor M2 is coupled to the resistor R3, the emitter is coupled to the base of the transistor M1, and the collector is coupled to the second bypass capacitor CB2 and the control voltage V2. The second bypass capacitor CB2 is coupled between the collector of the transistor M2 and the ground. The third bypass capacitor CB3 is coupled between the base of the transistor M2 and the ground. The resistor R3 is coupled between the base of the transistor M2 and the power detecting circuit 410.

In FIG. 4, the base voltage of the control transistor M2 is controlled by the variable impedance circuit 210A, the first and second wave packet detecting circuits 220A and 230A, and the control circuit 240A to make the power transistor Q1 output highly linear. Power, and adaptive control of the current of the power transistor Q1. In this example, the control voltages V1, V2 are appropriately selected, and the base voltage of the control transistor M2 is fed back and forth by the power detecting circuit 410 to operate the transistors M1 and M2 in the nonlinear region. In addition, profit The input signal IN input to the power transistor Q1 is dynamically sensed by the second filter capacitor CF2 in series with the inductor L1 (first wave packet detecting circuit 220A) and the resistor R2 series transistor M3 (second wave packet detecting circuit 230A). Moreover, in this example, the current flowing through the transistor M3 is adaptively suppressed to thereby improve the adjacent channel power ratio (ACPR) of the power transistor Q1 at a high output power.

When the transistor M2 operates in a non-linear region, the transistor M2 can operate as a switching circuit. After the power detecting circuit 410 detects the output power of the power transistor Q1, the base voltage of the transistor M2 can be dynamically feedback controlled so that the power amplifier circuit is more sensitive to the input signal IN input to the power transistor Q1. When power transistor Q1 is operating in the low power region, transistor M1 provides a low quiescent current; when power transistor Q1 operates in the high power region, transistor M1 provides sufficient dynamic current.

Further, in Fig. 4, the memory effect of the power amplifier circuit of the embodiment of the present invention can be improved by appropriately designing the inductance value of the inductance L1. The so-called memory effect refers to the degree of symmetry between two third-order distortion signals on the adjacent sides of the main signal. The lower the memory effect, the more symmetric the two third-order distortion signals are.

Referring now to Figure 5, there is shown a circuit block diagram of a power amplifier circuit 200B in accordance with an embodiment of the present invention. Unlike the fourth figure, the control circuit 240B of the power amplifier circuit 200B of Fig. 5 does not include the power detecting circuit. In the control circuit 240B, the other end of the resistor R3 is coupled to the control voltage V3.

The operation of Fig. 5 is similar to Fig. 4, so the details thereof are omitted here.

Referring now to Figure 6, there is shown a comparison of the performance of the second embodiment (Figs. 4 and 5) of the present case and the technique without the use of the present invention. As shown in Fig. 6, in the high power region and the same linearity, the current consumption without the technique of the present invention is higher than the current consumption of the second embodiment (the fourth and fifth figures); and in the low power region. The quiescent current of the embodiment (200B) in Fig. 5 of this case is lower than the quiescent current without using the technology of the present invention, but the quiescent current of the embodiment (200A) of Fig. 4 is lower than that of the embodiment (200B) of Fig. 5 of the present case. Current. It can be seen from Fig. 6 that the second embodiment of the present invention can improve the current consumption in the high power region under the premise of the same linearity, and utilizes the feedback control of the power detection circuit (as in the fourth embodiment of the present case). , can further reduce the quiescent current in the low power zone.

Referring now to Figure 7, there is shown a graph of voltage V _CE , current I _C and current I _B of transistor M1 in accordance with an embodiment of the present invention, wherein voltage V _CE represents the voltage difference between the collector and the emitter, Current I _C represents the collector current and current I _B represents the base current. As can be seen from FIG. 7, the transistor M1 of the embodiment of the present invention can operate in the non-linear region such that the equivalent impedance of the transistor M1 changes (larges) as the input signal IN changes (larges).

Referring now to Figure 8A, there is shown a block diagram of a power amplifier circuit 200C1 in accordance with an embodiment of the present invention. As shown in FIG. 8A, the variable impedance circuit 210C includes a resistor R1, a transistor M1, and a first filter capacitor CF1. The control circuit 240C1 includes a resistor R3 and a power detection circuit 410. The resistor R3 is coupled between the base of the transistor M1 and the power detecting circuit 410. Figure 8A The operation is briefly described below.

The power detecting circuit 410 detects the output power of the power transistor Q1 to output a current to the resistor R3 to control the base of the transistor M1. For details of the operation of other components, reference may be made to the above embodiments, and will not be repeated here.

In another possible embodiment of the present invention, the power detecting circuit of the control circuit of FIG. 8A can be removed, as shown in FIG. 8B. That is, in the power amplifier circuit 200C2 of FIG. 8B, the control circuit 240C2 includes a resistor R3 coupled between the control voltage V3 and the base of the transistor M1. For details of the operation of this embodiment, reference may be made to the above embodiments, and the details are not described herein.

Referring now to Figure 9A, there is shown a circuit block diagram of a power amplifier circuit 200D1 in accordance with an embodiment of the present invention. As shown in FIG. 9A, the control circuit 240D1 includes an inductor L2 (also referred to as a feedback inductor) and a power detecting circuit 410. The inductor L2 is coupled between the base of the transistor M1 and the power detecting circuit 410. . The operation of Figure 9A is briefly described below.

The power detection circuit 410 detects the output power of the power transistor Q1 to output a current to the inductor L2, and controls the base of the transistor M1. For details of the operation of other components, reference may be made to the above embodiments, and will not be repeated here.

In another possible embodiment of the present invention, the power detecting circuit of the control circuit of FIG. 9A can be removed, as shown in FIG. 9B. That is, in the power amplifier circuit 200D2 of FIG. 9B, the control circuit 240D2 includes an inductor L2 coupled between the control voltage V3 and the base of the transistor M1. For details of the operation of this embodiment, reference may be made to the above embodiments, and the details are not described herein.

Referring now to Figure 10, there is shown a circuit block diagram of a power amplifier circuit 200E in accordance with an embodiment of the present invention. As shown in FIG. 10, the control circuit 240E includes a resistor R3, a transistor M2, a power detecting circuit 410, an inverter 1010, a comparator 1020, and a voltage converter 1030. The operation of Fig. 10 is as follows.

The power detection circuit 410 is coupled to the power transistor Q1 to detect the output power of the power transistor Q1 to output a detection signal to the inverter 1010. The inverter 1010 is coupled to the power detection circuit 410, and the detection signal of the power detection circuit 410 is inverted, and then output to the comparator 1020. The comparator 1020 is coupled to the inverter 1010 to compare the inverted detection signal with the reference voltage Vref to obtain a comparison result to the voltage converter 1030. The voltage converter 1030 is coupled to the comparator 1020 and the resistor R3, and converts the comparison result into a voltage signal. The voltage signal is fed through the resistor R3 to the base of the transistor M2 to further feedback control feeding to the transistor. The base current of M1.

The base of the transistor M2 is coupled to the resistor R3, the emitter is coupled to the second packet detecting circuit 230A, and the collector is coupled to the control voltage V2.

When the input signal IN is a small signal, the power detection circuit 410 detects the small output power of the power transistor Q1 to output a small detection voltage signal to the inverter 1010. The inverter 1010 inverts the small detection voltage signal of the power detection circuit 410 and outputs it to the comparator 1020. The comparator 1020 compares the inverted detection voltage signal with the reference voltage Vref to obtain a comparison result (low voltage level signal) to the voltage converter 1030. The voltage converter 1030 converts the comparison result (low voltage level signal) to be input to the base of the transistor M2 to control the degree of switching of the transistor M2. When the transistor M2 approaches a turn-off, the base current fed into the transistor M1 also decreases, at which time the low current required for the power transistor Q1 is provided. Therefore, the quiescent current consumption in the low power region can be reduced.

Conversely, when the input signal IN is a large signal, the power detecting circuit 410 detects the large output power of the power transistor Q1 to output a large detecting voltage signal to the inverter 1010. The inverter 1010 inverts the large detection voltage signal of the power detection circuit 410 and outputs it to the comparator 1020. The comparator 1020 compares the inverted detection voltage signal with the reference voltage Vref to obtain a comparison result (high voltage level signal) to the voltage converter 1030. The voltage converter 1030 converts the comparison result (high voltage level signal) to feedback control of the base current fed to the transistor M1. As such, the base current fed into the transistor M1 can be higher to provide the high current required for the power transistor Q1. Therefore, the linearity in the high power region can be improved.

For details of the operation of other components, reference may be made to the above embodiments, and will not be repeated here.

Referring now to Figure 11, a block diagram of a power amplifier circuit 200F in accordance with an embodiment of the present invention is shown. As shown in FIG. 1, the control circuit 240F includes a power detection circuit 410, a comparator 1110, and a Finite Stage Machine (FSM) 1120. The operation of Fig. 11 is briefly described below.

The power detection circuit 410 is coupled to the power transistor Q1 to detect the output power of the power transistor Q1 to output a detection signal to the comparator 1110. The comparator 1110 is coupled to the power detection circuit 410 to compare the detection signal with the reference voltage Vref to obtain a comparison result to the finite state machine 1120. Finite state machine 1120 is coupled to The comparator 1110 returns the base voltage of the control transistor M1 according to the comparison result.

In detail, when the input signal IN is a small signal, the power detecting circuit 410 detects the small output power of the power transistor Q1 to output a detection signal (for example, logic low) to the comparator 1110. The comparator 1110 compares the detection signal to the reference voltage Vref to obtain a comparison result (eg, a logic high) to the finite state machine 1120. The finite state machine 1120 retries the base voltage/base current of the control transistor M1 based on the comparison result (eg, logic high) to provide the small current required for the power transistor Q1. Therefore, the quiescent current consumption in the low power region can be reduced.

Conversely, when the input signal IN is a large signal, the power detection circuit 410 detects the large output power of the power transistor Q1 to output a detection signal (eg, logic high) to the comparator 1110. The comparator 1110 compares the detection signal to the reference voltage Vref to obtain a comparison result (eg, a logic low) to the finite state machine 1120. The finite state machine 1120 retries the base voltage/base current of the control transistor M1 according to the comparison result (for example, a logic low), so that the base voltage of the transistor M1 can be higher to provide the power transistor Q1. The high current required. Therefore, the linearity in the high power region can be improved.

For details of the operation of other components, reference may be made to the above embodiments, and will not be repeated here.

In other possible embodiments of the present invention, the output of the finite state machine 1120 may have more orders to control the base voltage/base current of the transistor M1 at different stages to achieve a more precise control effect.

Further, in the embodiments of FIGS. 8A to 11 , the variable impedance The circuit may further include a first bypass capacitor CB1 (as in Figures 4 and 5), which is also within the spirit of the present invention.

Fig. 12 is a circuit block diagram showing a power amplifier circuit 200G according to an embodiment of the present invention. The power amplifier circuit 200G includes a power transistor Q1 that receives the input signal IN and outputs an output signal OUT. The variable impedance circuit 210C is coupled to the power transistor Q1. The variable impedance circuit 210C includes an impedance control transistor M1. The first end of the compensating resistor R1 is coupled to the power transistor Q1, and the second end of the compensating resistor R1 is coupled to the first end of the impedance controlling transistor M1, and the impedance controlling transistor M1 is coupled to the capacitor R1 and the compensating resistor R1. The second end is coupled to the first filter capacitor CF1, and the third end of the impedance control transistor M1 receives the first control voltage V1. The first filter capacitor CF1 is coupled to the second end of the impedance control transistor M1 and the ground terminal. The operation and architecture of the first wave packet detection circuit 220A is coupled to the input signal IN and the variable impedance circuit 210C. The first wave packet detection circuit 220A includes a second filter capacitor CF2 and a filter inductor L1. The second filter capacitor CF2 is coupled to the input signal IN, and the filter inductor L1 is coupled between the second end of the impedance control transistor M1 and the second filter capacitor CF2. The operation and architecture can be understood by the above description; The second wave packet detecting circuit 230A is coupled to the input signal IN and the variable impedance circuit 210C. The second wave packet detecting circuit 230A includes a protection resistor R2 and an input signal amplifying transistor M3. The first end of the input signal amplifying transistor M3 is coupled. Connected to the ground terminal, the second end of the input signal amplifying transistor M3 is coupled to the protection resistor R2, and the third end of the input signal amplifying transistor M3 is coupled to the second end of the impedance control transistor M1, and the protection resistor R2 is coupled. Connected to the input signal IN and the input signal The operation and architecture between the second ends of the amplifying transistor M3 can be understood from the above description. The power amplifier circuit 200G may optionally include, for example, the input matching circuit, the output matching circuit, the control circuit, the first bypass capacitor, and/or other components of the above embodiment, and the operational details of the power amplifier circuit 200G may be described by the above embodiments. Understand that the details are omitted here.

Figure 13 is a circuit block diagram showing a power amplifier circuit 200H according to an embodiment of the present invention. The power amplifier circuit 200H includes a power transistor Q1, receives an input signal IN and outputs an output signal OUT. The variable impedance circuit 210H is coupled to a power transistor Q1. The variable impedance circuit includes an impedance control transistor M1 and a first filter. The first end of the impedance control transistor M1 is coupled to the power transistor Q1, and the second end of the impedance control transistor M1 is coupled to the first filter capacitor CF1 and the third of the input signal amplification transistor M3. The first receiving voltage V1 is coupled between the second end of the impedance control transistor M1 and a ground; the first wave packet detecting circuit 220 is coupled to the input signal IN and the variable The impedance circuit 210H detects the input signal IN to dynamically control the equivalent impedance value of the variable impedance circuit 210H, and its operation and architecture can be understood by the above description; and the second wave packet detection circuit 230A is coupled to the input signal IN and variable The impedance circuit 210H, the second wave packet detecting circuit 230A detects the input signal IN to dynamically control the equivalent impedance value of the variable impedance circuit 210H, and the second wave packet detecting circuit 230A includes the protective resistor R2 and the input signal. The first end of the input signal amplifying transistor M3 is coupled to the ground terminal, the second end of the input signal amplifying transistor M3 is coupled to the protection resistor R2, and the third end of the input signal amplifying transistor M3 is coupled to the large transistor M3. To the first filter capacitor The second end of the CF1 and the impedance control transistor M1, the protection resistor R2 is coupled between the input signal IN and the second end of the input signal amplifying transistor M3, and the second wave packet detecting circuit 230A amplifies the input signal IN and inputs it to the impedance. Controlling the second end of the transistor M1, the operation and architecture of the second packet inspection circuit 230A can be understood from the above description. The power amplifier circuit 200H can optionally include, for example, the input matching circuit, the output matching circuit, the control circuit, the first bypass capacitor, and/or other components of the above embodiment, and the operational details of the power amplifier circuit 200H can be described by the above embodiments. Understand that the details are omitted here.

Fig. 14 is a circuit block diagram showing a power amplifier circuit 200I according to an embodiment of the present invention. The power amplifier circuit 200I includes: a power transistor Q1 that receives an input signal IN and outputs an output signal OUT; a variable impedance circuit 210I that is identical in structure or operation to the variable impedance circuit 210H; the first wave packet detecting circuit 220, The input signal IN is coupled to the variable impedance circuit 210I, and the input signal IN is detected to dynamically control the equivalent impedance value of the variable impedance circuit 210I. The second wave packet detection circuit 230 is coupled to the input signal IN and the variable impedance. The circuit 210I detects the input signal IN to dynamically control the equivalent impedance value of the variable impedance circuit 210I; and the control circuit 240 is coupled to the variable impedance circuit 210I, and controls the variable impedance circuit to provide one of the power transistors. Current. The power amplifier circuit 200H can optionally include, for example, the input matching circuit, the output matching circuit, the first bypass capacitor, and/or other components of the above embodiments, and the operational details of the power amplifier circuit 200I can be understood from the description of the above embodiments. Details are omitted here.

It can be seen from the above that the power amplifier circuit of the above embodiment of the present invention can be In order to make the power transistor balance efficiency and linearity.

The power amplifier circuit of the above embodiment of the present invention can reduce the consumption of quiescent current of the power transistor in the low power region.

The power amplifier circuit of the above embodiment of the present invention can suppress the third-order term distortion signal and avoid deterioration of the communication signal quality.

In summary, although the present invention has been disclosed above by way of example, it is not intended to limit the present invention. Those who have ordinary knowledge in the technical field of the present invention can make various changes and refinements without departing from the spirit and scope of the present case. Therefore, the scope of protection of this case is subject to the definition of the scope of the patent application attached.

Claims (23)

A power amplifier circuit includes: a power transistor receiving an input signal and outputting an output signal; and a variable impedance circuit coupled to the power transistor, the variable impedance circuit including an impedance control transistor, a first a filter capacitor and a compensation resistor, the first end of the compensating resistor is coupled to the power transistor, and the second end of the compensating resistor is coupled to a first end of the impedance control transistor, the impedance control circuit a second end of the crystal is coupled to the first filter capacitor, and a third end of the impedance control transistor receives a first control voltage, and the first filter capacitor is coupled to the second end of the impedance control transistor And a first wave packet detecting circuit coupled to the input signal and the variable impedance circuit, the first wave packet detecting circuit includes a second filter capacitor and a filter inductor, and the second filter The capacitor is coupled to the input signal, the filter inductor is coupled between the second end of the impedance control transistor and the second filter capacitor; and a second wave packet detection circuit is coupled to the input signal and the a variable impedance circuit, the second wave packet detecting circuit includes a protection resistor and an input signal amplifying transistor, and the first end of the input signal amplifying transistor is coupled to the ground end, and the input signal amplifying the transistor The second end is coupled to the protection resistor, and the third end of the input signal amplifying transistor is coupled to the second end of the impedance control transistor, and the protection resistor is coupled to the input signal and the input signal to amplify the transistor Between the second ends. The power amplifier circuit of claim 1, wherein the variable impedance circuit further includes a first bypass capacitor coupled to the impedance control transistor The power amplifier circuit further includes a control circuit coupled to the variable impedance circuit, the control circuit includes: a feedback control transistor having a first end, a a second end, the first end of the feedback control transistor is coupled to the second end of the impedance control transistor, and the third end of the feedback control transistor is coupled to the first end a second bypass capacitor coupled between the third end of the feedback control transistor and the ground; a third bypass capacitor coupled to the feedback control transistor Between the second end and the ground end; a feedback resistor coupled to the second end of the feedback control transistor; and a power detection circuit coupled to the power transistor and the feedback resistor The power detection circuit detects an output power of the output signal of the power transistor. The power amplifier circuit of claim 1, wherein the variable impedance circuit further includes a first bypass capacitor coupled between the third end of the impedance control transistor and the ground. The power amplifier circuit further includes a control circuit coupled to the variable impedance circuit, the control circuit includes: a feedback control transistor having a first end, a second end, and a third end, the feedback The first end of the control transistor is coupled to the impedance control transistor The second end of the feedback control transistor is coupled to the second control voltage; the second bypass capacitor is coupled to the third end of the feedback control transistor and the ground end a third bypass capacitor coupled between the second end of the feedback control transistor and the ground; and a feedback resistor coupled to the second end of the feedback control transistor Between with a third control voltage. The power amplifier circuit of claim 1, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback resistor coupled to the impedance control transistor a second end; and a power detection circuit coupled between the power transistor and the feedback resistor, the power detection circuit detecting an output power of the output signal of the power transistor. The power amplifier circuit of claim 1, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback resistor coupled to the impedance control transistor The second end is between a third control voltage. The power amplifier circuit of claim 1, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback inductor coupled to the impedance control transistor a second end; and a power detection circuit coupled between the power transistor and the feedback inductor, The power detection circuit detects an output power of the output signal of the power transistor. The power amplifier circuit of claim 1, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback inductor coupled to the impedance control transistor The second end is between a third control voltage. The power amplifier circuit of claim 1, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a power detection circuit coupled to the power transistor, detecting Measuring an output power of the output signal of the power transistor to output a detection voltage signal; an inverter coupled to the power detection circuit, and inverting the detection voltage signal of the power detection circuit becomes a reverse phase detecting voltage signal; a comparator coupled to the inverter, comparing the inverted detection voltage signal to a reference voltage to obtain a comparison result; a voltage converter coupled To the comparator, converting the comparison result to a converted signal; a feedback resistor coupled to the voltage converter; and a feedback control transistor having a first end coupled to the second wave packet detection a second end is coupled to the feedback resistor, a third end is coupled to a second control voltage, and the converted signal is fed through the feedback resistor to the second end of the feedback control transistor . The power amplifier circuit as described in claim 1 of the patent scope further includes: An input matching circuit is coupled to the power transistor for matching the input signal; and an output matching circuit coupled to the power transistor for matching the output signal. A power amplifier circuit includes: a power transistor receiving an input signal and outputting an output signal; and a variable impedance circuit coupled to the power transistor, wherein an equivalent impedance value of the variable impedance circuit is based on the input The variable impedance circuit includes an impedance control transistor and a first filter capacitor, and the first end of the impedance control transistor is coupled to the power transistor, and the second end of the impedance control transistor And coupled to the first filter capacitor, the third end of the impedance control transistor receives a first control voltage, the first filter capacitor is coupled between the second end of the impedance control transistor and a ground terminal a first wave packet detecting circuit coupled to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit; and a second wave packet detecting circuit, Coupled to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit, the second wave packet detecting circuit includes a protection resistor and The input signal amplifying the transistor, the first end of the input signal amplifying transistor is coupled to the grounding end, and the second end of the input signal amplifying transistor is coupled to the protective resistor, and the input signal amplifying the transistor The third end is coupled to the first filter capacitor and the impedance control transistor The second end of the impedance control transistor is coupled between the input signal and the second end of the input signal amplifying transistor, and the second wave packet detecting circuit amplifies the input signal and inputs the second to the impedance control transistor end. The power amplifier circuit of claim 10, further comprising: a control circuit coupled to the variable impedance circuit to control a current supplied to the power transistor by the variable impedance circuit. The power amplifier circuit of claim 10, wherein the variable impedance circuit further comprises: a compensation resistor coupled between the power transistor and the first end of the impedance control transistor; A first bypass capacitor is coupled between the third end of the impedance control transistor and the ground. The power amplifier circuit of claim 10, wherein the first wave packet detecting circuit comprises: a second filter capacitor coupled to the input signal; and a filter inductor coupled to the impedance control circuit Between the second end of the crystal and the second filter capacitor. The power amplifier circuit of claim 10, further comprising: an input matching circuit coupled to the power transistor for matching the input signal; An output matching circuit is coupled to the power transistor for matching the output signal. A power amplifier circuit includes: a power transistor receiving an input signal and outputting an output signal; and a variable impedance circuit coupled to the power transistor, wherein an equivalent impedance value of the variable impedance circuit is based on the input The variable impedance circuit includes an impedance control transistor and a first filter capacitor, and the first end of the impedance control transistor is coupled to the power transistor, and the second end of the impedance control transistor And coupled to the first filter capacitor, the third end of the impedance control transistor receives a first control voltage, the first filter capacitor is coupled between the second end of the impedance control transistor and a ground terminal a first wave packet detecting circuit coupled to the input signal and the variable impedance circuit, detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit, the first wave packet detecting circuit includes a a filtering unit for extracting the input signal and providing the second end of the impedance control transistor of the variable impedance circuit; a second wave packet detecting circuit coupled to the input signal and the variable a circuit for detecting the input signal to dynamically control the equivalent impedance value of the variable impedance circuit, the second wave packet detecting circuit amplifying the input signal and inputting to the second end of the impedance control transistor; and a control The circuit is coupled to the variable impedance circuit and controls a current supplied by the variable impedance circuit to the power transistor. The power amplifier circuit of claim 15, wherein The variable impedance circuit further includes a first bypass capacitor coupled between the third end of the impedance control transistor and the ground. The power amplifier circuit further includes a control circuit coupled to the variable An impedance circuit, the control circuit includes: a feedback control transistor having a first end, a second end and a third end, the first end of the feedback control transistor being coupled to the impedance control transistor The second end of the feedback control transistor is coupled to a second control voltage; a second bypass capacitor coupled to the third end of the feedback control transistor and the ground a third bypass capacitor coupled between the second end of the feedback control transistor and the ground; a feedback resistor coupled to the second of the feedback control transistor And a power detection circuit coupled between the power transistor and the feedback resistor, the power detection circuit detecting an output power of the output signal of the power transistor. The power amplifier circuit of claim 15, wherein the variable impedance circuit further includes a first bypass capacitor coupled between the third end of the impedance control transistor and the ground. The power amplifier circuit further includes a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback control transistor having a first end, a second end and a third end, The first end of the feedback control transistor is coupled to the second end of the impedance control transistor, the third end of the feedback control transistor is coupled to a second control voltage; a second bypass a capacitor is coupled between the third end of the feedback control transistor and the ground; a third bypass capacitor is coupled between the second end of the feedback control transistor and the ground And a feedback resistor coupled between the second end of the feedback control transistor and a third control voltage. The power amplifier circuit of claim 15, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback resistor coupled to the impedance control transistor a second end; and a power detection circuit coupled between the power transistor and the feedback resistor, the power detection circuit detecting an output power of the output signal of the power transistor. The power amplifier circuit of claim 15, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback resistor coupled to the impedance control transistor The second end is between a third control voltage. Such as the power amplifier circuit described in claim 15 of the patent scope, a control circuit is coupled to the variable impedance circuit, the control circuit includes: a feedback inductor coupled to the second end of the impedance control transistor; and a power detection circuit coupled to the Between the power transistor and the feedback inductor, the power detection circuit detects an output power of the output signal of the power transistor. The power amplifier circuit of claim 15, further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a feedback inductor coupled to the impedance control transistor The second end is between a third control voltage. The power amplifier circuit of claim 15 further comprising: a control circuit coupled to the variable impedance circuit, the control circuit comprising: a power detection circuit coupled to the power transistor, detecting Measuring an output power of the output signal of the power transistor to output a detection voltage signal; an inverter coupled to the power detection circuit, and inverting the detection voltage signal of the power detection circuit becomes a reverse phase detecting voltage signal; a comparator coupled to the inverter, comparing the inverted detection voltage signal to a reference voltage to obtain a comparison result; a voltage converter coupled Up to the comparator, converting the comparison result to a converted signal; a feedback resistor coupled to the voltage converter; and a feedback control transistor having a first end coupled to the second wave packet detecting circuit, a second end coupled to the feedback resistor, The third end is coupled to a second control voltage, and the converted signal is fed through the feedback resistor to the second end of the feedback control transistor. The power amplifier circuit of claim 15, wherein the second wave packet detecting circuit comprises a protection resistor and an input signal amplifying transistor, and the first end of the input signal amplifying transistor is coupled to the a second end of the input signal amplifying transistor is coupled to the protection resistor, and a third end of the input signal amplifying transistor is coupled to the first filter capacitor and the second of the impedance control transistor The protection resistor is coupled between the input signal and the second end of the input signal amplifying transistor.