JP2005019768A - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance breakdown voltage by facilitating relaxation of the electric field on the end face of PN junction of an IMPATT diode. <P>SOLUTION: A P type silicon carbide low resistance layer 5 is formed directly under a P type ohmic contact electrode 6 through diffusion of boron from a boride layer 4. Consequently, resistance and contact resistance are decreased, power loss due to resistance is reduced and operational efficiency is improved. Since sheet resistance on the periphery of the P type ohmic contact electrode 6 is larger than that directly under the P type ohmic contact electrode 6, a current does not flow easily to the peripheral part. Consequently, breakdown voltage is enhanced as compared with prior art and a larger high frequency output can be attained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a silicon carbide semiconductor device, and more particularly, to a method for manufacturing an in-pad diode made of silicon carbide that is improved in withstand voltage and improved in reproducibility in mass production.
[0002]
[Prior art]
Impat diodes are well-known and well-known as one of so-called high-frequency devices that use ionization due to collisions in semiconductors and transit time effects to obtain negative resistance in microwaves. Conventionally, silicon and gallium arsenide have been used. Research and development has been promoted using this. Details of such in-pad diodes are described in many books on semiconductor devices (see Non-Patent Document 1, for example).
For example, the operation principle will be described using a known and well-known lead type diode having a typical structure of an impat diode as an example. In the lead-type diode, after forming a low-concentration high-resistance layer serving as a carrier travel layer on a low-resistance N-type semiconductor substrate, the impurity concentration is 10 ¹⁶ cm ⁻³ N-type semiconductor layers and 10 ¹⁹ cm ^{−. It} has a structure in which ^three P-type semiconductor layers are stacked. When a reverse voltage is applied to the diode, the electric field is maximized at the PN junction portion composed of the N-type and P-type semiconductor junctions, and when this electric field reaches a critical electric field at which avalanche doubling starts, the avalanche doubling starts. ing. Therefore, a DC voltage is applied to such an extent that an electric field smaller than the critical electric field is generated, and an alternating current (high frequency electric field) is superimposed on the electric field so that the high frequency electric field causes an avalanche doubling, and avalanche doubling starts. Then, the holes generated in the avalanche region are quickly absorbed by the P layer, and the electrons enter the traveling layer. This electron arrives at the N-type semiconductor substrate after a time determined by the thickness of the traveling layer and the electron saturation speed. At this time, the high-frequency electric field rotates just 180 degrees with the phase of the electric field when avalanche doubling occurs. If so, the electrons arriving at the N-type semiconductor substrate expel energy into the space. That is, a high frequency is emitted into the space.
[0003]
Thus, an impatt diode that generates microwaves can currently obtain the highest continuous-wave output power in the millimeter wave region, but the element must be made smaller as the frequency increases, so that it operates at high power. The decrease in output due to the temperature rise in the case becomes a problem.
On the other hand, silicon carbide has a physical property value in which the electron saturation rate is twice as large as that of silicon, the dielectric breakdown electric field is about ten times larger, and the thermal conductivity is three times larger. Therefore, it is considered promising as a material for high-frequency and high-power semiconductor elements.
Although it is silicon carbide like this, until a few years ago, the quality of the substrate and the epitaxial film was poor, and even if a PN junction was formed, the avalanche doubling phenomenon could not be observed. However, in 2000, according to Vasilevski et al., The temperature coefficient of the avalanche start voltage is positive in the diode using the commercially available p ⁺ / n / n ⁺ epi substrate (the avalanche start voltage increases with increasing temperature). Was reported (see Non-Patent Document 2), and it was shown that a high-quality epitaxial substrate could be obtained even if it was commercially available, and the momentum for developing an impat diode increased.
[0004]
To date, L. By Yuan et al., N in the N-type conductive substrate ^- with ^/ n ⁺ / p + epi substrate layers are epitaxially grown, with a prototype IMPATT diode of the mesa structure by dry etching, microwave oscillation reported (See Non-Patent Document 3). They reported that a prototype output power diode was installed in a waveguide and a peak output of 1 mW was obtained at 7.75 GHz. K.K. Vassilevski et al. Have reported the operation of an impat diode having a mesa structure in the same manner using an epitaxial substrate obtained by epitaxially growing an n ⁻ / p ⁺ layer on an N-type conductive substrate (see Non-Patent Document 4). As described above, the progress of silicon carbide epitaxial technology in recent years has increased the feasibility of an impatt diode utilizing avalanche doubling.
[0005]
Here, the above-mentioned mesa structure is known and well-known. If the structure is outlined with reference to FIG. 5, the N-type epitaxial layer 22 and the P-type silicon carbide layer are formed on the N-type silicon carbide substrate 21. 23 are sequentially formed, and an ohmic electrode 24 is formed on the P-type silicon carbide layer 23, while an N-type ohmic electrode 25 is provided on the other surface side of another silicon carbide substrate 21. It is a structure.
[0006]
[Non-Patent Document 1]
S. M.M. Jie, Yasuo Minami Nichi et al., “Semiconductor Device”, Sangyo Tosho, 1987, p. 233-266
[Non-Patent Document 2]
Vassilevski, IEEE Electron Device Letters. 2000, Vol 21, No. 10, p. 485
[Non-Patent Document 3]
L. Yuan, IEEE Electron Device Letters. , 2001, Vol 22, No. 6, p. 266-268
[Non-Patent Document 4]
K. Vassilevski, Materials Science Forum, 2002, Vols. 389-393, p. 1353-1358
[0007]
[Problems to be solved by the invention]
However, the silicon carbide inpatient diode with the mesa structure described above has a problem that avalanche doubling occurs in a part around the mesa and the avalanche operation cannot be realized uniformly in the plane of the diode. It was.
The reason is that the electric field intensity on the side surface of the mesa is stronger than that inside the semiconductor. This is because a space charge region is formed by surface defects and charges at the PN junction end face of the mesa structure (where the silicon carbide continuation is interrupted). At this time, the electric flux generated in the space charge region is more dielectric than the air. This is because the electric field on the mesa surface is larger than the electric field in the semiconductor. When a reverse voltage is applied to such a diode, the electric field on the surface where the PN junction is exposed on the mesa side surface of the silicon carbide becomes higher than that inside the semiconductor, and therefore, avalanche collapse and Discharge will occur. In such avalanche collapse around the mesa, current flows only locally, so even if it operates as an impat diode, high output cannot be expected. In addition, since a current flows locally, it easily breaks down and the reliability is significantly reduced.
[0008]
As a technique for reducing such a surface electric field, for example, a technique of forming a taper on a side surface of a mesa called beveling is known and well known (B. Baliga, “Modern Power Devices”, Malabar, (Floroda, Krieger Publishing Company, 1992, p. 100-110).
However, even if the taper as described above is formed on the side surface of the mesa, depending on the accuracy of the surface treatment, the surface electric field may be affected by the surface state and the electric field may not be relaxed. In addition, in order to relax the surface electric field sufficiently smaller than that in the semiconductor, the taper angle must be formed to an extremely gentle taper of 10 degrees or less, and there is a problem that the manufacturing process is difficult.
[0009]
The present invention has been made in view of the above circumstances, and provides a method for manufacturing an in-pad diode made of silicon carbide that can easily relax the electric field at the PN junction end face of the inpatient diode and has an excellent breakdown voltage.
Another object of the present invention is to provide a method for manufacturing an in-pad diode made of silicon carbide which is highly reproducible and excellent in mass productivity.
[0010]
[Means for Solving the Problems]
In order to achieve the above object, a method for manufacturing a silicon carbide semiconductor device according to the present invention includes:
Preparing a silicon carbide substrate comprising a low-resistance N-type silicon carbide substrate and an N-type epitaxial layer having an impurity concentration of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ¹⁸ cm ⁻³ ;
Forming a P-type layer by ion-implanting impurities into the surface of the N-type epitaxial layer;
Depositing a refractory metal boride on the surface of the P-type layer and performing a heat treatment to form a low-resistance layer on the P-type layer surface;
Forming an ohmic electrode on the surface of the deposited boride layer, removing the boride layer and the low resistance layer using the ohmic electrode as a mask, and exposing a P-type layer;
A high resistance layer is formed by implanting impurity ions deeper than the interface between the P-type layer and the N-type epitaxial layer from the exposed P-type layer surface using a mask for ion implantation having a diameter larger than that of the ohmic electrode. It consists of a process.
[0011]
In such a configuration, by performing cap annealing using a refractory metal boride, the low resistance layer of the P layer can be formed while suppressing the roughening of the substrate surface due to heat treatment, and thereby contact resistance. A silicon carbide semiconductor device in which the rate is reduced and the high-frequency loss due to resistance is reduced is provided. Furthermore, in an in-pad diode made of silicon carbide with such a configuration, when an avalanche doubling occurs, if the current tries to spread from the ohmic electrode to the periphery of the diode, the peripheral sheet resistance is larger than immediately below the electrode. In the periphery of the diode, the potential drops due to a voltage drop, which makes it difficult for the current to flow to the periphery.As a result, local avalanche doubling in the periphery is suppressed, the breakdown voltage is improved, and the diode surface is uniform. Avalanche doubling is possible.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 6.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, the configuration of an in-pad diode made of silicon carbide in the embodiment of the present invention will be described with reference to FIG.
In an in-pad diode as a silicon carbide semiconductor device according to an embodiment of the present invention, an epitaxial layer 2 made of N-type silicon carbide is stacked on an N-type silicon carbide substrate 1, and a P-type is formed at the substantially central portion of the epitaxial layer 2. A silicon carbide layer 3 is formed, and a high-resistance amorphous layer 7 is formed in the epitaxial layer 2 around the P-type silicon carbide layer 3. A P-type silicon carbide low resistance layer 5 and a boride layer 4 are formed in this order on the P-type silicon carbide layer 3, and a P-type ohmic contact electrode 6 is formed on the boride layer 4. ing. An N-type ohmic electrode 8 is formed on the opposite surface of the N-type silicon carbide substrate 1.
[0013]
Next, a method for manufacturing an in-pad diode made of silicon carbide having the above-described configuration will be described with reference to FIGS.
First, an epitaxial layer 2 of silicon carbide having an N-type impurity concentration of 3 × 10 ¹⁷ cm ⁻³ and a thickness of 1.5 μm is formed on the low-resistance N-type silicon carbide substrate 1 by a CVD (Chemical Vapor Deposition) method. (See FIG. 2 (a)). Next, in order to form a PN junction, aluminum ion implantation is performed at an acceleration voltage of 50 keV and a dose amount of 9 × 10 ¹⁴ cm ⁻² , an acceleration voltage of 100 keV and a dose amount of 1.4 × 10 ¹⁵ cm ⁻² and an acceleration voltage of 180 keV. A P-type silicon carbide layer 3 made of a P ⁺ layer is formed in the order of a dose of 3 × 10 ¹⁵ cm ⁻² (see FIG. 2A). At this time, the substrate temperature is set to 500 ° C. Alternatively, boron can be ion-implanted to form the P-type silicon carbide layer 3.
Next, heat treatment at 1700 ° C. is performed in an argon atmosphere in order to activate the P-type silicon carbide layer 3. In order to suppress the evaporation of silicon from the surface of the silicon carbide due to this heat treatment and the occurrence of surface roughness, the melting point is high as an annealing cap material, and molybdenum boride is formed by sputtering as a boride composed of P-type impurities. A boride layer 4 is formed by depositing 50 nm (see FIG. 2B). Here, if the thickness of the molybdenum boride deposit is too thin, it will not play a role as a cap material. Conversely, if it is too thick, cracks may occur or peel off due to the difference in thermal expansion coefficient and thermal conductivity with silicon carbide. Therefore, it is important to set the thickness to an appropriate value because it cannot function as a cap material. And when the thickness of molybdenum boride is appropriate, the effect as a cap material is exhibited and the surface roughness of the substrate is suppressed. Further, excess boron from molybdenum boride diffuses into the silicon carbide substrate, and a P-type silicon carbide low-resistance layer 5 that becomes a low-resistance layer is formed immediately below the electrode (see FIG. 2C). As a result, the P-type contact resistivity is reduced, and an ohmic electrode is realized.
[0014]
Next, an ohmic electrode (aluminum) is formed by a lift-off method, and an electrode (titanium / platinum / gold) 6 serving as a pad is formed thereon by vapor deposition and a lift-off process (see FIG. 3A). Then, using this ohmic electrode as an etching mask, the unnecessary boride layer 4 and the P-type silicon carbide low-resistance layer 5 are removed (see FIG. 3B).
Then, an oxide film mask (not shown) for ion implantation is formed on the P-type silicon carbide layer 3 in order to form a portion to be an in-pad diode region having a radius larger than the electrode 6 by about 10 μm.
Next, vanadium was added at room temperature in the order of acceleration voltages of 700 keV, 400 keV, 300 keV, 200 keV, 100 keV, and 500 keV, and doses of 1.4 × 10 ¹⁴ cm ⁻² and 1.7 × 10 ¹⁵ cm ⁻² , 1.4, respectively. Ions are implanted at × 10 ¹⁵ cm ⁻² , 1.8 × 10 ¹⁵ cm ⁻² , 1.0 × 10 ¹⁵ cm ⁻² , and 1.2 × 10 ¹⁵ cm ⁻² to form the high-resistance amorphous layer 7 ( (Refer FIG.3 (c)).
Finally, an ohmic electrode 8 is formed on the back surface of the N-type silicon carbide substrate 1 to complete an in-pad diode made of silicon carbide (see FIG. 1).
[0015]
In order to operate the in-pad diode made of silicon carbide having such a configuration, a voltage is applied to the P-type ohmic contact electrode 6 so as to be negative with respect to the N-type ohmic electrode 8. As a result, the electric field is maximized at the interface between the N-type epi layer 2 and the P-type silicon carbide layer 3, and carriers are generated when the electric field strength becomes larger than the occurrence of avalanche decay. The inside of the layer 2 travels toward the N-type silicon carbide substrate 1. At this time, the flow of the induced current flowing in the external circuit and the phase of the voltage applied between the P-type ohmic contact electrode 6 and the N-type ohmic electrode 8 are opposite to each other. Will be released.
[0016]
In the in-pad diode made of silicon carbide in the embodiment of the present invention, the resistance value of the P layer immediately below the P-type ohmic contact electrode 6, that is, the P-type silicon carbide low resistance layer 5 is small, and the contact resistance is small. The power loss due to the resistance is small, and the efficiency is improved. Also, when avalanche doubling occurs, if the current tries to spread from the P-type ohmic contact electrode 6 to the periphery of the diode, the sheet resistance around the electrode 6 is higher than immediately below the electrode 6, so the potential is lowered at the diode periphery due to the voltage drop. Therefore, it becomes difficult for the current to flow to the peripheral portion, the current density around the diode is reduced, and local current concentration around the diode is suppressed, and as a result, the breakdown voltage is improved. Therefore, the in-pad diode made of silicon carbide in the embodiment of the present invention enables uniform avalanche doubling on the inner surface of the diode, and allows more diode current to flow than the conventional mesa structure. A large high-frequency output can be obtained.
[0017]
In the in-pad diode made of silicon carbide in the embodiment of the present invention, the state of light emission when avalanche collapse occurred was observed. As a result, in the in-pad diode of the present invention, light emission was observed uniformly in the diode surface, the electric field in the periphery was relaxed, and it was confirmed that avalanche collapse occurred uniformly in the diode surface.
In addition, in the in-pad diode made of silicon carbide in the embodiment of the present invention, the periphery is covered with silicon carbide having good heat conduction, so that heat can be released in the horizontal direction (left and right direction in FIG. 1). It has a good heat dissipation.
[0018]
Next, another configuration example of the in-pad diode made of silicon carbide in the embodiment of the present invention will be described with reference to FIG. The same components as those in the configuration example shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Hereinafter, different points will be mainly described.
The configuration example shown in FIG. 4 shows that the surface other than the electrode of the in-pad diode made of silicon carbide is covered with a protective member in order to improve the heat diffusion efficiency. This is different from the configuration example described above.
Specifically, in the configuration example shown in FIG. 4, the surface of the high resistance amorphous layer 7 is coated with diamond by, for example, the CVD method except for the portion of the P-type ohmic contact electrode 6. Thus, a diamond film 9 is formed.
[0019]
The manufacturing procedure in such a configuration will be described with a focus on the process of forming the diamond film 9. First, the thickness of the P-type ohmic contact electrode 6, which is the cathode electrode on the upper part of the impat diode, is previously determined by gold plating or the like. As shown in the configuration example shown in FIG. 1, a thickness of about 3 microns is formed as compared with the configuration without the diamond film 9, and titanium is deposited thereon in an order of about 50 nm and a platinum layer is deposited in an order of about 100 nm.
Then, diamond is grown on the surface of the impat diode by the CVD method. Since silicon carbide originally contains carbon, there is an advantage that diamond is easy to grow and a heat conductive film having excellent adhesion. Also. Since diamond also grows on platinum, it is possible to grow diamond on the P-type ohmic contact electrode 6.
[0020]
Next, a resist is applied to the entire surface, and the resist and the diamond layer 9 are subjected to back etching by oxygen plasma ashing until the P-type ohmic contact electrode 6 is exposed. It will be completed. Other manufacturing procedures are basically the same as those in the configuration example shown in FIG. 1, and detailed description thereof will not be repeated here.
[0021]
In the above-described configuration example, molybdenum boride is used as a boride. However, it is not necessary to be limited to this, and niobium boride or titanium boride is also suitable.
[0022]
【The invention's effect】
As described above, according to the present invention, cap annealing using a boride is performed to suppress the roughening of the substrate surface due to the heat treatment, and the low resistance layer of the P layer is formed. Since the contact resistance of the layer can be reduced, the loss is small and the oscillation efficiency can be improved.
In addition, since the sheet resistance of the P layer is larger in the periphery of the ohmic electrode than immediately below the electrode, the current is difficult to flow because the potential of the peripheral portion is low even if the current flows into the peripheral portion. It is possible to suppress the destruction caused by the current concentration.
Furthermore, since the silicon carbide layer with good heat conduction is also located around the PN junction, heat can be easily released in the surface direction, so that it has better heat dissipation than conventional ones. There is an effect.
Furthermore, it is possible to provide an in-pad diode that has good reproducibility, is easy to manufacture, and is suitable for high power operation.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view schematically showing a configuration of an in-pad diode made of silicon carbide in an embodiment of the present invention.
2 is a schematic view schematically showing a first half of a manufacturing process of an in-pad diode made of silicon carbide shown in FIG. 1. FIG.
3 is a schematic diagram schematically showing the latter half of the manufacturing process of the in-pad diode made of silicon carbide shown in FIG. 1. FIG.
FIG. 4 is a longitudinal sectional view schematically showing another configuration example of the in-pad diode made of silicon carbide in the embodiment of the present invention.
FIG. 5 is a longitudinal sectional view schematically showing a configuration of an impatt diode having a conventional mesa structure.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... N type silicon carbide substrate 2 ... Epitaxial layer 3 ... P type silicon carbide layer 4 ... Boride layer 5 ... P type silicon carbide low resistance layer 6 ... P type ohmic contact electrode 7 ... High resistance amorphous layer 8 ... N type ohmic electrode

Claims (3)

Preparing a silicon carbide substrate comprising a low-resistance N-type silicon carbide substrate and an N-type epitaxial layer having an impurity concentration of 1 × 10 ¹⁶ cm ^{−3 to} 1 × 10 ¹⁸ cm ⁻³ ;
Forming a P-type layer by ion-implanting impurities into the surface of the N-type epitaxial layer;
Depositing a refractory metal boride on the surface of the P-type layer and performing a heat treatment to form a low-resistance layer on the P-type layer surface;
Forming an ohmic electrode on the surface of the deposited boride layer, removing the boride layer and the low resistance layer using the ohmic electrode as a mask, and exposing a P-type layer;
A high resistance layer is formed by implanting impurity ions deeper than the interface between the P-type layer and the N-type epitaxial layer from the exposed P-type layer surface using a mask for ion implantation having a diameter larger than that of the ohmic electrode. A method for manufacturing a silicon carbide semiconductor device comprising the steps of: 2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the boride of the refractory metal is any one of molybdenum boride, niobium boride, and titanium boride. 3. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the P-type layer and the surface of the high resistance layer exposed on the surface of the silicon carbide substrate are coated with diamond.

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