JP2005018240A - Two or more chip mounting device and power supply control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the generation of the power consumption of a chip which is not put in a processing status, or in which it is not necessary to put in the processing status. <P>SOLUTION: In a status that not only normal chips 12 and 13 but also a power control chip 11 and a power supply on/off chip 14 are included in the same package, a power supply control signal corresponding to the normal chips 12 and 13 is generated according to the size of a processing load as a whole in the power source control chip 11, and power supply to the normal chips 12 and 13 is actually turned on/off in the power supply on/off chip 14 based on the power supply control signal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is configured such that, based on a power supply control signal from a power supply control chip, the power supply on / off chip is actually turned on / off to the normal chip used for normal processing. The present invention relates to a multi-chip mounting apparatus and a power supply control method.
[0002]
[Prior art]
In the past, it has been considered to reduce power consumption in general data processing apparatuses. In order to suppress the power consumption, for example, in the standby state, the clock signal or data to the functional block that does not need to be in the active state is stopped, the supply of the clock signal to the functional block is stopped, Data state transition to the functional block is stopped.
[0003]
On the other hand, in the recent miniaturization process (for example, 95 nm and 65 nm), the integration rate is increased and the operating current itself is decreasing, but the off-leak current not related to the operation itself is increasing. Is the actual situation. For this reason, the power consumption of the entire chip does not decrease compared to the previous generation process, or rather tends to increase conversely. This situation is the same in SIP (system in package) which has been attracting attention in recent years as a complement to SOC (system on a chip, which is equivalent to a so-called system LSI).
[0004]
Incidentally, in Patent Document 1, a power switch is provided in a logic circuit in a system LSI as a single chip, and the leakage current is reduced by shutting off the power switch in a standby state. . At the same time, in a static random access memory (SRAM) circuit, leakage current is reduced by controlling the substrate bias.
[0005]
[Patent Document 1]
Japanese Patent Laid-Open No. 2003-132683
[Problems to be solved by the invention]
As described above, measures have been taken so far to stop the supply of the clock signal and the stop of the data state transition in order to reduce the power consumption in the standby state. However, since the proportion of off-leakage current dominates in power consumption in recent advanced processes, it is no longer meaningful to reduce power consumption by taking these measures.
[0007]
It is an object of the present invention to provide a chip used for some normal processing for a multiple chip mounting apparatus in which a plurality of chips are mounted in a sealed state in the same package (this is usually referred to as a normal process) Multi-chip mounting device that does not generate power consumption as a matter of course of off-leakage current in a normal chip that is not in a processing state or is not required to be in a processing state. Another object is to provide a power supply control method.
[0008]
[Means for Solving the Problems]
The multi-chip mounting apparatus according to the present invention includes at least a normal chip, a power control chip including at least a power supply control block, and at least a normal chip based on a power supply control signal from the power supply control block in the power control chip. And a power supply on / off chip that actually turns on / off the power supply. That is, based on the power supply control signal from the power control chip, the power supply on / off chip is configured to actually turn on / off the power supply to the normal chip.
[0009]
In the power supply control block in the power control chip, it is possible to identify a normal chip that is not in the processing state or unnecessary to be in the processing state from the size of the processing load and the processing request type as a whole. However, when the power supply to these normal chips is forcibly stopped, the off-leak current in these normal chips is naturally not generated.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
First, prior to specific description of the present invention, the outline thereof will be described. The present invention is intended to reduce off-leakage current in the entire SIP, and hence power consumption, for a multi-chip mounting device, specifically, SIP. A power control chip and a power supply on / off chip are newly provided separately from the normal chip (logic circuit, etc.) manufactured by the most advanced miniaturization process. Based on the power supply control signal from the chip, the power supply on / off chip normally turns on / off the power supply to the chip.
[0011]
As described above, the power supply to the normal chips that are not in the processing state or are not required to be in the processing state is stopped, so that the off-leak current in these normal chips is naturally consumed. No power will be generated. However, not only the power supply control in units of chips, but also when the normal chip is divided into a plurality of blocks and the power supply in units of blocks is possible, the power supply is turned on / off in units of blocks. It is also possible.
[0012]
Incidentally, if the power supply control chip and the power supply on / off chip are supplementarily explained, the power supply control chip itself may be provided exclusively for power supply control, but a power supply control function is provided as a partial function of the normal chip. You may do it. Further, the power supply on / off chip is manufactured by a state-of-the-art miniaturization process because each of a plurality of analog switches made of, for example, bipolar elements or the like may be simply configured to be capable of on / off control. There is no need, and it is only necessary to make use of the characteristics of SIP and to be manufactured by a previous generation process, or to be composed of a bipolar element or the like, and the cost increase can be suppressed in the implementation of the present invention.
[0013]
Now, specifically explaining the present invention, FIG. 1 shows a basic internal configuration of an example of a multi-chip mounting apparatus according to the present invention. As shown in the figure, the multi-chip mounting device 1 is mounted with a power control chip 11, normal chips 12, 13 and a power supply on / off chip 14 sealed in the same package. A power source is also introduced from the outside of the multi-chip mounting apparatus 1. Thus, based on the power supply control signal from the power control chip 11 that is always in the power-on state, the power supply on / off chip 14 that is always in the power-on state is Power supply to each of the chips 12 and 13 can be turned on / off.
[0014]
With the above configuration, when the power supply to each of the chips 12 and 13 is normally turned off, there is no room for generating off-leakage current in the chip, and there is no room for generating power consumption in the chip. Therefore, it is possible to reduce the power consumption of the entire multi-chip mounting apparatus 1. Incidentally, the power control chip 11 in this case may be dedicated for power control, or may be a normal chip having a power control function as a partial function.
[0015]
As described above, the power supply to the normal chips 12 and 13 is turned on / off by the power control chip 11, but how each of the normal chips 12 and 13 is controlled to be turned on / off is, for example, as a whole. This depends on the size of the processing load. The power control chip 11 determines the size of the processing load, and if it is determined to be a heavy processing load, the normal chip 12 and 13 and the power control chip 11 perform processing so that the normal chip 12 is processed. , 13 is supplied with power. In addition, when it is determined that the processing load is medium or light or in an idle state, power is supplied to the corresponding normal chip so that the processing is performed by the normal chips 12 and 13 or either one of them. It has come to be.
[0016]
In addition to the processing load as a whole, it is also possible to supply power to a normal chip corresponding to a function type related to a processing request from the outside of the multi-chip mounting device 1, for example, focusing on the function type of the chip. It is done. More specifically, for example, assuming that the normal chips 12 and 13 are MPEG (Moving Picture Coding Experts Group) encode LSI and MPEG decode LSI, respectively, and the power control chip 11 is a system control LSI. It is as follows.
[0017]
That is, when an image is recorded on some kind of media, an MPEG encoding LSI is required, so that power may be supplied to the normal chip 12. In addition, when an image recorded on the medium is reproduced, an MPEG decode LSI is required, so that power is normally supplied to the chip 13. Further, when the video is reproduced while the video is recorded, the power is normally supplied to both the chips 12 and 13. As a matter of course, when neither video recording nor reproduction is performed, the power is not normally supplied to the chips 12 and 13.
[0018]
Although the basic internal configuration and operation of an example of a multiple chip mounting apparatus according to the present invention have been described, the power supply to each of the chips 12 and 13 is not necessarily performed in units of chips, and in some cases, All the chips or a part of these chips may be performed in units of blocks. The internal configuration in such a case is shown in FIG. As shown in the figure, the power supply to the normal chip 13 is performed in units of chips. However, in terms of function, the power is supplied in units of blocks more finely to the normal chip 12 that is divided in advance into four blocks. It is possible to do.
[0019]
Furthermore, it is also conceivable that, among a plurality of blocks in a normal chip, some blocks have a power supply control function and the power supply control for each remaining block is performed on a block basis. The internal configuration in this case is shown in FIG. As shown in the figure, for example, each of the normal chips 15 and 16 is divided into four, and one of the blocks is a power supply control block (indicated by hatching). Therefore, in such a case, power supply control for the remaining blocks (non-power supply control block) and the normal chip 13 is performed via the power supply on / off chip 14 by these power supply control blocks. Become. The remaining blocks need only be controlled in units of blocks, and the normal chip 13 only needs to be controlled in units of chips.
[0020]
Here, a specific configuration of an example of the power supply on / off chip 14 will be described as shown in FIG. As illustrated, in this example, it is assumed that power supply control is performed for each of three power supply destinations (chips or blocks). Switch elements (bipolar transistors, p / n channel MOS transistors, MEMS (Micro Electro Mechanical Systems) switches, etc.) 141 to 143 are provided for each of these power supply destinations, and power from the outside of the chip is also the same. It is turned on / off by an external power supply control signal. In some cases, the switch elements 141 to 143 may be replaced with switching regulators, and whether or not the output voltage is supplied to the power supply destination may be controlled by the power supply control signal.
[0021]
As described above, the power supply on / off chip 14 itself does not need to be manufactured by a state-of-the-art miniaturization process, and is manufactured by a previous generation process utilizing the characteristics of SIP, or by using a bipolar element or the like. What is necessary is just to be comprised, and the increase in cost can be suppressed on implementation of this invention. From this point of view, the above power control cannot be applied to the SOC, that is, the system LSI as it is.
[0022]
Finally, the SIP structure will be generally described. First, FIG. 5 schematically shows a lateral structure type SIP. As shown in FIG. 5, for example, power wirings 54 and 55 and signal wiring 56 are formed on an interposer substrate 51 made of silicon or an organic substrate. On the other hand, a plurality of chips 52 and 53 are positioned and mounted in a predetermined manner. The wirings 54 to 56 are connected to the chips 52 and 53 by bonding between the bonding pads 58 with wires 57 or using bumps 59. In this case, the aforementioned power supply on / off chip 14 is mounted like a chip 52, for example.
[0023]
Next, the vertical structure type SIP schematically shown in FIG. 6 will be described. As shown in the drawing, a plurality of chips 61 and 62 are stacked on the interposer substrate 51 in a vertical direction. Positioned and mounted. The power supply wiring and signal wiring of the chips 61 and 62 are connected by bonding the bonding pads 58 by wires 57 or by bumps 59 via bump pads 60. In this case, the aforementioned power supply on / off chip 14 is mounted as one of the chips 61 and 62.
[0024]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0025]
【The invention's effect】
Of course, off-leakage current is not generated in chips that are not in the processing state or are not required to be in the processing state among the multiple mounted chips. A supply control method is provided.
[Brief description of the drawings]
FIG. 1 is a diagram showing a basic internal configuration of an example of a multiple chip mounting apparatus according to the present invention.
FIG. 2 is a diagram showing an internal configuration in a case where power supply to each normal chip is partially performed in units of blocks.
FIG. 3 is a diagram showing an internal configuration when power supply control is performed on a non-power supply control block or the like by a normal chip including a power supply control block.
FIG. 4 is a diagram showing a specific configuration of an example of a power supply on / off chip.
FIG. 5 is a diagram showing a structure of a lateral structure type SIP.
FIG. 6 is a view similarly showing the structure of a vertically structured SIP.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Multiple chip mounting apparatus, 11 ... Power supply control chip, 12, 13 ... Normal chip, 14 ... Power supply on / off chip

Claims (8)

A multiple chip mounting device in which a plurality of chips are mounted in a sealed state in the same package,
A normal chip whose power supply is controllable and usually used for some normal processing;
A power control chip including at least a power supply control block;
A multi-chip mounting device including at least a power supply on / off chip that actually turns on / off power supply to the normal chip based on a power supply control signal from a power supply control block in the power control chip. The multi-chip mounting apparatus according to claim 1,
In the power supply control chip, a multi-chip mounting apparatus in which power supply to each normal chip is controlled so that power is supplied to many normal chips as the overall processing load increases. The multi-chip mounting apparatus according to claim 1,
In the power control chip, a multi-chip mounting apparatus in which power supply to each normal chip is controlled so that power is supplied to the normal chip corresponding to the function type related to the processing request. The multi-chip mounting apparatus according to claim 1,
In the power control chip, the normal chip is divided into two or more blocks, or the power control chip includes a non-power supply control block. A multi-chip mounting device in which power supply to each block is controlled so that power supply to each control block is performed in units of blocks. A power supply control method in a multi-chip mounting apparatus in which a plurality of chips are mounted in a sealed state in the same package,
A power supply control signal that can control power supply from a power supply control chip including at least a power supply control block and that normally issues a power supply control signal corresponding to the normal chip used for some normal processing An issue step;
A power supply including a power supply on / off step of actually turning on / off the power supply to the normal chip by the power supply on / off chip based on the power supply control signal issued in the power supply control signal issuing step Supply control method. The power supply control method according to claim 5, wherein
In the power supply control signal issuance step, a power supply control method in which a power supply control signal is issued corresponding to a normal chip so that power is supplied to each of many normal chips as the processing load increases. The power supply control method according to claim 5, wherein
In the power supply control signal issuing step, a power supply control method in which a power supply control signal is issued for a normal chip so that power is supplied to the normal chip corresponding to the function type related to the processing request. The power supply control method according to claim 5, wherein
In the power supply control signal issuing step, when the normal chip is divided into two or more blocks, or the power control chip includes a non-power supply control block, at least one of them corresponds to the normal chip, the non-power supply A power supply control method in which a power supply control signal is issued for each block so that power supply to each supply control block is performed in units of blocks.

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