JP2005006471A - Voltage converting circuit, and semiconductor integrated circuit device and mobile terminal equipped with it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a circuit scale and power consumption in order to match voltage reduction while stabilizing the operation of an inside circuit, in a voltage converting circuit 31 that is manufactured as a step-down converter or the like that is formed inside an integrated circuit. <P>SOLUTION: A pulse signal generating circuit 32 that drives a switch circuit 33 is constituted of a reference pulse signal generating circuit 41 that generate, at a constant frequency, a reference pulse signal V3 that becomes a reference; a delay circuit 42 that delays the reference pulse signal V3; a delay-time control circuit 43 that sets up a delay time; and a drive circuit 44 that detects the transition between the reference pulse signal V3; and a delay pulse signal V4 and generates control signals X1, X2 that have time duration according to the delay time at the delay circuit 42. This constitution enables an output voltage V2 to be controlled by PWM modulation, ripple voltages to be controlled to a constant value, and the operation of internal circuits to be stabilized. Also, this circuit is applicable to the voltage reduction by being made up of a shift register and the like. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a voltage conversion circuit that supplies a power supply voltage that is optimal for the operation of an integrated circuit, and a semiconductor integrated circuit device and a portable terminal that include the voltage conversion circuit.
[0002]
[Prior art]
In general, in an integrated circuit in which arithmetic processing or the like is performed according to an operation clock, it is necessary to provide a large design margin in order to always perform normal operation against variations in manufacturing processes, power supply fluctuations, temperature changes, and the like. is there. In other words, it is necessary to design so that the operation of the entire integrated circuit can be accommodated within one clock even if the delay time increases due to various fluctuations. In addition, a sufficiently high power supply voltage is applied to the integrated circuit so that it operates even when all conditions are worst.
[0003]
However, these large design margins and application of a high power supply voltage hinder the speeding up of integrated circuits and the reduction in power consumption. Therefore, development of a voltage conversion circuit that controls the power supply voltage is progressing so that the operation status of the integrated circuit is detected and the minimum power supply voltage necessary for the operation of the integrated circuit can be applied.
[0004]
FIG. 23 is a schematic configuration diagram of a typical conventional voltage conversion circuit 1. This voltage conversion circuit 1 is disclosed in Japanese Patent Laid-Open No. 10-242831. As shown in the figure, the voltage conversion circuit 1 includes a duty ratio control circuit 2, a buffer circuit 3, a filter circuit 4, a critical path circuit 5, a delay circuit 6, a correct / incorrect determination circuit 7, and an adder 8. ing.
[0005]
The duty ratio control circuit 2 is a circuit that controls the variable operation of the output voltage from the buffer circuit 3, and includes a counter 11 and a comparison circuit 12. Counter 11 is 0-2 ⁿ -1 (for example, 0 to 63 when n = 6) is incremented by 1 for each cycle of a supplied clock signal (not shown), and the counted number is set as an n-bit signal NA. The data is sent to the comparison circuit 12. Note that the count number is 2 ⁿ After −1, it returns to 0. In addition to the signal NA, an n-bit signal NB is input from the adder 8 to the comparison circuit 12.
[0006]
The comparison circuit 12 is a circuit that performs on / off control of the PMOS transistor mp and the NMOS transistor mn constituting the buffer circuit 3, and control signals x1 and x2 from the comparison circuit 12 are respectively supplied to the gates of the transistors mp and mn. Have been supplied. The comparison circuit 12 sets the voltage levels of the control signals x1 and x2 to L level when the signal NA becomes 0, and sets the voltage levels of the control signals x1 and x2 to H level when the signal NA matches the signal NB. And
[0007]
In the buffer circuit 3, the first power supply voltage (here, VDD) at the H level is applied to the source of the PMOS transistor mp, and the second power supply voltage (here, ground) is applied to the source of the NMOS transistor mn. Voltage) is applied. The drains of both transistors mp and mn are connected to each other, and the connection node is the output terminal of the buffer circuit 3.
[0008]
Therefore, when the control signals x1 and x2 are at the L level, the PMOS transistor mp is turned on and the NMOS transistor mn is turned off, so that the output voltage of the buffer circuit 3 is equal to the first power supply voltage (VDD). On the other hand, when the control signals x1 and x2 are at the H level, the PMOS transistor mp is turned off and the NMOS transistor mn is turned on, so that the output voltage of the buffer circuit 3 becomes equal to the second power supply voltage (ground voltage). . That is, the output voltage of the buffer circuit 3 is a pulsed voltage signal v1 that rises when the signal NA is 0 and falls when the signal NA becomes equal to the signal NB.
[0009]
The voltage signal v1 is smoothed by the filter circuit 4 including the inductor l and the capacitor c to become the output voltage v2. This output voltage v2 is supplied to an internal circuit (not shown) formed on the same substrate and used as a drive voltage for the internal circuit. The output voltage v2 is also used as a power supply voltage for the critical path circuit 5.
[0010]
The time when the PMOS transistor mp constituting the buffer circuit 3 is turned on and the NMOS transistor mn is turned off (that is, the time when the control signals x1 and x2 are at the L level) is set as the on time T1, and the PMOS transistor mp is turned off. When the time when the NMOS transistor mn is turned on (that is, the time when the control signals x1 and x2 are at the H level) is the off time T2, the output voltage v2 of the filter circuit 4 is generally obtained by the following equation (1). be able to.
[0011]
v2 = (T1 / (T1 + T2)) * VDD (1)
Here, the on time T1 (right numerator) in the above equation represents the pulse width of the voltage signal v1, and the sum T1 + T2 (right side denominator) of the on time T1 and off time T2 is the voltage signal v1. Represents the pulse period. That is, in order to control the output voltage v2 to the minimum power supply voltage necessary for the operation of the integrated circuit, the ratio between the pulse width and the pulse period in the voltage signal v1 (hereinafter referred to as the duty ratio) is controlled. It will be understood that
[0012]
Therefore, in the voltage conversion circuit 1 configured as described above, the on-time T1 (pulse width) is changed by changing the value of the signal NB input from the adder 8 to the comparison circuit 12, and is output from the buffer circuit 3. The duty ratio of the voltage signal v1 is controlled. As a result, the drive voltage (output voltage v2) supplied to the internal circuit can be controlled. (Hereinafter, such a duty ratio control method is called a pulse width modulation (PWM) method.) Further, as a means for setting the signal NB to an optimum value, a method of detecting the operating speed of the critical path circuit 5 is adopted. Has been.
[0013]
The critical path circuit 5 is a circuit that duplicates a path circuit that is considered to have the largest signal delay among the internal circuits to which the output voltage v2 is supplied. As described above, the output voltage v2 of the filter circuit 4 is applied as the power supply voltage of the critical path circuit 5. That is, the drive voltage of the internal circuit that is the target of power supply is monitored by the critical path circuit 5. Here, it is assumed that the operable voltage of the critical path circuit 5 is the operable voltage of the internal circuit.
[0014]
When the critical path circuit 5 is operable by the output voltage v <b> 2 of the filter circuit 4, the critical path circuit 5 sends predetermined data to the correctness determination circuit 7. At this time, not only the data sent from the critical path circuit 5 is directly input to the correctness determination circuit 7, but also delay data obtained by delaying the data by a predetermined time by the delay circuit 6 is input.
[0015]
When data is not directly input from the critical path circuit 5 to the correctness determination circuit 7, the target internal circuit is not operating normally, that is, the drive voltage of the internal circuit (of the filter circuit 4). It is determined that the output voltage v2) is too low, and a signal s1 that increases the value of the signal NB by 1 is sent to the adder 8 in order to increase the drive voltage v2.
[0016]
On the other hand, when the delay data through the delay circuit 6 is input to the correctness determination circuit 7, the correctness determination circuit 7 operates normally even if a delay is given to the target internal circuit. That is, it is determined that the drive voltage of the internal circuit is too high, and a signal s2 for reducing the value of the signal NB by 1 is sent to the adder 8 in order to lower the drive voltage.
[0017]
Furthermore, when data is directly input from the critical path circuit 5 to the correctness determination circuit 7, but the delay data via the delay circuit 6 is not input, the correctness determination circuit 7 is not included in the target internal circuit. It is determined that the optimum driving voltage is supplied, and the signals s1 and s2 are not sent to the adder 8.
[0018]
When the signal s1 is input from the correctness determination circuit 7, the adder 8 supplies the duty ratio control circuit 2 with a value obtained by adding 1 to the current value of the signal NB. On the other hand, when the signal s2 is input from the correctness determination circuit 7, the adder 8 supplies the duty ratio control circuit 2 with a value obtained by adding -1 to the current value of the signal NB.
[0019]
As described above, in the voltage conversion circuit 1 configured as described above, the critical path circuit 5, the delay circuit 6, and the correctness determination circuit 7 detect the operating speed of the internal circuit that is the target of power supply, and the detected operating speed is The duty ratio of the voltage signal v1 is such that the drive voltage (output voltage v2) of the internal circuit is lowered when it is too fast, and the drive voltage of the internal circuit is raised when the detected operation speed is too slow. Is controlling.
[0020]
As described above, the voltage conversion circuit 1 using the circuit for detecting the operation speed of the critical path circuit 5 and the duty ratio control circuit 2 as shown in Japanese Patent Laid-Open No. 10-242831 is provided with the output voltage v2. It is understood that the variable range of the above is wide and useful as a step-down circuit of a general integrated circuit.
[0021]
However, in the above-described prior art, the counter circuit 11 used for controlling the duty ratio operates at a high speed at a frequency 64 times the frequency of the voltage signal v1, and thus has a problem of high power consumption by itself. . For example, when the frequency of the pulse voltage signal v1 is 1 MHz, the frequency is 64 MHz.
[0022]
In general, when the power supply voltage of the internal circuit is low or the load current is small, the power consumption of the entire integrated circuit is small, so that the power consumption ratio of the step-down circuit itself is relatively large. Therefore, it is necessary to reduce the power consumption of the step-down circuit itself, and the step-down circuit based on the above technique is disadvantageous when the internal circuit operates with a low power supply voltage. For example, the power consumption of an internal circuit using a device driven with a power supply voltage of 0.5V is 1/36 compared to the power consumption of an internal circuit using a device driven with a power supply voltage of 3V. Thus, when the power supply voltage and load current of the internal circuit are small, the influence of the step-down circuit on the power consumption becomes extremely large.
[0023]
There is also a problem that the scale of the circuit necessary for controlling the adder 8 and the like necessary for widening the variable range of the output voltage v2 increases. This leads to an increase in the circuit scale of the entire step-down circuit, which also causes an increase in power consumption of the step-down circuit itself.
[0024]
In view of the above, the present inventors have proposed a step-down circuit with a reduced circuit scale and power consumption suitable for lowering the output voltage in Japanese Patent Application Laid-Open Nos. 2002-153050 and 2002-223564. ing. FIG. 24 shows a voltage conversion circuit 21 according to those conventional techniques. 24, parts corresponding to those in FIG. 23 are given the same reference numerals, and descriptions thereof are omitted. In the voltage conversion circuit 21, the pulse signal generation circuit 22 drives the switch circuit 3. The pulse signal generation circuit 22 includes a reference pulse signal generation circuit 23, a delay circuit 24, a delay time control circuit 25, and a switch timing control circuit 26.
[0025]
The reference pulse signal v3 of a predetermined unit time generated by the reference pulse signal generation circuit 23 is given to the delay circuit 24, and a delay pulse signal v4 delayed by the delay time set by the delay time control circuit 24 is generated. Is done. The delayed pulse signal v4 is given to the switch timing control circuit 26, and the voltage levels of the control signals x1 and x2 are set to L level. The delayed pulse signal v4 is fed back to the reference pulse signal generation circuit 22 for triggering, and the reference pulse signal generation circuit 22 outputs the next reference pulse signal v3 in response to the delay pulse signal v4.
[0026]
Accordingly, in the switch circuit 3, the PMOS transistor mp is turned on only while the delayed delay pulse signal v4 is input, and thus the reference pulse signal of the predetermined unit time in the cycle of the delay time in the delay circuit 24. The switch circuit 3 is driven by pulse frequency modulation (PFM) that is on-duty only during the period of v3, and the shorter the delay time set by the delay time control circuit 24, the higher the frequency and thus the output voltage v2 becomes higher. .
[0027]
[Patent Document 1]
JP 10-242831 A (publication date: September 11, 1998)
[0028]
[Patent Document 2]
JP 2002-153050 A (publication date: May 24, 2002)
[0029]
[Patent Document 3]
JP 2002-223564 A (publication date: August 9, 2002)
[0030]
[Problems to be solved by the invention]
The above-described conventional technique does not require the high-speed counter circuit 11 as described in JP-A-10-242831, and realizes a voltage conversion circuit that is small in circuit scale and power consumption and suitable for lowering the output voltage. be able to. However, in JP-A-10-242831, the control signals x1 and x2 are subjected to pulse width modulation, whereas in these JP-A-2002-153050 and JP-A-2002-223564, pulses are used as described above. Frequency modulated.
[0031]
Here, the ripple voltage of the output voltage varies depending on the pulse frequency and is inversely proportional to the square of the pulse frequency. Therefore, the longer the delay time and the longer the pulse period, the larger the ripple voltage. Then, although not shown in FIG. 24, an error may occur in the determination result of the replica circuit referred to when the delay time control circuit 24 determines the delay time, and the internal circuit that supplies the output voltage v2 There is a problem that operation becomes unstable.
[0032]
An object of the present invention is to provide a voltage conversion circuit with a small circuit size and low power consumption suitable for lowering the output voltage while stabilizing the operation of the internal circuit, and a semiconductor integrated circuit device and a portable terminal including the voltage conversion circuit. is there.
[0033]
[Means for Solving the Problems]
In the voltage conversion circuit of the present invention, the switch circuit switches the power supply voltage, smooths and outputs the output voltage, and the pulse signal generation circuit generates a switch pulse signal for obtaining a desired output voltage, In the voltage conversion circuit provided to the transistor of the switch circuit, the pulse signal generation circuit includes a reference pulse signal generation circuit that generates a reference pulse signal serving as a reference at a constant frequency, and a delay that delays the reference pulse signal. A delay time control circuit for setting a delay time in the delay circuit, a delay time control circuit for detecting a transition between the delay pulse signal from the delay circuit and the reference pulse signal, and a time corresponding to the delay time in the delay circuit And a drive circuit for generating the switch pulse signal having a width and driving the transistor.
[0034]
According to the above configuration, in the voltage conversion circuit realized as a step-down converter or the like formed in the integrated circuit, when generating the switch pulse signal to be applied to the control terminal of the transistor of the switch circuit, the pulse signal generation circuit is A reference pulse signal generation circuit that generates a reference pulse signal serving as a reference at a constant frequency, a delay circuit that delays the reference pulse signal, a delay time control circuit that sets a delay time in the delay circuit, and the delay circuit A drive circuit that detects a transition between the delayed pulse signal from the reference pulse signal and the reference pulse signal, generates the switch pulse signal having a time width corresponding to a delay time in the delay circuit, and supplies the switch pulse signal to the transistor To do.
[0035]
Therefore, by controlling the delay time of the delay circuit, the pulse width of the switch pulse signal can be changed, and thus the output voltage can be controlled by pulse width modulation (duty control), and the ripple voltage of the output voltage. Can be kept constant. As a result, the operation of the internal circuit that supplies the output voltage can be stabilized. In addition, such pulse width modulation control can be realized by a delay circuit configured by a shift register or a drive circuit configured by a logic circuit, so that a high-speed counter circuit is not required, and the circuit scale In addition, it is possible to realize a voltage conversion circuit that consumes less power and is suitable for lowering the output voltage.
[0036]
In the voltage conversion circuit of the present invention, the delay circuit can receive a basic delay circuit that delays the reference pulse signal by a predetermined time and an output signal from the basic delay circuit, and take out an internal signal thereof. An additional delay circuit having one or a plurality of output terminals that can be selected, and one of an output signal from the basic delay circuit or an output signal from each output terminal of the additional delay circuit is selected and output as the delayed pulse signal The delay time control circuit causes the drive circuit to generate a switch pulse signal having a time width for obtaining the desired output voltage by selectively controlling the selection circuit. It is characterized by.
[0037]
According to the above configuration, the delay time can be adjusted largely by the basic delay circuit, and the delay time can be finely adjusted by the additional delay circuit, so that the delay time and therefore the output can be reduced with a small number of selected channels (number of selected data bits). The voltage can be changed greatly and can be finely adjusted.
[0038]
Furthermore, in the voltage conversion circuit of the present invention, the delay circuit receives a basic delay circuit that delays the reference pulse signal by a predetermined time and an output signal from the basic delay circuit, and takes out an internal signal thereof. An additional delay circuit having one or a plurality of output terminals, and a first selection circuit that selects one of an output signal from the basic delay circuit or an output signal from each output terminal of the additional delay circuit; The output signal from the first selection circuit is delayed for an arbitrary time, the arbitrary time delay circuit having one or a plurality of output terminals, and the output signal from the first selection circuit or each output of the arbitrary time delay circuit A second selection circuit that selects one of the output signals from the terminals and outputs the selected signal as the delayed pulse signal, and the delay time control circuit includes the first and second selection circuits. By selecting the control, to the drive circuit, characterized in that to produce a switch pulse signal having a time width to obtain an output voltage to said desired.
[0039]
According to the above configuration, the delay time is largely adjusted by the basic delay circuit, the delay time is finely adjusted by the additional delay circuit, and the delay time is finely adjusted by the number of selection channels (number of selected data bits) of the first selection circuit. The delay time can be further finely adjusted by the second selection circuit and the arbitrary time delay circuit. Therefore, highly accurate output voltage control is possible.
[0040]
The voltage conversion circuit of the present invention applies the smoothed output voltage lower than the power supply voltage as a power supply voltage for the reference pulse signal generation circuit, the delay circuit, the delay time control circuit, and the drive circuit. The drive circuit includes a boost level shifter, a start signal generation circuit, and a start control circuit, and the switch circuit forcibly switches the power supply voltage by these circuits driven by the input power supply voltage, A power supply voltage to the reference pulse signal generation circuit, delay circuit, delay time control circuit, and drive circuit is raised.
[0041]
According to the above configuration, in a voltage conversion circuit used as a step-down converter, a boost level shifter is provided, and the circuit is mainly configured by a logic circuit other than a portion that requires a high voltage by driving a transistor of a switch circuit. A smoothed output voltage is applied to the power supply voltages of the reference pulse signal generation circuit, the delay circuit, the delay time control circuit, and the drive circuit, thereby reducing the power consumption of the voltage conversion circuit itself.
[0042]
On the other hand, if the output voltage of the voltage conversion circuit is used as a power supply, it will not start after it has stopped operating for a long time, so a start signal generation circuit and a start control circuit are further provided. By these circuits driven by the input power supply voltage, the switch circuit is forcibly switched at the time of startup, and the power supply voltage to the reference pulse signal generation circuit, the delay circuit, the delay time control circuit and the drive circuit is raised. In this way, the power consumption of the voltage conversion circuit itself can be reduced without causing a start-up failure.
[0043]
Furthermore, in the voltage conversion circuit of the present invention, the delay circuit, the basic delay circuit, the additional delay circuit, and the arbitrary time delay circuit are connected in series with one or more unit time delay elements that perform a unit time delay. It is characterized by comprising.
[0044]
According to the above configuration, the configuration of the delay circuit is simplified and the design can be easily changed.
[0045]
In the voltage conversion circuit of the present invention, the unit time delay element is a flip-flop circuit.
[0046]
According to said structure, the setting of delay time becomes easy and the design of the said delay circuit becomes easy.
[0047]
Furthermore, in the voltage conversion circuit according to the present invention, the drive circuit includes a switch pulse generation circuit and a switch control circuit including a buffer circuit, and the switch pulse generation circuit includes a flip-flop circuit. It is characterized by being.
[0048]
According to said structure, the circuit structure of the switch pulse generation circuit which comprises the said drive circuit can be simplified.
[0049]
In the voltage conversion circuit of the present invention, the switch circuit includes a series circuit of a P-type transistor and an N-type transistor connected in series between a pair of power supply lines, and the drive circuit has an arbitrary delay time. AND operation of two delay circuits connected in series with each other, an inverter circuit that logically negates the output of the first-stage delay circuit, and a logical OR operation of the input signal and the output signal of the second-stage delay circuit An output of the inverter circuit is output as a first control signal to the control terminal of the P-type transistor of the switch circuit, and the output of the OR circuit of the logical sum is a second control signal. A switch pulse generation circuit that outputs a control signal to a control terminal of an N-type transistor of the switch circuit is provided.
[0050]
According to the above configuration, in controlling a switch circuit in which a series circuit of a P-type transistor and an N-type transistor is connected in series between a pair of power supply lines, the N-type transistor is turned on in response to an input signal. After switching to OFF, the P-type transistor is switched from OFF to ON with a delay of the delay time of the first-stage delay circuit, and after the P-type transistor is switched from ON to OFF, The N-type transistor is switched from off to on after a delay time.
[0051]
Therefore, the two delay times are dead times in which the two transistors are not turned on at the same time, the through current of the switch circuit can be suppressed, and the power consumption of the voltage conversion circuit itself can be reduced.
[0052]
Furthermore, in the voltage conversion circuit of the present invention, the delay time control circuit detects the operation speed of an internal circuit supplied with the output voltage as a power supply voltage in synchronization with a clock signal supplied from the outside. And a signal indicating the operation speed output from the replica circuit as an input signal, and a selection signal for selecting one output terminal among the plurality of output terminals of the delay circuit according to the detected operation speed. And a selection signal generation circuit for outputting.
[0053]
According to the above configuration, the operation state of the internal circuit constituting the integrated circuit can be detected by the replica circuit, and the minimum driving voltage necessary for the operation of the internal circuit can be supplied, thereby reducing the power consumption of the integrated circuit. Can contribute.
[0054]
In the voltage conversion circuit of the present invention, the replica circuit includes an operation state detection pulse generation circuit that generates a pulse for detecting an operation state, and the input pulse from the operation state detection pulse generation circuit In the internal circuit, the delay is equivalent to that of the path circuit considered to have the largest signal delay, the critical path circuit divided into a plurality of parts, and the pulse signal output from each part of the critical path circuit And a latch circuit that latches in response to a pulse from the operation state detection pulse generation circuit and sends the output signal to the selection signal generation circuit as an operation state signal.
[0055]
According to the above configuration, for example, when the critical path circuit is divided into two and the latch timing of the latch circuit is set to the half cycle and one cycle of the pulse from the operation state detection pulse generation circuit, the critical path circuit When the entire output pulse follows within a half cycle of the pulse from the operating state detection pulse generation circuit, it can be determined that the operating frequency of the internal circuit is too high, that is, the output voltage is too high, If the output pulse of the first half of the critical path circuit does not follow within one cycle of the pulse from the operation state detection pulse generation circuit, the operating frequency of the internal circuit is too low, that is, the output voltage is too low. The output pulse in the first half of the critical path circuit is a pulse from the operation state detection pulse generating circuit. If the output pulse in the latter half does not follow within the half cycle and follows within one cycle, the operating frequency of the internal circuit is optimal, that is, the output voltage Can be determined to be optimal, the output pulse of the first half of the critical path circuit does not follow within the half cycle of the pulse from the operation state detection pulse generation circuit, and the output pulse of the second half follows within one cycle. In this case, it can be determined that the internal circuit is operable at present, but becomes inoperable with a slight environmental change, that is, it is preferable that the output voltage is slightly higher.
[0056]
If the operating frequency of the internal circuit is too high, that is, if the output voltage is too high, the delay time is shortened, and if the operating frequency is too low, that is, if the output voltage is too low, the delay time. If the operating frequency is optimal, i.e., the output voltage is optimal, the delay time is maintained and operation is possible, but the operating frequency is slightly lower, i.e., if the output voltage is slightly higher, it is preferable By increasing the delay time, the output voltage can be optimally controlled.
[0057]
As described above, various operation states can be detected and optimum control can be performed by setting the number of divisions of the critical path circuit and the number of latch timings of the latch circuit. When the operation state of the critical path circuit is classified into four as described above, it becomes possible to detect the operation state of the internal circuit in detail, can appropriately cope with any process variation and environmental change, and the optimum output voltage. Can contribute to lower power consumption of the entire integrated circuit.
[0058]
Furthermore, in the voltage conversion circuit of the present invention, the critical path circuit is divided into two, and the latch circuit converts the pulse signal output from the first half critical path circuit into a half of the pulse from the operation state detection pulse generation circuit. A first latch circuit that latches after a period; a second latch circuit that latches a pulse signal output from the second half critical path circuit after a half period of a pulse from the operation state detection pulse generation circuit; and the second half critical path circuit And a third latch circuit that latches the pulse signal output from the operation state detection pulse generation circuit after one cycle of the pulse from the operation state detection pulse generation circuit.
[0059]
According to said structure, it determines with the said critical path circuit itself being in the state which is not operating | operating other than the above-mentioned 4 operation state from the output of 8 types of combinations from 3 latch circuits. Therefore, the internal circuit can be operated more stably. In addition, since a failure or the like of the replica circuit can be detected at an early stage, it is possible to perform a quick post-treatment.
[0060]
In the voltage conversion circuit of the present invention, the selection signal generation circuit includes a flag signal generation circuit that generates a flag signal that represents a history of the operation state of the replica circuit, and the replica circuit depends on a value of the flag signal. One of a delay time increasing / decreasing operation required from the output signal and a different delay time increasing / decreasing operation are selected, and an output terminal of the delay circuit is selected.
[0061]
According to said structure, the control function of an output voltage can be improved by introduce | transducing the flag signal showing the log | history of the operation state of the said replica circuit. For example, if the operation frequency of the replica circuit is too high or too low, the target is obtained by increasing or decreasing the delay time required from the output signal of the replica circuit regardless of the value of the flag signal. The operating frequency (output voltage) can be quickly changed. On the other hand, referring to the flag signal near the target operating frequency, for example, when it is required to maintain the delay time from the output signal of the replica circuit, if the delay time is increased, the delay time is increased. It corresponds to the minimum voltage required for the internal circuit and maintains the delay time, but if the delay time has been reduced, it is further reduced to the minimum voltage. Unlike the operation for maintaining the delay time required from the output signal of the replica circuit, the decreasing operation is further continued.
[0062]
In this way, the output voltage can be maintained at the minimum voltage at which the internal circuit operates stably, and the power consumption can be minimized.
[0063]
Furthermore, a semiconductor integrated circuit device according to the present invention includes the voltage conversion circuit.
[0064]
According to the above configuration, the power consumption ratio of the step-down circuit relative to the power consumption of the entire integrated circuit has been relatively increased in recent years with the reduction in power consumption of the internal circuits constituting the semiconductor integrated circuit device. By using the voltage conversion circuit configured as described above as the step-down circuit that generates the drive voltage of the semiconductor integrated circuit device from the external power supply voltage, the power consumption of the step-down circuit itself can be reduced, and the low power consumption of the internal circuit This can contribute to the reduction in power consumption of the entire semiconductor integrated circuit device without impairing the above.
[0065]
In addition, a portable terminal of the present invention includes the semiconductor integrated circuit device described above.
[0066]
According to the above configuration, in recent years, there has been an increasing demand for longer driving time of the mobile terminal, and a semiconductor integrated circuit device equipped with a voltage conversion circuit having the above configuration is used as a signal processing LSI or the like in a mobile terminal. By using it, it is possible to contribute to lower power consumption of the entire mobile terminal.
[0067]
DETAILED DESCRIPTION OF THE INVENTION
The following describes the first embodiment of the present invention with reference to FIGS.
[0068]
FIG. 1 is a block diagram showing an electrical configuration of a voltage conversion circuit 31 according to the first embodiment of the present invention. The voltage conversion circuit 31 is a step-down circuit that is formed in a semiconductor integrated circuit device mounted on a portable terminal or the like, and steps down the power supply voltage VDD supplied from the outside to the power supply voltage V2 of the internal circuit and outputs it. The voltage conversion circuit 31 is generally configured to include a pulse signal generation circuit 32, a switch circuit 33, and a filter circuit 34.
[0069]
The pulse signal generation circuit 32 is a circuit for generating control signals X1 and X2 having a desired duty ratio, as will be described later, and the control signals X1 and X2 are given to the switch circuit 33. Similar to the conventional switch circuit 4, the switch circuit 33 is configured by connecting a series circuit of a PMOS transistor MP and an NMOS transistor MN in series between a pair of power supply lines, and a control signal from the pulse signal generation circuit 32. In response to X1 and X2, the MOS transistors MP and MN perform a reciprocal operation, and output a voltage signal V1 obtained by switching the power supply voltage VDD to the filter circuit 34. The source terminal of the PMOS transistor MP is connected to the external power supply VDD, the source terminal of the NMOS transistor MN is connected to the ground GND, and the control signal X1 from the pulse signal generation circuit 32 is connected to the gate terminals of these transistors MP and MN, respectively. , X2 are input, the drain terminal becomes the output terminal, and the pulsed voltage signal V1 is output.
[0070]
The voltage signal V1 is applied to one terminal of the inductor L of the filter circuit 34, and the other terminal of the inductor L serves as an output terminal to output the output voltage V2 and is supplied to each internal circuit. A capacitor C is interposed between the ground GND. Accordingly, when the PMOS transistor MP is turned on, the NMOS transistor MN is turned off, the voltage from the external power supply VDD is output to the output terminal, and magnetic energy is accumulated in the inductor L. When the PMOS transistor MP is turned off, the NMOS transistor MN is turned off. The transistor MN is turned on, and the magnetic energy stored in the inductor L is output via the NMOS transistor MN. The capacitor C smoothes the output voltage V2.
[0071]
Thus, when the control signals X1 and X2 from the pulse signal generation circuit 32 are input, the PMOS transistor MP and the NMOS transistor MN alternately turn on and off, and the output voltage signal V1 is smoothed by the filter circuit 34. Thus, a desired internal power supply voltage V2 can be obtained, and the filter circuit 34 functions as a low-pass filter (hereinafter referred to as LPF). Here, an LC circuit is used as the LPF, but of course, any configuration such as an RC circuit may be used.
[0072]
It should be noted that the voltage conversion circuit 31 includes a reference pulse signal generation circuit 41, a delay circuit 42, a delay time control circuit 43, and a drive circuit 44. The drive circuit 44 includes a switch pulse generation circuit 45 and a switch control circuit 46. The reference pulse signal V3 generated by the reference pulse signal generation circuit 41 and output at a predetermined frequency (period) and having a predetermined unit time sufficiently shorter than the pulse period is supplied to the delay circuit 42, and the delay time control circuit 43 A delayed pulse signal V4 delayed by the delay time set in is generated.
[0073]
The delayed pulse signal V4 and the reference pulse signal V3 are supplied to a switch pulse generation circuit 45 of the drive circuit 44. The switch pulse generation circuit 45 detects the transition of the pulse signals V3 and V4, and the reference pulse A switch pulse V5 that becomes active at the active timing of the signal V3 and becomes inactive at the active timing of the delayed pulse signal V4 is generated. Therefore, the switch pulse V5 is a pulse-width-modulated signal that is active at a constant frequency for the delay time set by the delay time control circuit 43.
[0074]
The switch pulse V5 is supplied to the switch control circuit 46. In the configuration of FIG. 1, the control signals X1 and X2 are set to L level, and the power supply voltage VDD is supplied to the switch circuit 33 only during the active period of the switch pulse V5. In the remaining inactive period, the control signals X1 and X2 are set to the H level to output the GND potential.
[0075]
FIG. 2 is a block diagram showing a configuration example of the delay circuit 42. The delay circuit 42 includes a basic delay circuit 47, an additional delay circuit 48, and a selection circuit 49.
[0076]
The basic delay circuit 47 is composed of an arbitrary M-stage flip-flop and the like, and is a circuit that delays the input reference pulse signal V3 by M times a unit time. The additional delay circuit 48 is similarly composed of an arbitrary N-stage flip-flop and the like. The additional delay circuit 48 receives the output signal of the basic delay circuit 47 as an input, and delays the input signal by N times the unit time. This is a circuit having a terminal for taking out an output having a delay time which is an integer multiple of a unit time from time to N unit time. In FIG. 2, the flip-flop having a simple configuration is used as a specific example of the circuit for delaying by a unit time. Of course, the type of flip-flop is not limited, and a delay circuit having another configuration may be used.
[0077]
In response to the selection signal given from the delay time control circuit 43, the selection circuit 49 is drawn from the output terminal of the basic delay circuit 47 and each output terminal of the additional delay circuit 48 in the configuration of FIG. This is a circuit that selects one delay signal from a plurality of delay signals and outputs it as the delay pulse signal V4. The delay time control circuit 43 is a circuit that generates a signal for controlling the delay time of the delay circuit 42 according to the determination result of the replica circuit of the critical path circuit, the output voltage V2, and the like. A delay time, that is, an active period of the switch pulse V5 is set.
[0078]
The reference pulse signal generation circuit 41 uses the internal clock signal ICLK, and generates a reference pulse signal V3 having a pulse width corresponding to one clock of the internal clock signal ICLK at regular intervals. Any circuit configuration may be used for the reference pulse signal generation circuit 41 as long as a pulse signal having a pulse width corresponding to one clock of the internal clock signal ICLK can be generated every fixed period. For example, a low-speed counter circuit that counts the internal clock signal ICLK is used. The counter circuit counts up and outputs a pulse for one clock cycle in which all bits of the counter are “H”. After “H”, a circuit that resets and performs counting again may be used.
[0079]
The selection circuit 49 receives the control signal received from the delay time control circuit 43 from the output D0 of the flip-flop at the final stage of the basic delay circuit 47 and the outputs D1 to D3 of the flip-flops at the respective stages of the additional delay circuit 48. Select the output corresponding to. The internal clock signal ICLK is also a clock signal for driving the shift register that constitutes the basic delay circuit 47 and the additional delay circuit 48. The internal clock signal ICLK is given from the outside of the integrated circuit, and divides the external clock signal. It may be generated by any means such as that obtained by the above, or generated by an oscillation circuit inside the integrated circuit.
[0080]
FIG. 3 is a block diagram showing a specific configuration example of the switch pulse generation circuit 45. As described above, the switch pulse generation circuit 45 detects the transition between the input delay pulse signal V4 and the reference pulse signal V3, and generates the switch pulse V5 having a time width corresponding to the delay time in the delay circuit 42. This circuit can be realized by using an SR latch. As shown in FIG. 3, the SR latch is composed of two inverters INV1 and INV2 and two NAND gates G1 and G2, and since the circuit configuration is simple, the SR latch is easy to implement. Of course, a latch circuit other than the SR latch may be used.
[0081]
FIG. 4 is a block diagram showing a specific configuration example of the switch control circuit 46. The switch control circuit 46 provides buffer circuits BUF1 and BUF2 for giving the switch pulse V5 generated by the switch pulse generation circuit 45 sufficient driving force to drive the gate terminals of the PMOS transistor MP and NMOS transistor MN. It is configured with.
[0082]
FIG. 5 is a waveform diagram for explaining the operation of the delay circuit 42 and the switch pulse generation circuit 45 in the voltage conversion circuit 31 configured as described above. As shown in FIG. 2, the following description will be made assuming that the delay stage number M = 6 of the basic delay circuit 47 and the delay stage number N = 3 of the additional delay circuit 48. Therefore, basic delay circuit 47 and additional delay circuit 48 employ a shift register configuration in which six and three flip-flops are connected in series, respectively. The output of the final flip-flop of the basic delay circuit 47 is D0, and the outputs of the three flip-flops constituting the additional delay circuit 48 are D1, D2, and D3 from the input side, respectively.
[0083]
Here, it is assumed that the reference pulse signal V3 from the reference pulse signal generation circuit 41 is a signal that outputs a pulse every 32 cycles of the internal clock signal ICLK. Therefore, the delayed pulse signal V4 is indicated by a broken line in FIG. 5 after the reference pulse signal V3 is delayed by M unit time (here, 6 unit time) by the basic delay circuit 47 as shown by a solid line in FIG. As described above, the pulse signal is delayed by N unit time (here, 0 to 3 unit time) by the additional delay circuit 48. That is, the delay time of the pulse can be changed between M and (M + N) unit time by the control signal of the delay time control circuit 43, and in the configuration of FIG. 2, it becomes 6 to 9 unit time.
[0084]
The switch pulse generation circuit 45 is configured to be “H” at the rising edge of the reference pulse signal V3 and to be “L” at the rising edge of the delay pulse signal V4. The switch pulse V5 generated here is delayed. The pulse signal has a pulse width Pw corresponding to the delay time of the pulse signal V4. That is, if the pulse is delayed by M + N unit time, the pulse width is M + N. Here, since the pulse period T is 32, the duty ratio is (M + N) / 32, and the internal power supply voltage V2 is
V2 = ((M + N) / 32) * VDD
It becomes.
[0085]
For example, in the case of FIG. 5, assuming that the power supply voltage VDD is 2V, when N is 0, the duty ratio is 6/32, so the internal power supply voltage V2 is 375 mV. When N is 1, the duty ratio is 7/32 and the internal power supply voltage V2 is 437.5 mV. When N is 2, the duty ratio is 8/32 and the internal power supply voltage V2 is 500 mV. When N is 3, the duty ratio is 9/32 and the internal power supply voltage V2 is 562.5 mV. That is, in this case, the variable width of the internal power supply voltage V2 by selecting the output terminal of the delay circuit 42 is 187.5 mV.
[0086]
As described above, according to the voltage conversion circuit 31 of the present invention, although the number of selectable output voltages V2 is limited by the number of selection channels of the selection circuit 49, the high-speed counter 11 in the prior art of FIG. It is possible to control the internal power supply voltage V2 without using a control circuit. As a result, the circuit scale of the voltage conversion circuit can be reduced and the operating frequency, and hence the power consumption of the voltage conversion circuit 31, can be reduced as compared with the prior art, so that the circuit scale suitable for lowering the output voltage V2 can be reduced. A voltage conversion circuit with low power consumption can be realized.
[0087]
Further, since the pulse period T, that is, the pulse frequency is constant and the pulse width (duty ratio) is changed, the ripple voltage of the output voltage V2 is always constant. FIG. 1 and FIG. Although not shown, no error occurs in the determination result of the replica circuit referred to when the delay time control circuit 42 determines the delay time, and the operation of the internal circuit that supplies the output voltage V2 can be stabilized.
[0088]
Furthermore, the delay circuit 42 includes a basic delay circuit 47 and an additional delay circuit 48, the delay time is largely adjusted by the basic delay circuit 47, and the delay time is finely adjusted by the additional delay circuit 48. The selection circuit 49 can greatly change the delay time, and hence the output voltage V2, with a small number of selected channels, and can also finely adjust the delay time.
[0089]
The following describes the second embodiment of the present invention with reference to FIGS.
[0090]
FIG. 6 is a block diagram showing an electrical configuration of the voltage conversion circuit 51 according to the second embodiment of the present invention. The voltage conversion circuit 51 is similar to the voltage conversion circuit 31 shown in FIG. 1 described above, and the corresponding parts are denoted by the same reference numerals and description thereof is omitted. It should be noted that in this voltage conversion circuit 51, the adjustment unit of the delay time in the delay circuit 62 of the pulse signal generation circuit 52 is small. The pulse signal generation circuit 52 includes the reference pulse signal generation circuit 41, the delay circuit 62, a delay time control circuit 63, the switch pulse generation circuit 45, and the switch control circuit 46. Yes.
[0091]
The delay circuit 62 includes the basic delay circuit 47, the additional delay circuit 48, and a selection circuit 64. As described above, the basic delay circuit 47 is a circuit that delays the input reference pulse signal V3 and delays it by M times the unit time. As described above, the additional delay circuit 48 also receives the output signal of the basic delay circuit 47 and delays the input signal by N times the unit time, while the unit time from 1 unit time to N unit time. This is a circuit having a plurality of terminals for taking out an output having a delay time that is an integer multiple of.
[0092]
On the other hand, the selection circuit 64 includes the selection circuit 49 that is a first selection circuit, a selection circuit 65 that is a second selection circuit, and an arbitrary time delay circuit 66. The selection circuit 49 responds to the first selection signal given from the delay time control circuit 63 and, as described above, the output terminal of the final stage flip-flop of the basic delay circuit 47 and each stage of the additional delay circuit 48. This is a circuit that selects and outputs one delay signal among a plurality of delay signals drawn from the output terminal of the flip-flop.
[0093]
On the other hand, the second selection circuit 65 responds to the second selection signal given from the delay time control circuit 63, and outputs the output signal of the first selection circuit 49 and the output signal of the arbitrary time delay circuit 66. Among these, it is a circuit that selects and outputs one signal. The arbitrary time delay circuit 66 is provided with a plurality of terminals that take the output signal of the first selection circuit 64 as an input, perform a delay set by an external control signal or set in advance internally, and extract a delay output. Circuit. The delay time control circuit 63 is a circuit that generates a signal for controlling the delay time of the delay circuit 62, and the internal circuit determines whether or not the internal circuit is in accordance with the determination result of the replica circuit of the critical path circuit as will be described later, the output voltage V2 A delay time of the delay pulse signal V4 for stable operation, that is, an active period of the switch pulse V5 is set.
[0094]
FIG. 7 is a block diagram showing a specific example of the configuration of the delay circuit 62. Parts corresponding to those in FIG. 2 are denoted by the same reference numerals. It should be noted that in the selection circuit 64, the output signal from the first selection circuit 49 is supplied to the switch pulse generation circuit 45 via the second selection circuits 65a and 65b sequentially. In each of the selection circuits 65a and 65b, whether or not to pass through the flip-flop 66a of the negative edge trigger as the arbitrary time delay circuit 66 and the flip-flop 66b is selected. Here, although the flip-flop having a simple configuration is used as the arbitrary time delay circuit 66, of course, the type of the flip-flop is not limited, and a delay circuit having another configuration may be used.
[0095]
In response to the first selection signals S0, S1 from the delay time control circuit 66, the first selection circuit 49 is one of the outputs D0, D1, D2, D3 of the basic delay circuit 47 and the additional delay circuit 48. One is selected and input to the second selection circuit 65a and the flip-flop 66a in the first stage. The flip-flop 66 a performs a delay operation for the half cycle of the internal clock signal ICLK with respect to the output signal from the first selection circuit 49. Then, the second selection circuit 65a outputs either the direct output signal from the first selection circuit 49 or the output signal delayed by a half cycle by the flip-flop 66a from the delay time control circuit 66. The selection is made in response to the second selection signal SH.
[0096]
Similarly, the flip-flop 66b latches the output signal from the second selection circuit 65a with the internal clock ICLK2. The internal clock ICLK2 has a frequency twice that of the internal clock ICLK. Therefore, the flip-flop 66b is 1/4 of the internal clock signal ICLK with respect to the output signal from the second selection circuit 65a. A delay operation for a period is performed. The second selection circuit 65b in the second stage uses either the output signal of the second selection circuit 65a or the output signal obtained by delaying the output signal by a ¼ cycle by the flip-flop 66b as the delay time control circuit. Selection is made in response to the second selection signal SQ from 66.
[0097]
Therefore, the delay time control circuit 63 uses the first selection signals S0 and S1 for selecting any one of the outputs D0, D1, D2 and D3, and the second circuit for selecting the signal delayed by a half cycle in the selection circuit 64. A selection signal SH and a second selection signal SQ for selecting a signal delayed by a quarter cycle are output. As the delay pulse signal V4 from the delay circuit 62, if one of the outputs D0, D1, D2 and D3 is to be selected as it is, for example, the second selection signals SH and SQ may be set to “L”. If it is desired to delay the cycle, only the second selection signal SH is set to “H”. If it is desired to delay the quarter cycle, only the second selection signal SQ is set to “H”. Both the selection signals SH and SQ may be set to “H”.
[0098]
In this way, in the voltage conversion circuit 51, the variable accuracy of the internal power supply voltage V2 is four times that of the voltage conversion circuit 31. That is, the variable width of the delay of the delayed pulse signal V4 is subdivided every ¼ period instead of every period of the internal clock ICLK. Thus, the variable accuracy of the output voltage V2 can be greatly improved by a slight circuit change in which the flip-flops 66a and 66b and the second selection circuits 65a and 65b are added.
[0099]
FIG. 8 is a block diagram showing a specific configuration example of the delay time control circuit 63. The delay time control circuit 63 is generally configured to include a replica circuit 71 and a selection signal generation circuit 72.
[0100]
The replica circuit 71 includes an operation state detection pulse generation circuit 73, a critical path circuit 74, and a latch circuit 75. In general, the replica circuit 71 inputs the pulse signal generated by the operation state detection pulse generation circuit 73 to the critical path circuit 74, and responds to the pulse signal output from the critical path circuit 74 by the latch circuit 75. The signal is latched and the output signal is sent to the selection signal generation circuit 72 as an operation state signal.
[0101]
The operation state detection pulse generation circuit 73 is a circuit that generates a pulse signal to be input to a critical path circuit 74 described later, and generates a pulse signal from a desired operation clock signal that drives an internal circuit.
[0102]
The critical path circuit 74 is a circuit that performs a delay equivalent to a critical path of an internal circuit, that is, a path circuit that is considered to have the largest signal delay. In order to cope with process variations and operating environment changes, Created using the same process technology. Therefore, as the power supply voltage of the critical path circuit 74, the output voltage V2 of the filter circuit 34 is applied. That is, the critical path circuit 74 monitors the power supply voltage V2 of the internal circuit, and its output signal indicates the operating state of the internal circuit. The circuit used as the critical path circuit 74 is preferably a so-called inverter chain in which a plurality of inverter circuits are connected in series. However, a NAND circuit or a NOR circuit may be used instead of the inverter circuit.
[0103]
FIG. 9 is a block diagram showing a specific configuration example of the replica circuit 71. In general, in a replica circuit, it is monitored whether the critical path circuit can output a pulse signal within a desired time, that is, within one period of the operating frequency. If the pulse signal can be detected, “operation is possible” (hereinafter referred to as “OK”). If the signal cannot be detected, a signal indicating “operation not possible” (hereinafter “NG”) is output.
[0104]
In the present invention, in order to achieve more optimal control, “overspeed” (hereinafter referred to as “Fast”) in which the operation speed of the critical path circuit 74 is too high and “NG” is output during operation with a slight environmental change. Add detection of “danger” (hereinafter “Warn”), which is a state that is judged to be possible, and detect four states of “OK”, “NG”, “Fast”, “Warn” It was.
[0105]
In order to detect the above four operating states, the critical path circuit 74 with a delay time of 1 is divided into two parts, a first-half critical path circuit 74a and a second-half critical path circuit 74b, and the respective delay times are set. 0.5 + α and 0.5−α. That is, the delay time of the first half critical path circuit 74a is divided to be slightly longer than the delay time of the second half critical path circuit 74b. Then, the replica circuit 71 may detect the operation state immediately before selecting the delay pulse signal V4 of the delay circuit 62. That is, the operation state of the internal circuit corresponding to the current power supply voltage V2 is detected, and the output to be selected next as the delayed pulse signal V4 in the selection circuit 64 is determined.
[0106]
FIG. 10 is a signal waveform diagram of the operation state detection pulse generation circuit 73. The operation state detection pulse generation circuit 73 includes flip-flops 73a, 73b, 73c and AND gates 73d, 73e. First, the input signal RepEnb is input to a flip-flop 73a driven by an external operation clock signal ECLK which is an operation clock signal of the internal circuit. The output signal RPL of the flip-flop 73a is input to the critical path circuit 74, and input to the negative edge trigger flip-flop 73b and the positive edge trigger flip-flop 73c driven by the operation clock signal ECLK.
[0107]
Therefore, the output N1 of the negative edge trigger flip-flop 73b is a signal that is inverted by delaying the signal RPL by a half cycle of the operation clock signal ECLK, and the output N2 of the positive edge trigger flip-flop 73c is the signal RPL. Thus, the operation clock signal ECLK is delayed by one cycle and inverted. As a result, the logical product signal of the signal N1 and the signal RPL from the AND gate 73d becomes a pulse signal EV1 having a pulse width corresponding to a half cycle of the operation clock signal ECLK of the internal circuit. The logical product signal of the signal N2 from the AND gate 73e and the signal RPL is a pulse signal EV2 having a pulse width corresponding to one cycle of the operation clock signal ECLK of the internal circuit. These pulse signal EV1 and pulse signal EV2 are used as signals for latching output signals RA and RB of the first-half critical path circuit 74a and second-half critical path circuit 74b, respectively, as will be described later.
[0108]
Finally, the replica circuit 74 has a latch circuit 75a that latches the signal RA from the first half critical path circuit 74a with the negative edge of the pulse signal EV1, and a latch circuit 75b from the second half critical path circuit 74b. The signal LB obtained by latching the signal RB with the negative edge of the pulse signal EV1 and the signal LC obtained by latching the signal RB with the negative edge of the pulse signal EV2 by the latch circuit 75c are output to the selection signal generation circuit 72. .
[0109]
FIG. 11 is a signal waveform diagram showing a method for determining each operation state in the replica circuit 71. When it is first determined to be “Fast” in response to the signals RPL, EV1, and EV2 shown in FIG. 11A, as shown in FIG. 11B, the output signal RA of the first half critical path circuit 74a. Is latched to the “H” level by the latch circuit 75a at the falling edge of the pulse signal EV1. Further, the output signal RB of the second-half critical path circuit 74b is latched at the “H” level by the latch circuit 75b at the falling edge of the pulse signal EV1. Further, the signal RB is also latched to the “H” level by the latch circuit 75c at the falling edge of the pulse signal EV2.
[0110]
Therefore, in this state, it can be determined that the delay time of the critical path circuit 74 is less than a half cycle of the operation clock signal ECLK, and the operation is fast enough. Therefore, this state is determined as “Fast”. At this time, the outputs LA, LB, and LC from the replica circuit 71 are all “H”.
[0111]
Next, when it is determined as “OK”, as shown in FIG. 11C, the output signal RA of the first half critical path circuit 74a is at the “H” level in the latch circuit 75a by the falling edge of the pulse signal EV1. Is latched on. Further, the output signal RB of the second-half critical path circuit 74b is latched to the “L” level by the latch circuit 75b at the falling edge of the pulse signal EV1. Further, the signal RB is latched to the “H” level by the latch circuit 73c at the falling edge of the pulse signal EV2.
[0112]
Therefore, in this state, the first half critical path circuit 74a operates with a delay time within a half cycle of the operation clock signal ECLK, and the entire critical path circuit 74 is longer than the half cycle of the operation clock signal ECLK. It shows that it is operating with a delay time shorter than minutes. Therefore, this state is determined as “OK”. At this time, the outputs LA, LB, and LC from the replica circuit 71 become “H”, “L”, and “H”, respectively.
[0113]
Subsequently, when it is determined as “Warn”, as shown in FIG. 11D, the output signal RA of the first-half critical path circuit 74a is set to the “L” level by the latch circuit 75a at the falling edge of the pulse signal EV1. Is latched on. Further, the output signal RB of the second-half critical path circuit 74b is latched to the “L” level by the latch circuit 75b at the falling edge of the pulse signal EV1. Further, the signal RB is latched to the “H” level by the latch circuit 75c at the falling edge of the pulse signal EV2.
[0114]
Therefore, in this state, the delay time of the first-half critical path circuit 74a does not fall within the half cycle of the operation clock signal ECLK, but the entire critical path circuit 74 has a delay time shorter than one cycle of the operation clock signal ECLK. Indicates that it is working. For this reason, there is no margin in the operation margin, and there is a high possibility that the operation will not be performed due to a slight environmental change or the like. Therefore, this state is determined as “Warn”. At this time, the outputs LA, LB, and LC from the replica circuit 71 are “L”, “L”, and “H”, respectively.
[0115]
Finally, when it is determined as “NG”, as shown in FIG. 11E, the output signal RA of the first half critical path circuit 74a is set to the “L” level by the latch circuit 75a at the falling edge of the pulse signal EV1. Is latched on. Further, the output signal RB of the second-half critical path circuit 74b is latched to the “L” level by the latch circuit 75b at the falling edge of the pulse signal EV2. Further, the signal RB is also latched to the “L” level by the latch circuit 75c at the falling edge of the pulse signal EV2.
[0116]
Therefore, this state indicates that the delay time of the critical path circuit 74 exceeds one cycle of the operation clock signal ECLK, and the possibility that the internal circuit does not operate is extremely high. Therefore, this state is determined as “NG”. To do. At this time, the outputs LA, LB, and LC from the replica circuit 71 are all “L”.
[0117]
As described above, when the operation state of the critical path circuit 74 is classified into four according to the combination of the outputs LA, LB, and LC of the replica circuit 71, the operation state of the internal circuit can be finely detected, and any process Appropriately responding to variations and environmental changes, and supplying the optimum output voltage can contribute to lower power consumption of the entire integrated circuit.
[0118]
On the other hand, combinations of outputs LA, LB, and LC of the replica circuit 71 are summarized in a table shown in FIG. At this time, a combination of outputs LA, LB, and LC not shown above, for example, “L”, “H”, “L”, etc., is very likely that the critical path circuit 74 itself is not operating properly. Since it is high, it is determined to be “NG” (in order to distinguish it from the above example of “operating but not in time”, “(NG)” is shown in the figure). As a result, the internal circuit can be operated more stably. In addition, since a failure or the like of the replica circuit 71 can be detected at an early stage, it is possible to perform a quick post-treatment.
[0119]
The selection signal generation circuit 72 generates a selection signal for selecting the output of the delay circuit 62 based on the outputs LA, LB, and LC of the replica circuit 71. For example, when the signals LA, LB, and LC indicate the operation state “Fast”, a selection signal that lowers the internal power supply voltage by one stage, that is, shortens the delay time by one stage is generated. When the signals LA, LB, and LC indicate the operation state “OK”, a selection signal that maintains the internal power supply voltage, that is, maintains the delay time is generated. When the signals LA, LB, and LC indicate the operation states “Warn” and “NG”, a selection signal is generated that increases the internal power supply voltage by one stage, that is, increases the delay time by one stage.
[0120]
By the way, when the variable width of the internal power supply voltage is large, there is a possibility that the range of “OK” or “Warn” may be jumped by only increasing or decreasing the internal power supply voltage by one stage. On the other hand, if the variable width of the internal power supply voltage is sufficiently small, there may be a plurality of internal power supply voltage values within the range of “OK” or “Warn”. At this time, the power consumption is minimized while the entire circuit is stably operated when the lowest internal power supply voltage value is selected from among a plurality of internal power supply voltage values that are determined to be “OK”.
[0121]
Therefore, in order to determine the minimum output voltage that is “OK”, a flag signal that represents the past history of the operating state is used to determine whether or not the internal power supply voltage can be further lowered by one step when determining “OK”. WF is provided. A specific configuration example of the selection signal generation circuit 72 based on the above examination is shown in FIG.
[0122]
The selection signal generation circuit 72 is a circuit that outputs the selection signals S0, S1, SH, and SQ to the delay circuit 62, and includes a coefficient generation circuit 81, a 4-bit adder 82, and a 4-bit register 83. And a counter circuit 84 that generates a signal RepEnb.
[0123]
The coefficient generation circuit 81 is a circuit that receives the outputs LA, LB, and LC from the replica circuit 71 and the output signal CNT from the 4-bit register 83 and generates a 4-bit signal COEF.
[0124]
The 4-bit adder 82 receives the signal COEF generated by the coefficient generation circuit 81 and the output signal CNT of the 4-bit register 83 storing the numerical value indicating the previous selection position, and inputs a numerical value indicating the new selection position. Calculate.
[0125]
The 4-bit register 83 uses the reference pulse signal V3 as a clock signal and latches the output from the 4-bit adder 82. This is a periodic signal in which the reference pulse signal V3 rises immediately before output selection in the delay circuit 62, and the selection signals S0, S1, SH, and SQ output from the selection signal generation circuit 72 are output selection signals. This is because it may be determined immediately before.
[0126]
The 4-bit register 83 is configured using a negative edge triggered flip-flop. Further, each flip-flop of the 4-bit register 83 is reset to “H” at the time of activation (the reset signal line is not shown). Therefore, since all the selection signals S0, S1, SH, and SQ are set to “H” at the time of resetting, the output D3 having the maximum delay time is selected as the output of the delay circuit 62, and further 3/4 of the internal clock ICLK. Delayed by a period. As a result, at reset, the maximum value is generated as the internal power supply voltage V2. This ensures that the internal circuit operates reliably. The second bit from the bottom of the output signal CNT of the 4-bit register 83 is used as the selection signal SH, and the least significant bit is used as the selection signal SQ.
[0127]
FIG. 14 is a block diagram showing a specific configuration example of the coefficient generation circuit 81. The coefficient generation circuit 81 includes a WF signal generation circuit 85 and a coefficient signal generation circuit 86. The WF signal generation circuit 85 is a circuit that generates the flag signal WF from the outputs LA, LB, and LC of the replica circuit 71. The counter circuit 86 is a circuit that generates the signal RepEnb used in the replica circuit 71 and the coefficient generation circuit 81 by counting up the reference pulse signal V3.
[0128]
The flag signal WF is determined as follows. When the outputs LA, LB, and LC of the replica circuit 71 indicate the operation state “Warn”, the flag signal WF is set to “H”. When the outputs LA, LB, LC indicate the operation state “Fast”, the flag signal WF is set to “L”. When the operation state indicated by the outputs LA, LB, and LC is not “Warn” or “Fast”, the flag signal WF is maintained as it is. That is, the WF signal generation circuit 85 is realized by mounting the truth table of FIG. 15 as a logic circuit. The flag signal WF may be determined in synchronization with the reference pulse signal V3, and the value of the flag signal WF one cycle before is referred to as “WF0”.
[0129]
On the other hand, the coefficient signal generation circuit 86 is a circuit that generates a coefficient signal COEF from the outputs LA, LB, LC from the replica circuit 71 and the flag signal WF from the WF signal generation circuit 85. In the coefficient signal generation circuit 86, the coefficient signal COEF is determined as follows.
[0130]
When the outputs LA, LB, and LC of the replica circuit 71 indicate the operation state “NG”, the coefficient COEF that increases the signal CNT by “+1” is set to (0001) so that the internal power supply voltage V2 is increased by one stage regardless of the flag signal WF. ) B is output. Similarly, when the outputs LA, LB, and LC of the replica circuit 71 indicate the operation state “Warn”, (0001) b is output as the coefficient COEF regardless of the flag signal WF.
[0131]
On the other hand, when the outputs LA, LB, and LC of the replica circuit 71 indicate the operation state “OK” and the flag signal WF is “H”, the coefficient COEF is (0000) in order to maintain the internal power supply voltage V2. b is output. When the outputs LA, LB, and LC of the replica circuit 71 indicate the operation state “OK” and the flag signal WF is “L”, the signal CNT is set to “−1” so that the internal power supply voltage V2 is lowered by one stage. (1111) b is output as the coefficient COEF.
[0132]
Furthermore, when the outputs LA, LB, LC of the replica circuit 71 indicate the operation state “Fast”, (1111) b is set as the coefficient COEF so that the internal power supply voltage V2 is lowered by one stage regardless of the flag signal WF. Output. The coefficient signal generation circuit 86 is realized by mounting the truth table of FIG. 16 as a logic circuit.
[0133]
A method for controlling the internal power supply voltage V2 by the WF signal generation circuit 85 and the coefficient signal generation circuit 86 will be specifically described below. As described above, there may be a plurality of internal power supply voltage values at which the operation state determination result is “OK”. Therefore, even when the determination of the operation state is “OK”, the internal power supply voltage V2 is lowered by one stage depending on the conditions.
[0134]
That is, when the internal power supply voltage V2 is gradually raised so that the internal circuit operates, the operation state determination of the replica circuit 71 changes from “NG” → “Warn” → “OK”. In this case, since the operation state determination “Warn” is passed, the flag signal WF is “H”. Therefore, even if the operation state determination is “OK”, the internal power supply voltage V2 is not lowered according to the “H” flag signal WF. As a result, the internal power supply voltage V2 is maintained at a constant value.
[0135]
If the control by the flag signal WF is not performed, the determination of “Warn” and “OK” is performed alternately, and the internal power supply voltage V2 may rise and fall, which may cause unstable circuit operation. is there.
[0136]
On the other hand, consider a case where the operating state determination is “Fast” due to a change in the operating environment and the internal power supply voltage V2 is lowered. The operation state determination of the replica circuit 71 changes from “Fast” to “OK”. In this case, since the flag signal WF is reset to “L” when the operation state determination becomes “Fast”, even if the operation state determination becomes “OK”, the “L” flag signal WF is reset. Accordingly, control is performed so as to lower the internal power supply voltage V2. Thereafter, when the internal power supply voltage V2 is lowered, the operation state determination becomes “Warn”, the flag signal WF is switched to “H”, the internal power supply voltage V2 is increased by one stage as described above, and then the operation state determination is performed. Even if becomes “OK”, since the flag signal WF is “H”, the internal power supply voltage V2 is maintained without being lowered.
[0137]
In summary, when the operation state determination is “OK”, the internal power supply voltage V2 is lowered by one stage when the flag signal WF is “L”, but when the flag signal WF is “H” The power supply voltage V2 is maintained as it is. Thus, as described above, the internal power supply voltage V2 becomes the minimum voltage value in the “OK” determination that the internal circuit is stably operating, and as a result, the power consumption can be suppressed to the minimum.
[0138]
The above example describes the case where the number of basic delay stages M = 6 and the number of variable delay stages N = 3, but of course, it is effective when M ≧ 1 and N ≧ 1. Further, although the arbitrary time delay circuit 66 has been described for the case where the number of output terminals is two, it is of course effective when the number of output terminals is one or more.
[0139]
The following describes the third embodiment of the present invention with reference to FIGS.
[0140]
FIG. 17 is a block diagram showing an electrical configuration of the switch control circuit 46a in the voltage conversion circuit according to the third embodiment of the present invention. The switch control circuit 46a is used in place of the switch control circuit 46 shown in FIG. The switch control circuit 46a includes a switch timing control circuit 91, boost level shifters 92 and 93, activation control circuits 94 and 95, an activation signal generation circuit 96, and buffer circuits 97 and 98.
[0141]
First, a specific configuration example of the switch timing control circuit 91 is shown in FIG. The switch timing control circuit 91 includes two delay circuits 99 and 100, an inverter INV3, and a NOR gate G3. The switch pulse V5 is used as an input signal, the output signal V5a delayed by the delay circuit 99 is logically negated by the inverter INV3, and the output X1a is output to the boost level shifter 72 for the PMOS transistor MP, while the output signal of the delay circuit 99 is output. This is a circuit that further delays V5a by the delay circuit 100, performs NOR operation on the output signal V5b and the switch pulse V5 by the NOR gate G3, and outputs the output X2a to the boost level shifter 93 for the NMOS transistor MN.
[0142]
FIG. 19 is a waveform diagram for explaining the operation of the switch timing control circuit 91 configured as described above. Here, the delay times in the delay circuits 99 and 100 are both DT. The signals V5a and V5b are sequentially delayed by the delay time DT with respect to the switch pulse V5, and the intermediate signal V5a is inverted by the inverter INV3 to become the output X1a for the low-active PMOS transistor MP. On the other hand, the NOR gate G3 adds the pulse widths of the switch pulse V5 that makes the fastest transition and the signal V5b that makes the slowest transition, and inverts them so that the output X2a for the highly active NMOS transistor MN Become.
[0143]
Accordingly, as is well known from FIG. 19, since the PMOS transistor MP is turned on when the gate input signal X1 is "L", the PMOS transistor MP is turned on when the intermediate signal V5a is turned on. Only the period W2 during which it becomes active. On the other hand, since the NMOS transistor MN is turned on when the gate input signal X2 is “H”, the NMOS transistor MN is turned on when the switch pulse V5 is inactive and the signal V5b is inactive. Only periods W0 and W0 ′ are. In the period W1, W1 ′ in which only one of the switch pulse V5 and the signal V5b is active, both transistors MP, MN are off.
[0144]
As described above, by providing a period in which both the transistors MP and MN are turned off while the period in which the PMOS transistor MP is turned on and the period in which the NMOS transistor MN is turned on, a through current flows through the switch circuit 33. It is possible to prevent excessive power consumption. The delay circuits 99 and 100 may be any circuit as long as it has a function of delaying an input signal.
[0145]
In general, the power consumption of an integrated circuit is proportional to the square of the power supply voltage. Therefore, when the internal circuit operates at a low power supply voltage of 0.5 V, the power consumption of the internal circuit can be greatly reduced. it can. However, it is necessary to reduce the power consumption of the voltage conversion circuit itself so as not to impair the low power consumption of the internal circuit.
[0146]
Therefore, in the voltage conversion circuit 51, the critical path circuit 74 of the replica circuit 71 which is a detection circuit of the internal power supply voltage V2 is driven by the internal power supply voltage V2, but by using the boost level shifters 92 and 93, The control circuit portion from the reference pulse signal generation circuit 41 to the switch timing control circuit 91 can also be driven by this internal power supply voltage V2. As a result, the power consumption of the voltage conversion circuit itself can be greatly reduced, and the power consumption of the integrated circuit as a whole is reduced. Of course, the same configuration can also be applied to the voltage conversion circuit 31 described above.
[0147]
FIG. 20 is a block diagram showing a specific configuration example of the boost level shifters 92 and 93. The boost level shifters 92 and 93 convert the low-amplitude (V2 level) outputs X1a and X2a from the switch timing control circuit 91 into VDD level outputs X1b and X2b at which the transistors MP and MN can operate and output them. . Here, a DTMOS (Dynamic Threshold MOS) transistor is used as a transistor constituting the low voltage side circuit. Since this device operates with the power supply voltage of about 0.5 V, low power consumption is realized as described above by manufacturing an integrated circuit using this device.
[0148]
The step-up level shifters 92 and 93 include two-stage inverters INV11 and INV12, a level shifter SH, and two-stage inverters INV21 and INV22.
[0149]
The inverters INV11 and INV12 are inverters that use the output voltage V2 of the filter circuit 34 as a power source, and sequentially invert the switch pulses V5 of the duty ratio controlled as described above from the switch pulse generation circuit 45. Therefore, the inverter INV11 is configured by connecting a series circuit of a PMOS transistor QP11 and an NMOS transistor QN11 in series between the power supply lines of the output voltage V2, and the outputs X1a and X2a are given to the bases of these transistors QP11 and QN11. Thus, the drain becomes an output terminal, and an inverted output having a phase opposite to that of the outputs X1a and X2a is derived. Similarly, the inverter INV12 includes a PMOS transistor QP12 and an NMOS transistor QN12, the output of the inverter INV11 is given to the base, and a normal output in phase with the outputs X1a and X2a is derived from the drain.
[0150]
The level shifter SH uses the power supply voltage VDD as a power supply, amplifies the output from the inverters INV11 and INV12 to the power supply voltage VDD, and outputs the amplified power supply voltage VDD. Therefore, in the level shifter SH, a series circuit of the PMOS transistor QP31 and the NMOS transistor QN31 and a series circuit of the PMOS transistor QP32 and the NMOS transistor QN32 are connected in parallel between the power supply lines of the power supply voltage VDD, and one drain connection terminal is connected to the other. Connected to the gate of the PMOS transistor. The NMOS transistors QN31 and QN32 and the PMOS transistors QP11 and QP12 and the NMOS transistors QN11 and QN12 constituting the inverters INV11 and INV12 are formed of the DTMOS transistors. The output of the inverter INV11 is applied to the gate of the NMOS transistor QN31, the output of the inverter INV12 is applied to the gate of the NMOS transistor QN32, and the drains of the transistors QP32 and QN32 serve as output terminals. Therefore, a level-shifted output is derived in phase with the outputs X1a and X2a.
[0151]
The inverters INV21 and INV22 are inverters using the power supply voltage VDD as a power supply, and sequentially invert the outputs from the drains of the transistors QP32 and QN32. Therefore, the inverter INV21 is configured by connecting a series circuit of a PMOS transistor QP21 and an NMOS transistor QN21 in series between the power supply lines of the power supply voltage VDD, and the output of the level shifter SH is given to the bases of these transistors QP21 and QN21. The drain becomes the output terminal. Similarly, the inverter INV22 includes a PMOS transistor QP22 and an NMOS transistor QN22, the output of the inverter INV21 is given to the base, and the output X1b, which is a normal output in phase with the outputs X1a and X2a, is provided from the drain. X2b is output.
[0152]
In this way, even when the circuit upstream of the switch timing control circuit 91 is operated at a low voltage, the outputs X1b and X2b output by the boost level shifters 92 and 93 are boosted, and the two transistors MP and MN are boosted. Can perform certain operations.
[0153]
FIG. 21 is a block diagram showing a specific configuration example of the activation control circuits 94 and 95 and the buffer circuits 97 and 98. The activation control circuit 94 includes an inverter INV31a that receives the output X1b from the boost level shifter 92, a NAND circuit Ga that receives the output signal of the inverter INV31a and the control signal RSTH from the activation signal generation circuit 96, and It is configured with. The NAND circuit Ga outputs the output X1b from the boost level shifter 92 as it is when the level of the control signal RSTH is equal to the VDD level. On the other hand, when the level of the control signal RSTH is equal to the GND level, the NAND circuit Ga outputs the VDD level regardless of the output X1b.
[0154]
The output signal of the NAND circuit Ga is inverted by the buffer circuit BUFa composed of an inverter and the current driving capability is enhanced to become the control signal X1, which drives the gate of the PMOS transistor MP.
[0155]
Similarly, the activation control circuit 95 includes an inverter INV31b and a NAND circuit Gb. The output signal of the NAND circuit Gb becomes the control signal X2 through the buffer circuit BUFb formed of an inverter, and drives the gate of the NMOS transistor MN.
[0156]
FIG. 22 is a block diagram showing a specific configuration example of the activation signal generation circuit 96. Here, a circuit is shown in which the rise of the power supply voltage VDD is detected and the output is set to the GND level by the RC time constant. That is, a series circuit of a resistor Rs and a capacitor Cs is connected between the power supply lines of the power supply voltage VDD, and the charging voltage of the capacitor Cs is output as the control signal RSTH via the Schmitt trigger inverters STI1 and STI2. The In parallel with the resistor Rs, a diode D for discharging the capacitor Cs when the power is cut off is connected.
[0157]
Therefore, the activation signal generation circuit 96 constitutes a power-on reset circuit, and the reset period during which the control signal RSTH is at the L level is determined by the time constants of the resistor Rs and the capacitor Cs.
[0158]
Next, operations of the activation control circuits 94 and 95 and the activation signal generation circuit 96 at the time of activation will be described. Since the output voltage V2 is 0V at the start-up, the reference pulse signal generation circuit 41, the delay circuit 62 and the like using the output voltage V2 cannot operate as described above. On the other hand, since the power supply voltage VDD starts to be supplied to the start control circuits 94 and 95, the buffer circuits 97 and 98, and the start signal generation circuit 96, the operation is started.
[0159]
As a result, the reset signal RSTH is output from the activation signal generation circuit 96, and the voltage signal V1 from the switch circuit 33 is at the VDD level during the reset period Trsth. In the case of the circuit shown in FIG. 22, the reset period Trsth is determined with the product of the values of R and C as a time constant. During this time, the output voltage V2 of the filter circuit 34 continues to rise, and when the reference pulse signal generation circuit 41, the delay circuit 62, etc. reach a level at which they can operate, these circuits 41, 62, etc. start operating. To do.
[0160]
When the reset period Trsth ends, the output voltage V2 gradually decreases, but the reference pulse signal generation circuit 41, delay circuit 62, switch pulse generation circuit 45, switch timing control circuit 91, and boost level shifters 92 and 93 operate. Subsequently, the control signals X1 and X2 are continuously output. As a result, when the voltage signal V1 from the switch circuit 33 is a pulse signal having a desired duty ratio, the voltage conversion circuit is in a stable operation state.
[0161]
In this way, a configuration for activation control can be realized with a simple configuration of the activation signal generation circuit 96 and the activation control circuits 94 and 95. As the activation signal generation circuit 96, not only the RC circuit as shown in FIG. 22 but also any circuit such as a timer circuit or a combination of an oscillator and a counter circuit may be used.
[0162]
【The invention's effect】
As described above, in the voltage conversion circuit realized as a step-down converter or the like formed in an integrated circuit, the voltage conversion circuit of the present invention is configured to generate a switch pulse signal to be applied to the control terminal of the transistor of the switch circuit. The pulse signal generation circuit includes a reference pulse signal generation circuit that generates a reference pulse signal serving as a reference at a constant frequency, a delay circuit that delays the reference pulse signal, and a delay time control that sets a delay time in the delay circuit. A circuit that detects a transition between a delay pulse signal from the delay circuit and the reference pulse signal, generates the switch pulse signal having a time width corresponding to a delay time in the delay circuit, and applies the drive to the transistor And a circuit.
[0163]
Therefore, by controlling the delay time of the delay circuit, the pulse width of the switch pulse signal can be changed, and thus the output voltage can be controlled by pulse width modulation (duty control), and the ripple of the output voltage. The voltage can be kept constant. As a result, the operation of the internal circuit that supplies the output voltage can be stabilized. In addition, such pulse width modulation control can be realized by a delay circuit configured by a shift register or a drive circuit configured by a logic circuit, so that a high-speed counter circuit is not required, and the circuit scale In addition, it is possible to realize a voltage conversion circuit that consumes less power and is suitable for lowering the output voltage.
[0164]
In addition, as described above, the voltage conversion circuit of the present invention has the delay circuit as an input having a basic delay circuit that delays the reference pulse signal by a predetermined time and an output signal from the basic delay circuit. An additional delay circuit having one or a plurality of output terminals capable of extracting a signal, and one of an output signal from the basic delay circuit or an output signal from each output terminal of the additional delay circuit, and A selection circuit that outputs as a delayed pulse signal, and the delay time control circuit selectively controls the selection circuit so that the drive circuit has a time width for obtaining the desired output voltage. A switch pulse signal is generated.
[0165]
Therefore, the delay time can be adjusted greatly by the basic delay circuit and the delay time can be finely adjusted by the additional delay circuit, so that the delay time and therefore the output voltage can be changed greatly with a small number of selected channels (number of selected data bits). And can be finely adjusted.
[0166]
Furthermore, as described above, in the voltage conversion circuit of the present invention, the delay circuit receives as input the basic delay circuit that delays the reference pulse signal by a predetermined time and the output signal from the basic delay circuit. An additional delay circuit having one or a plurality of output terminals capable of taking out an internal signal, and one of selecting an output signal from the basic delay circuit or an output signal from each output terminal of the additional delay circuit. 1 selection circuit, an output signal from the first selection circuit, an arbitrary time delay circuit having one or more output terminals, and an output signal from the first selection circuit or the arbitrary time And a second selection circuit that selects one of the output signals from each output terminal of the delay circuit and outputs the selected signal as the delayed pulse signal, and the delay time control circuit includes the first delay circuit. Preliminary second selection circuit by selectively controlling cheat things, to the drive circuit to generate a switching pulse signal having a time width to obtain an output voltage to said desired.
[0167]
Therefore, the delay time is largely adjusted by the basic delay circuit, the delay time is finely adjusted by the additional delay circuit, and the second selection is further performed with the small number of selection channels (number of selected data bits) of the first selection circuit. The delay time can be further finely adjusted by the circuit and the arbitrary time delay circuit. Therefore, highly accurate output voltage control is possible.
[0168]
In addition, as described above, the voltage conversion circuit of the present invention is a voltage conversion circuit used as a step-down converter, except for a portion that requires a high voltage by providing a step-up level shifter and driving a transistor of a switch circuit. A smoothed output voltage is applied to the power supply voltage of the reference pulse signal generation circuit, delay circuit, delay time control circuit, and drive circuit mainly composed of logic circuits, thereby reducing the power consumption of the voltage conversion circuit itself. On the other hand, if the output voltage of the voltage conversion circuit is used as a power supply, it will not start after the operation has been stopped for a long time, so a start signal generation circuit and a start control circuit are further provided. By these circuits driven by the input power supply voltage, the switch circuit is forcibly switched at the time of startup, and the power supply voltage to the reference pulse signal generation circuit, the delay circuit, the delay time control circuit and the drive circuit is raised.
[0169]
Therefore, the power consumption of the voltage conversion circuit itself can be reduced without causing a start-up failure.
[0170]
Furthermore, as described above, the voltage conversion circuit of the present invention includes one unit time delay element that performs a unit time delay for the delay circuit, the basic delay circuit, the additional delay circuit, and the arbitrary time delay circuit. The above is connected in series.
[0171]
Therefore, the configuration of the delay circuit is simplified and the design can be easily changed.
[0172]
In the voltage conversion circuit of the present invention, the unit time delay element is a flip-flop circuit as described above.
[0173]
Therefore, the delay time can be easily set and the delay circuit can be easily designed.
[0174]
Furthermore, in the voltage conversion circuit of the present invention, as described above, the drive circuit includes a switch pulse generation circuit and a switch control circuit including a buffer circuit, and the switch pulse generation circuit includes a flip-flop. Consists of a circuit.
[0175]
Therefore, the circuit configuration of the switch pulse generation circuit constituting the drive circuit can be simplified.
[0176]
In addition, as described above, the voltage conversion circuit of the present invention responds to an input signal when controlling a switch circuit in which a series circuit of a P-type transistor and an N-type transistor is connected in series between a pair of power supply lines. After the N-type transistor is switched from on to off, the P-type transistor is switched from off to on after a delay time of the first delay circuit, and after the P-type transistor is switched from on to off. The N-type transistor is switched from OFF to ON with a delay of the delay time of the second-stage delay circuit.
[0177]
Therefore, the two delay times are dead times in which the two transistors are not turned on at the same time, the through current of the switch circuit can be suppressed, and the power consumption of the voltage conversion circuit itself can be reduced. .
[0178]
Furthermore, as described above, the voltage conversion circuit of the present invention synchronizes the operating time of the internal circuit supplied with the output voltage as the power supply voltage with the clock signal supplied from the outside. The replica circuit to be detected and a signal indicating the operation speed output from the replica circuit are used as input signals, and one output terminal is selected from the plurality of output terminals of the delay circuit according to the detected operation speed. And a selection signal generation circuit that outputs a selection signal for the purpose.
[0179]
Therefore, the operation state of the internal circuit constituting the integrated circuit can be detected by the replica circuit, and the minimum drive voltage necessary for the operation of the internal circuit can be supplied, which contributes to the reduction in power consumption of the integrated circuit. it can.
[0180]
In addition, as described above, the voltage conversion circuit of the present invention includes an operation state detection pulse generation circuit that generates a pulse for detecting an operation state, and an input pulse from the operation state detection pulse generation circuit. On the other hand, a delay equivalent to that of the path circuit considered to have the largest signal delay among the internal circuits is performed, and the critical path circuit divided into a plurality of parts is output from each part of the critical path circuit. And a latch circuit that latches the pulse signal in response to a pulse from the operation state detection pulse generation circuit and sends the output signal as an operation state signal to the selection signal generation circuit.
[0181]
Therefore, for example, when the critical path circuit is divided into two and the latch timing of the latch circuit is set to the half cycle and one cycle of the pulse from the operation state detection pulse generation circuit, the output pulse of the entire critical path circuit Can be determined that the operating frequency of the internal circuit is too high, that is, the output voltage is too high, and the critical path circuit Even in the first half of the output pulse, when it does not follow within one cycle of the pulse from the operation state detection pulse generation circuit, it is determined that the operation frequency of the internal circuit is too low, that is, the output voltage is too low. Output pulse of the first half of the critical path circuit is a half cycle of the pulse from the operation state detection pulse generation circuit If the output pulse in the latter half does not follow within the half cycle and follows within one cycle, the operating frequency of the internal circuit is optimal, that is, the output voltage is optimal. The output pulse of the first half of the critical path circuit does not follow within the half cycle of the pulse from the operation state detection pulse generation circuit, and the output pulse of the second half follows within one cycle. In this case, the internal circuit is operable at present, but becomes inoperable due to a slight environmental change, that is, it can be determined that a slightly higher output voltage is preferable. If the operating frequency is too high, i.e. the output voltage is too high, the delay time is shortened, and if the operating frequency is too low, i.e. the output voltage is too low, the delay time is If the operating frequency is optimal, i.e., the output voltage is optimal, the delay time is maintained and operation is possible, but the operating frequency is slightly lower, i.e., if the output voltage is slightly higher, the delay is preferred. By increasing the time, the output voltage can be optimally controlled.
[0182]
As a result, various operation states can be detected and optimal control can be performed by setting the number of divisions of the critical path circuit and the number of latch timings of the latch circuit, and it can respond appropriately to any process variations and environmental changes. In addition, by supplying an optimum output voltage, it is possible to contribute to lower power consumption of the entire integrated circuit.
[0183]
Furthermore, in the voltage conversion circuit according to the present invention, as described above, the critical path circuit is divided into two, and the latch circuit uses the pulse signal output from the first critical path circuit as the operation state detection pulse generation circuit. A first latch circuit that latches after a half cycle of the pulse from the second latch circuit, and a second latch circuit that latches a pulse signal output from the latter critical path circuit after a half cycle of the pulse from the operation state detection pulse generation circuit; And a third latch circuit that latches the pulse signal output from the latter critical path circuit after one cycle of the pulse from the operation state detection pulse generation circuit.
[0184]
Therefore, it can be determined that the critical path circuit itself is not operating properly except for the above-described four operating states from the outputs of the eight types of combinations from the three latch circuits. It becomes possible to operate the internal circuit more stably. In addition, since a failure or the like of the replica circuit can be detected at an early stage, it is possible to perform a quick post-treatment.
[0185]
Further, in the voltage conversion circuit of the present invention, as described above, the selection signal generation circuit includes a flag signal generation circuit that generates a flag signal indicating the history of the operation state of the replica circuit, and the value of the flag signal Thus, either the delay time increasing / decreasing operation required from the output signal of the replica circuit or a different delay time increasing / decreasing operation is selected, and the output terminal of the delay circuit is selected.
[0186]
Therefore, by introducing a flag signal indicating the history of the operation state of the replica circuit, the output voltage control function can be enhanced, and the output voltage can be maintained at the minimum voltage at which the internal circuit operates stably. Thus, power consumption can be minimized.
[0187]
Furthermore, as described above, the semiconductor integrated circuit device according to the present invention uses the voltage conversion circuit as a step-down circuit that generates a drive voltage for the semiconductor integrated circuit device from an external power supply voltage.
[0188]
Therefore, the power consumption of the step-down circuit itself can be reduced, and the overall power consumption of the semiconductor integrated circuit device can be reduced without impairing the low power consumption of the internal circuit.
[0189]
Moreover, the portable terminal of this invention is provided with the said semiconductor integrated circuit device as mentioned above.
[0190]
Therefore, it is possible to contribute to lower power consumption of the entire mobile terminal.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an electrical configuration of a voltage conversion circuit according to a first embodiment of the present invention.
2 is a block diagram showing an example of the configuration of a delay circuit in the voltage conversion circuit shown in FIG.
3 is a block diagram illustrating a specific configuration example of a switch pulse generation circuit in the voltage conversion circuit illustrated in FIG. 1. FIG.
4 is a block diagram showing a specific configuration example of a switch control circuit in the voltage conversion circuit shown in FIG. 1. FIG.
5 is a waveform diagram for explaining operations of a delay circuit and a switch pulse generation circuit in the voltage conversion circuit shown in FIG.
FIG. 6 is a block diagram showing an electrical configuration of a voltage conversion circuit according to a second embodiment of the present invention.
7 is a block diagram illustrating a specific configuration example of a delay circuit in the voltage conversion circuit illustrated in FIG. 6;
8 is a block diagram showing a specific example of the configuration of a delay time control circuit in the voltage conversion circuit shown in FIG.
9 is a block diagram showing a specific configuration example of a replica circuit in the delay time control circuit shown in FIG.
10 is a signal waveform diagram of an operation state detection pulse generation circuit in the replica circuit shown in FIG. 9;
11 is a signal waveform diagram showing a method for determining each operation state in the replica circuit shown in FIG. 9;
12 is a table summarizing operation states of the replica circuit shown in FIG.
13 is a block diagram showing a specific configuration example of a selection signal generation circuit in the delay time control circuit shown in FIG.
14 is a block diagram illustrating a specific configuration example of a coefficient generation circuit in the selection signal generation circuit illustrated in FIG. 13;
15 is a truth table of the WF signal generation circuit in the coefficient generation circuit shown in FIG.
16 is a truth table of a coefficient signal generation circuit in the coefficient generation circuit shown in FIG.
FIG. 17 is a block diagram showing an electrical configuration of a switch control circuit in a voltage conversion circuit according to a third embodiment of the present invention.
18 is a block diagram showing a specific example of the configuration of a switch timing control circuit in the switch control circuit shown in FIG.
FIG. 19 is a waveform diagram for explaining the operation of the switch timing control circuit shown in FIG. 19;
20 is a block diagram illustrating a specific configuration example of a level shifter in the switch timing control circuit illustrated in FIG.
FIG. 21 is a block diagram showing a specific example of the configuration of a start control circuit and a buffer circuit in the switch timing control circuit shown in FIG.
22 is a block diagram showing a specific example of the configuration of a start signal generation circuit in the switch timing control circuit shown in FIG.
FIG. 23 is a schematic configuration diagram of a typical prior art voltage conversion circuit.
FIG. 24 is a block diagram of another conventional voltage conversion circuit.
[Explanation of symbols]
31, 51 Voltage conversion circuit
32, 52 pulse signal generation circuit
33 Switch circuit
34 Filter circuit
41 Reference pulse signal generation circuit
42, 62 delay circuit
43, 63 Delay time control circuit
44 Drive circuit
45 Switch pulse generation circuit
46, 46a Switch control circuit
47 Basic delay circuit
48 Additional delay circuit
49 Selection circuit (first selection circuit)
64 selection circuit
65; 65a, 65b selection circuit (second selection circuit)
66 Arbitrary time delay circuit
66a, 66b flip-flop
71 Replica circuit
72 Selection signal generation circuit
73 Operation state detection pulse generation circuit
73a, 73b, 73c flip-flop
73d, 73e AND gate
74 Critical Path Circuit
74a First critical path circuit
74b Late critical path circuit
75 Latch circuit
75a Latch circuit (first latch circuit)
75b Latch circuit (second latch circuit)
75c Latch circuit (third latch circuit)
81 Coefficient generation circuit
82 4-bit adder
83 4-bit register
84 Counter circuit
85 WF signal generation circuit
86 Coefficient signal generation circuit
91 Switch timing control circuit
92,93 Boost Level Shifter
94,95 Start-up control circuit
96 Start-up signal generation circuit
97, 98 Buffer circuit
99,100 delay circuit
BUF1, BUF2 buffer circuit
C capacitor
L inductor
MN NMOS transistor
MP PMOS transistor
INV1, INV2, INV3 inverter
INV11, INV12; INV21, INV22 Inverter
G1, G2 NAND gate
G3 NOR gate
SH level shifter

Claims (14)

The switch circuit switches the power supply voltage, smooths and outputs the output voltage, and the pulse signal generation circuit generates a switch pulse signal for obtaining a desired output voltage and supplies it to the transistor of the switch circuit In the voltage converter circuit
The pulse signal generation circuit includes:
A reference pulse signal generation circuit for generating a reference pulse signal as a reference at a constant frequency;
A delay circuit for delaying the reference pulse signal;
A delay time control circuit for setting a delay time in the delay circuit;
A drive circuit for detecting a transition between the delay pulse signal from the delay circuit and the reference pulse signal, generating the switch pulse signal having a time width corresponding to a delay time in the delay circuit, and driving the transistor; A voltage conversion circuit comprising: The delay circuit is
A basic delay circuit for delaying the reference pulse signal by a predetermined time;
An additional delay circuit having one or a plurality of output terminals capable of receiving an output signal from the basic delay circuit and taking out the internal signal;
A selection circuit that selects one of the output signal from the basic delay circuit or the output signal from each output terminal of the additional delay circuit, and outputs the delayed pulse signal;
The delay time control circuit controls the selection circuit to cause the drive circuit to generate a switch pulse signal having a time width for obtaining the desired output voltage. The voltage conversion circuit described. The delay circuit is
A basic delay circuit for delaying the reference pulse signal by a predetermined time;
An additional delay circuit having one or a plurality of output terminals capable of receiving an output signal from the basic delay circuit and taking out the internal signal;
A first selection circuit that selects one of the output signal from the basic delay circuit or the output signal from each output terminal of the additional delay circuit;
An arbitrary time delay circuit that delays an output signal from the first selection circuit for an arbitrary time, and has one or a plurality of output terminals;
A second selection circuit that selects one of the output signal from the first selection circuit or the output signal from each output terminal of the arbitrary time delay circuit and outputs the selected signal as the delayed pulse signal;
The delay time control circuit causes the drive circuit to generate a switch pulse signal having a time width for obtaining the desired output voltage by selectively controlling the first and second selection circuits. The voltage conversion circuit according to claim 1, wherein: Applying the smoothed output voltage lower than the power supply voltage as a power supply voltage for the reference pulse signal generation circuit, the delay circuit, the delay time control circuit, and the drive circuit,
The drive circuit includes a boost level shifter, a start signal generation circuit, and a start control circuit, and the switch circuit forcibly switches the power supply voltage by these circuits driven by the input power supply voltage, and the reference pulse 4. The voltage conversion circuit according to claim 1, wherein a power supply voltage to the signal generation circuit, the delay circuit, the delay time control circuit, and the drive circuit is raised. 2. The delay circuit, the basic delay circuit, the additional delay circuit, and the arbitrary time delay circuit are formed by connecting one or more unit time delay elements that perform a unit time delay in series. 5. The voltage conversion circuit according to any one of 4 above. 6. The voltage conversion circuit according to claim 5, wherein the unit time delay element is a flip-flop circuit. 2. The drive circuit according to claim 1, wherein the drive circuit includes a switch pulse generation circuit and a switch control circuit including a buffer circuit, and the switch pulse generation circuit includes a flip-flop circuit. Voltage conversion circuit. The switch circuit is formed by connecting a series circuit of a P-type transistor and an N-type transistor in series between a pair of power supply lines,
The drive circuit is
Two delay circuits having an arbitrary delay time and connected in series with each other;
An inverter circuit that logically negates the output of the first stage delay circuit;
A logical sum negation circuit for performing a logical sum negation operation between the input signal and the output signal of the second-stage delay circuit;
The output of the inverter circuit is output as a first control signal to the control terminal of the P-type transistor of the switch circuit, and the output of the logical sum negation circuit is used as a second control signal to control the N-type transistor of the switch circuit. The voltage conversion circuit according to claim 1, further comprising a switch pulse generation circuit that outputs to a terminal. The delay time control circuit includes:
A replica circuit for detecting the operation speed of the internal circuit supplied as the power supply voltage in synchronization with a clock signal supplied from the outside;
A signal indicating the operation speed output from the replica circuit is used as an input signal, and a selection signal for selecting one output terminal among the plurality of output terminals of the delay circuit is output according to the detected operation speed. The voltage conversion circuit according to claim 1, further comprising a selection signal generation circuit. The replica circuit is
An operation state detection pulse generation circuit for generating a pulse for detecting the operation state;
A critical path circuit that performs a delay equivalent to a path circuit considered to have the largest signal delay in the internal circuit with respect to an input pulse from the operation state detection pulse generation circuit, and is divided into a plurality of ,
A latch circuit that latches a pulse signal output from each part of the critical path circuit in response to a pulse from the operation state detection pulse generation circuit, and sends the output signal to the selection signal generation circuit as an operation state signal; The voltage conversion circuit according to claim 9, comprising: The critical path circuit is divided into two,
The latch circuit is
A first latch circuit that latches a pulse signal output from the first half critical path circuit after a half cycle of a pulse from the operation state detection pulse generation circuit;
A second latch circuit for latching a pulse signal output from the second half critical path circuit after a half cycle of a pulse from the operation state detection pulse generating circuit;
11. A third latch circuit configured to latch a pulse signal output from the latter critical path circuit after one cycle of a pulse from the operation state detection pulse generation circuit. Voltage conversion circuit. The selection signal generation circuit includes a flag signal generation circuit that generates a flag signal indicating a history of operation states of the replica circuit, and a delay time required from an output signal of the replica circuit is determined by a value of the flag signal. 12. The method according to claim 9, wherein one of an increase / decrease operation and an increase / decrease operation with a different delay time is selected and an output terminal of the delay circuit is selected. Voltage conversion circuit. A semiconductor integrated circuit device comprising the voltage conversion circuit according to claim 1. 14. A portable terminal comprising the semiconductor integrated circuit device according to claim 13.

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