JP2009044814A - Synchronous rectifying dc/dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronous rectifying DC/DC converter which can set the dead time which is of optimal length, without having to depend on the input power supply voltage. <P>SOLUTION: In the synchronous rectifying DC/DC converter which obtains an output voltage (Vout) of a desired magnitude by converting a DC input voltage (PVDD), the converter comprises a switching element Q1, which performs on/off-operations; a rectifying element Q2 which performs on/off-operations at timing which is complementary to the switching element Q1; a control circuit 10, which controls the switching element Q1 and the rectifying element Q2 by using a dead time to turning them off; a level shift circuit 5, which converts a voltage level of a control signal outputted to the switching element Q1 from the control circuit 10; and a level shift circuit 6, which converts the voltage level of a control signal outputted to the rectifying element Q2 from the control circuit 10. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a synchronous rectification type DC / DC converter that converts a DC input voltage to obtain an output voltage of a desired magnitude, and particularly optimizes a dead time when a main switching element and a rectifying element are simultaneously turned off. The present invention relates to a synchronous rectification type DC / DC converter to be set.

  The synchronous rectification type DC / DC converter obtains an output voltage of a desired magnitude by turning on and off a main switching element for a main switch and a rectifying element for commutation at complementary timings. Here, if the switching timings of the two switching elements (on / off switching timing) coincide with each other, there is a possibility that a period during which both of them are turned on at the same time may occur. This causes inconvenience that the through current flows. As a means for preventing the occurrence of such a period, a timing difference between the two switching timings, that is, a dead time in which the main switching element and the rectifying element are simultaneously turned off is ensured.

  Such a synchronous rectification type DC / DC converter sometimes requires a voltage level conversion circuit in order to transmit a signal from a control circuit to a switching circuit or a drive circuit for driving a gate of the switching element.

FIG. 4 is a circuit diagram showing a synchronous rectification type DC / DC converter having a conventional voltage level conversion circuit.
This DC / DC converter includes a control circuit unit 10 for generating a PWM signal, a driver circuit unit 20 for driving the switching element Q1 and the rectifying element Q2, and the switching element Q1 and the rectifying element Q2 between the input power supply PVDD and the ground. The output unit 30, the smoothing circuit unit 40, the level shift circuit 5 and the like connected in series are configured. As the switching element Q1 and the rectifying element Q2, N-channel MOSFETs (field effect transistors using metal oxide film semiconductors, hereinafter simply referred to as NMOS) are used.

  In the figure, the control circuit power supply VDD is supplied to the control circuit section 10 in a magnitude different from the input power supply voltage (PVDD), and the output section 30 converts the input power supply voltage (PVDD) to the smoothing circuit section. A desired output voltage (Vout) is output from the terminal OUT via 40.

  The control circuit unit 10 includes an error amplification circuit 11, a reference power supply Vref, a PWM comparator 12, an oscillator 13, and a dead time generation circuit 14. The error amplifier circuit 11 receives the output voltage (Vout) of the terminal OUT and the reference voltage value (Vref) of the reference power supply Vref. The output voltage (Vout) may be divided and input. The error output of the error amplifier circuit 11 is input to the PWM comparator 12. The PWM comparator 12 compares this error output with a reference waveform such as a triangular wave generated by the oscillator 13, and a duty ratio corresponding to the magnitude of the error output between the output voltage (Vout) and the reference power supply value (Vref). Is output to the dead time generation circuit 14.

  The driver circuit unit 20 is a driver circuit 21 for driving the switching element Q1 (hereinafter referred to as a high side driver), an inverter circuit 22, and a driver circuit 23 for driving the rectifier element Q2 (hereinafter referred to as a low side driver). ). The outputs of the high side driver 21 and the low side driver 23 are connected to the gate of the switching element Q1 and the gate of the rectifying element Q2 of the output unit 30, respectively, and perform on / off control of the switching element Q1 and the rectifying element Q2. As a result, a rectangular wave having a desired duty ratio appears at a connection point M (hereinafter referred to as a switching terminal M) between the switching element Q1 and the rectifying element Q2 of the output unit 30.

  The smoothing circuit unit 40 is configured by a series circuit of an inductor L and a capacitor C, and the connection point thereof is connected to the terminal OUT. Here, one end of the inductor L is connected to the switching terminal M, and the other end of the capacitor C is grounded. In the smoothing circuit unit 40, the rectangular wave of the switching terminal M is smoothed by the inductor L, and a DC output voltage (Vout) having a desired magnitude can be obtained.

  Here, the switching element Q1 and the rectifying element Q2 of the output unit 30 are complementarily controlled on and off using the PWM signal of the control circuit unit 10. However, when the rectifying element Q2 is turned on before the switching element Q1 is completely turned off, or the switching element Q1 is turned on before the rectifying element Q2 is completely turned off, the switching element Q1 and the rectifying element Q2 are turned on. At the same time, it is turned on, and a short-circuit current flows between PVDD and GND.

  Therefore, in the control circuit unit 10, the dead time generating circuit 14 is provided in the subsequent stage of the PWM comparator 12, and the switching element Q1 and the rectifying element Q2 are controlled on and off by two signals having a dead time difference, respectively. Therefore, the switching element Q1 and the rectifying element Q2 of the output unit 30 turn on the rectifying element Q2 after the switching element Q1 is completely turned off, and turn on the switching element Q1 after the rectifying element Q2 is completely turned off. To prevent simultaneous on.

  In this DC / DC converter, since the switching element Q1 is an NMOS, the gate voltage for driving the switching element Q1 of the output unit 30 needs to be higher than the input power supply voltage (PVDD). Therefore, a bootstrap circuit that generates a voltage (Vbst) higher than the input power supply voltage (PVDD) is configured by the capacitor Cbst and the diode Dbst.

  In the bootstrap circuit, when the switching element Q1 is in the off state and the rectifying element Q2 is in the on state, the charging current flows into the capacitor Cbst from the control circuit power supply VDD via the diode Dbst. (The forward voltage of the diode Dbst is ignored). Next, when the switching element Q1 is turned on and the rectifying element Q2 is turned off, the voltage value (Vm) of the switching terminal M rises to the input power supply voltage (PVDD). Therefore, the voltage value (Vbst) of the connection point Vbst between the capacitor Cbst and the diode Dbst is the sum of the input power supply voltage (PVDD) and the charging voltage value (VDD) of the capacitor Cbst, that is, (PVDD + VDD), and is applied to the terminal Vbst. A voltage value higher than the input power supply voltage (PVDD) is generated.

  In this way, the high-side driver 21 operates with the voltage between terminals (Vbst−Vm) generated by the capacitor Cbst of the bootstrap circuit, and drives the gate of the switching element Q1 with a voltage higher than the input power supply voltage (PVDD). it can.

  Here, since the control circuit unit 10 operates between VDD and GND, and the high side driver 21 operates between Vbst and Vm, the level shift circuit 5 is provided in front of the high side driver 21, and the dead time generation circuit 14 is provided. It is necessary to convert the voltage level of the control signal from. On the other hand, the low-side driver 23 operates between VDD and GND similarly to the control circuit unit 10 as shown in FIG. 4, and therefore does not require voltage level conversion by the level shift circuit 5 as described above.

  For example, in Patent Document 1, a PWM controller is provided, and a level shift circuit is provided in the PWM controller. Here, the voltage level of the error voltage is appropriately shifted so that the dead time can be controlled. There is a description of the converter.

  Further, for example, in Patent Document 2, each switching timing of the first switching element and the second switching element is set according to a level shift amount generated by a level shift circuit in which the current determining resistor and the level shift resistor group are made of the same material. There is a description of a step-up / step-down chopper type DC / DC converter in which a difference in level difference is reduced by providing a level difference between applied voltage levels. According to this, it is possible to suppress a decrease in power conversion efficiency while realizing a more stable output voltage supply.

Furthermore, for example, in Patent Document 3, dead time required when switching between the main switching element and the switching element for synchronous rectification is switched, and even when soft starting the converter, a simpler circuit and useless dead time at steady state are provided. There is a description of a synchronous rectification type DC-DC converter that can be generated without generation.
JP 2001-112241 (paragraph numbers [0011] to [0015], FIGS. 1 and 2) Japanese Patent Laying-Open No. 2005-198410 (paragraph numbers [0105] to [0128], FIG. 8) Japanese Patent Laying-Open No. 2005-210820 (paragraph numbers [0020] to [0026], FIG. 1)

FIG. 5 is a timing diagram showing signal waveforms at various parts in the synchronous rectification type DC / DC converter of FIG.
FIG. 4A shows a PWM signal of the PWM comparator 12, FIG. 4B shows an output signal to the high side driver 21 side of the dead time generation circuit 14 (hereinafter referred to as a high side signal), FIG. ) Is an output signal to the inverter circuit 22 on the low side driver 23 side (hereinafter referred to as a low side signal), FIGS. 4D and 4E are input signals to the high side driver 21 and the low side driver 23, and FIG. In (f) and (g), control signals output from the high-side driver 21 and the low-side driver 23 to the output unit 30 are shown.

  In the conventional circuit as shown in FIG. 4 described above, the level shift circuit 5 having the delay time (Δt 1) converts the voltage level only at the front stage of the high side driver 21. Further, the high side driver 21 itself has a delay time (Δt 2), and the delay time (Δt 2) may be different from the delay time of the low side driver 23. Therefore, the delay times until the high-side signal and the low-side signal output from the control circuit unit 10 reach the gates of the switching element Q1 and the rectifying element Q2 are different.

  That is, as shown in FIGS. 5B and 5C, even if a control signal having an appropriate length of dead time (td1, td2) is generated in the dead time generation circuit 14, the level shift circuit 5 In conjunction with the delay time (Δt1), the dead time (td1, td2) changes like (td1a, td2a) on the input side of the drivers 21, 23, and further on the output side like (td1b, td2b) Therefore, the switching element Q1 and the rectifying element Q2 may be turned on at the same time. On the other hand, if the dead time (td1, td2) is made longer than necessary, there is a problem that power loss in the dead time period increases and the power conversion efficiency of the synchronous rectification type DC / DC converter decreases.

  As described above, it is necessary to determine an optimum value for the dead time including the delay time of the level shift circuit 5. However, since the delay time of the level shift circuit 5 varies due to the temperature deviation in the usage environment and the characteristic deviation in the manufacturing process of each product, the optimum dead time must be accurately estimated and designed. Is difficult. Therefore, in order to prevent a short circuit between PVDD and GND, a dead time longer than necessary is set, which is disadvantageous in terms of power conversion efficiency. In the above Patent Documents 1 to 3, there is no description about this problem and its solution due to the delay time.

  The present invention has been made in view of the above points, and provides a synchronous rectification type DC / DC converter capable of setting an optimum dead time regardless of the size of an input power source of a switching element. With the goal.

  In the present invention, in order to solve the above problem, in a synchronous rectification type DC / DC converter in which a DC input voltage is converted to obtain an output voltage of a desired magnitude, a main switching element that performs an on / off operation, A rectifying element that performs an on / off operation at a timing complementary to the main switching element, a control circuit that controls the main switching element and the rectifying element with a dead time for simultaneously turning off the main switching element, and an output from the control circuit to the main switching element A first voltage level conversion circuit for converting the voltage level of the control signal to be output, and a second voltage level conversion circuit for converting the voltage level of the control signal output from the control circuit to the rectifier element. A synchronous rectification type DC / DC converter is provided.

  In the synchronous rectification type DC / DC converter of the present invention, the second voltage level conversion circuit is inserted not only in the first voltage level conversion circuit but also in the previous stage of the rectification element. Since the signal transmission times to the elements are aligned, it is possible to prevent a variation in dead time due to a delay time difference in the first and second voltage level conversion circuits.

  According to the present invention, by preventing fluctuations in the dead time, the current passing through the switching element and the rectifying element is eliminated, and the dead time does not have to be set longer than necessary. Can be prevented.

Embodiments of the present invention will be described below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram showing a DC / DC converter according to the first embodiment. In FIG. 1, the same reference numerals are assigned to portions corresponding to those of the conventional circuit, and the description thereof is omitted. As in the conventional circuit shown in FIG. 4, NMOS is used as the switching element Q1 and the rectifying element Q2.

  The control circuit unit 10 has the same configuration as the conventional circuit shown in FIG. The DC / DC converter of FIG. 1 differs from the conventional circuit in that not only the level shift circuit 5 in the preceding stage of the high side driver 21 but also the low side signal output from the dead time generation circuit 14 is supplied to the low side driver 23. The level shift circuit 6 is inserted as a circuit for converting the voltage level of the control signal.

The high side signal and the low side signal from the dead time generation circuit 14 are respectively input to the level shift circuits 5 and 6 and then supplied to the driver circuit unit 20.
Here, the high-side level shift circuit 5 operates between Vbst and Vm, and the low-side level shift circuit 6 operates between VDD and GND. Here, the potential difference between Vbst and Vm is substantially the same as the potential difference between VDD and GND.

  In the driver circuit unit 20, the high side driver 21 operates with a potential difference between Vbst and Vm, and the low side driver 23 operates with a potential difference between VDD and GND. Therefore, the potential difference applied to both drivers 21 and 23 can be made almost the same. Therefore, the two drivers 21 and 23 may have the same configuration although there may be a difference in their element sizes depending on the difference in size between the switching element Q1 and the rectifying element Q2.

Next, the operation of the DC / DC converter of FIG. 1 will be described with reference to FIG.
FIG. 2 is a timing chart showing signal waveforms at various parts of the DC / DC converter according to the first embodiment.

  4A shows the PWM signal of the PWM comparator 12, FIG. 2B shows the output signal to the high side driver 21 side of the dead time generation circuit 14, and FIG. 3C shows the inverter on the low side driver 23 side. The output signals to the circuit 22, the input signals to the high-side driver 21 and the low-side driver 23 are shown in (d) and (e), and the high-side driver 21 and the low-side driver 23 are shown in FIGS. The control signal output to the output unit 30 is shown.

  Here, the two level shift circuits 5 and 6 connected to the high-side driver 21 and the low-side driver 23 have the same configuration. As a result, the delay times (Δt1) in the level shift circuits 5 and 6 coincide with each other. Therefore, the timing at which the control signal is input from the dead time generation circuit 14 to the driver circuit unit 20 is shown in FIGS. As shown, the dead time (td1, td2) generated by the dead time generation circuit 14 can be maintained while being supplied to the high side driver 21 and the low side driver 23 (the inverter circuit 22 has a simple configuration, so the delay can be ignored). .)

  The two level shift circuits 5 and 6 are formed on the same semiconductor integrated circuit substrate. Thus, the circuit operations of the level shift circuits 5 and 6 are affected to the same extent by the influence of the manufacturing process and the temperature change, and the absolute length of the dead time (td1, td2) is the level shift circuit 5, 6 hardly changes.

  Further, regarding the high-side driver 21 and the low-side driver 23, if they have the same circuit configuration, the delay time (Δt2) in the driver circuit unit 20 can be made almost the same. Therefore, the dead time (td1, td2) generated by the dead time generation circuit 14 can be maintained also in the driver circuit unit 20. However, strictly speaking, the delay of the inverter circuit 22 is negligible, but is not actually zero, and when the sizes of the switching element Q1 and the rectifying element Q2 are different, the influence of the size difference overlaps, The delay times are not exactly the same.

  Thus, the high-side signal generated by the dead time generation circuit 14 is provided by interposing the level shift circuits 5 and 6 and the drivers 21 and 23 having the same configuration in the preceding stage of the switching element Q1 and the preceding stage of the rectifying element Q2, respectively. The control signal can be transmitted to the gates of the switching element Q1 and the rectifying element Q2 while maintaining the dead time of the low-side signal. Therefore, the dead time disappears due to the delay generated in the level shift circuit 5 on the high side and a through current is generated in the output unit 30, or the inconvenience that the power conversion efficiency is lowered by setting the redundant dead time is eliminated. be able to.

(Embodiment 2)
FIG. 3 is a circuit diagram showing a DC / DC converter according to the second embodiment.
In the first embodiment, the DC / DC converter in which the switching element Q1 and the rectifying element Q2 are both composed of NMOS is shown. Here, as shown in FIG. 3, instead of the NMOS switching element Q1, a switching element Q3 of a P-channel MOSFET (hereinafter simply referred to as PMOS) is used, and the rectifying element Q2 is configured by NMOS.

  In the DC / DC converter of FIG. 3, the low-side level shift circuit 6 and the low-side driver 23 that drive the rectifying element Q2 are the same as those in the first embodiment, and the low-side driver 23 is driven by the potential difference between VDD and GND. Operate. Further, the inverter circuit 22 of the first embodiment is omitted. Therefore, a circuit for converting the voltage level such as the level shift circuit 6 is not necessary.

  On the high side for driving the switching element Q3, since the switching element Q3 is composed of PMOS, it is not necessary to apply a voltage higher than the input power supply voltage (PVDD) unlike the case where it is composed of NMOS. Therefore, the bootstrap circuit as shown in the first embodiment is not necessary here.

  Further, in the DC / DC converter of FIG. 3, the series regulator 7 based on the input power supply voltage (PVDD) is used as the power supply for the high side driver 21. This is because the high side driver 21 can be operated with a potential difference between PVDD and GND, but in order to make the delay time coincide with that of the low side driver 23, it can be driven with the same potential difference as the low side driver 23. . That is, the series regulator 7 is configured as a circuit whose output voltage Vs is (PVDD−VDD). As a result, the potential difference of the power source that drives the high-side driver 21 becomes VDD like the low-side driver 23, and the same delay time can be set by making the high-side driver 21 the same configuration as the low-side driver 23.

  As described above, since the high-side driver 21 operates between PVDD and Vs, it is necessary to perform level conversion of the output signal from the dead time generation circuit 14, and the stage before the high-side driver 21 is the same as in the first embodiment. The level shift circuit 5 is inserted into the circuit. The level shift circuit 5 may be configured to operate between PVDD and Vs similarly to the high side driver 21.

  Further, the level shift circuit 6 in the previous stage of the low side driver 23 is originally unnecessary, but the dead time at the gates of the switching element Q3 and the rectifying element Q2 changes depending on the delay time in the level shift circuit 5 on the high side. Inserted to prevent that. By adopting such a configuration, it is not necessary to consider the variation of the dead time due to the signal delay in the level shift circuits 5 and 6 and the driver circuit unit 20, and in the dead time generation circuit 14 as in the first embodiment. A control signal can be transmitted to the gates of the switching element Q3 and the rectifying element Q2 while maintaining the dead times of the generated high-side signal and low-side signal, so that the dead time can be generated with an optimum length.

  The present invention is particularly effective when the power loss caused by the dead time becomes larger than the increase in power consumption by the level shift circuits 5 and 6. That is, when a through current in the output unit 30 is prevented by a delay time when converting the voltage level, it is not necessary to set a large dead time before redundancy, thereby preventing a decrease in power conversion efficiency. it can.

1 is a circuit diagram showing a DC / DC converter according to Embodiment 1. FIG. FIG. 3 is a timing chart showing signal waveforms at various parts of the DC / DC converter according to Embodiment 1. 5 is a circuit diagram showing a DC / DC converter according to Embodiment 2. FIG. It is a circuit diagram which shows the synchronous rectification type DC / DC converter which has the conventional voltage level conversion circuit. FIG. 5 is a timing diagram showing signal waveforms at various parts in the synchronous rectification type DC / DC converter of FIG. 4.

Explanation of symbols

5, 6 Level shift circuit 7 Series regulator 10 Control circuit section 20 Driver circuit section 30 Output section 40 Smoothing circuit section Q1, Q3 Switching element Q2 Rectifier element

Claims (5)

In a synchronous rectification type DC / DC converter that converts a DC input voltage to obtain an output voltage of a desired magnitude,
A main switching element that performs on-off operation;
A rectifying element that performs on / off operation at a timing complementary to the main switching element;
A control circuit for controlling the main switching element and the rectifying element with a dead time for simultaneously turning off;
A first voltage level conversion circuit for converting a voltage level of a control signal output from the control circuit to the main switching element;
A second voltage level conversion circuit for converting a voltage level of a control signal output from the control circuit to the rectifying element;
A synchronous rectification type DC / DC converter characterized by comprising:   A delay time of a control signal transmitted from the control circuit to the main switching element via the first voltage level conversion circuit, and transmission from the control circuit to the rectifier element via the second voltage level conversion circuit 2. The synchronous rectification type DC / DC converter according to claim 1, wherein the delay time of the control signal to be matched is configured. The main switching element is supplied with the control signal from the first voltage level conversion circuit via a first driver circuit,
The rectifying element is supplied with the control signal from the second voltage level conversion circuit via a second driver circuit,
3. The synchronous rectification type DC / DC converter according to claim 1, wherein the first and second driver circuits are configured to be operated by power supplies having substantially equal potential differences.   4. The synchronous rectification type DC / DC converter according to claim 3, further comprising a bootstrap circuit for supplying power to the first driver circuit and the first voltage level conversion circuit.   4. The synchronous rectification type DC / DC converter according to claim 3, further comprising a series regulator circuit for supplying power to the first driver circuit and the first voltage level conversion circuit.

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