JP2005005907A - Signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal processor for removing noise superimposed on an analog signal, and to remove noise components without using any A/D converter having an excessive resolution for the contents of signal processing. <P>SOLUTION: This signal processor is provided with an A/D converter 10 for converting an analog signal into an n bit digital signal Sa<SB>n</SB>. A low order data applying circuit 14 adds the predetermined number α(two) of low order bits to the digital signal Sa<SB>n</SB>to generate an n+2 bit low order data application signal Sa<SB>n+2</SB>. An annealing processing circuit 16 operates annealing processing to the low order data application signal Sa<SB>n+2</SB>to generate n+2 bit annealing signal Sc<SB>n+2</SB>. A low order data omitting circuit 24 omits the low order α bits(2 bits) of the annealing signal Sc<SB>n+2</SB>to generate an n bit low order data omission signal Sc<SB>n</SB>. The low order data omission signal Sc<SB>n</SB>is outputted as a signal whose noise is removed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing device, and more particularly to a signal processing device suitable as a device for removing noise superimposed on an analog signal.
[0002]
[Prior art]
Conventionally, as disclosed in, for example, Japanese Patent Laid-Open No. 2000-91923, an apparatus for removing noise superimposed on an analog signal is known. This apparatus includes an A / D converter that converts an analog signal into a digital signal. The apparatus also includes a circuit for detecting the level of noise superimposed on the digital signal generated as described above, and a circuit for truncating the lower-order bits of the digital signal in accordance with the level.
[0003]
The above-described conventional apparatus reproduces the upper bit signal remaining after the lower bit is rounded down to a signal having the number of bits before the round down, and converts the reproduced signal into an analog signal and outputs it. According to such processing, the noise component superimposed on the input signal (analog signal) can be removed by a technique of discarding the lower-order bits of the digital signal after A / D conversion. For this reason, according to the conventional apparatus, only a signal component that does not include a noise component can be effectively extracted from an analog signal on which noise is superimposed.
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 2000-91923
[Problems to be solved by the invention]
However, if the lower bits of the digital signal generated by the A / D converter are discarded, the resolution of the A / D converter cannot be used effectively at the signal processing stage. In other words, when such a method is used, it is essential to provide the A / D converter with a resolution exceeding the resolution required in the signal processing stage in advance. For this reason, although the above conventional apparatus is useful for removing noise from an analog signal, it requires an A / D converter to have a specification (resolution) that is unnecessary for realizing desired signal processing. Met.
[0006]
The present invention has been made in view of the above points, and effectively removes noise components from an input signal without using an A / D converter having an excessive resolution with respect to the contents of signal processing to be executed. It is an object of the present invention to provide a signal processing device that can handle the above.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a first invention is a signal processing apparatus,
An A / D converter that converts an analog signal into an n-bit digital signal;
Low-order data giving means for adding a predetermined number α of low-order bits to the n-bit digital signal to generate a low-order data giving signal of n + α bits;
An annealing process means for performing an annealing process on the lower data giving signal to generate an n + α-bit annealing signal;
Lower-order data truncation means for truncating the lower α bits of the annealing signal to generate an n-bit lower-order data truncation signal;
It is characterized by providing.
[0008]
In a second aspect based on the first aspect, the smoothing processing means adds a predetermined ratio of the difference between the latest lower-level data giving signal and the previous smoothing signal to the previous smoothing signal. The latest annealing signal is generated.
[0009]
The third invention is the first or second invention, wherein
The analog signal is an output voltage of the sensor element,
The A / D converter samples the analog signal at every predetermined sampling timing,
Voltage application means for applying an impedance measurement voltage to the sensor element so as not to interfere with the sampling timing;
Impedance measuring means for measuring impedance of the sensor element when the impedance measurement voltage is applied;
It is characterized by providing.
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the element which is common in each figure, and the overlapping description is abbreviate | omitted.
[0010]
Embodiment 1 FIG.
FIG. 1 is a block diagram for explaining the control logic of the signal processing apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the signal processing apparatus of this embodiment includes an A / D converter 10. A / D converter 10 has a function of sampling the analog signal supplied to the input terminal 12 at a predetermined sampling period and converts the signal into a digital signal Sa _n of n bits.
[0011]
The n-bit digital signal generated by the A / D converter 10 is supplied to the lower data adding circuit 14. Lower data applying circuit 14, the digital signal Sa _n above, by adding the lower bits of a predetermined number of alpha, generates the low-order data grant signal n + alpha bits Sa n _{+ alpha.} Hereinafter, for convenience of explanation, it is assumed that the number of bits α added by the lower data adding circuit 14 is “2” and the lower data adding signal is represented as San _{+ 2} . Lower data grant signal _{Sa n + 2,} specifically, digital data Sa _n is "*****" (* bit) if it is, the value obtained by adding two bits (0) to the lower "* ****** ".
[0012]
The lower data application signal San _{+ 2} generated by the lower data application circuit 14 is supplied to the annealing circuit 16. The annealing circuit 16 is a circuit that generates an n + 2 bit annealing signal Sc _{n + 2} every time the low-order data providing signal San _{+ 2} is supplied in synchronization with the sampling period. The annealing circuit 16 includes a division circuit 18, a delay circuit 20, and a feedback circuit 22. The division circuit 18 is a circuit for dividing the low-order data application signal San _{+ 2} by the smoothing constant A. The delay circuit 20 is a circuit for storing the annealing signal Sb _{n + 2} calculated at the previous sampling timing. In addition, the feedback circuit 22 uses the value of the previous smoothing signal Sb _{n + 2} to reflect the new smoothing signal Sc _{n + 2} every time a new lower-level data providing signal San _{+ 2} is supplied in synchronization with the sampling period. This is a circuit for performing feedback at a predetermined ratio (1-1 / A). According to smoothing circuit 16, when the lower data providing signals Sa n _{+ 2} is newly supplied, by using a moderated signal Sb n _{+ 2,} and smoothing constants A last, the signal Sc n _{+ 2} moderation represented by the following formula Can be newly generated.
Sc _{n + 2} = Sb _{n + 2} + (San _{+ 2-} Sb _{n + 2} ) / A (1)
[0013]
The n + 2 bit annealing signal Sc _{n + 2} generated by the annealing circuit 16 is supplied to the lower data truncation circuit 24. The lower data truncation circuit 24 is a circuit for generating a lower data truncation signal Sc _n by truncating the lower 2 bits of the annealing signal Sc _{n + 2} . Here, the lower-order data truncation signal Sc _n is an n-bit signal, similar to the digital signal San generated by the A / D converter 10.
[0014]
FIG. 2 is a diagram for explaining a change in the number of bits that occurs in the process of signal processing in the signal processing apparatus shown in FIG. In the signal processing apparatus shown in FIG. 1, when each circuit performs signal processing by the above-described method, the shape of the signal processed there changes as shown in FIG. That is, if there a digital signal Sa _n is 10-bit data _{Sa 10} that are generated by the A / D converter 10 as shown in FIG. 2 (A), the lower data applying circuit 14, as shown in FIG. 2 (B) , lower data grant signals _{Sa 12} of 12 bits with two 00 to the lower _{Sa 10} is generated.
[0015]
In the annealing circuit 16, the calculation according to the above equation (1) is performed using the 12-bit annealing signal Sb ₁₂ obtained last time and the lower-order data addition signal Sa ₁₂ obtained this time, and as a result, 12-bit moderated signal _{Sc 12} as shown in FIG. 2 (C) is generated. Here, FIG. 2C shows an example in which the annealing signal Sc ₁₂ having “1” and “0” in the lower 2 bits is generated as a result of executing the annealing process according to the above equation (1). Show. Lower two bits of the moderated signal Sc ₁₂ can take four states, including a state shown in FIG. 2 (C). In other words, moderated signal _{Sc 12,} while following the 10-bit digital signal _{Sa 10} of a signal varies slowly compared to the signal _{Sa 10,} and the change at four times the resolution of _{Sa 10} It is a signal that can be represented.
[0016]
As shown in FIG. 2D, the lower data truncation circuit 24 generates a lower data truncation signal Sc ₁₀ equal to the upper 10 bits of the annealing Sc ₁₂ by truncating the lower 2 bits of the annealing signal Sc _12. Is done. According to the lower data truncation signal Sc _10, among the tendency to appear in moderated signal Sc _12, it can be expressed by extracting large tendency only.
[0017]
The analog signal input to the A / D converter 10 includes a relatively gradual change corresponding to information to be carried by the signal and a steep change caused by noise. For this reason, the digital signal Sa ₁₀ generated there is a superposition of a gradual change to be transmitted and a steep change that does not need to be transmitted. The gradual change appearing in the digital signal Sa ₁₀ causes a large change in the smoothed signal Sc ₁₂ with some delay. Therefore, the change is smoothed also becomes to be reflected in the value of the upper bit of the signal Sc _12, it can be extracted by the lower data truncation signal Sc _10. On the other hand, abrupt change that is superimposed on the digital signal Sa ₁₀ is smoothed averaging will be reflected in the signal Sc ₁₂ with a small proportion as a result of the processing, hard to be reflected only on the value of the lower bits. Therefore, when omitting lower bits of the moderated signal Sc _12, it is possible to eliminate the influence of the rapid change perhaps. Therefore, according to the low-order data truncation signal Sc ₁₀ generated by the above procedure to remove the noise component superimposed on the analog signal, to extract only a component corresponding to the information contained in the signal Is possible.
[0018]
Hereinafter, the operation and effect of the signal processing apparatus according to the present embodiment will be described more specifically with reference to FIG. 3 and FIG. 4.
FIG. 3A illustrates a change in a signal that is processed or generated in the signal processing apparatus of this embodiment. Specifically, a curve indicated by a solid line in the figure is a waveform of an analog signal input to the A / D converter 10. Here, the case where the steep change resulting from noise appears twice is illustrated. “·” And the broken line of the alternate long and short dash line indicate the 10-bit digital signal Sa ₁₀ or the 12-bit lower-level data giving signal Sa ₁₂ . Further, “Δ” indicates the annealing signal Sc ₁₂ calculated at each sampling timing, and “◯” and the solid broken line indicate the lower-order data truncation signal Sc ₁₀ . Here, three digits marked on the vertical axis of FIG. 3 (A) is a lower three bits of the digital signal Sa _10.
[0019]
The digital signal Sa ₁₀ (.reference) shown in FIG. 3 (A), the lower-order data application signal Sa ₁₂ corresponding to them, and the annealing signal Sc ₁₂ (see Δ) and the lower-order data truncation signal Sc shown in FIG. The value of ₁₀ (see ○) can be expressed as shown in FIG. However, the numbers shown in FIG. 3B are the values of the lower 3 bits for the digital signal Sa ₁₀ and the lower data truncation signal Sc ₁₀ , and the lower values for the lower data provision signal Sa ₁₂ and the annealing signal Sc _12. It is a 5-bit number. These numerical values are calculated by setting the annealing constant A used for the annealing process as “2”.
[0020]
As shown in FIG. 3A, the influence of noise greatly affects the digital signal Sa ₁₀ (dashed line broken line) obtained by A / D-converting an analog signal. On the other hand, the lower-order data truncation signal Sc ₁₀ (solid broken line) shows a change that accurately follows a gradual change of the analog signal without being affected by noise.
[0021]
The tendency shown in FIG. 3 (A) can be expressed as shown in FIG. 4 (A) and FIG. 4 (B) in relation to a larger time. That is, according to the signal processing apparatus of the present embodiment, by processing an analog signal as shown in FIG. 4A, that is, an analog signal including noise, as shown in FIG. it is possible to generate the lower data truncation signal Sc _n to accurately follow slow changes of the signal only. Then, the apparatus according to the present embodiment, by fully utilizing the resolution included in the A / D converter 10, that is, by utilizing all information of the digital signal Sa _n generated by the A / D converter 10, it is possible to generate the lower data truncation signal Sc _n. Therefore, according to the signal processing apparatus of the present embodiment, it is possible to effectively remove noise components from the input signal without using an A / D converter having an excessive resolution with respect to the contents of the signal processing to be executed. it can.
[0022]
Next, the case where the signal processing device of the present embodiment is applied to a vehicle oxygen sensor control device will be described.
FIG. 5 is a circuit diagram for explaining an outline of a circuit provided for driving the oxygen sensor 30 in the control device incorporating the signal processing device of the present embodiment. The oxygen sensor 30 is disposed in the exhaust passage of the internal combustion engine, for example, upstream of the catalyst. In this case, the oxygen sensor 30 generates an output corresponding to the oxygen concentration in the exhaust gas flowing into the catalyst. The oxygen sensor 30 is an electromotive force type sensor that generates a voltage corresponding to the oxygen concentration (the presence or absence of oxygen) in the gas to be detected. Equivalently, as shown in FIG. And can be expressed as
[0023]
As shown in FIG. 5, the circuit shown in FIG. 5 has a resistor 32 arranged in parallel with the oxygen sensor 30. Each of the oxygen sensor 30 and the resistor 32 has one end grounded and the other end connected to the A / D port 34. The oxygen sensor 30 is further connected with a switching element 38 via a resistor 36. The switching element 38 is an element that is turned on / off according to the potential of the control port 40, and a power supply voltage is supplied thereto.
[0024]
The oxygen sensor 30 generates an output corresponding to the oxygen concentration in the gas to be detected when the element temperature reaches the activation temperature. Further, the output characteristics of the oxygen sensor 30 are dependent on temperature. For this reason, in order for the oxygen sensor 30 to stably generate an output corresponding to the oxygen concentration in the gas to be detected, it is necessary to maintain the sensor element temperature at a constant activation temperature.
[0025]
Here, the sensor element temperature of the oxygen sensor 30 has a correlation with the impedance of the sensor element. Therefore, if the impedance of the sensor element can be detected, the sensor element temperature can be detected. As a result, the sensor element temperature can be controlled to the target activation temperature (for example, by heater control). For this reason, the control device for the oxygen sensor 30 is required to have a function for detecting the voltage generated by the oxygen sensor 30 and a function for detecting the impedance of the oxygen sensor 30.
[0026]
The circuit shown in FIG. 5 measures the impedance of the oxygen sensor 30 at a predetermined measurement cycle. Then, during the period when the measurement is not required, the switching element 38 is turned off. In the circuit shown in FIG. 5, the resistor 32 arranged in parallel with the oxygen sensor 30 has a sufficiently large value as compared with the impedance of the oxygen sensor 30. For this reason, while the switching element 38 is off, the output voltage of the oxygen sensor 30 appears at the A / D port 34. Therefore, during this period, the function of detecting the output of the oxygen sensor 30 can be realized by looking at the potential of the A / D port 34.
[0027]
The circuit shown in FIG. 5 temporarily turns on the switching element 38 when measuring the impedance of the oxygen sensor 30. When the switching element 38 is turned on, a power supply voltage is applied to the oxygen sensor 30 via the resistor 36. At this time, the same current I that flows through the resistor 36 flows through the oxygen sensor 30. The current I can be obtained as I = ΔV / R by detecting a voltage drop value ΔV generated before and after the resistor 36 and dividing the value ΔV by the impedance R (known) of the resistor 36, for example. In this case, the impedance Rs of the oxygen sensor 30 can be obtained as Rs = V / I by dividing the potential V of the A / D port 34 by the current I, for example. Thus, according to the circuit shown in FIG. 5, the function of detecting the impedance of the oxygen sensor 30 can be realized by turning on the switching element 38.
[0028]
FIG. 6A is a diagram schematically showing a change in potential appearing at the A / D port 34 shown in FIG. The signal processing circuit according to the present embodiment is combined with the circuit shown in FIG. 5 so that the A / D converter 10 shown in FIG. 1 takes in the potential appearing at the A / D port 34 described above. 6 (B) shows a series of lower data truncation signal Sc _n that the signal processor of this embodiment is produced in such combinations.
[0029]
As shown in FIG. 6A, the potential of the A / D port 34 varies greatly every time the switching element 38 is turned on for impedance measurement. The sampling timing of the analog signal (the voltage of the A / D port 34) by the A / D converter 10 is set so as not to overlap with the time when such a large fluctuation appears. However, particularly immediately after impedance measurement, the influence of voltage application tends to remain at the potential of the A / D port 34, and an analog signal on which noise is superimposed is easily captured by the A / D converter 10.
[0030]
On the other hand, the signal processing apparatus according to the present embodiment removes the influence of the noise when the analog signal on which the noise is superimposed is input to the A / D converter 10 as described above, and the information component of the analog signal. a digital signal accurately extract only, it can be generated as the lower data truncation signal Sc _n. For this reason, by incorporating the signal processing circuit of the present embodiment into the control circuit of the oxygen sensor 30, as shown in FIG. 6B, it is always accurate without being affected by the voltage application accompanying the impedance measurement. signal corresponding to the output voltage of the oxygen sensor 30 (it is possible to obtain a lower data truncation signal Sc _n.
[0031]
By the way, in Embodiment 1 mentioned above, although the component of a signal processing apparatus is demonstrated as the "lower data provision circuit 14", for example, those realization means are not restricted to hardware. In other words, the individual components of the signal processing device may be realized using software. In Embodiment 1 described above, the sensor driven by the control circuit shown in FIG. 5 is limited to the oxygen sensor, but the present invention is not limited to this. That is, the sensor driven by the control circuit shown in FIG. 5 may be an air-fuel ratio sensor that is used under the same conditions as the oxygen sensor 30, or any other sensor in which noise is superimposed on the input signal.
[0032]
In the first embodiment described above, the lower data adding circuit 14 is the “lower data adding means” in the first invention, and the annealing circuit 16 is the “annealing processing means” in the first invention. The lower data truncation circuit 24 corresponds to the “lower data truncation means” in the first invention. In the first embodiment, when the circuit shown in FIG. 5 appropriately turns on the switching element 38, the “voltage applying means” in the third invention also measures the impedance of the oxygen sensor 30 at that time. Thus, the “impedance measuring means” according to the third aspect of the present invention is realized.
[0033]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
According to the first invention, it is possible to generate an n + α-bit lower data giving signal based on an n-bit digital signal generated by the A / D converter. Then, an n + α-bit virtual signal, that is, an annealing signal can be generated by performing an annealing process on the low-order data addition signal. The annealing signal shows a change following the digital signal with a smaller change width (higher resolution) than the digital signal generated by the A / D converter. Normal changes in digital signals are gradual compared to noise. Therefore, the normal change is reflected in the upper n bits of the smoothed signal. On the other hand, the influence of noise hardly appears in the upper n bits of the smoothed signal and is easily absorbed in the lower α bits. In the present invention, the lower data truncation signal is generated by truncating the lower α bits of the smoothing signal. For this reason, the lower-order data truncation signal tends to be a signal in which only a normal change in the digital signal is reflected, that is, a signal from which noise is removed. As described above, according to the present invention, it is possible to generate an n-bit signal (lower data truncation signal) from which noise has been removed, using an A / D converter having an n-bit resolution.
[0034]
According to the second aspect of the invention, every time a new digital signal is generated by the A / D converter and the latest lower data giving signal corresponding to the digital signal is generated, the latest signal is approached so as to approach the latest signal. An annealing signal can be generated.
[0035]
According to the third invention, it is possible to measure the impedance of the sensor element at an appropriate timing while taking the output voltage of the sensor element as an analog signal at each sampling timing. Since a voltage is applied to the sensor element during impedance measurement, noise is easily superimposed on the output voltage. In the present invention, noise superimposed on the output signal of the sensor element is effectively removed in the process of signal processing. For this reason, according to this invention, the function which measures the impedance of a sensor element is realizable, without degrading the detection accuracy of a sensor.
[Brief description of the drawings]
FIG. 1 is a block diagram for explaining control logic of a signal processing apparatus according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a change in the number of bits that occurs in the process of signal processing in the signal processing apparatus according to Embodiment 1 of the present invention;
FIG. 3A is a diagram illustrating a change in a signal processed or generated in the signal processing apparatus according to the first embodiment of the present invention. FIG. 3B is a diagram in which the lower bits of the signal shown in FIG.
FIG. 4 is a diagram for explaining the effect of signal processing by the signal processing device according to the first embodiment of the present invention;
FIG. 5 is a circuit diagram for explaining an outline of a circuit provided for driving the oxygen sensor in the control device including the signal processing device according to the first embodiment of the present invention;
6A is a diagram schematically showing a change in potential appearing at the A / D port shown in FIG. 5. FIG. Also, FIG. 6 (B) is a diagram showing a state of the lower data truncation signal Sc _n signal processing apparatus according to the first embodiment of the present invention is produced as inputs the signal shown in FIG. 6 (A).
[Explanation of symbols]
10 A / D converter 14 lower data applying circuit 16 smoothing circuit 24 lower data truncation circuit 30 oxygen sensor _Sa n, _{Sa 10} digital signal _{Sa n + α,} Sa ₁₂ lower data grant signal Sb _{n + alpha,} moderation against _{Sb 12} previous sampling values Signal Sc _{n + α} , Sc ₁₂ Latest annealing signal Sc _n , Sc ₁₀ Lower data truncation signal

Claims (3)

An A / D converter that converts an analog signal into an n-bit digital signal;
Low-order data providing means for adding a predetermined number α of low-order bits to the n-bit digital signal to generate an n + α-bit low-order data giving signal;
An annealing process means for performing an annealing process on the lower data giving signal to generate an n + α-bit annealing signal;
Lower data truncation means for truncating the lower α bits of the smoothed signal to generate an n bit lower data truncation signal;
A signal processing apparatus comprising: The smoothing processing unit generates a latest smoothing signal by adding a predetermined ratio of a difference between the latest subordinate data giving signal and the previous smoothing signal to the previous smoothing signal. Item 1. The signal processing device according to Item 1. The analog signal is an output voltage of the sensor element,
The A / D converter samples the analog signal at every predetermined sampling timing,
Voltage application means for applying an impedance measurement voltage to the sensor element so as not to interfere with the sampling timing;
Impedance measuring means for measuring impedance of the sensor element when the impedance measurement voltage is applied;
The signal processing apparatus according to claim 1, further comprising:

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