JP2005005701A - Wafer edge etching device and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wafer edge etching method capable of increasing electric power without twisting a wafer when plasma etches a thin film layer at an edge bead. <P>SOLUTION: The wafer edge etching method is to etch a semiconductor wafer including a bottom electrode serving as a stage disposed below the semiconductor wafer for supporting the semiconductor wafer. The method comprises: a step of putting the semiconductor wafer in a chamber; a step of increasing pressure in the chamber; a step of supplying at least one kind of etching gas; a step of supplying electric power to the chamber; a step of etching the semiconductor wafer at the edge bead of the semiconductor wafer or the back surface of the same; a step of interrupting the supply of the electric power and the etching gas; and a step of exhausting and purging the exhaust gas from the chamber. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a wafer edge etching apparatus and method.

  Wafer edge etching is performed to remove the thin film layer on the peripheral area of the wafer. The peripheral area of the wafer is usually called edge bead. Since the thin film layer on the edge can induce defects on the chip during the manufacturing process and reduce the yield, the edge bead of the wafer is etched. The thin film layer can be removed from the edge by wet or dry etching methods. Due to the reduction in chip scale, the need to etch edges became more important.

  There are conventional devices for etching thin film layers with edge beads. However, the plasma generated by the conventional apparatus is too weak to etch a thin film layer with an edge bead. One solution to this problem is to increase power. However, the increased power can twist the wafer.

  An object of the present invention is to provide a wafer edge etching apparatus and method for solving the above problems.

  To achieve the above object, the present invention provides an apparatus for etching the edge of a semiconductor wafer including a bottom electrode arranged under the semiconductor wafer and acting as a stage to support the semiconductor wafer.

  To achieve the above object, the present invention includes a step of introducing a semiconductor wafer into a chamber, a step of increasing a pressure in the chamber, and a step of supplying at least one etching gas into the chamber while further increasing the pressure. Supplying power to the chamber and etching the semiconductor wafer at an edge bead or back surface of the semiconductor wafer; interrupting the power and etching gas; exhausting the chamber with exhaust gas; and purging exhaust gas from the chamber A semiconductor wafer etching method is provided.

  In order to achieve the above object, the present invention provides a step of arranging a bottom electrode under the semiconductor wafer, which serves as a stage for supporting the semiconductor wafer, a step of etching the semiconductor wafer at the edge bead or the back surface of the semiconductor wafer, and an insulation from the semiconductor wafer. A method of etching a semiconductor wafer is provided that includes maintaining a gap between the plates between 0.2 and about 1.0 mm.

  To achieve the above object, the present invention provides a step of arranging an insulating plate including protrusions on a semiconductor wafer, a step of etching a semiconductor wafer at an edge bead or a back surface of the semiconductor wafer, and a gap between the semiconductor wafer and the insulating plate is reduced to zero. A method of etching a semiconductor wafer is provided that includes maintaining the thickness between .2 and about 1.0 mm.

  To achieve the above object, the present invention provides a method for etching a semiconductor wafer, comprising: arranging a bottom electrode including a plurality of non-closed curved grooves under the semiconductor wafer; and etching the semiconductor wafer at an edge bead or back surface of the semiconductor wafer. provide.

  In order to achieve the above object, the present invention provides an insulating plate including a main body made of an insulating material and a protrusion including an inclined surface and a vertical surface.

  According to the present invention, the unnecessary material layer accumulated on the wafer edge is removed by processing with a precisely controlled plasma, so that the process time is shortened and the process equipment cost is reduced. In addition, since the plasma processing can be appropriately adjusted and applied according to the size of the wafer, the type and thickness of the material layer to be processed, the process efficiency is improved.

  The present invention will be understood in more detail from the following detailed description and the accompanying drawings, which are given for the purpose of illustration only and are not intended to limit the invention. .

  FIG. 1 represents an apparatus 100 according to an exemplary embodiment of the present invention. The apparatus 100 includes an upper electrode 10, a bottom electrode and stage 20, an edge electrode 30, an insulating plate 40, an RF power supply 50, an isolator and / or insulator 60, a central nozzle 70 and a process nozzle 80. As shown in FIG. 1, in the apparatus 100, the upper electrode 10 and the edge electrode 30 are anodes, and the bottom electrode 20 is a cathode. However, each of these can be reversed in other exemplary embodiments of the invention. As shown in FIG. 1, the bottom electrode 20 supports the wafer 1 while the top electrode 10 and the edge electrode 20 sufficiently generate plasma at the edge and / or the back surface of the wafer 1. At the edge of the wafer 1, the etching portion A is an area where desired etching must occur. Since RF power is supplied from the RF power supply 50 through the wafer 1, a sufficiently appropriate plasma is generated even with lower power to etch the thin film layer on the wafer 1. The low power is, for example, 500W. If the RF power commonly used in a typical semiconductor etcher is high, an edge bead may cause an arc.

  FIG. 2 shows a part of the apparatus of FIG. 1 in more detail. In particular, FIG. 2 shows the upper electrode 10, the bottom electrode 20, the edge electrode 30, the insulating plate 40 and the wafer 1 in detail. As shown in FIG. 2, the insulating plate 40 and the wafer 1 are separated by a variable distance H. As shown in FIG. 2, the insulating plate 40 may include a protrusion 41. In an exemplary embodiment, the protrusion 41 has an inclined portion or a contour for guiding the process gas, thereby preventing the process gas from flowing over the central region during the etching process, or fundamentally. Prevent it. Even though the protrusion 41 of FIG. 2 has a specific shape, this shape is exemplary, and other shapes that can guide the process gas appropriately so as to deviate from the central region of the wafer 1 during the etching process. May be used.

  FIG. 3 shows the exemplary protrusion 41 of FIG. 2 in detail. As illustrated, the protrusion 41 includes an inclined portion 43 and a precipice 45. The cliff 45 forms a gap 44 with the upper electrode 10. The gap 44 between the protrusion 41 and the upper electrode 10 can be controlled to adjust the etching area of the wafer 1. In an exemplary embodiment, the gap 44 is uniform or essentially uniform, even if not required to be the case. In other exemplary embodiments, the shape of the cliff 45 may be designed to increase the durability of the cliff 45 and / or the insulating plate 40.

  4A is a diagram illustrating the bottom electrode and the stage 20 of FIG. 1 according to an exemplary embodiment of the present invention. As shown in FIG. 4A, the bottom electrode 20 includes one or more grooves 31. The one or more grooves 31 prevent or reduce the possibility of the wafer 1 slipping from the bottom electrode and the stage 20. As shown in FIG. 4A, the one or more grooves 31 appear as straight lines that radiate from the center of the bottom electrode 20. In another exemplary embodiment, the groove 31 may be a curve. In another exemplary embodiment of the present invention, the straight and / or curved groove 31 may extend radially from other than the center of the bottom electrode 20. In another embodiment of the present invention, the groove 31 forms an open pattern that is opposed to a closed curve pattern such as a circle, rectangle, or triangle. In other exemplary embodiments, the bottom electrode and stage 20 may include one or more bolt holes 33 and / or one or more lift pin holes 35.

  4B shows a schematic diagram of the top electrode 10 and the insulating plate 40 in the exemplary embodiment of the present invention, and FIG. 4C shows the bottom electrode and stage 20 and the edge electrode 30 in the exemplary embodiment of the present invention. Show.

  FIG. 4B is a diagram illustrating an upper region in which process gas and / or inert gas is dispersed. As shown in FIG. 4B, the upper electrode 10 includes one or more process gas sources 75 and one or more inert gas sources 76, and is attached to the upper electrode support 74a. In addition, as shown in FIG. 4B, the insulating plate 40 may include one or more auxiliary gas discharge ports 79c and one or more auxiliary insulating plates 79d.

  In the exemplary embodiment of the present invention, the upper electrode 10 includes one or more bolt holes 79 b for connecting the insulating plate 40 to the upper electrode 10. In another exemplary embodiment of the present invention, the insulating plate 40 includes one or more bolt holes 79a for connecting the one or more auxiliary insulating plates 79d to the insulating plate 40.

  FIG. 4C is a diagram illustrating a lower region where the wafer 1 is loaded. As shown in FIG. 4C, a ring-shaped first insulator 84 and a cylindrical plate-shaped second insulator 85 may be used between the bottom electrode 20 and the edge electrode 30.

  FIG. 5 is a diagram illustrating the relationship between the bottom electrode and stage 20, the separator and / or insulator 60, the wafer 1, and the edge electrode 30 in an exemplary embodiment of the invention.

  FIG. 6 is a diagram illustrating an apparatus 200 according to an exemplary embodiment of the present invention. As shown in FIG. 6, the apparatus 200 includes an upper electrode 110, a bottom electrode and stage 120, a first edge electrode 130, a second edge electrode 140, an insulator 150, an RF power supply 160 and a ground terminal 170. Including. As shown in FIG. 6, the bottom electrode and the stage 120 are formed while the top electrode 110, the first edge electrode 130, and the second edge electrode 140 repeatedly generate plasma on the edge bead and / or the back surface of the wafer 1. The wafer 1 is supported. As described above, in connection with the embodiment shown in FIG. 1, the top electrode 110, the bottom electrode and stage 120, the first electrode 130, and the second electrode 140 may each be an anode or a cathode.

  In the exemplary embodiment, the first edge electrode 130 and / or the second edge electrode 140 are donut-shaped electrodes, and concentrate the plasma on the edge bead and / or the back surface of the wafer 1.

  In the exemplary embodiment shown in FIG. 6, since RF power is supplied through the wafer 1, low power can be used to generate enough plasma to etch the thin film layer on the wafer 1. The low power is 500 W, for example. As described above, conventional 2000 W RF power can generate an arc with an edge bead.

  Various exemplary embodiments of the insulating plate shown in FIGS. 2 and 4 and / or various exemplary embodiments of the bottom electrode 20 shown in FIGS. 4 and 5 are also shown in FIG. Can be used in the exemplary embodiment.

  FIG. 7 is a diagram illustrating an apparatus 300 according to another exemplary embodiment of the present invention. As shown, the apparatus 300 includes a bottom electrode and stage 220, an edge electrode 240, an insulator 250, and an RF power supply 280. As shown in FIG. 7, the bottom electrode and stage 220 supports the wafer 1. As shown in FIG. 7, the edge electrode 240 is a ring-shaped edge electrode that repeatedly generates plasma on the edge bead and / or the back surface of the wafer 1.

  Various exemplary embodiments of the insulating plate shown in FIGS. 2 and 3 and / or various exemplary embodiments of the bottom electrode 20 shown in FIGS. 4 and 5 are also shown in FIG. Can be used in conjunction with other exemplary embodiments.

  FIG. 8 is a diagram illustrating an exemplary method according to the present invention. In step S10, the wafer 1 is loaded into the chamber. In step S20, the pressure in the chamber is decreased. In step S30, the pressure is increased while at least one etching gas is supplied into the chamber. In step S30, power is also applied to the chamber to etch the semiconductor wafer at the edge bead or backside of the semiconductor wafer. After step S30, supply of at least the etching gas and the end power is interrupted, and exhaust gas is supplied into the chamber in step S40. In step S50, exhaust gas is purged from the chamber, and in step S60, the wafer is unloaded from the chamber.

  FIG. 9 is an exaggerated example of the wafer 1 after the etching process, such as the exemplary process of FIG. 10A and 10B are diagrams illustrating cell regions and edge regions of a wafer 1, respectively, according to an exemplary embodiment of the present invention. As shown in FIG. 10A, the wafer 1 includes a silicon substrate 310, a shallow trench isolation (STI) layer 320, an insulating layer 330, a tungsten (W) layer 340, and a first / second nitride layer. 350 and an oxide layer 360. As shown, FIG. 10A shows a cell region of wafer 1 that includes a silicon substrate 310 having an active region 311 and an inactive region 312. The cell region also includes a trench 320 formed by STI. The cell region may further include a polysilicon layer 325.

The insulating layer 330 may be BPSG (Boron-Doped Phospho Silicate Glass) or TEOS (Tetra Ethyl Ortho Silicate) of 3000 to 8000 mm. The tungsten layer 340 is formed using WF ₆ gas and may have a thickness of 300 to 1000 mm. The first and second nitride layers 330 and 350 have a thickness of 1500 to 3500 Å and 150 to 750 そ れ ぞ れ, respectively, and may be formed using SiH ₄ + NH ₃ gas. The oxide layer 360 is formed using SiH ₄ + O ₂ gas, and may have a thickness of 1000 to 5000 mm.

  The thicknesses and materials are exemplary, and others known to those skilled in the art can be used.

FIG. 11 illustrates exemplary process conditions that may be used to etch a wafer according to an embodiment of the present invention. As shown in FIG. 11, preparing the chamber for etching can be accomplished by a two-step process. The pressure increases in the first stage, the pressure further increases in the second preparation stage, and one or more etching gases are supplied. Pressure is maintained during the etching phase, the supply of etching gas is maintained, and RF power is supplied. In the first preparation stage, the pressure can be increased to 1 Torr. In the second preparatory stage, the pressure is increased to 1.5 Torr, and the etching gas includes argon gas and / or CF ₄ gas, for example in the range of 20 to 200 sccm for argon gas and 100 to 250 sccm for CF ₄ gas. Can be supplied within. In an exemplary embodiment, the RF power is increased to 500 W during the etching phase, the pressure is maintained at 1.5 Torr, and the flow rate of the etching gas is maintained constant as in the second preparation phase.

Once the wafer 1 is etched, the chamber can also be evacuated in a two-stage manner. In the first stage, power is interrupted, the pressure is restored to normal, and exhaust gas such as N ₂ gas is supplied. In an exemplary embodiment, the purge gas flow rate is between 10 and 200 sccm. In the second exhaust stage, exhaust gas is still supplied and purge gas is also supplied. In an exemplary embodiment, the purge gas is an inert gas and is supplied at a flow rate of, for example, 1200 sccm. In an exemplary embodiment, a gas such as an inert gas does not flow through the central nozzle 70 shown in FIG. 1 during the edge etch process, which causes such a gas to arc in the central region of the wafer 1. This is because

  The power, gas, pressure and flow rates are exemplary and others can be used as is known to those skilled in the art. The preparation, etching and evacuation steps are exemplary and may comprise more or fewer steps as is known to those skilled in the art.

  It should be noted that in an exemplary embodiment of the invention, a gas such as an inert gas can induce an arc in the central portion of the substrate and therefore does not flow through the central nozzle 70 during the edge etch process.

FIGS. 12A-12C show experimental results representing the relationship between the etch rates of various oxides on the wafer, which shows only the edge region of the etched wafer, not the central region of the wafer. The conditions for obtaining the results of FIGS. 12A to 12C are 500 W RF power, 1.5 Torr pressure, argon gas and CF ₄ gas process gas supplied at 70 sccm and argon gas and 150 sccm. CF ₄ gas, including a 1.5 mm gap. 12A-12C show that different material layers have the same or similar etch rates under the same or similar conditions. As a result, different material layers can be removed in one process step without changing or fundamentally changing the process conditions. This is an advantage over conventional wet methods where different chemicals are used to remove different material layers.

  FIG. 13 is a graph of gap 44 (X axis) between the insulating plate and the top electrode versus distance L (Y axis) from the center of the wafer to the edge point of the wafer in an exemplary embodiment of the invention. As shown in FIG. 13, “L + A” is the same as the radius of the wafer 1. For example, the first spot in FIG. 13 indicates that a 2.4 mm etched area A is obtained using a 200 mm diameter wafer (100 mm radius wafer) and a 1.0 mm gap 44. As shown in FIG. 13, L is shortened (and the corresponding A is enlarged) as the gap 44 is enlarged.

  FIG. 14 is a graph of semiconductor substrate distance (X axis) versus etching rate (Y axis) versus a plurality of different H values (between 0.3 and 10.0 as shown). As shown in the figure, there is a positive correlation between the distance H between the insulating plate 40 and the wafer 1 and the gap 44 between the cliff 45 of the insulating plate 40 and the upper electrode 10. In the exemplary graph of FIG. 14, a 1.6 mm gap 44 is used, and the etched layer is oxide.

  FIG. 14 shows data for different H values, some of which have even better performance even though a distance H of 0.3 mm to 10.0 mm is implemented by the exemplary embodiment of the present invention. Shown (eg, 0.3, 0.4, 0.5, 0.7 and 1.0 mm).

  FIG. 15 is a cross-sectional view illustrating a plasma processing apparatus for processing an edge of a wafer according to an exemplary embodiment of the present invention. As shown in the figure, the plasma processing apparatus includes a chamber 70, a chamber wall 71, a telescopic portion 71a, a wafer inlet / outlet 72, a purge gas inlet, an upper electrode 10, a support base 74a for the upper electrode 10, a stem 74b, and a process gas. A source 75, a process gas line 75a, an inert gas source 76, an inert gas line 76b, a plate 77 of the upper electrode 10 movable up and down, a support 77a for the plate 77 of the upper electrode 10, and a plate 77 of the upper electrode 10. Driver 78, insulating plate 40, auxiliary insulating plate 40a, auxiliary gas outlet 79c, wafer 1, bottom electrode and stage 20, first insulator 84, second insulator 85, edge electrode 30, and wafer 1 as bottom electrode and stage Lift pins 88 for receiving and loading on 20, baffle plates for exhausting process gas or inert gas uniformly 0, refrigerant line 92, the refrigerant source 94, RF power source 96, lift pin plate 97 can include lift pin plate 97 driver 98 and an exhaust pump 99.

  In an exemplary embodiment, the process apparatus may include one or more chambers. In an exemplary embodiment, the apparatus may include one or more preparation stations, one or more process chambers, one or more purge chambers, and at least one or more transfer chambers. In such an apparatus, one wafer can be transferred and another wafer can be loaded while another wafer is processed.

  As described above, in an exemplary embodiment, power, such as RF power, is supplied through the wafer to generate sufficient power to generate a plasma to etch the thin film layer. As known to those skilled in the art, the power may be supplied through other layers instead of or in addition to the wafer. In addition, the power may be conventional power of 2000 W or less, such as 500 W, in connection with one or more of the exemplary embodiments of the present invention.

  In the exemplary embodiment, the upper electrode 10 is a solid plate electrode. In an exemplary embodiment of the invention, the gap is used to control the etching area and size on the semiconductor wafer. In another exemplary embodiment, additionally replaceable insulating plates are used, each arranged adjacent to the upper electrode of the solid plate, each having a different gap size. In an exemplary embodiment, the gap between the semiconductor wafer and the insulating plate is 0.2 to about 1.0 mm.

In an exemplary embodiment, O ₂ and SF ₆ can be used as etching gases alone or in combination with argon gas and / or CF ₄ gas. In an exemplary embodiment, the etching gas etches all desired layers on the semiconductor wafer.

  In an exemplary embodiment, the insulating plate is made of an insulating material such as ceramic and / or quartz.

  It will be clear that the invention described above can be modified in many ways. Such variations should not be treated as departing from the spirit of the present invention, and as will be apparent to those skilled in the art, all such modifications are within the spirit of the claims.

  The present invention can remove a material layer that is unnecessarily formed on the edge of a wafer through plasma processing, and thus can be widely used in plasma-type equipment for manufacturing semiconductor devices.

FIG. 2 shows an apparatus according to an exemplary embodiment of the present invention. FIG. 2 shows in more detail a typical part of the device of FIG. FIG. 3 shows the exemplary protrusion of FIG. 2 in more detail. FIG. 2 is a diagram illustrating the bottom electrode and the stage of FIG. 1 in an exemplary embodiment of the invention. 2 is a schematic view of an upper electrode and an insulating plate of FIG. 1 according to an exemplary embodiment of the present invention. FIG. 2 is a schematic view of a bottom electrode, a stage, and an edge electrode of FIG. 1 in an exemplary embodiment of the present invention. FIG. 6 illustrates an exemplary relationship between a bottom electrode and stage, an isolator and / or insulator, a wafer, and an edge electrode in an exemplary embodiment of the invention. FIG. 6 shows an apparatus according to another exemplary embodiment of the present invention. FIG. 6 shows an apparatus according to another exemplary embodiment of the present invention. FIG. 4 illustrates a method according to another exemplary embodiment of the present invention. FIG. 9 illustrates an exaggerated exemplary wafer after an etching process, which is an exemplary process of FIG. 8. FIG. 4 shows the resulting cell cell and edge regions of a wafer according to an exemplary embodiment of the present invention. FIG. 4 shows the resulting cell cell and edge regions of a wafer according to an exemplary embodiment of the present invention. FIG. 4 illustrates exemplary process conditions that may be used to etch a wafer according to an exemplary embodiment of the present invention. FIG. 6 shows experimental results representing the relationship between the etch rates of various oxides on a wafer according to an exemplary embodiment of the present invention. FIG. 6 shows experimental results representing the relationship between the etch rates of various oxides on a wafer according to an exemplary embodiment of the present invention. FIG. 6 shows experimental results representing the relationship between the etch rates of various oxides on a wafer according to an exemplary embodiment of the present invention. 5 is a graph showing a gap between an insulating plate and an upper electrode versus a distance from an end point of a wafer in an exemplary embodiment of the present invention. FIG. 4 shows a variable gap according to an exemplary embodiment of the present invention. 1 is a cross-sectional view illustrating a plasma processing apparatus for processing an edge of a wafer according to an exemplary embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wafer 10 Upper electrode 20 Bottom electrode 30 Edge electrode 40 Insulating plate 41 Protrusion part 100 Apparatus H Variable distance

Claims (44)

  An edge etching apparatus for a semiconductor wafer, comprising a bottom electrode arranged under the semiconductor wafer and serving as a stage for supporting the semiconductor wafer.   2. The semiconductor wafer edge etching apparatus according to claim 1, further comprising an upper electrode of a solid plate arranged on the semiconductor wafer.   The edge etching apparatus for a semiconductor wafer according to claim 1, further comprising a ring-shaped upper electrode arranged on the semiconductor wafer.   3. The method according to claim 2, further comprising a lower edge electrode arranged under the semiconductor wafer, wherein the upper electrode and the lower edge electrode of the solid plate repeatedly generate plasma on the edge and back surface of the semiconductor wafer. An edge etching apparatus for a semiconductor wafer as described in 1.   4. The method according to claim 3, further comprising a lower edge electrode arranged under the semiconductor wafer, wherein the ring-shaped upper electrode and the lower edge electrode repeatedly generate plasma at an edge and a back surface of the semiconductor wafer. An edge etching apparatus for a semiconductor wafer as described in 1.   5. The semiconductor wafer edge etching apparatus according to claim 4, wherein any one of the bottom electrode, the upper electrode of the solid plate, and the lower edge electrode is a cathode or an anode.   The semiconductor wafer edge etching apparatus according to claim 2, further comprising an insulating plate arranged adjacent to the upper electrode of the solid plate with a gap.   4. The semiconductor wafer edge etching apparatus according to claim 3, further comprising an insulating plate arranged adjacent to the ring-shaped upper electrode with a gap.   The semiconductor wafer edge etching apparatus according to claim 4, further comprising a separator arranged between the bottom electrode and the lower edge electrode.   The distance between the insulating plate and the semiconductor wafer is set sufficiently small to substantially prevent plasma from being formed in a central region of the semiconductor wafer. Semiconductor wafer edge etching equipment.   The distance between the insulating plate and the semiconductor wafer is set to be small enough to fundamentally prevent plasma from being formed in a central region of the semiconductor wafer. Semiconductor wafer edge etching equipment.   The semiconductor wafer edge etching apparatus according to claim 7, wherein the insulating plate includes a protrusion.   13. The apparatus of claim 12, wherein the protrusion includes an inclined surface and a wall surface, and the wall surface forms a gap with the upper electrode of the solid plate.   13. The semiconductor wafer edge etching apparatus according to claim 12, wherein the protrusion substantially prevents an etching gas from flowing into a central region of the semiconductor wafer.   The apparatus of claim 13, wherein the gap adjusts a size of an etching region on the semiconductor wafer.   The semiconductor wafer edge etching apparatus according to claim 7, further comprising a replaceable insulating plate, each of which is arranged adjacent to the upper electrode of the solid plate and has gaps of different sizes.   2. The semiconductor wafer edge etching apparatus according to claim 1, wherein the bottom electrode includes a plurality of open grooves.   The semiconductor wafer edge etching apparatus according to claim 17, wherein the plurality of open grooves are straight lines or curved lines.   The semiconductor device further includes an upper edge electrode arranged on the semiconductor wafer, wherein the upper electrode, the lower edge electrode, and the upper edge electrode of the solid plate repeatedly generate plasma on the edge and back surface of the semiconductor wafer. An edge etching apparatus for a semiconductor wafer according to claim 4.   20. The apparatus of claim 19, wherein one of the bottom electrode, the upper edge electrode, the upper electrode of the solid plate, and the lower edge electrode is a cathode or an anode.   20. The apparatus of claim 19, further comprising an insulating plate arranged adjacent to the upper electrode of the solid plate with a gap.   The distance between the insulating plate and the semiconductor wafer is set to be sufficiently small to substantially prevent plasma from being formed in a central region of the semiconductor wafer. Semiconductor wafer edge etching equipment.   The apparatus of claim 21, wherein the insulating plate includes a protrusion.   24. The apparatus of claim 23, wherein the protrusion includes an inclined surface and a wall surface, and the wall surface forms a gap with the upper edge electrode.   24. The semiconductor wafer edge etching apparatus according to claim 23, wherein the protrusion substantially prevents an etching gas from flowing into a central region of the semiconductor wafer.   25. The apparatus of claim 24, wherein the gap adjusts a size of an etching region on the semiconductor wafer.   The semiconductor wafer edge etching apparatus according to claim 21, further comprising an exchangeable insulating plate, each being adjacent to the upper electrode of the solid plate and having a gap of a different size.   20. The apparatus of claim 19, wherein the bottom electrode includes a plurality of open grooves.   29. The apparatus of claim 28, wherein the plurality of open grooves are straight lines or curved lines.   The apparatus for etching an edge of a semiconductor wafer according to claim 1, further comprising an edge bead electrode for repeatedly generating plasma at an edge and a back surface of the semiconductor wafer.   The edge etching apparatus for a semiconductor wafer according to claim 1, further comprising an insulating plate arranged adjacent to the upper electrode of the solid plate with a gap.   The distance between the insulating plate and the semiconductor wafer is set to be sufficiently small to substantially prevent plasma from being formed in a central region of the semiconductor wafer. Semiconductor wafer edge etching equipment.   32. The apparatus of claim 31, wherein the insulating plate includes a protrusion.   The semiconductor wafer edge etching apparatus according to claim 33, wherein the protrusion includes an inclined surface and a wall surface, and the wall surface forms a gap with the upper edge electrode.   34. The apparatus of claim 33, wherein the protrusion substantially prevents an etching gas from flowing into a central region of the semiconductor wafer.   35. The apparatus of claim 34, wherein the gap adjusts a size of an etching region on the semiconductor wafer.   32. The edge etching apparatus for a semiconductor wafer according to claim 31, further comprising an additionally replaceable insulating plate, each of which is arranged adjacent to the upper electrode of the solid plate and has gaps of different sizes.   32. The apparatus of claim 30, wherein the bottom electrode includes a plurality of open grooves.   The semiconductor wafer edge etching apparatus according to claim 38, wherein the plurality of open grooves are straight lines or curved lines. Placing a semiconductor wafer into the chamber;
Increasing the pressure in the chamber;
Supplying at least one etching gas to the chamber while further increasing the pressure;
Supplying power to the chamber and etching the semiconductor wafer at an edge bead or backside of the semiconductor wafer;
Interrupting the power and the etching gas;
Evacuating the chamber with exhaust gas;
Purging the exhaust gas from the chamber. Arranging a bottom electrode that serves as a stage for supporting the semiconductor wafer under the semiconductor wafer; and
Etching the semiconductor wafer at an edge bead or back of the semiconductor wafer;
Maintaining the gap between the semiconductor wafer and the insulating plate at 0.2 to about 1.0 mm. Arranging an insulating plate including protrusions on a semiconductor wafer;
Etching the semiconductor wafer at an edge bead or back of the semiconductor wafer;
Maintaining a gap between the semiconductor wafer and the insulating plate at 0.2 to about 1.0 mm. Arranging a bottom electrode including a plurality of open grooves under a semiconductor wafer;
Etching the semiconductor wafer with an edge bead or backside of the semiconductor wafer. A body made of an insulating material;
An insulating plate including a protruding portion including an inclined surface and a wall surface.

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